Trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) of trench source electrode and preparation method

Abstract

The invention provides a trench gate silicon carbide VDMOS of a trench source electrode and a preparation method, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain electrode metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a low-resistance region and a first lug boss; a barrier layer is formed again, etching and ion implantation are carried out, and a first well region and a second protruding part are formed; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type source region and a P-type well region are formed; a barrier layer is formed again, an insulating medium layer is formed through etching and oxidation, and a groove is formed in the insulating medium layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. The gate reliability problem of the trench gate is solved, extra electrodes do not need to be led out, the follow current capability of the body diode is improved, and the on-resistance of the device is reduced.

Description

Technical Field

[0001] The invention relates to a trench gate silicon carbide VDMOS with a trench source and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the requirements for device performance in different fields have different focuses, but the overall requirements include higher voltage resistance, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), and lower body diode conduction loss.

[0003] In addition, in trench gate devices, electric field concentration is prone to cause gate breakdown at the corners of the gate insulating medium. Generally, there are two solutions. One is to use a P-type shielding area structure to suppress gate breakdown, but the introduction of P-type doping will affect the device on-resistance; the other is to use a deep trench P-type well area, but because the potential of the P-type well area is relatively high, the potential needs to be drawn out from the edge of the P-type well area, which will increase the complexity of the device structure and packaging. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a trench-source trench-gate silicon carbide VDMOS and a preparation method thereof, which solves the gate reliability problem of the trench gate without the need to lead out an additional electrode, thereby improving the freewheeling capability of the body diode and reducing the on-resistance of the device.

[0005] In a first aspect, the present invention provides a method for preparing a trench-source trench-gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a low resistance region and a first protrusion; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a first well region and a second protrusion; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first well region to form a P-type source region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a second well region, wherein the P-type well region includes a first well region and a second well region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the second well region to form an N-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the first well region and the drift layer, and then oxidizing to form an insulating dielectric layer, wherein the insulating dielectric layer is provided with a groove; Step 8: removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a gate metal layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the P-type source region, and then depositing metal to form a first source metal region; Step 10, remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the P-type well region and the N-type source region, then deposit metal to form a second source metal region. The source metal layer includes the first source metal region and the second source metal region, remove the barrier layer, and complete the preparation.

[0006] In a second aspect, the present invention provides a trench-source trench-gate silicon carbide VDMOS, which is prepared by the method for preparing a trench-source trench-gate silicon carbide VDMOS according to the first aspect.

[0007] The advantages of the present invention are: 1. When the device drain is subjected to a large voltage, the P-type well region of the present invention forms a pn junction with the drift layer and the P-type well region to achieve voltage resistance; when the device withstands voltage, the distribution of the space charge region in the pn junction located in the P-type well region is such that the P-type well region is distributed away from the gate corner, thereby avoiding the problem of breakdown at the device gate corner due to the high electric field of the drain; Second, when the device is subjected to drain voltage, the present invention makes the potential of the P-type well region lower than that of the device gate through the source metal layer, so as to achieve the diffusion of the pn junction electric field to the P-type well regions on both sides, thereby improving the withstand voltage capability; and a P-type source region is provided to reduce the potential of the P-type well region; 3. The pn junction body diode of the device formed by the P-type source region of the present invention increases the contact area between the body diode and the N-type region, thereby improving the freewheeling capability of the body diode; 4. The present invention constructs a low-resistance region below the P-type well region. Without affecting the source function of the device, the resistance at the edge of the device is reduced after the device is turned on, thereby allowing the device current to expand toward the edge, thereby achieving the purpose of reducing the total on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0009] Figure 1 The schematic diagram of a trench-source trench-gate silicon carbide VDMOS of the present invention.

[0010] Figure 2 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 1 .

[0011] Figure 3 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 2 .

[0012] Figure 4 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 3 .

[0013] Figure 5 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 4 .

[0014] Figure 6 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 5 .

[0015] Figure 7 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 6 .

[0016] Figure 8 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 7 .

[0017] Fig. 9 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 8 .

[0018] Fig.10 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 9 .

[0019] Fig.11 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 10 .

[0020] Fig.12 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 10 one.

[0021] Fig.13 A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 10 two.

[0022] Fig.14A cross-sectional view of the process of a trench gate silicon carbide VDMOS with a trench source according to the present invention Figure 10 three. DETAILED DESCRIPTION

[0023] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0025] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0026] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0027] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0028] like Figures 1 to 14 As shown, the embodiment of the present application provides a method for preparing a trench gate silicon carbide VDMOS with a trench source, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 109; epitaxially growing on the side of the silicon carbide substrate 101 to form a drift layer 102; Step 2: forming a barrier layer 110 on the drift layer 102, etching the barrier layer 110 to form a through hole, and performing ion implantation into the drift layer 102 to form a low resistance region 103 and a first protrusion 1021; Step 3, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, and performing ion implantation into the drift layer 102 to form a first well region 111 and a second protruding portion 1022; Step 4, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, and performing ion implantation into the first well region 111 to form a P-type source region 105; Step 5, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, and performing ion implantation into the drift layer 102 to form a second well region 112, wherein the P-type well region 104 includes a first well region 111 and a second well region 112; Step 6: remove the original barrier layer 110, re-form the barrier layer 110, etch the barrier layer 110 to form a through hole, and perform ion implantation into the second well region 112 to form an N-type source region 1041; Step 7, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, etching the first well region 111 and the drift layer 102, and then oxidizing to form an insulating dielectric layer 106, wherein the insulating dielectric layer 106 has a groove 1061; Step 8, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, and depositing metal to form a gate metal layer 107; Step 9, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, and etching the P-type source region 105, and then depositing metal to form a first source metal region 1081; Step 10, remove the original barrier layer 110, reform the barrier layer 110, etch the barrier layer 110 to form a through hole, and etch the P-type well region 104 and the N-type source region 1041, then deposit metal to form a second source metal region 1082, the source metal layer 108 includes a first source metal region 1081 and a second source metal region 1082, remove the barrier layer 110, and complete the preparation.

[0029] In this embodiment, preferably, a first opening (not shown in the figure) is provided on the P-type well region 104, and the P-type source region 105 is provided in the first opening; a second opening (not shown in the figure) is provided on the P-type source region 105, and the lower part of the source metal layer 108 is provided in the second opening.

[0030] In this embodiment, preferably, the lower side surface of the gate metal layer 107 is flush with the upper side surface of the second protruding portion 1022 .

[0031] In this embodiment, preferably, the doping concentration of the drift layer 102 is less than the doping concentration of the low resistance region 103 .

[0032] In this embodiment, preferably, the doping concentration of the P-type well region 104 is less than the doping concentration of the P-type source region 105 .

[0033] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 101, A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101; a first protrusion 1021 is provided on the drift layer 102, a second protrusion 1022 is provided on the first protrusion 1021, and a groove 10221 is provided on the second protrusion 1022; A low resistance region 103, wherein the lower side of the low resistance region 103 is connected to the upper side of the drift layer 102, and the inner side of the low resistance region 103 is connected to the outer side of the first protrusion 1021; A P-type well region 104, the P-type well region 104 is connected to the upper side of the low resistance region 103, the upper side of the drift layer 102, the upper side of the first protrusion 1021, the outer side of the second protrusion 1022 and the upper side of the second protrusion 1022; an N-type source region 1041 is provided on the P-type well region 104; A P-type source region 105 , wherein the P-type source region 105 is connected to the P-type well region 104 ; An insulating dielectric layer 106, wherein the lower portion of the insulating dielectric layer 106 is disposed in the groove 10221, and the outer side surfaces of the insulating dielectric layer 106 are respectively connected to the P-type well region 104 and the N-type source region 1041; a groove 1061 is disposed in the insulating dielectric layer 106; A gate metal layer 107, wherein the gate metal layer 107 is disposed in the groove 1061; A source metal layer 108 , wherein the source metal layer 108 is respectively connected to the P-type source region 105 , the P-type well region 104 , and the N-type source region 1041 ; and a drain metal layer 109 , wherein the drain metal layer 109 is connected to the lower side of the silicon carbide substrate 101 .

[0034] In another embodiment of the present invention, the silicon carbide substrate 101, the drift layer 102 and the low resistance region 103 are all N-type; the doping concentration of the silicon carbide substrate 101 is 2-8e18cm -3 , the doping concentration of the drift layer 102 is 6-10e16cm -3 , the doping concentration of the low resistance region 103 is 1-5e17cm -3 , the doping concentration of the P-type well region 104 is 6-10e16cm -3 , the doping concentration of the P-type source region 105 is 1-5e19cm -3 The material of the insulating dielectric layer 106 can be silicon dioxide, and the doping concentration of the N-type source region 1041 is 2-8e18cm -3 ; The doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 109, thereby reducing the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the P-type well region 104 is to achieve the withstand voltage of the pn junction structure of the device when the drain of the device is subjected to a high voltage; the doping concentration of the P-type source region 105 is to reduce the potential difference between the source metal layer 108 of the device and the P-type well region 104, thereby ensuring the low potential of the P-type well region 104 of the device; the doping concentration of the N-type low-resistance region 103 is to reduce the resistivity at the edge of the device, distribute the current in the JFET region of the device to the edge, and reduce the on-resistance of the device; the doping concentration of the N-type source region 1041 is to reduce the source contact resistance of the device and reduce the on-resistance of the device; The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, which is to form a low-resistance ohmic contact with the drain metal layer 109 and reduce the on-resistance of the device. The thickness of the N-type drift layer 102 is 50-100 μm, which is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device; the thickness of the second source metal region 1082 is 300 nm, the thickness of the first source metal region is 1.4 μm, the thickness of the P-type source region 105 located below the first source metal region 1081 is 200 nm, and the thickness of the P-type source region 105 located below the second source metal region 1082 is 1.3 μm and the width is 200 nm; the thickness of the P-type well region 104 located directly below the first source metal region 1081 is 1.3 μm and the width is 200 nm. The thickness of the P-type well region 104 located below the second source metal region 1082 is 1μm, the thickness of the P-type well region 104 located below the N-type source region 1041 is 100nm, the thickness of the N-type source region 1041 is 200nm, the width of the device N-type source region 1041 is 500nm, the total width of the P-type well region 104 is 2μm, the width of the insulating dielectric layer 106 is 50% of the width of the device structure, the gate metal thickness is 600nm, the bottom thickness of the insulating dielectric layer 106 is 200nm, the thickness of the N-type low resistance region 103 is 1μm, and the width is 800nm-1μm, in order to prevent the N-type low resistance region 103 from affecting the P-type well region 104 above it; In this embodiment, the source metal layer 108 and the P-type well region 104 of the device are extended to the inside of the device through the groove. When the drain of the device is subjected to a large voltage, the N-type drift layer 102 of the device and the P-type well region 104 of the device form a pn junction to achieve voltage resistance and avoid the breakdown problem of the gate corner of the device due to the high electric field of the drain. When the device is subjected to the drain voltage, it is necessary to ensure that the potential of the P-type well region 104 of the device is lower than that of the gate of the device, so as to achieve the diffusion of the pn junction electric field from the longitudinal direction to the P-type well region 104 on the left and right sides, and the potential of the P-type well region 104 of the device is balanced by constructing the first source metal region 1081. In order to reduce the potential of the P-type well region 104, a layer of P-type source region 105 is prepared; In addition to reducing the potential, the P-type source region 105 also forms a pn junction body diode of the device, increases the contact area between the body diode and the N-type region, and improves the freewheeling capability of the body diode; In this embodiment, an N-type low resistance region 103 is constructed. When the device is turned on, the resistance at the edge of the device is reduced without affecting the source function of the device, so that the device current extends to the edge, thereby achieving the purpose of reducing the total on-resistance.

[0035] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a trench-source trench-gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a low resistance region and a first protrusion; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a first well region and a second protrusion; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first well region to form a P-type source region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a second well region, wherein the P-type well region includes a first well region and a second well region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the second well region to form an N-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the first well region and the drift layer, and then oxidizing to form an insulating dielectric layer, wherein the insulating dielectric layer is provided with a groove; Step 8: removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a gate metal layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the P-type source region, and then depositing metal to form a first source metal region; Step 10, remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the P-type well region and the N-type source region, then deposit metal to form a second source metal region. The source metal layer includes the first source metal region and the second source metal region, remove the barrier layer, and complete the preparation.

2. The method for preparing a trench-source trench-gate silicon carbide VDMOS according to claim 1, characterized in that: A first opening is provided on the P-type well region, and the P-type source region is provided in the first opening; a second opening is provided on the P-type source region, and the lower part of the source metal layer is provided in the second opening.

3. The method for preparing a trench-source trench-gate silicon carbide VDMOS according to claim 1, characterized in that: The lower side surface of the gate metal layer is flush with the upper side surface of the second protrusion.

4. The method for preparing a trench-source trench-gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the drift layer is lower than the doping concentration of the low resistance region.

5. The method for preparing a trench-source trench-gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type well region is less than the doping concentration of the P-type source region.

6. A trench-source trench-gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

Images