Display substrate and display panel

Abstract

The invention provides a display substrate and a display panel, and the display substrate comprises a display area and a non-display area, and further comprises a substrate, and a first thin film transistor and a second thin film transistor which are located on the substrate. The first thin film transistor is located in the non-display area and comprises a first active layer, the first active layer comprises a first semiconductor layer, at least one second semiconductor layer and at least one carrier absorption layer which are stacked on the substrate, and the mobility of the first semiconductor layer is lower than that of the second semiconductor layer; the carrier absorption layer is adjacent to the second semiconductor layer. The second thin film transistor is located in the display area and comprises a second active layer, and the mobility of the second active layer is lower than that of the second semiconductor layer. The carrier absorption layer can absorb part of carriers generated in the second semiconductor layer, so that the size of the first thin film transistor is allowed to be further reduced, and narrowing design of a non-display area of the display substrate is facilitated.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a display substrate and a display panel. Background Art

[0002] With the development of information technology, the usage rate of electronic display products in daily life is increasing. Thin film transistors are the main switching elements of the driving circuits in electronic display products. However, the active layer in the current thin film transistors is limited by its own structural design and formation process. It is difficult to reduce the design size while ensuring the performance of the thin film transistor, so as to further narrow the border of the electronic display product. Summary of the invention

[0003] In a first aspect, the present disclosure provides a display substrate, which includes a display area and a non-display area, and further includes a substrate and a first thin film transistor and a second thin film transistor located on the substrate. The first thin film transistor is located in the non-display area, and the first thin film transistor includes a first active layer, and the first active layer includes a first semiconductor layer, at least one second semiconductor layer and at least one carrier absorption layer stacked on the substrate, the mobility of the first semiconductor layer is lower than the mobility of the second semiconductor layer, and the carrier absorption layer is adjacent to the second semiconductor layer. The second thin film transistor is located in the display area, and the second thin film transistor includes a second active layer, and the mobility of the second active layer is lower than the mobility of the second semiconductor layer.

[0004] In the above scheme, by adding a second semiconductor layer with high mobility to the first active layer, the length of the first active layer can be reduced, and the reduction in the length of the first active layer can reduce the size of the first thin film transistor, which is beneficial to the narrowing design of the non-display area of ​​the display substrate (extremely narrow frame or frameless design), the high-mobility second semiconductor layer and the reduction in the length of the first active layer will cause the first active layer to be unstable (the first thin film transistor is easily turned on), and the carrier absorption layer can absorb part of the carriers generated in the second semiconductor layer to ensure the stability of the first thin film transistor; in addition, the mobility of the first semiconductor layer and the second active layer of the first active layer is relatively low, so that they can be prepared in the same process to simplify the process of the first thin film transistor and the second thin film transistor, thereby controlling the cost of the display substrate.

[0005] In a specific embodiment of the first aspect of the present disclosure, the first semiconductor layer and the second active layer are in the same layer and made of the same material. In this way, the first semiconductor layer and the second active layer can be simultaneously prepared in the same process to further simplify the preparation process of the first thin film transistor and the second thin film transistor. It should be noted that under this design, because the mobility of the first semiconductor layer is relatively low, and under the design requirement of reducing the size of the first active layer to reduce the width of the non-display area, the first active layer with a high-mobility second semiconductor layer will be more easily turned on or have worse stability. Therefore, it is more necessary to set the above-mentioned carrier absorption layer.

[0006] Optionally, the length of the first active layer is greater than the length of the second active layer. In this way, the size of the first thin film transistor can be designed to be smaller than the size of the second thin film transistor, and in the case where the first active layer of the first thin film transistor is designed to include a carrier absorption layer, the provision of the second semiconductor layer will not affect the stability of the first thin film transistor, that is, by providing the carrier absorption layer, the adverse effects of reducing the first thin film transistor are eliminated, so that the width of the non-display area can be reduced while ensuring the performance of the display substrate, so as to facilitate the design of an extremely narrow frame of the display substrate.

[0007] In a specific embodiment of the first aspect of the present disclosure, the bandgap of the carrier absorption layer is greater than the bandgap of the second semiconductor layer. Thus, when the first active layer is operating, a portion of the carriers generated in the second semiconductor layer can enter the carrier absorption layer.

[0008] In a specific embodiment of the first aspect of the present disclosure, the second semiconductor layer includes an In element, and the content of the In element in the carrier absorption layer is 0. In this way, the band gap of the carrier absorption layer can be much larger than that of the second semiconductor layer, and the carrier absorption layer can be close to an insulating layer, thereby increasing the carrier absorption layer's ability to absorb carriers generated by the second semiconductor layer.

[0009] Optionally, the carrier absorption layer includes at least one of Ga and Zn.

[0010] Optionally, the carrier absorption layer includes Ga and Zn, and the Ga content is 30%-100% of the metal element content included in the carrier absorption layer, and the Zn content is 0%-70% of the metal element content included in the carrier absorption layer.

[0011] In another specific embodiment of the first aspect of the present disclosure, the content of In in the second semiconductor layer is greater than the content of In in the carrier absorption layer. In this way, the band gap of the carrier absorption layer can be ensured to be greater than the band gap of the second semiconductor layer, so as to ensure the absorption capacity of the carrier absorption layer for the carriers generated by the second semiconductor layer.

[0012] Optionally, the carrier absorption layer further includes at least one of Ga and Zn. Optionally, the carrier absorption layer includes In, Ga and Zn, and the In content is 0%-30% of the metal element content included in the carrier absorption layer, the Ga content is 30%-100% of the metal element content included in the carrier absorption layer, and the Zn content is 0%-70% of the metal element content included in the carrier absorption layer.

[0013] Optionally, the carrier absorption layer has a thickness of 1 nm-10 nm.

[0014] In a specific embodiment of the first aspect of the present disclosure, both the first semiconductor layer and the second semiconductor layer include the In element, and the In element content in the first semiconductor layer is lower than the In element content in the second semiconductor layer. Thus, by adjusting the In element content, the mobility in the first semiconductor layer can be lower than the mobility in the second semiconductor layer.

[0015] Optionally, the first semiconductor layer includes In, Ga, and Zn, and the In content is 30%-70%, the Ga content is 10%-40% of the metal element content included in the first semiconductor layer, and the Zn content is 10%-40% of the metal element content included in the first semiconductor layer; and / or, the second semiconductor layer includes In, Ga, and Zn, and the In content is 70%-90% of the metal element content included in the second semiconductor layer, the Ga content is 5%-20% of the metal element content included in the second semiconductor layer, and the Zn content is 5%-30% of the metal element content included in the second semiconductor layer.

[0016] Optionally, the thickness of the first semiconductor layer and / or the second semiconductor layer is 3 nm-20 nm.

[0017] In a specific embodiment of the first aspect of the present disclosure, the first active layer includes at least two carrier absorption layers, the second semiconductor layer is located between the substrate and the first semiconductor layer, and carrier absorption layers are provided between the second semiconductor layer and the substrate and between the second semiconductor layer and the first semiconductor layer.

[0018] In the above scheme, carrier absorption layers are arranged on both the upper and lower sides of the second semiconductor layer, so as to increase the carrier absorption efficiency; in addition, when the first thin film transistor is a dual-gate structure, carriers will be generated on both the upper and lower surfaces of the second semiconductor layer. Therefore, carrier absorption layers are arranged on both surfaces to absorb the carriers generated on both sides, thereby ensuring the performance stability of the first thin film transistor under the dual-gate design.

[0019] In another specific embodiment of the first aspect of the present disclosure, the second semiconductor layer, the carrier absorption layer and the first semiconductor layer are stacked in sequence on the substrate. In this way, the carrier absorption layer can absorb carriers on the surface of the second semiconductor layer facing the first semiconductor layer, and at the same time ensure that the second semiconductor layer has a higher conduction efficiency (lower threshold voltage), so that the length of the first active layer can be further reduced, so as to further reduce the size of the first thin film transistor.

[0020] In another specific embodiment of the first aspect of the present disclosure, the carrier absorption layer, the second semiconductor layer and the first semiconductor layer are stacked in sequence on the substrate. In this way, the carrier absorption layer can absorb carriers on the surface of the second semiconductor layer facing away from the first semiconductor layer, and at the same time ensure that the second semiconductor layer has a higher conduction efficiency (lower threshold voltage), so that the length of the first active layer can be further reduced, so as to further reduce the size of the first thin film transistor.

[0021] In a specific embodiment of the first aspect of the present disclosure, the first thin film transistor further includes a first source electrode and a first drain electrode, and the second thin film transistor further includes a second source electrode and a second drain electrode. The first source electrode and the first drain electrode are connected to a surface of the first semiconductor layer away from the second semiconductor layer, and the second source electrode and the second drain electrode are connected to a surface of the second active layer away from the substrate.

[0022] In a specific embodiment of the first aspect of the present disclosure, the second thin film transistor includes at least two gates, at least one gate is located between the second active layer and the substrate, and at least another gate is located on a side of the second active layer away from the substrate.

[0023] Optionally, the gate located on a side of the second active layer away from the substrate is connected to the second drain electrode.

[0024] Optionally, the second thin film transistor is a driving transistor.

[0025] A second aspect of the present disclosure provides a display panel, which includes the display substrate in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a schematic diagram of a planar structure of a display substrate provided in one embodiment of the present disclosure.

[0027] Figure 2 for Figure 1 A cross-sectional view of a partial structure of the display substrate along line MN.

[0028] Figure 3 A cross-sectional view of a partial structure of another display substrate provided in an embodiment of the present disclosure.

[0029] Figure 4 A cross-sectional view of a partial structure of another display substrate provided in an embodiment of the present disclosure.

[0030] Figure 5 A cross-sectional view of a partial structure of another display substrate provided in an embodiment of the present disclosure.

[0031] Figure 6 A cross-sectional view of a partial structure of another display substrate provided in an embodiment of the present disclosure.

[0032] Figure 7 A cross-sectional view of a partial structure of another display substrate provided in an embodiment of the present disclosure.

[0033] Description of reference numerals:

[0034] 1-display area; 2-non-display area;

[0035] 101 - substrate; 102 - lower gate insulating layer; 103 - upper gate insulating layer; 104 - interlayer dielectric layer;

[0036] 100 - first thin film transistor; 110 - first active layer; 111 - first semiconductor layer; 112 - second semiconductor layer; 113 - carrier absorption layer; 120 - first gate; 120A - first upper gate; 120B - first lower gate; 130A - first source electrode; 130B - first drain electrode;

[0037] 200 - a second thin film transistor; 210 - a second active layer; 220 - a second gate; 220A - a second upper gate; 220B - a second lower gate; 230A - a second source electrode; 230B - a second drain electrode;

[0038] 300 - light-emitting device; 310 - first electrode; 320 - light-emitting functional layer; 321 - first common layer; 322 - light-emitting layer; 323 - second common layer; 330 - second electrode.

[0039] 400-pixel defined layer. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of this specification to clearly and completely describe the technical solutions in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0041] In the design of narrowing the frame of the display product to improve the visual effect, the size of the electronic components in the frame area (non-display area described below) of the display product will be reduced, so that the frame size can be reduced. For example, the electronic components can be thin film transistors. In thin film transistors, the mobility and size (such as length) of the active layer will directly affect the stability of the thin film transistor. If the size of the active layer, such as the length, is reduced to reduce the size of the thin film transistor, then the mobility of the active layer needs to be increased. The increase in the mobility of the active layer and the reduction in the length will reduce the stability of the thin film transistor.

[0042] In addition, during the production of display products, thin film transistors in the display area and non-display area tend to be prepared in the same process to control production costs. Therefore, the mobility of at least part of the active layer of the thin film transistors in the two areas will be the same or similar, while the active layer of the thin film transistor in the display area needs to have a relatively low mobility to ensure the switching performance of the thin film transistor in the display area. That is, when the thin film transistors in the two areas can be prepared in the same process, the thin film transistors in the display area need to have low mobility, while the thin film transistors in the non-display area need to have relatively high mobility but also need to take into account performance stability. Therefore, the current technical problem is how to further narrow the border of the display product while ensuring the performance of the display product.

[0043] At least one embodiment of the present disclosure provides a display substrate and a display panel to at least solve the above technical problems. The display substrate includes a display area and a non-display area, and also includes a substrate and a first thin film transistor and a second thin film transistor located on the substrate. The first thin film transistor is located in the non-display area, the first thin film transistor includes a first active layer, the first active layer includes a first semiconductor layer stacked on the substrate, at least one second semiconductor layer and at least one carrier absorption layer, the mobility of the first semiconductor layer is lower than the mobility of the second semiconductor layer, and the carrier absorption layer is adjacent to the second semiconductor layer. The second thin film transistor is located in the display area, the first thin film transistor includes a second active layer, and the mobility of the second active layer is lower than the mobility of the second semiconductor layer. In the display substrate, by adding a second semiconductor layer with high mobility to the first active layer, the length of the first active layer can be reduced, and the reduction in the length of the first active layer can reduce the size of the first thin film transistor, which is beneficial to the narrowing design of the non-display area of ​​the display substrate (extremely narrow frame or frameless design), the high-mobility second semiconductor layer and the reduction in the length of the first active layer will cause the first active layer to be unstable (the first thin film transistor is easily turned on), and the carrier absorption layer can absorb part of the carriers generated in the second semiconductor layer to ensure the stability of the first thin film transistor; in addition, the mobility of the first semiconductor layer and the second active layer of the first active layer is relatively low, so that they can be prepared in the same process to simplify the process of the first thin film transistor and the second thin film transistor, thereby controlling the cost of the display substrate.

[0044] Below, the structures involved in the display substrate and the display panel according to at least one embodiment of the present disclosure are described in conjunction with the accompanying drawings. In these embodiments, a spatial rectangular coordinate system is established with the surface of the substrate in the display substrate (for example, or the display surface of the display panel) as a reference to describe the positions of various structures in the display substrate and the display panel. In the spatial rectangular coordinate system, the X-axis and the Y-axis are parallel to the substrate, and the Z-axis is perpendicular to the substrate.

[0045] like Figure 1 and Figure 2 As shown, the display substrate includes a display area 1 and a non-display area 2. A plurality of sub-pixels such as R, G, and B may be arranged in the display area. The physical structure of the sub-pixel may be a light-emitting device. For example, the light-emitting devices respectively located in the sub-pixels R, G, and B are respectively designed to emit red light (R), green light (G), and blue light (B).

[0046] like Figure 1 and Figure 2As shown, the physical structure of the display substrate includes a substrate 101 and a first thin film transistor 100 and a second thin film transistor 200 located on the substrate 101. The first thin film transistor 100 is located in the non-display area 2, and includes a first active layer 110. The first active layer 110 includes a first semiconductor layer 111, at least one second semiconductor layer 112 and at least one carrier absorption layer 113 stacked on the substrate 101. The mobility of the first semiconductor layer 111 is lower than that of the second semiconductor layer 112, and the carrier absorption layer 113 is adjacent to the second semiconductor layer 112. The second thin film transistor 200 is located in the display area 1, and includes a second active layer 210. The mobility of the second active layer 210 is lower than that of the second semiconductor layer 112.

[0047] For example, the display substrate includes a pixel driving circuit located in the display area 1, and the pixel driving circuit may include a plurality of transistors TFT (second thin film transistor 200), capacitors, etc., for example, formed in various forms such as 2T1C (i.e., 2 transistors (TFT) and 1 capacitor (C)), 3T1C or 7T1C. The pixel driving circuit is connected to a light emitting device (see the light emitting device 300 in the following embodiment) to control the switching state and light emitting brightness of the light emitting device.

[0048] For example, the display substrate may include a gate drive circuit located in the non-display area 2, and the gate drive circuit may include a plurality of transistors (first thin film transistors 100) to form a logic circuit, thereby controlling the signal input to the pixel drive circuit. The gate drive circuit will occupy the plane space of the non-display area 2, thereby limiting the width of the non-display area 2. If the size of the first thin film transistor 100 is reduced, the area occupied by the gate drive circuit will be reduced, so that the width of the non-display area 2 can be reduced, which is conducive to the extremely narrow frame design of the display substrate.

[0049] Adding a high-mobility second semiconductor layer 112 to the first active layer 110 can make the first active layer 110 more easily turned on (compared with only the first semiconductor layer 111), thereby allowing the first active layer 110 to be designed with a smaller length to further reduce the size of the first thin film transistor 100, and ultimately reduce the size of the gate drive circuit and the non-display area 2. If the first active layer 110 is only composed of a first semiconductor layer 111 and a second semiconductor layer 112 stacked together, then after the length of the first active layer 110 is reduced, due to the provision of the second semiconductor layer 112, the first active layer 110 will be easily turned on, making the performance of the first thin film transistor 100 unstable. In the scheme described in the embodiment of the present disclosure, a carrier absorption layer 113 is provided to absorb part of the carriers generated in the second semiconductor layer 112 to ensure the stability of the first thin film transistor 100. In addition, the mobility of the first semiconductor layer 111 and the second active layer 210 of the first active layer 110 is relatively low, so that they can be prepared in the same process to simplify the process of the first thin film transistor 100 and the second thin film transistor 200, thereby controlling the cost of the display substrate.

[0050] When preparing a high-mobility transistor and a low-mobility transistor under the same process conditions, if the threshold voltage of the low-mobility transistor is met, the high-mobility transistor is easily turned on; conversely, if the threshold voltage of the high-mobility transistor is met, the low-mobility transistor is easily forward biased, resulting in poor stability, thereby reducing the life of the display substrate. In the embodiment of the present disclosure, an active layer (first active layer 110) with a stacked structure is provided to obtain a high-mobility transistor (first thin film transistor 100), and a carrier absorption layer is added to the active layer to control its mobility, thereby solving the problem that the transistor is easily turned on.

[0051] In at least one embodiment of the present disclosure, it is possible to refer to Figure 2 , the first semiconductor layer 111 and the second active layer 210 are in the same layer and made of the same material. In this way, the first semiconductor layer 111 and the second active layer 210 can be simultaneously prepared in the same process to further simplify the preparation process of the first thin film transistor 100 and the second thin film transistor 200. It should be noted that under this design, because the mobility of the first semiconductor layer 111 is relatively low, and under the design requirement of reducing the size of the first active layer 110 to reduce the width of the non-display area 2, the first active layer 110 with the second semiconductor layer 112 having high mobility will be more easily turned on or have worse stability. Therefore, it is more necessary to provide the above-mentioned carrier absorption layer 113.

[0052] In at least one embodiment of the present disclosure, the length of the first active layer 110 may be greater than the length of the second active layer 210. In this way, the size of the first thin film transistor 100 may be designed to be smaller than the size of the second thin film transistor 200, and in the case where the first active layer 110 of the first thin film transistor 100 is designed to include the carrier absorption layer 113, the provision of the second semiconductor layer 112 will not affect the stability of the first thin film transistor 100, that is, by providing the carrier absorption layer 113, the adverse effects of reducing the first thin film transistor 100 are eliminated, so that the width of the non-display area 2 can be reduced while ensuring the performance of the display substrate, so as to facilitate the design of an extremely narrow frame of the display substrate.

[0053] In at least one embodiment of the present disclosure, the bandgap width of the carrier absorption layer 113 is greater than the bandgap width of the second semiconductor layer 112. The larger the bandgap width of the carrier absorption layer 113, the less it participates in conduction, and the easier it is to bind and absorb carriers (such as electrons). In this way, when the first active layer 110 is working, a part of the carriers generated in the second semiconductor layer 112 can enter the carrier absorption layer 113.

[0054] In the embodiments of the present disclosure, when the carrier absorption layer 113 can absorb the carriers in the second semiconductor layer 112, there is no further restriction on the specific material of the carrier absorption layer 113, and it can be designed according to actual process requirements. In the following, several material composition methods of the carrier absorption layer 113 are exemplified.

[0055] In some embodiments of the present disclosure, the second semiconductor layer 112 includes the In element, and the content of the In element in the carrier absorption layer 113 is zero, that is, the carrier absorption layer 113 does not include the In element. In this way, the band gap of the carrier absorption layer 113 can be much larger than that of the second semiconductor layer 112, and the carrier absorption layer 113 can be close to an insulating layer, thereby increasing the carrier absorption layer 113's ability to absorb carriers generated by the second semiconductor layer 112.

[0056] For example, when the carrier absorption layer 113 does not include the In element, the carrier absorption layer 113 includes at least one of Ga and Zn. For example, further, the carrier absorption layer 113 includes Ga and Zn, and the Ga content is 30%-100% of the metal element content included in the carrier absorption layer 113, and the Zn content is 0%-70% of the metal element content included in the carrier absorption layer 113. For example, the material of the carrier absorption layer 113 can be GZO.

[0057] It should be noted that in the embodiments of the present disclosure, when describing the content of an element, the content is the percentage of the number of atoms. For example, taking the case where the metal elements of the carrier absorption layer 113 only include Ga and Zn, the content of Ga is the ratio of the number of Ga atoms to the total number of Ga and Zn atoms.

[0058] In other embodiments of the present disclosure, the content of In in the second semiconductor layer 112 is greater than the content of In in the carrier absorption layer 113, that is, the content of In in the carrier absorption layer 113 is low. In this way, the band gap of the carrier absorption layer 113 can be ensured to be greater than the band gap of the second semiconductor layer 112, so as to ensure the absorption capacity of the carrier absorption layer 113 for the carriers generated by the second semiconductor layer 112.

[0059] For example, in the case where the carrier absorption layer 113 includes the In element, the carrier absorption layer 113 also includes at least one of Ga and Zn. For example, further, the carrier absorption layer 113 includes In, Ga and Zn, and the In content is 0%-30% of the metal element content included in the carrier absorption layer 113, the Ga content is 30%-100% of the metal element content included in the carrier absorption layer 113, and the Zn content is 0%-70% of the metal element content included in the carrier absorption layer 113. For example, the material of the carrier absorption layer 113 can be IGZO.

[0060] In at least one embodiment of the present disclosure, the thickness of the carrier absorption layer 113 may be 1nm-10nm, for example, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, 8nm, 8.5nm, 9nm, 9.5nm, etc. The specific thickness of the carrier absorption layer 113 may be set according to actual process requirements, and thus may not be limited to the above numerical range.

[0061] In at least one embodiment of the present disclosure, both the first semiconductor layer 111 and the second semiconductor layer 112 include the In element, and the content of the In element in the first semiconductor layer 111 is lower than the content of the In element in the second semiconductor layer 112. In this way, by adjusting the content of the In element, the mobility in the first semiconductor layer 111 can be lower than the mobility in the second semiconductor layer 112.

[0062] For example, the first semiconductor layer 111 includes In, Ga, and Zn, and the In content is 30%-70% of the metal element content included in the first semiconductor layer 111, the Ga content is 10%-40% of the metal element content included in the first semiconductor layer 111, and the Zn content is 10%-40% of the metal element content included in the first semiconductor layer 111; and / or, the second semiconductor layer 112 includes In, Ga, and Zn, and the In content is 70%-90% of the metal element content included in the second semiconductor layer 112, the Ga content is 5%-20% of the metal element content included in the second semiconductor layer 112, and the Zn content is 5%-30% of the metal element content included in the second semiconductor layer 112. For example, the material of the first semiconductor layer 111 and / or the second semiconductor layer 112 may be IGZO.

[0063] For example, the thickness of the first semiconductor layer 111 and / or the second semiconductor layer 112 is 3nm-20nm, and can also be 5nm, 8nm, 10nm, 12nm, 15nm, 18nm, etc. The specific thickness of the first semiconductor layer 111 and / or the second semiconductor layer 112 can be set according to actual process requirements, and thus is not limited to the above numerical range.

[0064] In the embodiment of the present disclosure, when the carrier absorption layer 113 is disposed on at least one side of the second semiconductor layer 112, there is no further restriction on the number and stacking relationship of the first semiconductor layer 111, the second semiconductor layer 112 and the carrier absorption layer 113 included in the first active layer 110, and they can be specifically disposed according to actual process requirements. In the following, several configurations of the first active layer 110 are exemplarily described.

[0065] In some embodiments of the present disclosure, it can be referred to again Figure 2 , the first active layer 110 includes at least two carrier absorption layers 113, the second semiconductor layer 112 is located between the substrate 101 and the first semiconductor layer 111, and the carrier absorption layer 113 is provided between the second semiconductor layer 112 and the substrate 101 and between the second semiconductor layer 112 and the first semiconductor layer 111. In this way, the carrier absorption layer 113 is provided on both the upper and lower sides of the second semiconductor layer 112, so that the absorption efficiency of the carriers can be increased; in addition, when the first thin film transistor 100 is a dual-gate structure, the upper and lower surfaces of the second semiconductor layer 112 will generate carriers, therefore, the carrier absorption layer 113 is provided on both surfaces to absorb the carriers generated on both sides, thereby ensuring the performance stability of the first thin film transistor 100 under the dual-gate design.

[0066] In other embodiments of the present disclosure, Figure 3As shown, in the first active layer 110, the second semiconductor layer 112, the carrier absorption layer 113 and the first semiconductor layer 111 are sequentially stacked on the substrate 101. In this way, the carrier absorption layer 113 can absorb the carriers on the surface of the second semiconductor layer 112 facing the first semiconductor layer 111, and at the same time ensure that the second semiconductor layer 112 has a higher conduction efficiency (lower threshold voltage), so that the length of the first active layer 110 can be further reduced, so as to further reduce the size of the first thin film transistor 100.

[0067] In other embodiments of the present disclosure, Figure 4 As shown, in the first active layer 110, the carrier absorption layer 113, the second semiconductor layer 112 and the first semiconductor layer 111 are sequentially stacked on the substrate 101. In this way, the carrier absorption layer 113 can absorb the carriers on the surface of the second semiconductor layer 112 facing away from the first semiconductor layer 111, and at the same time ensure that the second semiconductor layer 112 has a higher conduction efficiency (lower threshold voltage), so that the length of the first active layer 110 can be further reduced, so as to further reduce the size of the first thin film transistor 100.

[0068] In such Figure 2 and Figure 3 to Figure 4 In the preparation process of the display substrate shown, a high-mobility semiconductor material film layer and a carrier absorption material film layer can be formed on the substrate 101, and then the high-mobility semiconductor material film layer and the carrier absorption material film layer are subjected to a composition process to form a stacked second semiconductor layer 112 and a carrier absorption layer 113 in the non-display area 2; thereafter, a low-mobility semiconductor material film layer can be deposited, and the low-mobility semiconductor material film layer is subjected to a composition process to form a first semiconductor layer 111 and a second active layer 210 in the display area 1 and the non-display area 2, respectively.

[0069] In an embodiment of the present disclosure, the patterning process may be a photolithography patterning process, which may include, for example, coating a photoresist on a structure layer to be patterned, exposing the photoresist using a mask, developing the exposed photoresist to obtain a photoresist pattern, etching the structure layer using the photoresist pattern (optionally wet etching or dry etching), and then optionally removing the photoresist pattern. It should be noted that, in the case where the material of the structure layer includes a photoresist, the structure layer may be directly exposed through a mask to form a desired pattern.

[0070] In at least one embodiment of the present disclosure, Figure 4As shown, the first thin film transistor 100 may further include a first source electrode 130A and a first drain electrode 130B, and the second thin film transistor 200 may further include a second source electrode 230A and a second drain electrode 230B. The first source electrode 130A and the first drain electrode 130B are connected to a surface of the first semiconductor layer 111 away from the second semiconductor layer 112, and the second source electrode 230A and the second drain electrode 230B are connected to a surface of the second active layer 210 away from the substrate 101.

[0071] In the embodiments of the present disclosure, the thin film transistor also includes a gate, which corresponds to the channel region of the active layer. Thus, by controlling the voltage of the gate, the active layer can generate carriers and adjust the concentration of the generated carriers, thereby controlling the switching and conduction degree of the thin film transistor. Figure 4 and Figure 5 As shown, the first thin film transistor 100 may include a first gate electrode 120, the second thin film transistor 200 may include a second gate electrode 220, the orthographic projection of a portion of the channel region of the first active layer 110 on the substrate 101 is located within the orthographic projection of the first gate electrode 120 on the substrate 101 or coincides with the orthographic projection of the first gate electrode 120 on the substrate 101, and the orthographic projection of a portion of the channel region of the second active layer 210 on the substrate 101 is located within the orthographic projection of the second gate electrode 220 on the substrate 101 or coincides with the orthographic projection of the second gate electrode 220 on the substrate 101.

[0072] In some embodiments of the present disclosure, Figure 6 As shown, the first thin film transistor 100 and / or the second thin film transistor 200 includes a gate 120 / 220. For example, optionally, the second thin film transistor 200 is a driving transistor.

[0073] In some other embodiments of the present disclosure, please refer to Figure 4 and Figure 5 The first thin film transistor 100 and / or the second thin film transistor 200 includes at least two gates, thereby being at least configured as a dual-gate thin film transistor. Figure 4 and Figure 5 As shown, the first thin film transistor 100 includes a first upper gate 120A and a first lower gate 120B, the first lower gate 120B is located between the first active layer 110 and the substrate 101, and the first upper gate 120A is located on the side of the first active layer 110 away from the substrate 101; the second thin film transistor 200 includes a second upper gate 220A and a second lower gate 220B, the second lower gate 220B is located between the second active layer 210 and the substrate 101, and the second upper gate 220A is located on the side of the second active layer 210 away from the substrate 101.

[0074] In at least one embodiment of the present disclosure, it is possible to refer to Figure 5 , the gate electrode (second upper gate electrode 220A) located on the side of the second active layer 210 away from the substrate 101 is connected to the second drain electrode 230B. In this way, taking the second transistor 200 as a driving transistor as an example, in the pixel driving circuit, at a specific stage, the gate electrode of the driving transistor is connected to the drain electrode by controlling the relevant circuit. At this time, the driving transistor can be regarded as a diode, and its characteristics can be used for current control and voltage regulation in the circuit, etc., and can stably provide a suitable driving current for the light-emitting device to ensure the uniformity and stability of the light-emitting brightness of the light-emitting device; in addition, the threshold voltage of the driving transistor will fluctuate due to factors such as process deviation and temperature change, which will affect the display effect. By connecting the gate electrode to the drain electrode, the threshold voltage compensation can be performed using the characteristics of the driving transistor itself. For example, in the write operation stage of a pixel driving circuit, the gate electrode and the drain electrode of the driving transistor are short-circuited, so that the voltage of its source electrode is charged to the sum of the data voltage and the threshold voltage. In this way, in the subsequent light-emitting stage, the influence of the threshold voltage change on the driving current can be eliminated, thereby improving the quality of the display screen.

[0075] In at least one embodiment of the present disclosure, Figure 7 As shown, the display substrate further includes a plurality of light emitting devices 300 , which are physical light emitting structures of sub-pixels R, G, and B. The light emitting devices 300 are connected to the second thin film transistor 200 of the pixel driving circuit in the display substrate.

[0076] The light emitting device 300 may include an anode 310, a light emitting functional layer 320 and a cathode 330 sequentially stacked on an array substrate, and the light emitting functional layer 320 may include a first common layer 321, a light emitting layer 322 and a second common layer 323 sequentially stacked on the anode 310. For example, the first common layer 321 may include a hole injection layer, a hole transport layer, and may further include an electron blocking layer, etc. For example, the second common layer 323 may include an electron injection layer, an electron transport layer, and may further include a hole blocking layer, etc.

[0077] In at least one embodiment of the present disclosure, Figure 7 As shown, the display substrate may further include a pixel defining layer 400 , wherein the pixel defining layer 400 includes a plurality of pixel openings to define the positions of the light emitting devices 300 , for example, the light emitting layer of each light emitting device 300 is located in the pixel opening.

[0078] At least one embodiment of the present disclosure provides a display panel, which includes the display substrate in any of the above embodiments. For example, in an embodiment of the present disclosure, the display panel may also include a touch function layer, a polarizer, a lens layer, a cover plate and other functional structures located on the display side.

[0079] For example, in the embodiments of the present disclosure, the display panel may be any product or component having a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, or the like.

[0080] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of this disclosure can be achieved, and this document is not limited here.

[0081] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

[0082] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, etc. made within the spirit and principles of this specification should be included in the protection scope of this specification.

Claims

1. A display substrate, characterized in that: It includes a display area and a non-display area, and also includes: substrate; a first thin film transistor, located on the substrate and in the non-display area, wherein the first thin film transistor comprises a first active layer, the first active layer comprises a first semiconductor layer, at least one second semiconductor layer and at least one carrier absorption layer stacked on the substrate, the mobility of the first semiconductor layer is lower than the mobility of the second semiconductor layer, and the carrier absorption layer is adjacent to the second semiconductor layer; The second thin film transistor is located on the substrate and in the display area, wherein the second thin film transistor includes a second active layer, and the mobility of the second active layer is lower than the mobility of the second semiconductor layer.

2. The display substrate according to claim 1, characterized in that: The first semiconductor layer and the second active layer are in the same layer and made of the same material; Preferably, the length of the first active layer is greater than the length of the second active layer.

3. The display substrate according to claim 1 or 2, characterized in that: The bandgap of the carrier absorption layer is greater than the bandgap of the second semiconductor layer.

4. The display substrate according to claim 3, characterized in that: The second semiconductor layer includes In element, and the content of In element in the carrier absorption layer is zero. Preferably, the carrier absorption layer includes at least one of Ga and Zn. Further preferably, the carrier absorption layer includes Ga and Zn, and the Ga content is 30%-100% of the content of the metal element included in the carrier absorption layer, and the Zn content is 0%-70% of the content of the metal element included in the carrier absorption layer; or The In element content in the second semiconductor layer is greater than the In element content in the carrier absorption layer. Preferably, the carrier absorption layer further comprises at least one of Ga and Zn. Further preferably, the carrier absorption layer comprises In, Ga and Zn, and the In content is 0%-30% of the metal element content included in the carrier absorption layer, the Ga content is 30%-100% of the metal element content included in the carrier absorption layer, and the Zn content is 0%-70% of the metal element content included in the carrier absorption layer. Preferably, the carrier absorption layer has a thickness of 1 nm-10 nm.

5. The display substrate according to claim 3, characterized in that: The first semiconductor layer and the second semiconductor layer both include In element, and the content of In element in the first semiconductor layer is lower than the content of In element in the second semiconductor layer; Preferably, the first semiconductor layer comprises In, Ga, and Zn, and the content of In is 30%-70% of the content of the metal elements included in the first semiconductor layer, the content of Ga is 10%-40% of the content of the metal elements included in the first semiconductor layer, and the content of Zn is 10%-40% of the content of the metal elements included in the first semiconductor layer; and / or The second semiconductor layer includes In, Ga, and Zn, and the content of In is 70%-90% of the content of the metal elements included in the second semiconductor layer, the content of Ga is 5%-20% of the content of the metal elements included in the second semiconductor layer, and the content of Zn is 5%-30% of the content of the metal elements included in the second semiconductor layer; Preferably, the thickness of the first semiconductor layer and / or the second semiconductor layer is 3nm-20nm.

6. The display substrate according to claim 1 or 2, characterized in that: The first active layer includes at least two carrier absorption layers, the second semiconductor layer is located between the substrate and the first semiconductor layer, and The carrier absorption layer is disposed between the second semiconductor layer and the substrate and between the second semiconductor layer and the first semiconductor layer.

7. The display substrate according to claim 1 or 2, characterized in that: The second semiconductor layer, the carrier absorption layer and the first semiconductor layer are stacked in sequence on the substrate; or The carrier absorption layer, the second semiconductor layer and the first semiconductor layer are sequentially stacked on the substrate.

8. The display substrate according to claim 1 or 2, characterized in that: The first thin film transistor also includes a first source electrode and a first drain electrode, and the second thin film transistor also includes a second source electrode and a second drain electrode, the first source electrode and the first drain electrode are connected to a side surface of the first semiconductor layer away from the second semiconductor layer, and the second source electrode and the second drain electrode are connected to a side surface of the second active layer away from the substrate.

9. The display substrate according to claim 8, characterized in that: The second thin film transistor comprises at least two gates, at least one of the gates is located between the second active layer and the substrate, and at least another of the gates is located on a side of the second active layer away from the substrate; Preferably, the gate located on a side of the second active layer away from the substrate is connected to the second drain electrode; Preferably, the second thin film transistor is a driving transistor.

10. A display panel, characterized in that: A display substrate comprising the display substrate according to any one of claims 1 to 9.

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