Computing device, method for load allocation of such a computing device, and computing system

Abstract

The invention relates to a computing device (1) comprising a processor unit (2) having a plurality of computing cores (2.1) working in cooperation and a plurality of storage elements (2.2) assigned to the computing cores (2.1), and having at least one input interface (3) for receiving information to be processed by the computing cores (2.1) and at least one output interface (4) for outputting information processed by the computing cores (2.1). The computing device according to the invention is characterized in that the storage elements (2.2) are formed by two-port RAM, each processor core (2.1) has exactly two inputs (E) for receiving information and exactly one output (A) for outputting information, each input (E) and each output (A) being each formed by one storage element (2.2), the physical distances (d) starting from the respective processor core (2.1) to the storage elements (2.2) connected to the processor core (2.1) are equidistant.

Description

Technical Field

[0001] The invention relates to a computing device of the type defined in more detail in the preamble of claim 1, as well as a method for load distribution of such a computing device and a computer system having such a computing device. Background Art

[0002] The processor is an essential component of computer equipment. Processors are available in various specifications, for example as central processing units for personal computers, also called central processing units or CPUs for short, or as integrated circuits in the form of microprocessors and microcontrollers in embedded systems. CPUs are characterized by relatively few but computationally powerful computing cores or processor cores. This makes it possible to execute relatively complex and computationally intensive programs. Parallelization of program flows is also possible. CPUs are designed to solve a large number of different types of tasks and problems.

[0003] The processor is also implemented in the form of a so-called graphics processing unit (GPU for short). Compared with the CPU, modern GPUs are characterized by computing cores in the order of thousands of units per chip. These are relatively weak computing cores that are optimized for solving a few special tasks. That is, GPUs are mainly used to calculate matrices or tensors, for example for graphic calculations or to provide / accelerate artificial intelligence. GPUs are therefore particularly suitable for parallel processing tasks.

[0004] The provision of information to be processed by the processor core of a graphics processor, in particular the connection to the CPU, is usually carried out via a bus system such as PCI Express (PCIe). The processing of the corresponding information by the processor core of the graphics processor requires caching of this information before, during and after processing. For this purpose, various storage elements are known, which are located inside and outside the processor (but arranged on the same circuit board).

[0005] Typically, these storage elements are arranged in a two-dimensional structure inside or on the graphics processor. Here, the individual components are usually arranged at right angles. This results in different physical distances between the processor core and the interface for information transmission (e.g., the above-mentioned storage elements, bus connections and / or other processor cores). Therefore, it takes more time to send information via a correspondingly longer data line. As a result, the delay increases, which makes the graphics processor work less efficient.

[0006] A DDR4-SSD dual-port DIMM device is known from US2015 / 0255130 A1. This is a device that can be used as both a working memory and a main memory, i.e. a mass storage device such as a hard disk or an SSD. The device can be connected to the bus system of the motherboard via a RAM slot or a PCIe slot. Since the storage element used is implemented as a dual-port storage element, it is possible to write and read access to the device simultaneously by two host systems. The storage elements are also arranged along lines that are parallel or orthogonal to each other, i.e. in a square or rectangular shape.

[0007] Furthermore, it is common practice for a person skilled in the art to use a computing unit with a multi-core processor to process multiple tasks in parallel and thus in a particularly efficient manner, as evidenced by the following: Multi-core processor. From: Wikipedia, the free encyclopedia. Edited: September 4, 2022. URL: https: / / en.wikipedia.org / w / index.php?title=Multi-core_processor&oldid=1108514820.

[0008] The connection of storage elements to the individual processor cores of a processor in a conventional manner is known to those skilled in the art, for example by means of: CPU cache. Source: Wikipedia, the free encyclopedia. Edit status: September 30, 2022. URL: https: / / en.wikipedia.org / w / index.php?title=CPU_cache&oldid= 1113266567 That is, it is common practice to set up a multi-level cache. Here, each processor core is assigned its own L1 cache. Multiple processor cores can share an L2 or L3 cache. The corresponding cache can be implemented as a multi-port cache.

[0009] Furthermore, US 2009 / 0 216 924 A1 discloses a composite system exhibiting processor cores arranged in the form of a hexagonal honeycomb.

[0010] Such an arrangement of a processor core is also known from US 2020 / 0 243 154 A1. Summary of the invention

[0011] The object of the present invention is to provide an improved computing device which is distinguished by an increased computing efficiency.

[0012] This object is achieved according to the invention by a computing device having the features of claim 1. Advantageous embodiments and developments as well as a method for load distribution of such a computing device and a computer system having such a computing device result from the dependent claims.

[0013] A computing device of the above type, comprising a processor unit having a plurality of processor cores working in coordination and a plurality of storage elements assigned to the processor cores, and having at least one input interface for receiving information to be processed by the processor cores and at least one output interface for outputting information processed by the processor cores, is improved according to the present invention in the following manner: the storage elements are composed of a dual-port RAM, each processor core having exactly two input terminals for receiving information and exactly one output terminal for outputting information, and being connected to exactly three storage elements, wherein the first two of the three storage elements each constitute one of the two input terminals of the processor core, and the third storage element constitutes the output terminal of the processor core, the three storage elements are arranged in a star shape around the processor core, each forming an angle of 120° with respect to each other, and the physical distance from the corresponding processor core to the storage element connected to the processor core is equidistant.

[0014] The idea of ​​the computing device according to the invention is to configure the physical distances of the memory connections of the respective processor cores to be identical, so that the respective processor cores are at equal distances from the memory elements connected to them. The length of time required to provide information to be processed to a processor core or to extract processed information from a processor core is therefore the same for each processor core. This increases the efficiency of the processor unit, since information is thus transferred from processor core to processor core at the same speed, so that a processor core that receives information from two preceding processor cores in the direction of the data flow does not have to wait for information sent by the second processor core after receiving information from the first processor core, since both information arrive at the same time. This makes particularly fast data processing possible.

[0015] The processor unit can be, for example, a central processing unit, CPU for short, or a graphics processor, GPU for short. The computing device is a corresponding chip or a printed circuit board or circuit board, such as a card, such as a graphics card. The bottom surface of the processor unit can be square or rectangular. Any polygonal surface shapes are also taken into account. In particular, the processor cores are implemented identically and particularly preferably have the same geometric design, i.e. the same geometry and the same area.

[0016] The computing device can be integrated in a superordinate computer system. The computing device and / or other components of the corresponding computer system can also have direct storage access rights, i.e. write and / or read access rights, to the input interface and / or output interface. This is also referred to as direct memory access (DMA).

[0017] Depending on the implementation, a single processor core can now execute a fixed program, for example a program read from a read-only memory (ROM), which can be part of the computing device or also part of a superordinate computer system, or the processor core can read and interpret information from a random access memory (RAM), thereby executing the code contained in the RAM as instructions.

[0018] Since each processor core has two inputs and one output stage, it is straightforward to execute each function to be processed in parallel, since each processor core can also read two operands simultaneously.

[0019] According to the invention, the respective processor cores and the storage elements forming their two inputs and their outputs are arranged in a star shape on the processor unit, wherein the angle between the respective storage elements is 120 degrees. In this way, the processor cores can be distributed particularly efficiently on the processor unit. In this way, a symmetrical arrangement of the processor cores can be achieved while maintaining a spatial angle of 120 degrees between the storage elements, and the physical distance between the respective storage elements and the processor cores can be implemented particularly easily as equidistant.

[0020] Preferably, six processor cores are arranged in the form of a hexagonal honeycomb on the processor unit. This makes it possible to maintain the spatial angle of 120 degrees with the corresponding storage element for each of these processor cores in a simple and reliable manner, and at this time, the distances between the processor cores and the storage elements are implemented to be equal. Another special advantage is that the distances of the corresponding data lines can be shortened compared to the embodiments known in the prior art, in particular the distance of the longest data path between the processor core and the storage element assigned to the processor core in the case of a rectangular arrangement. As a result, delays in data processing can be further reduced.

[0021] A single processor core in the same hexagonal honeycomb can at the same time also be part of a hexagonal honeycomb adjacent to the hexagonal honeycomb. The distribution of the processor cores on the processor unit can be compared to the honeycomb structure in a honeycomb. Particularly preferably, the processor unit also has a hexagonal honeycomb cross-sectional shape. This allows the processor unit to be implemented particularly compactly on the one hand, and on the other hand, sufficient spacing can be maintained between the individual processor cores, thereby providing a sufficiently large heat dissipation area. This improves the thermal management of the computing device, thereby being able to save particularly large and complex cooling devices. It is therefore feasible to cool by passive or simple active cooling devices.

[0022] An advantageous design of the computing device further provides that the at least one input interface and the at least one output interface are each formed by a dual-port RAM, and the at least one input interface forms the input end of the input core arranged at the periphery of the interconnection chain of the processor core, and the at least one output interface forms the output end of the output core arranged at the periphery of the interconnection chain. The input interface and the output interface can be read or written by the processor unit. In addition, other components of the computing device or other components of the computer system above the computing device can have write and / or read access rights to the input interface and the output interface. Since it is implemented as a dual-port RAM, it is feasible here that write access and read access are performed simultaneously by the processor unit and other components corresponding thereto.

[0023] Preferably, the at least one input interface and the at least one output interface are arranged on two opposite sides of the processor unit. In order to complete the task, i.e., to process the information, for example by executing a program, the information is processed by the processor core of the processor unit. For this purpose, the information is provided to the processor unit via the input interface and the processed information is output at the output interface. This involves a directed graph along which the information is transferred through the interconnected chains of the processor cores. If the input interface and the output interface are arranged at two end points of the directed graph, a particularly simple directed graph can be constructed, which can therefore be traversed quickly.

[0024] Another advantageous embodiment of the computing device also provides that the computing device has at least one second input interface and / or at least one second output interface. Information can thus be fed in or out at a plurality of locations in the data flow graph provided by the processor core. This simplifies the parallelization of a plurality of tasks to be processed by the processor unit. It is also possible to access further input interfaces or output interfaces via DMA.

[0025] According to another advantageous design of the computing device, the at least one second input interface and / or the at least one second output interface are arranged on a side of the processor unit that is different from the side where the first input interface and the first output interface are located. The computing device structure according to the present invention allows information to be transmitted not only in one dimension along a line, but also in two dimensions through the interconnected chain of processor cores, i.e., the corresponding directed data flow graph. Then, information can also be introduced into the data flow graph or exported from the data flow graph, for example, at the center of the corresponding data flow graph or other intermediate positions. On the one hand, this makes it possible to execute particularly complex programs, and on the other hand, it makes large-scale parallelization possible, because multiple tasks that can be solved in a relatively simple manner only need to be distributed to fewer processor cores, so it is not necessary to bind all processor cores of the data flow graph to the same task. As a result, the corresponding other processor cores are available for solving other tasks.

[0026] Within the interconnected chain of processor cores in a processor unit, "islands" of connected processor cores can thus be formed, with different tasks being processed on each island. Due to the additional laterally arranged input and output interfaces, it is possible for each island to feed information in and out in an individualized manner. These islands can also be referred to as groups or clusters.

[0027] The geographical distribution of the processor cores in the processor unit as islands is carried out according to the complexity of the respective task. Complex tasks requiring relatively many processor cores can be geographically transferred to the central area of ​​the processor unit, because the connections to the input and output interfaces are farther away here, which is particularly suitable for tasks that do not require new information to be fed into the processor chain for a longer time or for a large number of computing operations and only need to provide results at the end. Simpler tasks can then be correspondingly distributed to the following processor islands, which are more likely to be distributed in the peripheral areas of the processor unit. This makes it possible to easily import and export information via the above-mentioned input and output interfaces.

[0028] An advantageous development of the computing device according to the invention also provides that all processor cores operate at essentially the same clock frequency / tick. This makes it possible to further increase the efficiency of the computing device according to the invention. As described above, the corresponding data lines for transmitting information in the interconnection chain of the processor cores have the same length, so that information is exchanged at the same speed between the processor cores. If the time required for processing information by the processor cores themselves when solving a task is now equal due to the essentially identical clock cycles, the delays in the data processing by the processor unit can be further reduced. That is, if a processor core requires information from two preprocessor cores, then the two preprocessor cores receive the input data simultaneously, process them simultaneously, and simultaneously provide these data to the processor core for further processing.

[0029] Preferably, the processor cores are adapted to switch between a sleep mode and an active mode, wherein the respective processor core does not process information in the sleep mode and is able to process information in the active mode. The energy efficiency of the processor unit can thereby be improved. Depending on the complexity of the task to be processed, it may be necessary to involve a certain number of processor cores in the task. If involving more processor cores does not yield runtime benefits or other tasks do not need to be solved, individual processor cores of the processor unit can be put into sleep mode. Since these processor cores are no longer "running", the energy consumption of the processor unit can be reduced.

[0030] According to the present invention, a method for load distribution of the aforementioned computing device provides that the compiler determines a data flow graph available by linking the processor cores of the processor unit, and distributes the load distribution of the information to be processed by the processor cores to solve the task to each processor core by applying pattern matching according to the determined data flow graph. It is thereby possible to achieve a particularly uniform and therefore efficient load distribution. Therefore, the program can be executed with a particularly short runtime, which further improves the efficiency of the computing device of the present invention. Since each processor core is allocated two inputs and one output, when the processor cores are arranged in a hexagonal honeycomb, the two inputs of two adjacent processor cores can partially overlap. The compiler takes this fact into account when determining the data flow graph, thereby avoiding information transfer directed in one direction through the data flow graph. Since each storage element is constructed as a dual-port RAM, it is feasible to read or write from both sides. Therefore, two processor cores connected to each other via the input can be used to transfer information in a cyclic manner / in a circle in the interconnected chain of the processor cores. This further improves the efficiency of the computing device of the present invention, because unused processor cores are not omitted when processing information.

[0031] According to the invention, the aforementioned computing device is integrated into a computer system. The computer system may be, for example, a personal computer, an embedded system or other information technology system. The computing device of the invention may be implemented, for example, as a pluggable card for a personal computer motherboard. As plug-in connections and corresponding information transmission protocols, all common variants are applicable. This is, for example, a PCIe interface. The computer system may also be constructed by a vehicle structure or by a computing unit integrated in the vehicle. The computing device of the invention may be used, in particular in vehicle-related situations, for example, when using artificial neural networks, to accelerate artificial intelligence. It is therefore possible to incorporate the computing device of the invention into a vehicle to provide automated or even autonomous driving functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Other advantageous technical solutions of the computing device according to the present invention are also reflected in the embodiments described in detail below with reference to the accompanying drawings.

[0033] in:

[0034] Figure 1 A schematic diagram showing a processor core having its respective input and output terminals formed by a dual-port RAM;

[0035] Figure 2 A partial schematic diagram showing a plurality of processor cores interconnected in a hexagonal honeycomb pattern into an interconnected chain; and

[0036] Figure 3A schematic diagram showing a computing device according to the present invention. DETAILED DESCRIPTION

[0037] Figure 1 The computing device 1 of the present invention is explained as follows Figure 3 The relative arrangement according to the invention of the processor core 2.1 and the memory element 2.2 of the processor unit 2 is shown. The exact shapes of the processor core 2.1 and the memory element 2.2 are to be understood here only as symbolic. That is, the processor core 2.1 can also have a geometric shape different from a circle and the memory element 2.2 can also have a geometric shape different from a rectangle.

[0038] Each processor core 2.1 of the processor unit 2 is connected to exactly three dual-port RAMs. Two of these storage elements 2.2 form inputs E for feeding information into the respective processor core 2.1, and one storage element 2.2 forms output A for outputting information processed by the processor core 2.1.

[0039] As from Figure 1 As can be seen in FIG. 1 , the storage elements 2.2 are each arranged in a star shape around the respective processor core 2.1 at an angle α of 120°. The distance d between the processor core 2.1 and the respective storage element 2.2 is implemented as equidistant. Figure 1 In each storage element in the storage element 2.2 shown in FIG, the distance d is equal. In addition, according to Figure 1 In the embodiment shown in FIG. 1 , all storage elements 2.2 have the same length, in particular they have the same geometric design. This enables the processor core 2.1 and the storage element 2.2 to be arranged on the processor unit 2 in the same manner. Figure 2 Symmetrical arrangement of the particular pattern shown in .

[0040] Figure 2 Therefore, the arrangement of a plurality of the above-mentioned processor cores 2.1 and storage elements 2.2 is explained. That is, the processor cores 2.1 and storage elements 2.2 are interconnected in the form of a hexagonal honeycomb to establish a data flow graph. The advantage of this structure is that the length of the data line between each storage element 2.2 and the adjacent processor core 2.1 is equal, so that the same length of time is always required to transfer information from the storage element 2.2 to the processor core 2.1. In addition, the processor core 2.1 can read two different information, such as different variables, at the same time, which is conducive to parallelization, that is, processing different tasks at the same time.

[0041] In particular, all processor cores 2.1 operate at the same clock frequency, which makes data processing more efficient. In this way, in particular, information is provided to each processor core 2.1 at the same time and processed by them at the same time. Accordingly, the processor cores 2.1 provide information simultaneously via their respective output terminals A, and this information can be provided simultaneously to the subsequent processor cores 2.1 via their input terminals E. In this way, the corresponding network or data flow graph formed by such a connection of the processor cores 2.1 can be traversed in a particularly efficient manner.

[0042] The network consisting of processor cores 2.1 and storage elements 2.2 is further extended with a corresponding design. Figure 2 In the diagram, the data flow direction at the corresponding output A is indicated by a small arrow in order to better illustrate which output A is assigned to which processor core 2 . 1 . For the sake of clarity, not all elements are provided with reference numerals.

[0043] Figure 3 Here, the computing device 1 is shown again in a more comprehensive manner. Only the essential components are shown here. Typical components, such as a memory controller, are not shown. Figure 3 The input interface 3 is arranged on the first side S1 and the output interface 4 is arranged opposite the processor unit 2 on the second side S2. The input interface 3 and the output interface 4 are in particular also formed by a dual-port RAM. This makes it possible to read and write to the input interface 3 and the output interface 4 simultaneously both by the processor unit 2 and by a superordinate computing unit of the computing device 1. The superordinate computing unit or computer system can access the interfaces, for example Figure 3 , the input interface 3 has direct memory access or direct memory access (DMA) rights. In order to control the computing device 1, the corresponding computer system does not have to go through a main processor such as a CPU, but can directly provide information without going through the CPU of the computing device 1. This further improves the runtime of the task to be executed, that is, the program.

[0044] The processor cores 2.1 arranged at the edge, ie at the periphery, of the interconnection chain of the processor cores 2.1 can be arranged as follows: Figure 3 2.2 are connected directly to the corresponding input interface 3 or output interface 4. The processor core 2.1 directly connected to the input interface 3 is also called input core 2.E, and the processor core 2.1 directly connected to the output interface 4 is called output core 2.A. Any number of processor cores 2.1 can be connected to the input interface 3 or output interface 4, for example, one, two, three, four or even more processor cores 2.1 can be connected to each.

[0045] Furthermore, the computing device 1 may have at least one second input interface 3.2 and / or at least one second output interface 4.2. In particular, the second input interface 3.2 and the second output interface 4.2 are arranged at sides S3, S4 that are different from the first side S1 and the second side S2. A plurality of second input interfaces 3.2 or output interfaces 4.2 may also be provided on the same side. This facilitates providing or exporting information in a central area of ​​the interconnection chain of the processor cores 2.1. The interconnection chain of the processor cores 2.1 is also connected to the corresponding second input interface 3.2 and the second output interface 4.2 (not shown) via the input core 2.E and the output core 2.A.

Claims

1. A computing device (1), comprising a processor unit (2), the processor unit having a plurality of processor cores (2.1) working in coordination and a plurality of storage elements (2.2) allocated to the processor cores (2.1), and having at least one input interface (3) for receiving information to be processed by the processor cores (2.1) and at least one output interface (4) for outputting information processed by the processor cores (2.1), characterized in that: The storage element (2.2) is formed by a dual-port RAM, each processor core (2.1) has exactly two input terminals (E) for receiving information and exactly one output terminal (A) for outputting information, and is connected to exactly three storage elements (2.2), the first two of the three storage elements (2.2) each forming one of the two input terminals (E) of the processor core (2.1), the third storage element (2.2) forming the output terminal (A) of the processor core (2.1), the three storage elements (2.2) are arranged in a star shape around the processor core (2.1) at an angle (α) of 120° to each other, and the physical distance (d) from the corresponding processor core (2.1) to each storage element (2.2) connected to the processor core (2.1) is equidistant.

2. The computing device (1) according to claim 1, It is characterized in that Six processor cores (2.1) are arranged in each case in the form of a hexagonal honeycomb on the processor unit (2).

3. The computing device (1) according to claim 1 or 2, It is characterized in that The at least one input interface (3) and the at least one output interface (4) are each formed by a dual-port RAM, the at least one input interface (3) forming an input end (E) of an input core (2.E) arranged at the periphery of the interconnection chain in the processor core (2.1), and the at least one output interface (4) forming an output end (A) of an output core (2.A) arranged at the periphery of the interconnection chain.

4. The computing device (1) according to any one of claims 1 to 3, It is characterized in that The at least one input interface (3) and the at least one output interface (4) are arranged on two opposite sides (S1, S2) of the processor unit (2).

5. The computing device (1) according to any one of claims 1 to 4, It is characterized in that At least one second input interface (3.2) and / or at least one second output interface (4.2) are provided.

6. The computing device (1) according to claim 5, It is characterized in that The at least one second input interface (3.2) and / or the at least one second output interface (4.2) are arranged on a side (S3, S4) of the processor unit (2) which is different from the side on which the first input interface (3) and the first output interface (4) are located.

7. The computing device (1) according to any one of claims 1 to 6, It is characterized in that All processor cores (2.1) operate at substantially the same clock frequency.

8. The computing device (1) according to any one of claims 1 to 7, It is characterized in that The processor core (2.1) is adapted to switch between a sleep mode, in which the processor core (2.1) does not process information, and an active mode, in which the processor core (2.1) is capable of processing information.

9. A method for load distribution of a computing device (1) according to any one of claims 1 to 8, It is characterized in that The compiler determines a data flow graph available by linking the processor cores (2.1) of the processor unit (2), and distributes the load of information to be processed by the processor cores (2.1) in order to solve a task to each processor core (2.1) by applying pattern matching based on the determined data flow graph.

10. A computer system, It is characterized in that At least one computing device (1) according to any one of claims 1 to 8 is provided.

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