Package architecture with die-to-die coupling using glass interposer

Abstract

An embodiment of a microelectronic assembly includes: an interposer structure of glass; comprising an organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of IC dies. A first IC die of the plurality of IC dies is coupled to the substrate through a first interconnect, a second IC die of the plurality of IC dies is embedded in an organic dielectric material of the substrate, the second IC die is coupled to the first IC die through a second interconnect, the second IC die is coupled to a first side of the interposer structure through a third interconnect, and a third IC die of the plurality of IC dies is coupled to a second side of the interposer structure through a fourth interconnect, the second side of the interposer structure being opposite the first side of the interposer structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the priority date benefit of U.S. application serial number 17 / 937,519, filed on October 3, 2022. Technical Field

[0002] The present disclosure relates to techniques, methods, and apparatuses involving a packaging architecture with die-to-die coupling using a glass interposer. Background Art

[0003] Electronic circuits are called integrated circuits (ICs) when they are usually manufactured on a wafer of semiconductor material such as silicon. Wafers with such ICs are typically cut into many individual dies. The dies may be packaged into an IC package containing one or more dies along with other electronic components such as resistors, capacitors, and inductors. The IC package may be integrated into an electronic system such as a consumer electronic system or a server such as a mainframe. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The embodiments will be easily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate the description, similar reference numerals designate similar structural elements. By way of example and not by way of limitation, the embodiments are illustrated in the figures of the accompanying drawings.

[0005] Figure 1A is a schematic cross-sectional view of an example microelectronic assembly according to some embodiments of the present disclosure.

[0006] Figure 1B yes Figure 1A Schematic top view of a microelectronic assembly.

[0007] Figure 2 is a schematic cross-sectional view of a portion of an example microelectronic assembly according to some embodiments of the present disclosure.

[0008] Figure 3 is a schematic cross-sectional view of a portion of an example microelectronic assembly according to some other embodiments of the present disclosure.

[0009] Figure 4 is a schematic cross-sectional view of a portion of another example microelectronic assembly according to some other embodiments of the present disclosure.

[0010] Figure 5A is a schematic cross-sectional view of a portion of a passive component in an example microelectronic assembly according to some other embodiments of the present disclosure.

[0011] Figure 5B yes Figure 5A Schematic top view of a portion of a microelectronic assembly.

[0012] Figure 6 is a schematic cross-sectional view of a portion of a passive component in an example microelectronic assembly according to some other embodiments of the present disclosure.

[0013] Fig. 7A is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure.

[0014] Figure 7B yes Fig. 7A Schematic top view of a microelectronic assembly.

[0015] Figure 8 is a simplified flow chart illustrating various operations that may be associated with fabricating an example microelectronic assembly according to various embodiments.

[0016] Fig. 9 is a cross-sectional view of a device package including one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0017] Fig.10 is a cross-sectional side view of a device assembly including one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0018] Fig.11 is a block diagram of an example computing device including one or more microelectronic components according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0019] Overview For the purpose of explaining the IC packaging described herein, it is important to understand the phenomena that may come into play during the assembly and packaging of the IC. The following basic information may be considered as a basis for properly explaining the present disclosure. This information is provided for explanation purposes only, and accordingly should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

[0020] As Moore's Law approaches its natural limit, supercomputing faces inherent physical problems as it moves toward zettascale systems. Zettascale computing aims to create 1,000 times the current level of today's computing in or around the second half of a decade to take advantage of both consumer and enterprise high demand for computing resources and enable data-hungry applications such as artificial intelligence, machine learning, and the like. Zettascale supercomputers target computing performance on the order of one zettaflops. One zettaflops is equal to 1,000 exaflops or 1 thousand to the seventh power floating-point operations per second. Although there have been advances in semiconductor processing and logic design that have allowed for an increase in the amount of logic circuits that can be included in processors and other IC devices, signal speeds reach physics-based bottlenecks to achieve zettascale performance, for example, from inherent limitations in materials used for signal propagation (such as copper in dielectrics), heat transfer challenges from high-intensity computing, and power delivery constraints to power thousands of simultaneous computations in multiple processors.

[0021] Many processors in current supercomputers and other processing devices already have multiple cores monolithically integrated on a single die. Generally, these types of monolithic ICs are also described as planar, because they take the form of a flat surface and are typically built on a single silicon wafer made of a single crystal silicon ingot (boule). The typical manufacturing process for such a monolithic IC is called a planar process, allowing photolithography, etching, thermal diffusion, oxidation and other such processes to appear on the surface of the wafer, so that active circuit elements (e.g., transistors and diodes) are formed on the planar surface of the silicon wafer. Current technology allows hundreds or thousands of such active circuit elements to be formed on a single die, so that many logic circuits can be enabled thereon. In such a monolithic die, the manufacturing process must be optimized equally for all circuits, resulting in a compromise between different circuits. In addition, due to the limitation that the circuit must be placed on a planar surface, some circuits are further away from some other circuits, resulting in a decreased performance such as a longer delay. The manufacturing yield may also be severely affected, because if even one circuit fails, the entire die may have to be discarded.

[0022] Therefore, the trend in the processor industry is to move toward disaggregation, thereby using multiple known good small chips (smaller size IC dies) made using different manufacturing technologies and assembling them together into a microprocessor using new bonding technologies. Smaller dies are part of the components of interconnected dies that form a complete IC in terms of application and / or function, such as memory chips, microprocessors, microcontrollers, commodity ICs (e.g., chips for repetitive processing routines, simple tasks, special ICs, etc.) and systems on chip (SOCs). In other words, individual dies are connected to create the functions of a monolithic IC. By using separate dies, each individual die can be optimally designed and manufactured for a specific function. For example, a processor core containing logic circuits may be targeted for performance, and thus may require a layout that is very optimized for speed. This has different manufacturing requirements compared to a USB controller, which is built to meet certain universal serial bus (USB) standards, rather than built for processing speed. Therefore, by separating different parts of the overall design into different dies that are each optimized in design and manufacturing, the overall yield and cost of the combined die solution can be improved.

[0023] The connectivity between these tube cores can be realized in many ways. For example, in 2.5D packaging solutions, silicon interposers and through-silicon vias (TSVs) connect tube cores at silicon interconnect speeds in a minimum footprint. In a certain such architecture, bridge tube cores are also used to provide lateral connectivity between adjacent IC tube cores. In another example, a silicon bridge embedded below the edge of two interconnected tube cores promotes electrical coupling between them. In a three-dimensional (3D) architecture, tube cores are stacked one on top of another, thereby creating a smaller footprint overall. Typically, TSVs and bumps based on high pitch solder (e.g., C2 interconnects) are used to achieve electrical connectivity and mechanical coupling in this 3D architecture. Bridges and 3D stacking architectures can also be combined to allow the top package chip to use bridges horizontally and vertically to use through-mold vias (TMVs) that are typically larger than TSVs to communicate with other chips. However, these current interconnect technologies use silicon-based interposers or organic interposers, and silicon-based interposers may be costly, and organic interposers may be prone to errors and are not suitable for fine pitch interconnects.

[0024] Accordingly, embodiments described herein implement a microelectronic assembly comprising: an interposer structure of glass; a substrate comprising an organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of IC dies. A first IC die of the plurality of IC dies is coupled to the substrate via a first interconnect, a second IC die of the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is coupled to the first IC die via a second interconnect, the second IC die is coupled to the first side of the interposer structure via a third interconnect, and a third IC die of the plurality of IC dies is coupled to a second side of the interposer structure via a fourth interconnect, the second side of the interposer structure being opposite the first side of the interposer structure.

[0025] Various other embodiments of microelectronic assemblies disclosed herein include a package substrate including: an interposer including glass; and a substrate layer on a first side of the interposer, the substrate layer including an organic dielectric material; and a plurality of IC dies coupled to a second side of the interposer via an interconnect, the second side being opposite the first side. IC dies in the plurality of IC dies are conductively coupled to each other via a first conductive structure in the interposer, the substrate layer including a second conductive structure in the organic dielectric material, and TGVs in the interposer conductively couple the plurality of IC dies to a second conductive trace.

[0026] Embodiments disclosed herein further include a method comprising: providing a substrate comprising multiple layers of conductive traces in an organic dielectric material; attaching an interposer structure comprising glass to the substrate; attaching a plurality of IC dies to the interposer structure; and conductively coupling the plurality of IC dies through the interposer structure.

[0027] Each of the structures, components, packages, methods, devices, and systems disclosed herein may have several innovative aspects, no single aspect of which is solely responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0028] In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

[0029] The terms "circuit" and "circuitry" mean one or more passive and / or active electrical and / or electronic components that are arranged to cooperate with each other to provide a desired functionality. The term also refers to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, microcontroller circuitry, and / or any other type of physical hardware electrical and / or electronic components.

[0030] The term "integrated circuit" means an electrical circuit integrated into a single piece of semiconductor or similar material.

[0031] In some embodiments, the IC die disclosed herein may include a substantially single-crystal semiconductor, such as silicon or germanium, as a base material (e.g., substrate, body) on which integrated circuits are manufactured using conventional semiconductor processing methods. The semiconductor base material may include, for example, an N-type or P-type material. The die may include, for example, a single-crystal base material formed using bulk silicon (or other bulk semiconductor materials) or a silicon-on-insulator (SOI) structure. In some other embodiments, the base material of one or more of the IC dies may include an alternative material that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV materials. In yet other embodiments, the base material may include a compound semiconductor, for example, a first sub-lattice having at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice having at least one element from Group V of the periodic table (e.g., P, As, Sb). In yet other embodiments, the substrate material may include an intrinsic IV or III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, a nominal impurity doping level may be present. In still other embodiments, the die may include an amorphous material, such as a polymer; for example, the substrate material may be a silica-filled epoxy. In other embodiments, the substrate material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the substrate material may include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N or P type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of the following: gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, magnesium, etc. Although a few examples of materials for the die are described here, any material or structure that can serve as a foundation (e.g., a substrate material) on which IC circuits and structures as described herein can be built falls within the spirit and scope of the present disclosure.

[0032] Unless otherwise described, the IC die described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) a certain function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., ICs that implement one or more of a memory device, a memory array, control logic configured to control the memory device and array, etc.). In another such example, the term "compute die" may be used to describe a die that includes one or more ICs that implement logic / compute circuitry (e.g., ICs that implement one or more of I / O functions, arithmetic operations, pipelining of data, etc.).

[0033] In another example, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die.” Note that the terms “chip,” “die,” and “IC die” are used interchangeably herein.

[0034] The term "optical structure" includes an arrangement of forms fabricated in an IC to receive, transform and / or transmit optical signals as described herein. It may include optical conductors such as waveguides, electromagnetic radiation sources such as lasers and light emitting diodes (LEDs), and electro-optical devices such as photodetectors.

[0035] In various embodiments, any photonic IC (PIC) described herein may include semiconductor materials including, for example, N-type or P-type materials. The PIC may include, for example, a crystalline substrate material formed using bulk silicon (or other bulk semiconductor materials) or an SOI structure (or, generally, a semiconductor-on-insulator structure). In some embodiments, the PIC may be formed using alternative materials that may or may not be combined with silicon, including, but not limited to, lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, aluminum indium arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of III-N or IV group materials. In some embodiments, the PIC may include an amorphous material, such as a polymer. In some embodiments, the PIC may be formed on a printed circuit board (PCB). In some embodiments, the PIC may be heterogeneous, including a carrier material such as glass or silicon carbide as a base material with a thin semiconductor layer having an active side thereon including transistors and similar components. Although several examples of materials for PICs are described herein, any material or structure that can serve as a foundation upon which a PIC can be built falls within the spirit and scope of the present disclosure.

[0036] The term "insulation" means "electrical insulation" and the term "conduction" means "conductive conduction" unless otherwise specified. With reference to optical signals and / or devices, components and elements that operate on or use optical signals, the term "conduction" may also mean "optical conduction".

[0037] The terms "oxide," "carbide," "nitride," and the like refer to compounds containing oxygen, carbon, nitrogen, and the like, respectively.

[0038] The term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide.

[0039] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to solid materials (and / or liquid materials that solidify after processing as described herein) that are substantially non-conductive. By way of example and not limitation, they may include organic polymers and plastics and inorganic materials such as ionic crystals, porcelain, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride and alumina or combinations thereof. They may include dielectric materials, high polarizability materials and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Further examples of insulating materials are underfill and mold or mold-like materials used in packaging applications, including, for example, materials used in organic interposers, packaging supports and other such components.

[0040] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those elements monolithically integrated within the IC, mounted on the IC, or connected to the IC. The ICs described herein may be analog or digital and may be used in a variety of applications such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The ICs described herein may be employed in a single IC die or as part of a chipset for performing one or more related functions in a computer.

[0041] In various embodiments of the present disclosure, the transistor described herein may be a field effect transistor (FET), such as a MOSFET. In many embodiments, the FET is a four-terminal device. In a silicon on insulator or nanoribbon or gate-all-around (GAA) FET, the FET is a three-terminal device that includes a source, a drain, and a gate terminal and uses an electric field to control the current flowing through the device. A FET typically includes a channel material, a source region and a drain region provided in and / or above the channel material, and a gate stack including a gate electrode material (alternatively referred to as a "work function" material) provided above a portion of the channel material ("channel portion") between the source and drain regions, and optionally also includes a gate dielectric material between the gate electrode material and the channel material.

[0042] In a general sense, "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, thereby facilitating the communication of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, thereby facilitating the communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are included in the term "interconnect". The properties of the interconnect described herein should be understood with reference to the signal medium associated therewith. Therefore, when used with reference to an electronic device (such as an IC that operates using electrical signals), the term "interconnect" describes any element formed of a conductive material used to provide electrical connectivity between one or more elements associated with the IC and / or various such elements. In this case, the term "interconnect" can refer to both conductive traces (sometimes also referred to as "wires", "conductors", "metallicity" or "grooves") and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, conductive traces and vias may be referred to as "conductive traces" and "conductive vias," respectively, to highlight the fact that these elements include conductive materials such as metals. Likewise, when used with reference to devices that also operate on optical signals, such as photonic ICs (PICs), "interconnects" may also describe any element formed of a material that conducts light for providing optical connectivity to one or more elements associated with a PCI. In this case, the term "interconnect" may refer to optical waveguides, including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0043] The term "waveguide" refers to any structure that acts to guide the propagation of light from one location to another, typically through a substrate material such as silicon or glass. In various examples, the waveguide can be formed of silicon, doped silicon, silicon nitride, glass such as silica (e.g., silicon dioxide or SiO2), borosilicate (e.g., 70-80wt% SiO2, 7-13wt% B2O3, 4-8wt% Na2O or K2O, and 2-8wt% Al2O3), and the like. The waveguide can be formed using various techniques including, but not limited to, in-situ waveguide formation. For example, in some embodiments, a waveguide can be formed in-situ in glass using low temperature glass-to-glass bonding or by laser direct writing. The in-situ formed waveguide can have lower loss characteristics.

[0044] The term "conductive trace" may be used to describe conductive elements that are isolated by insulating materials. Within an IC die, such insulating materials include interlayer low-k dielectrics provided within the IC die. Within package substrates and PCBs, such insulating materials include organic materials such as Ajinomoto built-up film (ABF), polyimide, or epoxy. Such conductive lines are typically arranged in several levels or layers of a metallization stack.

[0045] The term "conductive via" may be used to describe a conductive element that interconnects two or more conductive lines at different levels of a metallization stack. To this end, a via may be provided substantially perpendicular to the plane of the IC die / chip or a support structure above which the IC structure is provided, and may interconnect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels.

[0046] The term "package substrate" may be used to describe any substrate material that facilitates packaging together any collection of semiconductor dies and / or other electrical components (such as passive electrical components). As used herein, a package substrate may be formed of any material including, but not limited to, an insulating material such as resin-impregnated fiberglass (e.g., a PCB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. Additionally, as used herein, a package substrate may refer to a substrate including a buildup layer (e.g., an ABF layer).

[0047] The term "metallization stack" may be used to refer to a stack of one or more interconnects used to provide connectivity to different circuit components of an IC die / chip and / or a package substrate.

[0048] As used herein, the term "pitch" of an interconnect refers to the center-to-center distance between adjacent interconnects.

[0049] In the context of a stack of dies coupled to each other or in the context of a die coupled to a package substrate, the term "interconnect" may also refer to a die-to-die (DTD) interconnect and a die-to-package substrate (DTPS) interconnect, respectively. A DTD interconnect may also be referred to as a first-level interconnect (FLI). A DTPS interconnect may also be referred to as a second-level interconnect (SLI).

[0050] Although not specifically shown in all current illustrations so as not to clutter the drawings, when describing a DTD or DTPS interconnect, a surface of a first die may include a first set of conductive contacts, and a surface of a second die or package substrate may include a second set of conductive contacts. One or more conductive contacts of the first set may then be electrically and mechanically coupled to some of the conductive contacts of the second set via the DTD or DTPS interconnect.

[0051] In some embodiments, the pitch of the DTD interconnects may be different than the pitch of the DPTS interconnects, although in other embodiments the pitches may be substantially the same.

[0052] The DTPS interconnects disclosed herein may take any suitable form. In some embodiments, the set of DTPS interconnects may include solder (e.g., solder bumps or balls subject to thermal reflow to form DTPS interconnects). The DTPS interconnects including solder may include any suitable soldering material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, the set of DTPS interconnects may include anisotropic conductive materials, such as anisotropic conductive films or anisotropic conductive pastes. Anisotropic conductive materials may include conductive materials dispersed in non-conductive materials. In some embodiments, anisotropic conductive materials may include microscopic conductive particles embedded in an adhesive or a thermosetting adhesive film (e.g., a thermosetting biphenyl epoxy or an acrylic-based material). In some embodiments, the conductive particles may include polymers and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include gold coated with nickel or copper coated with silver, which in turn is coated with a polymer. In another example, the conductive particles may include nickel. When the anisotropic conductive material is uncompressed, there may not be a conductive path from one side of the material to the other side. However, when the anisotropic conductive material is sufficiently compressed (e.g., sufficiently compressed by conductive contacts on either side of the anisotropic conductive material), the conductive materials near the compression zone may contact each other so as to form a conductive path from one side of the film to the other side in the compression zone.

[0053] The DTD interconnects disclosed herein may take any suitable form. In some embodiments, some or all of the DTD interconnects in a microelectronic assembly or IC package as described herein may be metal-to-metal interconnects (e.g., copper-to-copper interconnects or electroplated interconnects). In such embodiments, the conductive contacts on either side of the DTD interconnect may be joined together (e.g., under elevated pressure and / or temperature) without the use of an intervening solder or anisotropic conductive material. In some metal-to-metal interconnects, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide) may be present between the metals joined together (e.g., between copper pads or columns providing associated conductive contacts). In some embodiments, one side of the DTD interconnect may include a metal column (e.g., a copper column), and the other side of the DTD interconnect may include a metal contact (e.g., a copper contact) recessed in the dielectric. In some embodiments, a metal-to-metal interconnect (e.g., a copper-to-copper interconnect) may include a noble metal (e.g., gold) or a metal (e.g., silver) whose oxide is conductive. In some embodiments, metal-to-metal interconnects may include metal nanostructures (e.g., nanorods) that may have a reduced melting point. Metal-to-metal interconnects may be able to reliably conduct higher currents than other types of interconnects; for example, some solder interconnects may form brittle intermetallic compounds when current flows, and the maximum current provided through such interconnects may be constrained to mitigate mechanical failure.

[0054] In some embodiments, the die on either side of the set of DTD interconnects may be a bare (eg, unpackaged) die.

[0055] In some embodiments, the DTD interconnect may include solder. For example, the DTD interconnect may include a conductive bump or column (e.g., a copper bump or column) attached to a corresponding conductive contact portion by solder. In some embodiments, a thin cap of solder may be used in the metal-to-metal interconnect to conform to the flat type, and the solder may become an intermetallic compound during processing. In some embodiments, the solder used in some or all of the DTD interconnects may have a higher melting point than the solder included in some or all of the DTPS interconnects. For example, when the DTD interconnects in the IC package are formed before the DTPS interconnects are formed, the solder-based DTD interconnects may use a higher temperature solder (e.g., having a melting point of more than 200 degrees Celsius), while the DTPS interconnects may use a lower temperature solder (e.g., having a melting point of less than 200 degrees Celsius). In some embodiments, the higher temperature solder may include: tin; tin and gold; or tin, silver and copper (e.g., 96.5% tin, 3% silver and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (eg, eutectic tin-bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.

[0056] In some embodiments, the set of DTD interconnects may include anisotropic conductive materials, such as any of the materials discussed above for DTPS interconnects. In some embodiments, DTD interconnects may be used as data transfer channels, while DTPS interconnects may be used for power and ground lines, and so on.

[0057] In a microelectronic assembly or IC package as described herein, some or all of the DTD interconnects may have a finer pitch than the DPTS interconnects. In some embodiments, the DTPS interconnects disclosed herein may have a pitch between about 80 microns and 300 microns, while depending on the type of the DTD interconnects, the DTD interconnects disclosed herein may have a pitch between about 0.5 microns and 100 microns. An example of silicon-level interconnect density is provided by the density of some DTD interconnects. In some embodiments, the DTD interconnects may have a pitch that is too fine to be directly coupled to the package substrate (e.g., too fine to act as a DTPS interconnect). Due to the greater similarity of materials in different dies on either side of the set of DTD interconnects compared to between the die and the package substrate on either side of the set of DTPS interconnects, the DTD interconnects may have a pitch smaller than the DTPS interconnects. In particular, due to the heat generated during operation (and the heat applied during various manufacturing operations), the differences in the material composition of the die and the package substrate may cause differential expansion and contraction of the die and the package substrate. To mitigate damage caused by this differential expansion and contraction (e.g., cracking, solder bridging, etc.), the DTPS interconnects in any of the microelectronic assemblies or IC packages described herein may be formed larger and further apart than the DTD interconnects, which may experience less thermal stress due to greater material similarity of the die pairs on either side of the DTD interconnects.

[0058] It will be appreciated that one or more levels of underfill (e.g., organic polymer materials such as benzotriazole, imidazole, polyimide, or epoxy) may be provided in the IC packages described herein and may not be labeled so as to avoid cluttering the drawings. In various embodiments, the levels of underfill may include the same or different insulating materials. In some embodiments, the levels of underfill may include a thermosetting epoxy with silicon oxide particles; in some embodiments, the levels of underfill may include any suitable material that can perform an underfill function, such as supporting the die and reducing thermal stress on the interconnects. In some embodiments, the selection of underfill material may be based on design considerations, such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of underfill material may be based on material properties and processing conditions, such as curing temperature, glass transition temperature, viscosity and chemical resistance, and other factors; in some embodiments, the selection of underfill material may be based on both design and processing considerations.

[0059] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic, solvent) may be provided in the IC packages described herein and may not be labeled or shown to avoid cluttering the drawings. The solder resist may be a liquid or dry film material including a photoimageable polymer. In some embodiments, the solder resist may not be photoimageable.

[0060] The terms "substantially," "close," "approximately," "around," and "about" generally refer to being within + / - 20% of a target value (e.g., within + / - 5% or 10% of a target value), based on the context of a particular value as described herein or as known in the art.

[0061] Terms indicating the orientation of various elements (e.g., "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements) generally refer to being within + / - 5%-20% of a target value based on the context of the specific value as described herein or as known in the art.

[0062] The term "connected" means a direct connection between the connected things without any intermediate devices (which may be one or more of mechanical, electrical and / or thermal connections), while the term "coupled" means a direct connection between the connected things or an indirect connection through one or more passive or active intermediate devices.

[0063] The description uses the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments.

[0064] Furthermore, as used with respect to embodiments of the present disclosure, the terms "comprising," "including," "having," and the like are synonymous.

[0065] The present disclosure may use perspective-based descriptions, such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0066] As used herein, the terms "above," "below," "between," and "on" refer to the relative positioning of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described as being "on" a second layer refers to the layer that is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with an adjacent feature or may have one or more intervening layers.

[0067] The term "disposed" as used herein refers to positioning, location, placement, and / or arrangement, rather than to any particular method of formation.

[0068] The term "between" when used with reference to a measuring range includes the ends of the measuring range.

[0069] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0070] Although certain elements may be mentioned in the singular herein, such elements may include multiple sub-elements. For example, a "conductive material" may include one or more conductive materials. In another example, a "dielectric material" may include one or more dielectric materials.

[0071] Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates that different instances of similar objects are referred to and is not intended to imply that the objects so described are necessarily in a given order temporally, spatially, hierarchically, or in any other manner.

[0072] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and in which are shown, as illustrations, embodiments that can be practiced. It should be understood that other embodiments may be utilized and that structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be taken in a limiting sense.

[0073] The drawings are not necessarily drawn to scale.

[0074] In the drawings, the same reference numerals refer to the same or similar elements / materials, which are illustrated such that, unless otherwise stated, the interpretation of an element / material with a given reference numeral provided in the context of one of the drawings applies to the other drawings in which the element / material with the same reference numeral may be illustrated. Further, singular and plural forms of labels may be used with reference numerals to designate single elements and multiple elements of the same or similar element type, kind, or class, respectively.

[0075] Furthermore, in the accompanying drawings, some schematic illustrations of example structures of various devices and components described herein may be shown with precise right angles and straight lines, but it should be understood that when any of the structures described herein are examined using, for example, images of suitable characterization tools such as scanning electron microscopy (SEM) images, transmission electron microscopy (TEM) images, or non-contact profilometers, such schematic illustrations may not reflect real-life process limitations that may prevent features from appearing so "ideal." In such images of real structures, possible processing and / or surface defects may also be visible, such as surface roughness, deviations from curvature or contour, pits or scratches, imperfectly straight edges of materials, tapered through holes or other openings, inadvertent rounding of corners or variations in thickness of different material layers, temporary screws, edges, or combined dislocations within (one or more) crystalline regions, and / or temporary dislocation defects of single atoms or clusters of atoms. Other defects not listed here but common in the field of device manufacturing and / or packaging may exist.

[0076] Note that in the figures, various components (e.g., interconnects) are shown as aligned (e.g., at corresponding interfaces) only for ease of illustration; in reality, some or all of them may not be aligned. In addition, there may be other components present in the assembly that are not shown in the figures to prevent clutter, such as bonding pads, planar pads, metallizations, etc. Further, the figures are intended to show the relative arrangement of components within their assemblies, and generally such assemblies may include other components that are not shown (e.g., various interface layers or various other components related to optical functions, electrical connectivity, or thermal relief). For example, in some further embodiments, the assemblies shown in the figures may include more dies along with other electrical components. In addition, although some components of the assembly are illustrated in the figures as planar rectangles or formed by cuboids, this is only for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped, as dictated by the manufacturing process used to manufacture the various components and sometimes unavoidable due to the manufacturing process.

[0077] In the drawings, specific numbers and arrangements of structures and components are presented for illustrative purposes, and any desired number or arrangement of such structures and components may be present in various embodiments.

[0078] Further, unless otherwise specified, the structures shown in the figures may take any suitable form or shape depending on material properties, manufacturing processes and operating conditions.

[0079] For convenience, if there is a collection of drawings designated by different letters (e.g. Fig.10 A-10C), such collection may be referred to herein without a letter (e.g., as " Fig.10 ”). Similarly, if there is a collection of reference numerals designated with different letters (e.g., 112a-112e), such collection may be referred to herein without the letters (e.g., as “112”).

[0080] The various operations may then be described as a plurality of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be understood to imply that the operations necessarily rely on the order. In particular, the operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0081] Example Embodiments Figure 1Ais a schematic cross-sectional view of an example microelectronic assembly 100 according to some embodiments of the present disclosure. The microelectronic assembly 100 includes an interposer structure 102, which includes glass. In some embodiments, the glass may include borosilicate glass, for example, including silica (e.g., 52%-56%), alumina (e.g., 12%-16%), borate (e.g., 5%-10%), calcined products (e.g., 16%-25%), and magnesium oxide (e.g., 0%-6%). In some embodiments, the glass may have a composition that achieves a low coefficient of thermal expansion (CTE) (e.g., around 2.8 PPM / C); in some such embodiments, the glass may include approximately 60%-65% silica and 20%-25% alumina. In some other embodiments, the glass can have a composition to achieve low electrical losses, for example, having a dielectric constant of approximately 4.8 at 1 GHz and 4.69 at 10 GHz and a loss tangent of 0.0043 at 1 GHz; in some such embodiments, the glass can include approximately 52%-56% silica, 10%-15% alumina, 15%-20% borate, 0%-10% calcined products, and 0%-5% magnesium oxide.

[0082] Side 103 of interposer structure 102 may be attached to substrate 104 on side 106 of substrate 104. Substrate 104 includes a buildup of layers having an organic dielectric material 108 having conductive structures 110 therein. In some embodiments, conductive structures 110 include bonding pads, conductive traces, and conductive vias. In some embodiments, there may be multiple layers of conductive traces, each separated by organic dielectric material 108 and conductively coupled to each other through conductive vias. Only some of these structures are shown in the figure for ease of illustration and to avoid cluttering the figure. Within a wide range of embodiments, any suitable configuration of conductive structures 110 may be provided in substrate 104. In some embodiments, substrate 104 may include a core 112 having a different composition than organic dielectric material 108; for example, organic dielectric material 108 may include polyimide, and core 112 may include fiber-reinforced epoxy. In some other embodiments, organic dielectric material 108 may include one type of epoxy, and core 112 may include a different type of epoxy. Within the broad scope of embodiments, any suitable organic material typically used in packaging substrates and as listed in the previous subsections may be included in the organic dielectric material 108 in the substrate 104 and / or in the core 112 .

[0083] In some embodiments, substrate 104 may include a buildup layer having an organic dielectric material 108 with conductive structures 110 therein on either side of core 112. In some such embodiments, through hole vias (THVs) 114 through core 112 provide conductive coupling of conductive structures 110 on either side of core 112. Side 116 is the opposite side 106 of substrate 104 and may include bonding pads 118 that may be configured to couple substrate 104 to a motherboard or a socket of a motherboard.

[0084] In various embodiments, side 119 of interposer structure 102 may be parallel and opposite to side 103 and coupled to one or more of the various IC dies. For example, different IC dies 120, 122, and 124 may be present in microelectronic assembly 100. In the figures, each of IC dies 120 is represented as a single block, but may actually include a single IC die, or a stack of IC dies arranged one on top of another, or a multi-chip package. In some embodiments, IC die 120 may include a memory circuit, such as a high bandwidth memory (HBM). In some embodiments, IC die 120 may include a semiconductor die made using older technology. IC die 122 may include, for example, a computing die manufactured on the latest semiconductor technology node or other such advanced process technology. Generally, transistors in IC die 120 may be larger than transistors in IC die 122. Die sizes may also be different: IC die 120 may be larger in footprint (and thickness) than any of IC die 122. In some embodiments, IC die 120 may vary in area between 100-700 square millimeters, with a thickness ranging between 100 and 2000 microns; in some embodiments, IC die 122 may vary in area between 25-500 square millimeters, with a thickness ranging between 5 and 500 microns. IC die 124 may include a bridge circuit that serves to conductively couple IC die 120 with IC die 122. Therefore, IC die 124 may also be referred to herein as "bridge die 124". In some embodiments, interposer structure 102 may include active circuit elements that may be fabricated on a glass substrate using an appropriate complementary metal oxide semiconductor (CMOS) process.

[0085] In various embodiments, IC die 120 may be directly coupled to substrate 104 via conductive interconnects 126 having a pitch in a range between 10 microns and 200 microns. IC die 120 may be conductively coupled to IC die 124 via interconnects 128 having the same pitch as interconnects 126 or a different pitch in a range between 10 microns and 135 microns. IC die 124 may be conductively coupled to interposer structure 102 via interconnects 130. IC die 122 may be conductively coupled to side 119 of interposer structure 102 via interconnects 132. In many embodiments, interconnects 126, 128, 130, and 132 may include DTD interconnects as described in the previous subsections. Interconnects 130 on side 103 of interposer structure 102 and interconnects 132 on side 119 of interposer structure 102 may be conductively coupled together via through glass vias (TGVs) 134. Further, two or more IC dies 122 on the side 119 of the interposer structure 102 may be conductively coupled together via conductive structures 136 in the interposer structure 102 .

[0086] Figure 1B yes Figure 1A 1 is a schematic top view of an example microelectronic assembly 100. Note that only a few components are shown; this is for ease of illustration only and is not intended to be limiting. Within the broad scope of the embodiments, any number of components (e.g., IC dies) may be included in microelectronic assembly 100. Portions of IC die 124 are shown as dashed lines to indicate that the dashed portions are beneath structures (e.g., IC dies 120 and 122) that overlie them.

[0087] IC die 120 may be coupled to IC die 122 via conductive paths 140. Note that in various embodiments, conductive paths 140 may include a number of conductive traces, conductive vias, and more than one interconnects 128, 130, and 132. The conductive paths 140 shown are merely conceptually representative and are not intended to be an accurate physical or geometric representation. Conductive paths 140 may pass through IC die 124 in substrate 104. Conductive paths 140 may include interconnects 128 between IC dies 120 and 124, conductive traces and vias in IC die 124, interconnects 130 between IC die 124 and interposer structure 102, TGVs 134, and interconnects 132 between IC die 122 and interposer structure 102.

[0088] The IC die 122 on the interposer structure 102 may be conductively coupled via conductive paths 142. Note that in various embodiments, the conductive paths 142 may include a number of conductive traces, conductive vias, and more than one interconnect 132. In some embodiments, the conductive paths 142 may be optical waveguides that enable optical connectivity between the IC die 122. The conductive paths 142 shown are merely conceptually representative and are not intended to be accurate physical or geometric representations. The conductive paths 140 may include interconnects 132 between the IC die 122 and the interposer structure 102 and conductive structures 136 in the interposer structure 102. In various embodiments, the IC die 122 may form a computing array on the interposer structure 102 that communicates with memory circuits provided in the IC die 120 via the bridge die 124. In some embodiments, one or more of the IC die 120 may also include peripheral interconnect circuitry, for example, to enable connectivity with another component or microelectronic assembly.

[0089] Note that although conductive paths 140 and 142 are shown between adjacent IC dies, within the broad scope of the embodiments, such conductive paths may also be extended to non-adjacent IC dies. For example, two of IC dies 120 may be conductively coupled across IC die 122 (and other components not shown in the figure) via appropriate conductive paths in interposer structure 102 and more than one bridge die 124.

[0090] Figure 2 is a schematic cross-sectional view of a portion of an example microelectronic assembly 100 according to some embodiments of the present disclosure. The portion shown is a portion of an interposer structure 102 indicating an example conductive structure 136 therein. The interconnect structure 102 includes a glass material 202. In some embodiments, the interconnect structure 102 can be fabricated in sequential layers of the glass material 202 (e.g., silicon oxide along with other elements, such as borates, etc.) along with layers 204 of other materials. For example, the sides 103 and 119 of the interposer structure 102 can be coated with a layer 204 that predominantly includes silicon nitride. The selection of materials for the layers in the interconnect structure 102 can be based on manufacturing, operational, and other considerations outside the scope of the present disclosure.

[0091] In various embodiments, the conductive structure 136 includes a conductive trace 206, a conductive via 208, and a conductive bonding pad 210. The conductive trace 206 can be disposed in multiple layers in the interconnect structure 102, wherein the conductive via 208 conductively couples the conductive trace 206 in different layers. In some embodiments, each layer can be approximately 3 microns thick. In other embodiments, each layer can be approximately 1.2 microns thick. For example, the conductive via 208 can be in a layer having a thickness T1; the conductive trace 206 can be in an adjacent layer having a thickness T2. In some embodiments, T1 can be the same as T2; in other embodiments, T1 may not be the same as T2. In some embodiments (as shown), the conductive trace 206 close to the side 103 of the interposer structure 102 has approximately the same thickness as the conductive trace 206 close to the bonding pad 210 and the side 119 of the interposer structure 102.

[0092] The spacing between conductive traces 206 and the width of conductive traces 206 in any layer can vary depending on the thickness of the corresponding conductive traces 206 in the same layer. In some embodiments, the row spacing of conductive traces 206 can be 1 micron, and in other embodiments, the row spacing of conductive traces 206 can be 20 microns. In different embodiments, the via spacing (e.g., between TGVs 134 and / or conductive vias 208) can vary between 2 microns and 15 microns. The via diameter (e.g., of TGVs 134 and / or conductive vias 208) can vary between 2 microns in some embodiments and 50 microns in other embodiments.

[0093] The number of layers of conductive traces 206 may vary depending on factors outside the scope of the present disclosure. In some embodiments (as shown), the layers in some portions of the interposer structure 102 may extend through the thickness of the interposer structure 102 between the sides 103 and 119. In some other embodiments (not shown), the layers may extend partially through the thickness of the interposer structure 102. In some embodiments, the conductive structures 136 may extend partially through the thickness in some portions of the interposer structure 102 and fully through the thickness in some other portions of the interposer structure 102. In some embodiments (not shown), the conductive traces 206 may be suitably conductively coupled to the TGVs 134. In various embodiments, the total thickness of the interposer structure 102 may depend on the number of layers of conductive traces 206; in other embodiments, the thickness may be constant to the number of layers of the conductive traces 206 (e.g., an increase in the number of layers may be offset by a reduced length of the TGVs 134 and / or other configuration options). In some embodiments, the interposer structure 102 may vary in thickness between 100 microns in some embodiments and 1000 microns in other embodiments.

[0094] In some embodiments, the thickness of layer 204 can vary between 0.4 microns and 2.7 microns. In some embodiments, layer 204 can exist between conductive bond pads 210 and conductive traces 206. In such embodiments, a subset of conductive vias 208 can pass through such layer 204. In some embodiments, conductive bond pads 210 can be approximately 6 microns thick. In some embodiments, the size and thickness of conductive bond pads 210 can vary depending on the type of interconnects 126, 128, 130, and / or 132.

[0095] Figure 3 is a schematic cross-sectional view of a portion of an example microelectronic assembly 100 according to some embodiments of the present disclosure. Features of the illustrated embodiment are similar to those of Figure 2 119, except that the thickness of the various layers of the conductive traces 206 and conductive vias 208 vary between sides 103 and 119 of the interposer structure 102. In the illustrated embodiment, the thickness T3 of the conductive traces 206 proximate to side 103 can be less than the thickness T4 of the conductive traces proximate to side 119. In some embodiments (as shown), the layers in some portions of the interposer structure 102 can extend through the thickness of the interposer structure 102 between sides 103 and 119. The spacing between the conductive traces 206 and the width of the conductive traces 206 in any layer can vary depending on the thickness of the corresponding conductive traces 206 in the same layer, as described with reference to FIG. Figure 2 As described in more detail.

[0096] The number of layers of conductive trace 206 may vary depending on factors outside the scope of the present disclosure. In some embodiments (as shown), the layers in some portions of interposer structure 102 may extend through the thickness of interposer structure 102 between sides 103 and 119. In some other embodiments (not shown), the layers may extend partially through the thickness of interposer structure 102. In some embodiments, conductive structure 136 may extend partially through the thickness in some portions of interposer structure 102 and fully through the thickness in some other portions of interposer structure 102. In some embodiments (not shown), conductive trace 206 may be suitably conductively coupled to TGV 134.

[0097] Figure 4 is a schematic cross-sectional view of a portion of an example microelectronic assembly according to some embodiments of the present disclosure. Features of the illustrated embodiments are similar to Figure 22. The conductive trace 206 may be substantially the same as those in , except that the conductive trace 206 may be disposed in a layer of glass material 402 that is different from the glass material 202. For example, in some embodiments, the glass material 402 may include carbon-doped silica. The layers of glass material 202 may alternate with the layers of glass material 402 such that the conductive trace 206 is disposed in the layer of glass material 402 and the conductive via 208 is disposed in the layer of glass material 202. In some embodiments, the layer of glass material 402 may have a different thickness than the layer of glass material 202. For example, the thickness T5 of the layer of glass material 202 may be greater than the thickness T6 of the layer of glass material 402. In some embodiments, T5 may be approximately 3 microns and T6 may be approximately 2 microns.

[0098] The number of layers of conductive traces 206 may vary depending on factors within or outside the scope of the present disclosure. In some embodiments, a layer may extend partially through the thickness of the interposer structure 102; the conductive traces 206 may be suitably conductively coupled to the TGVs 134. In some embodiments (not shown), a layer in some portions of the interposer structure 102 may extend through the thickness of the interposer structure 102 between sides 103 and 119. In some embodiments, the conductive structures 136 may extend partially through the thickness in some portions of the interposer structure 102 and completely through the thickness in some other portions of the interposer structure 102. The spacing between conductive traces 206 and the width of a conductive trace 206 in any layer may vary depending on the thickness of the corresponding conductive trace 206 in the same layer, as described with reference to FIG. Figure 2 As described in more detail.

[0099] Figure 5A 5 is a schematic cross-sectional view of a portion of passive components in an example microelectronic assembly 100 according to some embodiments of the present disclosure. In various embodiments, the interposer structure 102 may include passive components, such as a capacitor (not shown) and an inductor 502. The inductor 502 may have a spiral shape and may be disposed at any suitable location in the interposer structure 102. In the illustrated embodiment, the inductor 502 is positioned partially through the thickness of the interposer structure 102 between the sides 103 and 119. The inductor 502 may include: bonding pads 504, such as 504A and 504B, conductively coupled to the side 119 of the interposer structure 102 through conductive vias. Magnetic material 508 may be disposed around the conductive trace 506 to implement the function of the inductor. The magnetic material 508 may include any suitable magnetic material known in the art for use in thin film inductors, such as cobalt alloys and magnesium alloys.

[0100] Figure 5B is along axis BB' Figure 5ASchematic top view of an inductor 502 of FIG. Conductive trace 506 may form a spiral (e.g., a helix) shape between bonding pads 504A and 504B using multiple planar coils. Within a wide range of embodiments, multiple such inductors 502 may be provided in the interposer structure 102. In some embodiments, such multiple inductors 502 may be coplanar; in other embodiments, the inductors 502 may be provided in different layers in the interposer structure 102.

[0101] Figure 6 6 is a schematic cross-sectional view of a portion of another passive component in an example microelectronic assembly 100 according to some other embodiments of the present disclosure. In the illustrated embodiment, the passive component includes an array of capacitors 602. The capacitors 602 may include any suitable type of capacitor compatible with thin film or CMOS process operation, including metal-insulator-metal capacitors or deep trench capacitors 604, as shown in the figure. In the figure, the deep trench capacitors 604 are shown in a representative form without structural details, such as conductor plates and capacitor dielectrics between the conductor plates, for ease of illustration only. Within a wide range of embodiments, capacitors 602 of any suitable size, shape, and type may be included in the interposer structure 102. The capacitors 602 may be disposed at any suitable location in the interposer structure 102. In the illustrated embodiment, the capacitors 602 are positioned partially through the thickness of the interposer structure 102 between the sides 103 and 119. In some embodiments, the capacitors 602 may be conductively coupled to the bonding pads 210 on the side 119 through the conductive vias 208. In other embodiments (not shown), capacitor 602 may be conductively coupled to another bond pad on side 103 through TGV 134 .

[0102] Fig. 7A1 is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Microelectronic assembly 100 includes a package substrate 702, which includes an interposer 704, and the interposer 704 includes glass. Examples of glass materials are listed with reference to the interposer 102 of FIG. 1. Package substrate 702 further includes a substrate layer 706, which includes an organic dielectric material 108 attached to the interposer 704 along a common contact interface 708. In some embodiments, substrate layer 706 can be constructed above interposer 704. In other embodiments, substrate layer 706 can be attached to interposer 704 using a suitable adhesive. In various embodiments, interposer 704 is substantially similar to interposer 102 of FIG. 1 in terms of structure, except that interposer 704 occupies the entire surface of substrate layer 706. In addition, interposer 704 does not have a free side 119 like interposer 102 of FIG. 1, but is attached along a common contact interface 708 with substrate layer 706. Note also that the conductive structures 136 and passive components in the interposer 704 are similar in various embodiments to those in the reference Figure 2-6 The structure shown and described is essentially the same.

[0103] In various embodiments, the substrate layer 706 is substantially similar in structure to the substrate 104 of FIG. 1 , except that the substrate layer 706 does not have a free surface 106 as the substrate 104, but is attached along a common contact interface 708 with the interposer 704. The conductive structures 136 in the interposer 704 can be conductively coupled to the conductive structures 110 in the substrate layer 706 through the TGVs 134 in the interposer 704. Note that the substrate layer 706 can have suitable bonding pads and other conductive elements to facilitate conductive coupling with the interposer 704; such features are not shown for ease of illustration only. In addition, passive components such as inductors (e.g., 502) and capacitors (e.g., 602) can be appropriately provided in the interposer 704 and / or the substrate layer 706. It will be reasonably understood by those skilled in the art that such features, although not shown or labeled, can be provided in the package substrate 702 to achieve the electrical functionality of the microelectronic assembly 100.

[0104] The IC dies 120, 122 can be coupled to the side 710 of the interposer 704 through the interconnects 132. In some such embodiments, the bridge die 124 may not be present. The lateral coupling between the IC dies 120 and 122 can be through conductive paths in the conductive structures 136 of the interposer 102. The IC dies 120, 122 can be coupled to the conductive structures 110 in the substrate layer 706 through the TGVs 134.

[0105] Figure 7B yes Fig. 7ASchematic top view of an example microelectronic assembly 100. Note that only a few components are shown; this is for ease of illustration only and is not intended to be limiting. Within a wide range of embodiments, any number of components (e.g., IC dies) may be included in the microelectronic assembly 100. The IC die 120 may be coupled to the IC die 122 via a conductive path 712 that passes through the interposer 704. Note that in various embodiments, the conductive path 712 may include more than one of a number of conductive traces, conductive vias, and interconnects 132. The conductive paths 712 shown are merely conceptually representative and are not intended to be an accurate physical or geometric representation. The conductive paths 712 may include interconnects 132 between the IC dies 120, 122 and the interposer 704, as well as conductive structures 136 in the interposer 704. The IC die 122 on the interposer 704 may be conductively coupled via conductive paths 142, as shown in reference Figure 1B As described. In some embodiments, the conductive paths 712 and 142 may be optical waveguides to enable optical communication between the IC dies 120 and 122 or between two IC dies 122. Note that although the conductive paths 712 and 142 are shown between adjacent IC dies, within the broad scope of the embodiments, such conductive paths may also extend to non-adjacent IC dies. For example, two of the IC dies 120 may be conductively coupled across the IC dies 122 (and other components not shown in the figure) via appropriate conductive paths in the interposer 704.

[0106] In various embodiments, any of the features discussed herein with reference to any of Figures 1-7 may be combined with any other features to form a package with one or more IC dies as described herein. For example, in some microelectronic assemblies, some IC dies may be coupled by interconnects having solder, and other IC dies may be coupled by non-solder joints. Some such combinations are described above, but in various embodiments, further combinations and modifications are possible. The various different embodiments described in the different figures may be appropriately combined based on specific needs within a wide range of embodiments.

[0107] Example Method Figure 88 is a schematic flow diagram of example operations 800 that may be associated with fabrication of a microelectronic assembly 100 according to some embodiments of the present disclosure. At 802, a substrate 104 may be provided that includes multiple layers of conductive structures 110 (e.g., traces and vias) in an organic dielectric material 108. In some embodiments (e.g., as described with reference to FIG. 1 ), the substrate 104 may include a core 112; in other embodiments (e.g., as described with reference to FIG. 7 ), the substrate 104 may not include a core 112. The substrate 104 may be fabricated using a standard (e.g., known) process in which the conductive structures 110 are patterned according to specific needs (e.g., based on the various functions provided in the microelectronic assembly 100).

[0108] At 804, the interposer structure 102 including glass may be attached to the substrate 104. In various embodiments, the interposer structure 102 may be provided with the TGVs 134 and the conductive structures 136 before being attached to the substrate 104. The formation of the TGVs 134 and the conductive structures 136 in the interposer structure 102 may be based on known processes, such as laser drilling, electroplating, sequential deposition of silicon oxide, carbon doped silicon oxide, silicon nitride, etc., as described in detail based on specific needs. Figure 2-4 In some embodiments, for example, as described with reference to FIG. 1 , the interposer structure 102 can be attached to the substrate 104 via a conductive interconnect 130. In some such embodiments, the interposer structure 102 can be conductively coupled to a bridge die 124 embedded in an organic dielectric material 108 of the substrate 104. In some other embodiments, for example, as described with reference to FIG. 7 , attaching the interposer structure 102 to the substrate 104 includes: building the substrate 104 on an exposed surface of the interposer structure 102 so that a substrate layer is formed on the interposer. In some other embodiments, for example, as described with reference to FIG. 7 , attaching the interposer structure 102 includes: using an adhesive to attach the substrate 104 to the interposer structure 102.

[0109] At 806, the plurality of IC dies 122 can be attached to the interposer structure 102 via the interconnects 132. In some embodiments, additional plurality of IC dies 120 can also be attached to the interposer structure 102 via the interconnects 132. In some embodiments, the plurality of IC dies 120 can further be attached to the substrate 104 via the interconnects 126. Some of the IC dies 120 in such embodiments can also be coupled to the bridge die 124 in the substrate 104 via the interconnects 128.

[0110] At 808, the plurality of IC dies 122 may be conductively coupled to each other through the conductive structures 136 in the interposer structure 102. In some embodiments, for example, as described with reference to FIG. 7 , the IC die 120 may also be coupled to the IC die 122 through the conductive structures 136 in the interposer structure 102. In some other embodiments, the IC die 120 that is not directly attached to the interposer structure 102 may be conductively coupled to the IC die 122 that is attached to the interposer structure 102 through the TGVs 134, the conductive interconnects 128, 130, and the bridge die 124.

[0111] although Figure 8 Various operations are illustrated as being performed in a particular order, but this is merely illustrative and the operations discussed herein may be reordered and / or repeated as appropriate. Further, additional processes not illustrated may be performed without departing from the scope of the present disclosure. Moreover, the descriptions herein of the present invention may be modified in accordance with the present disclosure. Figure 8 Various operations in the operations discussed are performed to manufacture other microelectronic assemblies in the microelectronic assembly 100 disclosed herein. Although each is performed once in Figure 8 Various operations are illustrated in the drawings, but the operations may be repeated as often as desired. For example, one or more operations may be performed in parallel with substantially simultaneous fabrication and testing of multiple microelectronic assemblies. In another example, the operations may be performed in a different order to reflect the structure of a particular microelectronic assembly in which one or more substrates or other components may be included as described herein.

[0112] also, Figure 8 The operations illustrated in the drawings may be combined or may include more details than described. For example, the operations may be appropriately modified for IC dies that do not have a semiconductor substrate but are manufactured on other materials (such as glass or ceramic materials) without departing from the scope of the present disclosure. Still further, the various operations shown and described may further include other manufacturing operations related to the manufacture of other components of the microelectronic assemblies described herein or any device that may include a microelectronic assembly as described herein. For example, Figure 8 Operations not shown may include various cleaning operations, additional surface planarization operations, operations for surface roughening, operations to include barrier and / or adhesion layers where desired, and / or operations for incorporating a microelectronic assembly as described herein into or with an IC component, a computing device, or any desired structure or device.

[0113] Example Devices and Components The packages disclosed herein (eg, any of the embodiments shown in FIGS. 1-8 or any further embodiments described herein) may be included in any suitable electronic component. Figure 9-11 Various examples of packages, components, and devices that may be used with or include any of the IC packages as disclosed herein are illustrated.

[0114] Fig. 9 is a cross-sectional side view of an example IC package 2200 that may include an IC package according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a SiP.

[0115] As shown in the figure, the package substrate 2252 may be formed of an insulator (e.g., ceramic, a deposited film, an epoxy film having filler particles therein, etc.), and may have conductive paths extending through the insulator between the first side 2272 and the second side 2274 or between different locations on the first side 2272 and / or between different locations on the second side 2274. These conductive paths may take the form of any of interconnect structures including lines and / or through-holes.

[0116] The packaging substrate 2252 may include: conductive contacts 2263, which are coupled to conductive paths 2262 through the packaging substrate 2252, thereby allowing the circuits within the die 2256 and / or the interposer 2257 to be electrically coupled to various conductive contacts in the conductive contacts 2264 (or to other devices included in the packaging substrate 2252, not shown).

[0117] IC package 2200 may include an interposer 2257 coupled to a package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in the figure are solder bumps, but any suitable first-level interconnects 2265 may be used, such as solder bumps, solder pillars, or bonding wires.

[0118] The IC package 2200 may include: one or more dies 2256, coupled to an interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive paths (not shown) through the interposer 2257, thereby allowing the circuits within the die 2256 to be electrically coupled to various conductive contacts in the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in the figure are solder bumps, but any suitable first-level interconnects 2258 may be used, such as solder bumps, solder columns, or bonding wires. As used herein, "conductive contacts" may refer to portions of a conductive material (e.g., metal) that serve as an interface between different components; the conductive contacts may be recessed in the surface of a component, flush with the surface of a component, or extend away from the surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

[0119] In some embodiments, an underfill material 2266 may be disposed around the first level interconnect 2265 between the package substrate 2252 and the interposer 2257, and a mold 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold 2268. An example material that may be used for the underfill material 2266 and the mold 2268 is an epoxy resin when appropriate. A second level interconnect 2270 may be coupled to the conductive contact 2264. The second level interconnect 2270 illustrated in the figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable second level interconnect 2270 may be used (e.g., pins in a pin grid array arrangement or contacts in a contact grid array arrangement). The second level interconnect 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference Fig.10 discussed.

[0120] In various embodiments, any of the dies 2256 may be a microelectronic assembly 100 as described herein. In embodiments where the IC package 2200 includes a plurality of dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuits that perform any desired functions. For example, in addition to one or more of the dies 2256 being a microelectronic assembly 100 as described herein, one or more of the dies 2256 may also be a logic die (e.g., a silicon-based die), one or more of the dies 2256 may also be a memory die (e.g., an HBM), etc. In some embodiments, any of the dies 2256 may be implemented as discussed with reference to any of the previous figures. In some embodiments, at least some of the dies 2256 may not include an implementation as described herein.

[0121] Although the IC package 2200 illustrated in the figure is a flip chip package, other packaging architectures can be used. For example, the IC package 2200 can be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 can be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are illustrated in the IC package 2200, the IC package 2200 can include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mount resistors, capacitors, and inductors disposed above the first side 2272 or the second side 2274 of the package substrate 2252 or on either of the two sides of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0122] In some embodiments, interposer 2257 may not be included in IC package 2200 ; instead, die 2256 may be directly coupled to conductive contacts 2263 at first side 2272 through first level interconnects 2265 .

[0123] Fig.10is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein. The IC device assembly 2300 includes a plurality of components disposed above a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed above a first side 2340 of the circuit board 2302 and an opposing second side 2342 of the circuit board 2302; generally, the components may be disposed above one or both sides 2340 and 2342. In particular, any suitable component among the components of the IC device assembly 2300 may include any of the one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein; for example, any of the IC packages discussed below with reference to the IC device assembly 2300 may take the form of a package as described above with reference to the IC device assembly 2300. Fig. 9 A form of any of the embodiments of IC package 2200 discussed.

[0124] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by insulator layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 2302 (optionally, in conjunction with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB packaging substrate.

[0125] As illustrated in the figure, in some embodiments, the IC device assembly 2300 may include: a package structure on an interposer 2336, coupled to a first side 2340 of a circuit board 2302 via a coupling component 2316. The coupling component 2316 may electrically and mechanically couple the package structure on the interposer 2336 to the circuit board 2302, and may include solder balls (as illustrated), external and internal threaded portions of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0126] Package structure 2336 on interposer may include: IC package 2320 coupled to interposer 2304 via coupling component 2318. Coupling component 2318 may take any suitable form depending on the desired functionality, such as the form discussed above with reference to coupling component 2316. In some embodiments, IC package 2320 may be or include IC package 2200, for example, as discussed above with reference to Fig. 9 In some embodiments, IC package 2320 may include at least one microelectronic assembly 100 as described herein. Microelectronic assembly 100 is not specifically shown in the figures so as not to clutter the drawings.

[0127] Although a single IC package 2320 is shown in the figure, multiple IC packages can be coupled to the interposer 2304; alternatively, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intermediate package substrate for bridging the circuit board 2302 and the IC package 2320. In general, the interposer 2304 can redistribute connections to a wider pitch or reroute connections to different connections. For example, the interposer 2304 can couple the IC package 2320 to the BGA of the coupling component 2316 for coupling to the circuit board 2302.

[0128] In the embodiment illustrated in the figure, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected via interposer 2304.

[0129] The interposer 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of replaceable rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 2304. Package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.

[0130] In some embodiments, IC device assembly 2300 may include: IC package 2324, coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0131] In some embodiments, IC device assembly 2300 may include: a package stack structure 2334 coupled to second side 2342 of circuit board 2302 via coupling component 2328. Package stack structure 2334 may include: IC package 2326 and IC package 2332 coupled together via coupling component 2330, such that IC package 2326 is disposed between circuit board 2302 and IC package 2332. Coupling components 2328 and 2330 may take the form of any of the embodiments of coupling component 2316 discussed above, and IC package 2326 and / or 2332 may take the form of any of the embodiments of IC package 2320 discussed above. Package stack structure 2334 may be configured according to any of the package stack structures known in the art.

[0132] Fig.11 2400 that may include one or more components having one or more IC packages in accordance with any of the embodiments disclosed herein. For example, any suitable component among the components of computing device 2400 may include a microelectronic assembly (e.g., 100) in accordance with any of the embodiments disclosed herein. In another example, any one or more of the components of computing device 2400 may include any embodiment of IC package 2200 (e.g., Fig. 9 In yet another example, any one or more of the components of computing device 2400 may include IC device assembly 2300 (e.g., as shown in Fig.10 ).

[0133] In the figure, a number of components are illustrated as being included in computing device 2400, but any one or more of these components may be omitted or repeated as appropriate for the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single SOC die.

[0134] Additionally, in various embodiments, computing device 2400 may not include one or more of the components illustrated in the figure, but computing device 2400 may include interface circuitry for coupling to the one or more components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., connector and driver circuitry) to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry (e.g., connector and supporting circuitry) to which audio input device 2418 or audio output device 2408 may be coupled.

[0135] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any of the following devices or device portions: it processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include: a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a self-selected transfer torque magnetic random access memory (STT-MRAM).

[0136] In some embodiments, computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communications for transferring data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0137] The communication chip 2412 can implement any one of a plurality of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 modification), LTE projects, together with any modifications, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed conformity and interoperability testing for the IEEE 802.16 standard. The communication chip 2412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 can operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and beyond. In other embodiments, the communication chip 2412 can operate according to other wireless protocols. The computing device 2400 may include an antenna 2422 for facilitating wireless communications and / or receiving other wireless communications (such as, AM or FM radio transmissions).

[0138] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As mentioned above, the communication chip 2412 can include multiple communication chips. For example, the first communication chip 2412 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication chip 2412 can be dedicated to longer-range wireless communications, such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or other. In some embodiments, the first communication chip 2412 can be dedicated to wireless communications, and the second communication chip 2412 can be dedicated to wired communications.

[0139] Computing device 2400 may include battery / power circuit 2414. Battery / power circuit 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of computing device 2400 to an energy source separate from computing device 2400 (e.g., AC line power).

[0140] Computing device 2400 may include display device 2406 (or corresponding interface circuitry, as discussed above). Display device 2406 may include any visual indicator such as, for example, a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0141] Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry, as discussed above). Audio output device 2408 may include any device that generates an audible indicator, such as, for example, a speaker, headphones, or earbuds.

[0142] Computing device 2400 may include audio input device 2418 (or corresponding interface circuitry, as discussed above). Audio input device 2418 may include any device that generates a signal representative of sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0143] Computing device 2400 may include GPS device 2416 (or corresponding interface circuitry, as discussed above). GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0144] Computing device 2400 may include other output devices 2410 (or corresponding interface circuitry, as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0145] Computing device 2400 may include other input devices 2420 (or corresponding interface circuitry, as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (such as a mouse), a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0146] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a notebook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0147] Select Example Example 1 provides a microelectronic assembly (e.g., 100, FIG. 1 ) comprising: an interposer structure (e.g., 102) comprising glass; a substrate (e.g., 104) comprising an organic dielectric material, the substrate being coupled to a first side (e.g., 103) of the interposer structure; and a plurality of IC dies (e.g., 120, 122, 124), wherein: a first IC die (e.g., 120) of the plurality of IC dies is coupled to the substrate via a first interconnect (e.g., 126), and a second IC die of the plurality of IC dies is coupled to the substrate via a first interconnect (e.g., 126). A second IC die (e.g., 124) is embedded in an organic dielectric material of the substrate, the second IC die is coupled to the first IC die via a second interconnect (e.g., 128), the second IC die is coupled to a first side of the interposer structure via a third interconnect (e.g., 130), and a third IC die (e.g., 122) of the plurality of IC dies is coupled to a second side (e.g., 119) of the interposer structure via a fourth interconnect (e.g., 132), the second side of the interposer structure being opposite to the first side of the interposer structure.

[0148] Example 2 provides the microelectronic assembly of Example 1, wherein the third IC die is conductively coupled to the second IC die through a TGV (eg, 134 ) in the interposer structure.

[0149] Example 3 provides a microelectronic assembly of any of Examples 1-2, wherein: a fourth IC die of the plurality of IC die is coupled to a second side of the interposer structure, and the fourth IC die is conductively coupled to the third IC die through a conductive structure (e.g., 136) in the interposer structure.

[0150] Example 4 provides the microelectronic assembly of Example 3, wherein the conductive structure in the interposer structure includes an optical waveguide.

[0151] Example 5 provides the microelectronic assembly of Example 3, wherein the conductive structure in the interposer structure includes (for example, Figure 2-4): conductive bonding pads (e.g., 210); multiple layers of conductive traces (e.g., 206); and conductive vias (e.g., 208) coupling the conductive traces and the conductive bonding pads in different layers.

[0152] Example 6 provides the microelectronic assembly of Example 5, wherein (for example, Figure 2 ) The conductive traces proximate to the first side of the interposer structure have substantially the same thickness as the conductive traces proximate to the second side of the interposer structure.

[0153] Example 7 provides the microelectronic assembly of any of Examples 5-6, wherein: the conductive traces are approximately between 2 microns and 3 microns thick, the row spacing between the conductive traces varies approximately between 1 micron and 20 microns, and the conductive vias have a via diameter between 2 microns and 50 microns.

[0154] Example 8 provides the microelectronic assembly of Example 5, wherein (for example, Figure 3 ) The conductive traces proximate to a first side of the interposer structure are thinner than the conductive traces proximate to a second side of the interposer structure.

[0155] Example 9 provides the microelectronic assembly of Example 5, wherein (for example, Figure 3 ) The conductive vias proximate to the first side of the interposer structure are smaller than the conductive vias proximate to the second side of the interposer structure.

[0156] Example 10 provides the microelectronic assembly of any of Examples 5-6, wherein (for example, Figure 4 ): The interposer structure includes alternating layers of a first glass material (eg, 202) and a second glass material (eg, 402), the conductive vias being in the first glass material, and the conductive traces being in the second glass material.

[0157] Example 11 provides the microelectronic assembly of Example 10, wherein the layer of the first glass material is approximately 2 micrometers thick and the layer of the second glass material is approximately 3 micrometers thick.

[0158] Example 12 provides the microelectronic assembly of Example 10, wherein: the first glass material includes silicon and oxygen, and the second glass material includes carbon, silicon, and oxygen.

[0159] Example 13 provides the microelectronic assembly of any of Examples 5-12, wherein: a layer (eg, 204) comprising silicon and nitrogen is between the conductive bond pad and the conductive trace, and a subset of the conductive vias is in the layer comprising silicon and nitrogen.

[0160] Example 14 provides the microelectronic assembly of Example 13, wherein the layer comprising silicon and nitrogen is approximately between 0.4 microns and 2.7 microns.

[0161] Example 15 provides the microelectronic assembly of any of Examples 1-14, wherein the first side of the interposer structure and the second side of the interposer structure have respective layers that include silicon and nitrogen.

[0162] Example 16 provides the microelectronic assembly of Example 15, wherein the respective layers comprising silicon and nitrogen are approximately between 0.4 microns and 2.7 microns.

[0163] Example 17 provides the microelectronic assembly of any of Examples 1-16, wherein (eg, FIGS. 5-6 ) the interposer structure further includes passive electronic components including inductors and capacitors.

[0164] Example 18 provides the microelectronic assembly of Example 17, wherein the inductor is a spiral inductor.

[0165] Example 19 provides the microelectronic assembly of Example 17, wherein the capacitor comprises an array of deep trench capacitors.

[0166] Example 20 provides the microelectronic assembly of any of Examples 1-19, wherein the substrate includes multiple layers of conductive traces (eg, 110 ) in the organic dielectric material (eg, 108 ).

[0167] Example 21 provides the microelectronic assembly of Example 20, wherein the substrate further includes a core (eg, 112) having a through-hole via (THV) (eg, 114) passing through the core.

[0168] Example 22 provides the microelectronic assembly of Example 21, wherein the core includes a fiber-reinforced epoxy material.

[0169] Example 23 provides the microelectronic assembly of any of Examples 21-22, wherein the multiple layers of conductive traces in the organic dielectric material are on either side of the core.

[0170] Example 24 provides a microelectronic assembly of any of Examples 1-23, wherein: the substrate has a first side (e.g., 106) and an opposing second side (e.g., 116), the first side of the interposer structure is coupled to the first side of the substrate, and the substrate further includes a bonding pad (e.g., 118) on the second side.

[0171] Example 25 provides the microelectronic assembly of any of Examples 1-24, wherein: the first IC die includes memory circuitry, the second IC die includes a bridge circuit, and the third IC die includes computing circuitry.

[0172] Example 26 provides the microelectronic assembly of any of Examples 1-25, wherein: the interposer structure includes active circuit elements.

[0173] Example 27 provides a microelectronic assembly (e.g., 100, Figure 7), comprising: a packaging substrate (e.g., 702), comprising: an interposer (e.g., 704), comprising glass; and a substrate layer (e.g., 706), located on a first side (e.g., 703) of the interposer, the substrate layer comprising an organic dielectric material; and a plurality of IC dies (e.g., 120, 122), coupled to a second side (e.g., 119) of the interposer via an interconnect (e.g., 132), the second side being opposite to the first side, wherein: the IC dies in the plurality of IC dies are conductively coupled to each other via a first conductive structure in the interposer, the substrate layer comprises a second conductive structure in the organic dielectric material, and the TGV in the interposer conductively couples the plurality of IC dies to the second conductive structure.

[0174] Example 28 provides the microelectronic assembly of Example 27, wherein the first conductive structure in the interposer includes (e.g., Figure 2-4 ): a conductive bonding pad; multiple layers of conductive traces; and conductive vias coupling the conductive traces and the conductive bonding pads in different layers.

[0175] Example 29 provides the microelectronic assembly of Example 28, wherein (for example, Figure 2 )The conductive traces proximate to the first side of the interposer have substantially the same thickness as the conductive traces proximate to the second side of the interposer.

[0176] Example 30 provides the microelectronic assembly of Example 28, wherein (for example, Figure 3 ) The conductive traces proximate to the first side of the interposer are thinner than the conductive traces proximate to the second side of the interposer.

[0177] Example 31 provides the microelectronic assembly of Example 28, wherein (for example, Figure 3 ) The conductive vias proximate to the first side of the interposer are smaller than the conductive vias proximate to the second side of the interposer.

[0178] Example 32 provides the microelectronic assembly of any of Examples 28-31, wherein (for example, Figure 4 ): The interposer includes alternating layers of a first glass material (eg, 202) and a second glass material (eg, 402), the conductive vias being in the first glass material, and the conductive traces being in the second glass material.

[0179] Example 33 provides the microelectronic assembly of Example 32, wherein: the first glass material includes silicon and oxygen, and the second glass material includes carbon, silicon, and oxygen.

[0180] Example 34 provides the microelectronic assembly of any of Examples 28-33, wherein: a layer (eg, 204) comprising silicon and nitrogen is between the conductive bond pad and the conductive trace, and a subset of the conductive vias is in the layer comprising silicon and nitrogen.

[0181] Example 35 provides the microelectronic assembly of any of Examples 27-34, wherein the first side of the interposer and the second side of the interposer have respective layers that include silicon and nitrogen.

[0182] Example 36 provides the microelectronic assembly of any of Examples 27-35, wherein (eg, FIGS. 5-6 ) the interposer further includes passive electronic components including inductors and capacitors.

[0183] Example 37 provides the microelectronic assembly of Example 36, wherein the inductor is a spiral inductor.

[0184] Example 38 provides the microelectronic assembly of any of Examples 36-37, wherein the capacitor comprises an array of deep trench capacitors.

[0185] Example 39 provides the microelectronic assembly of any of Examples 27-38, wherein the second conductive structure in the substrate layer includes multiple layers of conductive traces in the organic dielectric material (eg, 108).

[0186] Example 40 provides the microelectronic assembly of any of Examples 27-39, wherein a first subset of the plurality of IC dies includes memory circuits and a second subset of the plurality of IC dies includes computing circuits.

[0187] Example 41 provides a method comprising: providing a first substrate comprising multiple layers of conductive traces in an organic dielectric material; attaching a second structure comprising glass to the first structure; attaching a plurality of IC dies to the second structure; and conductively coupling the plurality of IC dies through the second structure.

[0188] Example 42 provides the method of Example 41, wherein the second structure is attached to the first structure via a conductive interconnect.

[0189] Example 43 provides the method of any of Examples 41-42, further comprising: attaching an additional plurality of IC dies to the first structure; and conductively coupling the additional plurality of IC dies to the plurality of IC dies through the first structure.

[0190] Example 44 provides the method of Example 43, wherein: conductively coupling the additional multiple IC dies to the multiple IC dies includes: coupling the additional multiple IC dies to a bridge die embedded in the organic dielectric material of the first structure, and coupling the bridge die embedded in the organic dielectric material of the first structure to the second structure.

[0191] Example 45 provides the method of Example 43, wherein conductively coupling the additional plurality of IC dies to the plurality of IC dies includes providing TGVs in the second structure.

[0192] Example 46 provides the method of any of Examples 41-45, wherein attaching the second structure includes: building the first structure on an exposed surface of the second structure such that the substrate layer substantially covers an exposed surface of an underlying interposer.

[0193] Example 47 provides the method of any of Examples 41-45, wherein attaching the second structure includes attaching the second structure to the first structure via an adhesive.

[0194] Example 48 provides the method of any of Examples 41-47, wherein the plurality of IC dies are attached to the second structure via conductive interconnects.

[0195] Example 49 provides the method of any of Examples 41-48, further comprising conductively coupling the plurality of IC dies to the first structure.

[0196] Example 50 provides the method of Example 49, wherein conductively coupling the plurality of IC dies to the first structure includes providing TGVs in the second structure.

[0197] Example 51 provides a microelectronic component comprising: a packaging substrate; a first plurality of IC dies coupled to the packaging substrate; an interposer structure coupled to the packaging substrate laterally adjacent to the first plurality of IC dies; and a second plurality of IC dies coupled to the interposer structure on a side of the interposer structure opposite to the packaging substrate, wherein: the interposer structure is conductively coupled to the first plurality of IC dies through the packaging substrate, the interposer structure comprising glass, multiple layers of conductive traces and TGVs in the glass, and individual IC dies in the second plurality of IC dies are conductively coupled through conductive traces in the interposer structure.

[0198] Example 52 provides the microelectronic assembly of Example 51, wherein the interposer structure is conductively coupled to the first plurality of IC dies through a third plurality of IC dies embedded in the package substrate.

[0199] Example 53 provides the microelectronic assembly of Example 52, wherein individual IC dies of the third plurality of IC dies are between the first plurality of IC dies and an adjacent side of the interposer structure.

[0200] Example 54 provides the microelectronic assembly of any of Examples 52-53, wherein the packaging substrate includes multiple layers of conductive traces in an organic dielectric material.

[0201] The above description of the illustrated implementation of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the art will recognize.

Claims

1. A microelectronic assembly comprising: an interposer structure including glass; a substrate comprising an organic dielectric material, the substrate coupled to a first side of the interposer structure; as well as Multiple IC dies, in: A first IC die of the plurality of IC dies is coupled to the substrate via a first interconnect, a second IC die of the plurality of IC dies embedded in an organic dielectric material of the substrate, the second IC die is coupled to the first IC die via a second interconnect, The second IC die is coupled to the first side of the interposer structure via a third interconnect, and A third IC die of the plurality of IC dies is coupled to a second side of the interposer structure through a fourth interconnect, the second side of the interposer structure being opposite the first side of the interposer structure.

2. The microelectronic assembly of claim 1, wherein the third IC die is conductively coupled to the second IC die through a through glass via (TGV) in the interposer structure.

3. A microelectronic assembly as claimed in any one of claims 1 to 2, wherein: a fourth IC die of the plurality of IC dies coupled to a second side of the interposer structure, The fourth IC die is conductively coupled to the third IC die through conductive structures in the interposer structure.

4. The microelectronic assembly of claim 3, wherein the conductive structure in the interposer structure comprises an optical waveguide.

5. The microelectronic assembly of claim 3, wherein the conductive structure in the interposer structure comprises: a conductive bonding pad; multiple layers of conductive traces; as well as A conductive via couples the conductive trace and the conductive bond pad in different layers.

6. The microelectronic assembly of claim 5, wherein the conductive traces proximate the first side of the interposer structure have substantially the same thickness as the conductive traces proximate the second side of the interposer structure.

7. The microelectronic assembly of claim 5, wherein the conductive traces proximate the first side of the interposer structure are thinner than the conductive traces proximate the second side of the interposer structure.

8. The microelectronic assembly of claim 5, wherein the conductive vias proximate the first side of the interposer structure are smaller than the conductive vias proximate the second side of the interposer structure.

9. A microelectronic assembly as claimed in any one of claims 5 to 6, wherein: The interposer structure includes alternating layers of a first glass material and a second glass material, The conductive via is in the first glass material, and The conductive traces are in the second glass material.

10. The microelectronic assembly of claim 9, wherein: The first glass material includes silicon and oxygen, and The second glass material includes carbon, silicon and oxygen.

11. A microelectronic assembly as claimed in any one of claims 5 to 10, wherein: A layer including silicon and nitrogen is between the conductive bond pad and the conductive trace, and A subset of the conductive vias is in a layer comprising silicon and nitrogen.

12. A microelectronic assembly as claimed in any one of claims 1 to 11, wherein the first side of the interposer structure and the second side of the interposer structure have respective layers comprising silicon and nitrogen.

13. A microelectronic assembly as claimed in any one of claims 1 to 12, wherein the interposer structure further comprises passive electronic components including inductors and capacitors.

14. A microelectronic assembly as claimed in any one of claims 1 to 13, wherein the substrate comprises a plurality of layers of conductive traces in the organic dielectric material.

15. A microelectronic assembly comprising: Package substrate, including: interposer, including glass; and a substrate layer on a first side of the interposer, the substrate layer comprising an organic dielectric material; and a plurality of IC dies coupled to a second side of the interposer via interconnects, the second side being opposite to the first side, in: The IC dies of the plurality of IC dies are conductively coupled to each other via first conductive structures in the interposer, the substrate layer includes second conductive structures in the organic dielectric material, and Through glass vias (TGVs) in the interposer conductively couple the plurality of IC dies to the second conductive structure.

16. The microelectronic assembly of claim 15, wherein the first conductive structure in the interposer comprises: a conductive bonding pad; multiple layers of conductive traces; as well as A conductive via couples the conductive trace and the conductive bond pad in different layers.

17. The microelectronic assembly of claim 16, wherein the conductive traces proximate the first side of the interposer have substantially the same thickness as the conductive traces proximate the second side of the interposer.

18. The microelectronic assembly of claim 16, wherein the conductive traces proximate the first side of the interposer are thinner than the conductive traces proximate the second side of the interposer.

19. The microelectronic assembly of claim 16, wherein the conductive vias proximate the first side of the interposer are smaller than the conductive vias proximate the second side of the interposer.

20. A microelectronic assembly as claimed in any one of claims 16 to 19, wherein: The interposer comprises alternating layers of a first glass material and a second glass material, The conductive via is in the first glass material, and The conductive traces are in the second glass material.

21. A microelectronic assembly as claimed in claim 20, wherein: The first glass material includes silicon and oxygen, and The second glass material includes carbon, silicon and oxygen.

22. A microelectronic assembly comprising: Package substrate; a first plurality of IC dies coupled to the package substrate; an interposer structure coupled to a package substrate laterally adjacent to the first plurality of IC dies; as well as a second plurality of IC dies coupled to the interposer structure on a side of the interposer structure opposite the package substrate, in: the interposer structure conductively coupled to the first plurality of IC dies through the package substrate, The interposer structure includes glass, multiple layers of conductive traces, and through-glass vias (TGVs) in the glass, and Individual IC dies of the second plurality of IC dies are conductively coupled via conductive traces in the interposer structure.

23. The microelectronic assembly of claim 22, wherein the interposer structure is conductively coupled to the first plurality of IC dies through a third plurality of IC dies embedded in the package substrate.

24. The microelectronic assembly of claim 22, wherein individual IC dies of the third plurality of IC dies are between the first plurality of IC dies and an adjacent side of the interposer structure.

25. A microelectronic assembly as claimed in any one of claims 22 to 24, wherein the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material.

Images