Alarm suppression in analog-to-digital converters (adc)

Abstract

Techniques and apparatus for aliasing suppression in an analog-to-digital converter (ADC) in which only a portion of the ADC operates at a higher sampling rate than other portions of the ADC, thereby preventing aliasing while conserving power. One example ADC circuit generally includes a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial number 17 / 932,572 filed on September 15, 2022, which is incorporated herein by reference. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic components and, more particularly, to analog-to-digital converters (ADCs). Background Art

[0004] An analog-to-digital converter (ADC) is an electronic circuit used to convert an analog signal into a digital signal, typically used to perform signal processing in the digital domain. Several types of ADCs are available, each with different advantages and disadvantages, which makes some ADC types more suitable for specific applications than others. For example, a successive approximation register (SAR) ADC can provide an area and power efficient architecture for low to medium precision analog-to-digital conversion applications. A SAR ADC can use a digital-to-analog converter (DAC) and a comparator to approximate a digital value corresponding to an analog input. Compared to a SAR ADC, another type of ADC known as a flash ADC can provide faster conversion speeds at the expense of an exponential increase in power and area consumption. Another type of ADC with a faster sampling rate than a SAR ADC but lower power and area consumption than a flash ADC is called a pipelined ADC. Summary of the invention

[0005] The systems, methods, and devices of the present disclosure each have several aspects, no one of which is solely responsible for its desired attributes. Without limiting the scope of the present disclosure as expressed by the appended claims, some features will now be briefly discussed. After considering this discussion, and especially after reading the section entitled "Detailed Description of the Invention," those skilled in the art will understand how the features of the present disclosure provide the advantages described herein.

[0006] Certain aspects of the present disclosure generally relate to analog-to-digital converter (ADC) circuits with integrated aliasing rejection, wherein a portion of the ADC circuit operates at a higher sampling rate than other portions of the ADC circuit.

[0007] Certain aspects of the present disclosure provide an analog-to-digital converter (ADC) circuit. The ADC circuit generally includes a first circuit portion and a second circuit portion. The first portion is configured to operate at a first clock rate equal to a sampling rate of the ADC circuit, and the second circuit portion is configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.

[0008] Certain aspects of the present disclosure provide a pipeline ADC circuit. The pipeline ADC circuit generally includes a plurality of stages. One or more later stages of the plurality of stages are configured to operate at a first clock rate equal to a sampling rate of the pipeline ADC circuit, and one or more initial stages of the plurality of stages are configured to operate at a second clock rate higher than the sampling rate of the pipeline ADC circuit.

[0009] Certain aspects of the present disclosure provide a successive approximation register (SAR) ADC circuit. The SAR ADC circuit generally includes a plurality of capacitive digital-to-analog converters (CDACs) and a multi-input comparator. The multi-input comparator has a plurality of inputs coupled to the outputs of the plurality of CDACs. The multi-input comparator is configured to operate at a first clock rate equal to a sampling rate of the SAR ADC circuit, and the plurality of CDACs are configured to operate at a second clock rate higher than the sampling rate of the SAR ADC circuit.

[0010] Certain aspects of the present disclosure provide a signal conversion method. The method generally includes: using an ADC circuit to convert an analog signal to a digital signal at a sampling rate of the ADC circuit. The conversion involves operating a first circuit portion of the ADC circuit at a first clock rate equal to the sampling rate of the ADC circuit, and operating a second circuit portion of the ADC circuit at a second clock rate higher than the sampling rate of the ADC circuit.

[0011] Certain aspects of the present disclosure provide a signal conversion method. The method generally includes: using a pipeline ADC circuit to convert an analog signal to a digital signal at a sampling rate of the pipeline ADC circuit. The pipeline ADC circuit generally includes a plurality of stages. The conversion generally involves operating one or more later stages of the plurality of stages at a first clock rate equal to the sampling rate of the pipeline ADC circuit, and operating one or more initial stages of the plurality of stages at a second clock rate higher than the sampling rate of the pipeline ADC circuit.

[0012] Certain aspects of the present disclosure provide a signal conversion method. The method generally includes: using a SAR ADC circuit to convert an analog signal to a digital signal at a sampling rate of the SAR ADC circuit. The SAR ADC circuit generally includes a plurality of CDACs and a multi-input comparator having a plurality of inputs coupled to outputs of the plurality of CDACs. The conversion generally involves operating the multi-input comparator at a first clock rate equal to the sampling rate of the ADC circuit, and operating the plurality of CDACs at a second clock rate higher than the sampling rate of the SAR ADC circuit.

[0013] To achieve the above and related purposes, one or more aspects include features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative features of one or more aspects. However, these features are only indicative of several of the various ways in which the principles of the various aspects can be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to be able to understand in detail the manner in which the above features of the present disclosure are achieved, a more specific description of the content briefly summarized above may be made by reference to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate certain aspects of the present disclosure and therefore should not be considered as limiting the scope thereof, as the description may allow for other equally effective aspects.

[0015] Figure 1 is a block diagram and corresponding timing diagram of an example successive approximation register (SAR) analog-to-digital converter (ADC) circuit in which aspects of the present disclosure may be practiced;

[0016] Figure 2 An example power spectrum is provided, which shows the aliasing of unwanted frequencies into the frequency band of interest due to sampling;

[0017] Figure 3 is a block diagram of an example SAR ADC circuit having multiple capacitive digital-to-analog converters (CDACs) and multi-input comparators to implement an analog finite impulse response (FIR) filter to reduce aliasing according to certain aspects of the present disclosure;

[0018] Figure 4 is a circuit diagram of an example multi-input comparator according to certain aspects of the present disclosure;

[0019] Figure 5 According to certain aspects of the present disclosure Figure 3 An example timing diagram of an example implementation of a SAR ADC circuit;

[0020] Figure 6is a block diagram of an example SAR ADC circuit having multiple CDACs, multiple quantizers for coarse quantization, and multiple-input comparators for fine quantization according to certain aspects of the present disclosure;

[0021] Figure 7 According to certain aspects of the present disclosure Figure 6 Example timing diagram for an example SAR ADC circuit;

[0022] Fig. 8A is a block diagram of an example pipeline ADC circuit in which aspects of the present disclosure may be practiced;

[0023] Figure 8B yes Fig. 8A A block diagram of an example stage of a pipelined ADC circuit;

[0024] Fig.9A is a block diagram of an example pipeline ADC circuit according to certain aspects of the present disclosure, wherein an initial stage operates at a higher rate than a sampling rate of the ADC circuit;

[0025] Fig. 9B According to certain aspects of the present disclosure, Fig.9A an example power spectrum of an example input signal having both desired frequencies and undesired frequencies at various nodes in a pipeline ADC circuit of;

[0026] Fig.10 According to certain aspects of the present disclosure Fig.9A A block diagram of an example implementation of a pipeline ADC circuit; and

[0027] Fig.11 is a flow chart depicting example operations for signal conversion in accordance with certain aspects of the present disclosure.

[0028] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0029] Certain aspects of the present disclosure generally relate to an analog-to-digital converter (ADC) circuit with integrated aliasing suppression, wherein a portion of the ADC circuit operates at a higher sampling rate than other portions of the ADC circuit. For example, in a successive approximation register (SAR) ADC, multiple capacitive digital-to-analog converters (CDACs) can be coupled to a multi-input comparator to implement an analog finite impulse response (FIR) filter that is effectively integrated into the SAR operation. As another example, in a pipeline ADC, an initial stage(s) have a higher sampling rate than later stages(s), and additional anti-aliasing circuitry can be used in both the analog path and the digital path in the initial stage(s). By operating only a portion of the ADC circuit at a higher sampling rate than other portions of the ADC circuit, the ADC circuit can achieve aliasing suppression and can save power compared to a design in which the entire ADC circuit operates at a higher sampling rate.

[0030] Various aspects of the present disclosure will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings herein, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently of any other aspect of the present disclosure or implemented in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method, as a supplement or replacement of the various aspects of the present disclosure set forth herein, the device or method uses other structures, functions, or structures and functions to practice. It should be understood that any aspect of the present disclosure disclosed herein can be embodied by one or more elements of the claims.

[0031] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0032] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that component A is directly connected to component B or that other components may be connected between components A and B (i.e., component A is indirectly connected to component B). In the context of electrical components, the term "connected" may also be used herein to mean that a wire, trace, or other conductive material is used to electrically connect components A and B (and any components electrically connected therebetween). Example Successive Approximation Register Analog-to-Digital Converter

[0033] As mentioned above, there are several different types of analog-to-digital converters (ADCs), each with different advantages and disadvantages, which make some ADC types more suitable for specific applications than others. Successive approximation register (SAR) ADCs can provide an area and power efficient architecture for low to medium precision analog-to-digital conversion applications. SAR ADCs can use digital-to-analog converters (DACs), comparators, and logic to convert an analog input signal (continuous waveform) to a digital output signal (discrete time representation). The SAR ADC can use a binary search that goes through different quantization levels (e.g., different DAC step sizes) before converging on a final digital signal for output from the SAR ADC.

[0034] Figure 1 1 is a block diagram of an example SAR ADC circuit 100 and a corresponding timing diagram 150. Figure 1 As shown, the SAR ADC circuit 100 is implemented as a charge redistribution successive approximation ADC and, therefore, includes a capacitive digital-to-analog converter (CDAC) 102 (also referred to as a "charge scaling DAC"). The CDAC 102 may include a switched array of binary-weighted capacitors. In addition to the CDAC 102, the SAR ADC circuit 100 also includes a sample-and-hold switch S1, a comparator 104, and a SAR logic 106. The switch S1 may be coupled between an input node 108 of the SAR ADC circuit 100 and an output of the CDAC 102, which is also coupled to a positive input of the comparator 104. The negative input of the comparator 104 may be coupled to a reference potential node (e.g., electrical ground) of the SAR ADC circuit 100, and the output of the comparator 104 may be coupled to an input of the SAR logic 106. The SAR logic may have an output 110 that reflects the digital signal during quantization (e.g., during a binary search process) and the final digital signal at the end of quantization. As shown in FIG. Figure 1 As shown, output 110 can be fed back to the input of CDAC 102. The analog input signal (labeled “v i ”) is provided to the input node 108, and the digital output signal (labeled “d out ”) is available at output 110 of the SAR logic 106.

[0035] As shown in the timing diagram 150, the operation of the sample and hold switch S1 may be controlled by a sampling clock signal (labeled as “ck_s”) that is clocked at a sampling rate (f s , also called the “sampling frequency”) to the analog input signal (v i ) for sampling. The comparator 104 can be driven by a comparator clock (labeled as “ck comp”, also called “quantization clock”), which can be provided by SAR logic 106, as shown. During the conversion process, a SAR ADC with a nominal resolution of N bits can perform N comparisons with comparator 104 and generate a digital output signal with N bits. Therefore, the comparator clock (ck comp ) can have N pulses during each quantization interval.

[0036] Example Aliasing and Aliasing Suppression

[0037] Analog input signal (v i ) when received at the input of the ADC (e.g., at the input node 108 of the SAR ADC circuit 100), may include not only the desired signal, but may also have unwanted signals. Such unwanted signals may be out-of-band signals, and may be referred to as "jammers," such as in wireless communications and other applications. While some unwanted out-of-band signals may be filtered out before the signal content reaches the ADC, other unwanted signals may be folded back into the frequency band of interest due to aliasing and may be more difficult to suppress.

[0038] Figure 2 Includes example analog input signals (v i ) where the power spectral density (PSD) of the desired signal at a first frequency (f1) is similar to the PSD of the unwanted signal at a second frequency (f2). In this example, the ADC can be used at a sampling rate of f s The analog input signal is sampled at a first frequency in the frequency band of interest (for the receiver bandwidth, labeled “Rx-BW”) and a second frequency outside the frequency band of interest, the second frequency being less than the sampling rate of the ADC (but greater than the Nyquist rate f s / 2).

[0039] The sampling operation inside the ADC—that is, converting the analog input signal from the continuous time domain to the digital output signal in the discrete time domain—results in the power spectrum at frequencies greater than the Nyquist rate being folded back to 0 to f. s / 2, such as the digital output signal (d out ) is shown in the power spectrum 210. In the power spectrum 210, due to the nature of sampling, f s The nearby unwanted signal has been aliased back into the band of interest (Rx BW) and now appears at frequency f s -f2 appears. This aliasing interference will reduce the ADC's signal-to-noise ratio (SNR) and may reduce the effective resolution (i.e., reduce the effective number of bits (ENOB)).

[0040] Many techniques have been implemented to deal with this aliasing caused by sampling. One technique is to use an analog anti-aliasing filter (AAF) before the ADC to suppress unwanted signals before sampling, so that the unwanted signals that are folded back into the band of interest have much lower power and may not reduce the effective resolution. The AAF can be implemented in continuous time (e.g., a biquadratic low-pass filter) or in discrete time (e.g., an FIR filter running at a rate higher than the sampling rate of the ADC). However, in some space-limited applications, it may be challenging to design an analog AAF with a suitably steep roll-off for anti-aliasing that does not take up too much area. Another technique is to increase the sampling rate of the ADC to prevent aliasing, and perform filtering in the digital domain after sampling. In this way, complex high-order digital filters can be used for aliasing suppression. Time interleaving is an example method for increasing the sampling rate.

[0041] Example SAR ADC Circuit with Integrated Alias ​​Suppression

[0042] As another technique for addressing aliasing, certain aspects of the present disclosure provide a SAR ADC circuit that includes a discrete-time filter (e.g., a finite impulse response (FIR) filter internal to the SAR operation) so that rather than quantizing a single input sample, a linear combination of several consecutive samples is quantized. To achieve this, the SAR ADC circuit may include multiple capacitive digital-to-analog converters (CDACs) and multiple-input comparators, where over time, the inputs of the comparators are presented with different combinations of input samples and DAC signals. In this way, effectively, only a portion of the ADC is sampled at a rate greater than the sampling rate (f s ) at a higher rate, thereby preventing aliasing while saving power (compared to an implementation where the entire ADC operates at a higher rate).

[0043] Figure 3 3021, 3022, 3023, 3024, 3025, 3026, 3027, 3028, 3029, 3030, 3031, 3032, 3033, 3034, 3035, 3036, 3037, 3038, 3039, 3040, 3041, 3042, 3043, 3044, 3045, 3046, 3047, 3048, 3049, 3050, 3051, 3052, 3053, 3054, 3055, 3056, 3057, 3058, 3059, 3060, 3061, 3062, 30 m304; and SAR logic 306. Each of the CDACs 302 may include, for example, a switch array of binary weighted capacitors. Each of the sample and hold switches S1, S2, ..., Sm may be controlled by a corresponding sampling clock signal ck_s1, ck_s2, ..., ck_sm. In addition, each of the sample and hold switches S1, S2, ..., Sm may be coupled between the input node 108 of the SAR ADC circuit 300 and the output of the corresponding CDAC, which is also coupled to a corresponding positive input of the multi-input comparator 304. In other words, the multi-input comparator 304 has multiple positive inputs coupled to the outputs of the CDACs 302, wherein one of the CDAC outputs may be coupled to one of the comparator inputs. The negative input of the multi-input comparator 304 may be coupled to a reference potential node (e.g., electrical ground) of the SAR ADC circuit 300, and the output of the comparator 304 may be coupled to an input of the SAR logic 306. The inputs of the multi-input comparator 304 have different weights, which can be achieved by using input transistors of different sizes in the multi-input comparator.

[0044] Figure 4 4 is a circuit diagram of an example multi-input comparator 400 according to certain aspects of the present disclosure. The multi-input comparator 400 can be used to implement a multi-input comparator having three differential input signals. Figure 3 The multi-input comparator 304. Although Figure 4 Three differential input signals are shown in the multi-input comparator 400 , but it should be understood that the multi-input comparator can be implemented with two, four, or more input signals, which can be differential or single-ended.

[0045] like Figure 4 As shown, the multi-input comparator 400 may include transistors M1-M15, wherein transistors M1-M8 and M13-15 are implemented as n-type field effect transistors (NFETs), and wherein transistors M9-M12 are implemented as p-type field effect transistors (PFETs). The multi-input comparator 400 may include multiple input transistor pairs coupled in parallel. In this way, the drains of transistors M1, M3, and M5 may be coupled to the same node 402, and the drains of transistors M2, M4, and M6 may also be coupled to the same node 404. The gates of transistors M1 and M2 may receive a first differential input signal V1+ / V1-, the gates of transistors M3 and M4 may receive a second differential input signal V2+ / V2-, and the gates of transistors M5 and M6 may receive a third differential input signal V3+ / V3-. In order to implement Figure 3In the single-ended SAR ADC circuit 300, the gates of transistors M2, M4, and M6 for complementary differential input signals (e.g., V1-, V2-, and V3-) can be coupled to a reference potential node (e.g., electrical ground) of the SAR ADC circuit. Transistors M13-M15 can be used as tail transistors of an input transistor pair, each tail transistor having a drain coupled to a source of a corresponding input transistor pair and having a source coupled to a reference potential node (e.g., electrical ground) of the multi-input comparator 400.

[0046] The sources of transistors M9-M12 may be coupled to a power rail (labeled “VDD”), wherein the drains of transistors M11 and M12, the gate of transistor M10, and the drain of transistor M8 may be coupled to a positive output node (labeled “Vout+”), and wherein the drains of transistors M9 and M10, the gate of transistor M11, and the drain of transistor M7 may be coupled to a negative output node (labeled “Vout-”) of the comparator. The source of transistor M7 may be coupled to node 402, and the source of transistor M8 may be coupled to node 404. The gates of transistors M9, M12, and M13-15 may be coupled to a clock node (labeled “ck”, which may receive a comparator clock signal, such as ck comp ).

[0047] The weighting of the desired FIR function can be achieved by appropriate sizing of the transistors in the comparator 400. For example, to implement a FIR filter with coefficients [a1 a2 a3] =

[121] , Figure 4 As shown, the transistors in the input transistor pair M3 and M4 (and the tail transistor M14) can each be twice as large as the transistors in the input transistor pair M1 and M2 (and the tail transistor M13) and the input transistor pair M5 and M6 (and the tail transistor M15). In this way, different inputs of the multi-input comparator can be designed to have different weights. Although the weights are integers in this example, it should be understood that the weights (as implemented by the gain of the transistors) can be any positive real number. If the comparator input is not used for a specific conversion, the clock to the gate of the corresponding tail transistor in the input transistor pair can be disabled. This can present a high input impedance on this specific input, which can avoid distorting the CDAC voltage corresponding to the comparator input.

[0048] return Figure 3 SAR logic 306 may have an output 110 that reflects the digital signal (d out ) and the final digital signal at the end of quantization. Output 110 can be fed back to the input of CDAC302, such as Figure 3SAR logic 306 can be configured to generate a sampling rate (f s ) produces a digital output signal at its output.

[0049] In the SAR ADC circuit 300, the digital output signal (d out ) is an input voltage signal (v ) at the input node 108 based on the operation of the switches S1, S2, ..., Sm i ) is a linear weighted combination of different samples in the time domain. In other words, according to the following equation, the digital output signal (d out ) is a linearly weighted combination of the input signal and one or more delayed versions of the input signal:

[0050] d out =a1 v i [k]+a2 v i [k-1]+...+a n vi[k-n+1]

[0051] where a1, a2, ..., a n are the coefficients of the n-tap FIR filter, v i [k] is the current input voltage signal sample, v i [k-1] is the immediately previous sample in time, and v i [k-n+1] is the (n-1)th previous sample in time. The rate of the FIR filter is determined by the sampling clock signals ck_s1, ck_s2, ..., ck_sm and is higher than the ADC sampling rate (f s As mentioned above, the coefficients a1, a2, ..., a of the SAR integrated FIR filter are n is set by assigning weights (eg, parallel input transistor size ratios) to the inputs of the multi-input comparator 304. In addition, a weighted addition of consecutive samples is performed by the comparator 304 as described below.

[0052] although Figure 3 The SAR ADC circuit 300 is shown implemented as a single-ended circuit, but it should be understood that the SAR ADC circuit can be implemented as a fully differential circuit. In this case, the input analog signal will be a differential signal, the CDAC has positive and negative arrays of switched capacitors, and the comparator input is differential (e.g. Figure 4 4 (shown in a multi-input comparator 400).

[0053] Figure 5 is a CDAC having m=4 according to certain aspects of the present disclosure Figure 3An example timing diagram 500 of an example implementation of a SAR ADC circuit 300 and an FIR filter with n=3 taps, the FIR filter sampling at twice the sampling rate of the SAR ADC circuit (2f s ) is running. Since the FIR filter has 3 taps, at least three CDACs 302 (CDAC1, CDAC2, and CDAC3) may be involved in the quantization, during which the SAR loop is operating. However, since the FIR filter is designed in this example to operate at 2f s Run, so it should be every (2f s ) -1 Get a new sample (such as the input clock signal (labeled as "ck in ”). Therefore, in this example, the fourth CDAC (CDAC4) is used to sample the input voltage signal (v4), while the other three CDACs (CCA1, CDAC2 and CDAC3) in the SAR loop are busy.

[0054] Thus, as shown in timing diagram 500, one of the four CDACs is sampled (denoted by "S") in the middle of a conversion (denoted by "Q" for quantization) performed by the other three CDACs. Here, v i represents the voltage corresponding to CDACi, so v1 represents the voltage at the output of CDAC1, v2 represents the voltage at the output of CDAC2, v3 represents the voltage at the output of CDAC3, and v4 represents the voltage at the output of CDAC4. In each cycle Ts (=1 / f s ), the SAR ADC circuit 300 completes a sampling and quantization cycle. The sampling sequence is repeated with the sample and hold switches S1, S4, S2, and S3 (as controlled by the pulses on the sampling clock signals ck_s1, ck_s4, ck_s2, and ck_s3). In this way, each individual sampling clock signal (e.g., ck_s1) is repeated every 2Ts (=2 / f s ) for analog input signal (v i ) for sampling.

[0055] To implement an FIR filter with coefficients [1 2 1] (i.e., where a1=1, a2=2, and a3=1), the inputs from the outputs of CDAC1 and CDAC2 to the multi-input comparator 304 are weighted with a coefficient of 1, while the inputs from the outputs of CDAC3 and CDAC4 to the multi-input comparator 304 are weighted with a coefficient of 2.

[0056] Thus, the kth sample may be the voltage v2 at the output of CDAC2, the k-1th sample may be the voltage v4 (or v3) at the output of CDAC4 (or CDAC3), and the k-2th sample may be the voltage v1 at the output of CDAC1, according to the sampling order as described above and as shown in timing diagram 500. In other words, the timing is set so that the voltages v3 and v4 (at the outputs of CDAC3 and CDAC4) fall on the k-1th sample (and have a coefficient of 2) during each quantization.

[0057] Figure 5 The timing diagram 500 provides a method for implementing the SAR ADC circuit internally with 2f s One example timing for running a 3-tap FIR filter. However, it should be understood that other solutions with different timings (eg, different sample order and / or different FIR speeds) are possible.

[0058] Figure 6 602 is a block diagram of another example SAR ADC circuit 600 with internal aliasing suppression according to certain aspects of the present disclosure. The SAR ADC circuit 600 includes m sample and hold switches S1, S2, ..., Sm; m CDACs 6021, 6022, ..., 602 m (collectively referred to herein as “CDAC 602”); m quantizers 6031, 6032, ..., 603 for coarse quantization m (collectively referred to herein as "quantizer 603"); a multi-input comparator 304 for fine quantization; and a SAR logic 606. Each of the CDACs 602 may include, for example, a switch array of binary weighted capacitors. Each of the sample and hold switches S1, S2, ..., Sm may be controlled by a corresponding sampling clock signal ck_s1, ck_s2, ..., ck_sm. In addition, each of the sample and hold switches S1, S2, ..., Sm may be coupled between the input node 108 of the SAR ADC circuit 600 and the output of the corresponding CDAC, which is also coupled to the corresponding positive input of the multi-input comparator 304 and to the input of the corresponding quantizer.

[0059] The quantizers 603 may be implemented by relatively low resolution (eg, 4-bit) ADCs for coarse quantization. Each of the quantizers 603 has a corresponding coarse digital output d c1 ,d c2 ,……,d cm , the coarse digital output is coupled to the more significant bit control input (e.g., one or more most significant bits (MSBs)) of the corresponding CDAC, such as Figure 6 shown.

[0060] The coarse quantization from the quantizer is effectively subtracted from the sampled input signal by the corresponding CDAC. Therefore, the input of the multi-input comparator 304 represents the residual (i.e., quantization error) of the quantizer and is therefore smaller. This prevents or at least reduces the non-linear characteristics of the comparator 304.

[0061] The output of comparator 304 may be coupled to the input of SAR logic 606. Figure 6 As shown, the SAR logic 606 may have a fine digital output d that reflects the quantization period (eg, during a binary search process). fine The SAR logic 606 (or other logic, not shown) may have an output 612 that is coupled to a less significant bit control input (e.g., one or more least significant bits (LSBs)) of each CDAC 602. out ) output 110, the final digital signal is from a plurality of quantizers (d ci ) of a quantizer in the coarse quantization and fine quantization d fine The SAR logic 606 (or other logic) may be configured to calculate the weighted addition of the SAR ADC circuit 600 according to the sampling rate (f s ) produces a digital output signal at output 110.

[0062] According to some aspects, the final digital signal (d out ) can be based on the coarse quantization output (d c1 d c2 ,……,d cm ) and fine quantization d fine This implementation can be utilized in one or more of the techniques and devices described below.

[0063] Figure 7 is a circuit having m=4 CDACs (CDAC1-CDAC4) and at twice the sampling rate (2f s ) operates the multi-input comparator Figure 6 An example timing diagram 700 of the example SAR ADC circuit 600 is shown.

[0064] Three CDACs 302 (eg, CDAC1, CDAC2, and CDAC3) may be involved in fine quantization, during which the SAR loop is operating. However, since new samples are designed to be every (2f s ) -1 Get once (such as the input clock signal (marked as "ck in”), so in this example, a fourth CDAC (CDAC4) is used to i ) and performs coarse quantization (at Q c4 period), while the other three CDACs (CDAC1, CDAC2 and CDAC3) in the SAR loop are busy.

[0065] Thus, as shown in timing diagram 700, one of the four CDACs is quantized during fine quantization (denoted by “Q fine ”) during sampling (indicated by “S”). Here, Q ci represents the coarse quantization in the corresponding CDACi, so for example, Q c4 Indicates the coarse quantization in CDAC4. In each cycle Ts (=1 / f s ) period, the SAR ADC circuit 600 completes the sampling and quantization cycle (here, coarse quantization is performed first, and then fine quantization is performed). The sampling sequence, i.e., the sampling and holding switches S1, S4, S2, and S3, are repeated in sequence according to the control of the pulses on the sampling clock signals ck_s1, ck_s4, ck_s2, and ck_s3. In this way, each individual sampling clock signal (e.g., ck_s1) is repeated every 2Ts (=2 / f s ) for analog input signal (v i ) for sampling.

[0066] Figure 7 The timing diagram 700 of FIG. 7 provides an example timing for implementing a SAR ADC circuit with internal aliasing rejection. However, it should be understood that other solutions with different timings (eg, different sample orders) are possible.

[0067] Example Pipeline ADC

[0068] Pipeline analog-to-digital converters (ADCs) and other multi-stage ADCs can be used for high-speed and power-efficient analog-to-digital conversion in devices, such as in the receive chain of a transceiver in a fifth generation (5G) (or other radio access technology) wireless device. Pipeline ADCs can be used, for example, with sampling rates from a few megasamples per second (Msps) to around a thousand Msps and higher.

[0069] Fig. 8A800 is a block diagram of an example pipeline ADC circuit 800, but other multi-stage ADC circuits may also be represented. The pipeline ADC circuit 800 includes N stages 802a, 802b, ..., 802n (collectively referred to herein as "stages 802") and a decoder 804 (also referred to as a "digital combiner"), where N is a positive integer greater than 1. Although shown as a single-ended ADC circuit, the pipeline ADC circuit 800 may alternatively be implemented as a differential ADC circuit.

[0070] The first stage (eg, stage 1) of the pipeline ADC circuit 800 may receive an analog input signal (labeled “v in ”). Each stage of the pipeline ADC circuit 800 can be configured to output one or more bits (as well as an analog residual for passing to the next stage, as described below). Fig. 8A As shown, each stage can be operated at a sampling frequency (f s ) to generate the output bit(s) of the stage. The bit(s) (labeled “d1”) output by the first stage (e.g., stage 1) of the pipeline ADC circuit 800 may represent the digital output (labeled “d out ”) and the bit(s) output by the last stage (e.g., stage N) of the pipeline ADC circuit 800 (labeled “d N ”) may represent the least significant bit(s) (LSB) of the digital output. The outputs from these stages are coupled to the input of a decoder 804. The decoder 804 is used to combine the output bit(s) from stage 802 to generate a complete digital output. As shown, the digital output may be the sum of the bit(s) output by each stage of the pipelined ADC circuit 800 (e.g., after taking into account the relative importance of the bits).

[0071] Figure 8B yes Fig. 8A 850 is a block diagram of an example stage 850 of a pipelined ADC circuit 800. The example stage 850 can represent any stage 802 in the pipelined ADC circuit, but for the last stage (e.g., stage N). As shown, the stage 850 includes at least an ADC 852, a digital-to-analog converter (DAC) 854, an analog combiner 856, and an amplifier 858 (also referred to as a "gain stage"). The ADC 852 can be a relatively low resolution ADC and can be implemented, for example, by a flash ADC or any other suitable type of ADC.

[0072] ADC 852 has one or more input nodes 851 for receiving one or more analog inputs (labeled as “ i”, referred to herein as “stage input analog signal”). The one or more analog inputs may include an analog input signal to the pipeline ADC circuit 800 (in the case of the first stage) or a residual output of the previous stage of the pipeline ADC circuit 800 after quantization (in the case of a stage other than the first stage). Although illustrated with a single input node, in some cases, the ADC 852 may alternatively be implemented with a differential input node pair. The ADC 852 may be based on the analog input(s) and at the sampling frequency (f s ) generates a digital output (labeled “d o ”). Having an input coupled to the output of ADC 852, DAC 854 can receive the digital output signal of ADC 852 as an input signal. DAC 854 converts the digital input received from ADC 852 back into an analog voltage (referred to herein as a “level intermediate analog signal” and labeled “v i* ”). Although shown as having a single output node, DAC 854 may also be implemented with a differential output node pair. Analog combiner 856 may then output the voltage difference between the analog input(s) to the stage and the analog output(s) from DAC 854 (e.g., the stage intermediate analog signal at node 855 may be subtracted from the stage input analog signal at node 851). This voltage difference is referred to as the “residual voltage” (or “stage resident signal”) for a given stage, and is Figure 8B The res For some aspects, the residual voltage may be output from stage 850 as an output voltage (labeled “v o ”, also referred to as the “stage output analog signal”) is amplified by amplifier 858 before being output. Amplifier 858 may be implemented by any suitable type of amplifier. The residual voltage (or an amplified version thereof) may be used as an input to subsequent stages of the pipelined ADC circuit 800. Thus, each stage (with the typical exception of the last stage) may have two outputs: a digital output and a residual output.

[0073] Example Pipeline ADC Circuit with Integrated Alias ​​Suppression

[0074] As mentioned above about Figure 2 As described above, the sampling operation of an ADC (e.g., a pipeline ADC or other multi-stage ADC) may result in aliasing, where unwanted signals may fold back into the bandwidth of interest and reduce the signal-to-noise ratio (SNR) of the ADC. Certain aspects of the present disclosure provide a pipeline ADC in which the initial one or more stages are sampled at a rate faster than the output rate (f s) at a higher rate, rather than using an analog anti-aliasing filter before the ADC or increasing the sampling rate of the ADC. By operating only the initial stage (or stages) at a higher rate, the pipeline ADC achieves aliasing suppression while saving power compared to solutions where all stages, especially the interstage amplifiers between stages, are operated at a higher rate.

[0075] Fig.9A 900 is a block diagram of an example pipeline ADC circuit 900 having two stages: an initial stage 901 followed by a final stage 902. The initial stage 901 operates at a clock rate that is M times the clock rate of the final stage 902, which is equal to the total sampling rate (f s ), where M is any number greater than 1 and may be a fractional number (i.e., M is not necessarily limited to an integer). Although only one initial stage 901 is shown, it should be understood that a pipeline or other multi-stage ADC circuit may include a plurality of initial stages 901, each of which may be a plurality of initial stages 902. s Furthermore, although only one final stage 902 is shown, it should be understood that a pipeline or other multi-stage ADC circuit may include multiple initial stages of operation. s For some aspects, the pipeline ADC circuit 900 may also include a sampling switch 903 for sampling at a higher sampling rate (Mf s ) to sample the input voltage.

[0076] In addition to the above Fig. 8A In addition to the components described in Level 850, Fig.9A The initial stage 901 in may also include an analog filter 904, an analog downsampler 906, a digital filter 908, and a digital downsampler 912. The analog filter 904 may have an input coupled to the output of the combiner 856, and the analog downsampler 906 may have an input coupled to the output of the analog filter 904. The analog downsampler 906 may also have an output coupled to the input of the amplifier 858. Similarly, the digital filter 908 may have an input coupled to the output of the ADC 852 at node 853, and the digital downsampler 912 may have an input coupled to the output of the digital filter 908. The digital downsampler 912 may also have an output coupled to the input of the decoder 804.

[0077] like Fig.9A As shown, for example, analog filter 904 may have a transfer function H(z) to implement an analog low-pass filter. For certain aspects, the low-pass filter may be designed to obtain a signal from the initial stage residual signal (v res ) to filter out the Nyquist frequency (f s / 2). The analog filter 904 can be used to filter the initial stage residual signal (v res ) is filtered to generate the initial stage filtering residual signal (marked as “v h ”). Because ADC 852 and DAC 854 (and in some aspects, switch 903) operate at a higher sampling rate (Mf s ) operation, so the analog downsampler 906 can downsample the initial stage filtered residual signal to generate a signal with lower frequency content (e.g., with f s The initial downsampled residual signal (marked as “v m ”). The analog downsampler 906 may not be an explicit component, and in this case its operation may be performed by subsequent components at a rate of 1 / f s For signal v h In other words, the analog downsampler 906 may not be a physical circuit, but rather Fig.9A is shown in to illustrate the parallelism between the analog and digital paths of the initial stage 901.

[0078] Similarly, the digital filter 908 may also have a transfer function H(z) (or substantially equivalent to H(z)) to implement, for example, a digital low-pass filter that matches the frequency behavior of the analog filter 904. For certain aspects, the low-pass filter may be designed to filter out frequencies greater than the Nyquist frequency (f ) of the pipeline ADC circuit 900 from the initial stage digital signal (d1). s / 2). The digital filter 908 can filter the initial stage digital signal (d1) to generate an initial stage filtered digital signal (labeled as “d h ”). Because ADC 852 and DAC 854 are sampling at a higher rate (Mf s ) operation, the digital downsampler 912 can downsample the initial stage filtered digital signal to generate a signal having lower frequency content (e.g., with f s The initial downsampled digital signal (marked as “d m ”). The digital downsampler 912 may downsample the signal d by, for example, ignoring samples (e.g., keeping only every Mth sample) or combining samples (e.g., combining each group of M samples into a single sample). h Downsampling is performed.

[0079] For certain aspects, the pipeline ADC circuit 900 may include another digital filter 910 between the digital filter 908 and the digital downsampler 912. In this case, the input of the digital filter 910 may be coupled to the output of the digital filter 908, and the output of the digital filter 910 may be coupled to the input of the digital downsampler 912. The digital filter 910 may have a transfer function G(z) to implement another digital low-pass filter in the digital path of the initial stage 901. For example, the digital filter 910 may be implemented as a FIR filter. The transfer function G(z) may have a steeper roll-off and may implement a filter of a higher order than the filter implemented by the transfer function H(z). For certain aspects, the digital filter 910 may be programmable so that the transfer function G(z) may be changed. In this way, the digital filter 910 may provide a knob for adjusting aliasing suppression, ranging from no additional suppression to strong aliasing suppression. The digital filter 910 may implement a high-order filter while occupying a relatively small area and consuming relatively small power.

[0080] In addition, the digital filter 910 can be configured to be selectively bypassed, or can be programmed to effectively have a unity transfer function (G(z)=1) (e.g., by a controller associated with the pipeline ADC circuit 900). For example, when the presence of a strong jammer (or other signal with an unwanted frequency of relatively high power) is detected, the digital filter 910 can be used in the digital path for additional aliasing rejection. However, after a certain interval or after the jammer (or other specific signal) is no longer detected, the controller can configure the pipeline ADC circuit 900 to bypass the digital filter 910 or reduce the filtering rejection of the digital filter 910.

[0081] When the digital filter 910 exists, the digital filter 910 can also perform the initial stage digital filtering signal (d h ) to generate an initial stage further filtered digital signal (labeled as “d g ”). The digital downsampler 912 can then further filter the initial stage digital signal (d g ) to generate a signal with lower frequency content (e.g., with f s more compatible) initial stage downsampled digital signal (d m ).

[0082] For the pipeline ADC circuit 900 described above, a higher sampling rate (Mf s ) can be used by the initial stage 901 to avoid unwanted signals (for M=2, the frequency is at f s / 2 to f s904 and 908). Further aliasing filtering may be performed in the digital domain using an optional digital filter 910.

[0083] Furthermore, in a two-stage pipeline ADC circuit such as ADC circuit 900, the interstage amplifier (e.g., amplifier 858) can be the most challenging portion to design. Certain aspects of the present disclosure allow the amplifier to operate at a lower rate than the rest of the stage because an analog downsampler can be used before the amplifier.

[0084] The final stage 902 may include an ADC 914 having its input coupled to the output of the amplifier 858 of the previous stage (e.g., the initial stage 901). The ADC 914 may be implemented as a SAR ADC, a flash ADC, or any other suitable type of ADC. The ADC 914 may receive the initial stage output analog signal (e.g., the amplified residual signal (v) from the amplifier 858). o )) as the final input analog signal. ADC 914 can sample at the sampling rate (f s ) converts the received analog signal into a final stage digital signal (e.g., the digitized residual, but labeled here as stage 2 output d2). In this way, later stages of the pipeline ADC circuit do not waste power operating at a higher sampling rate.

[0085] Initial stage downsampled digital signal d m can be used as the digital output signal of the initial stage 901. As described above, the digital signal d m Both digital signals d1 and d2 are sent to decoder 804 for bit combination and generation of the output digital signal d2 from the pipeline ADC circuit. out .

[0086] Fig. 9B Provided Fig.9A Example power spectra at various nodes in the pipeline ADC circuit 900 of FIG. 9, showing the relationship between power spectral density (PSD) and frequency. In this example, the initial stage 901 is at 2f s (i.e., M=2), and the last stage 902 operates at f s run.

[0087] Analog input signal (v i) shows an input signal with a desired frequency f1 (or a frequency range centered around or including frequency f1) and an undesired frequency f2 (or a frequency range centered around or including frequency f2) for M=2. s ) and converted by ADC 852, the power spectrum 952 of the initial stage digital signal (d1) shows content at both the desired frequency and the unwanted frequency, but there is no aliasing of the unwanted frequency f2. The sampling and conversion also introduces a certain level of noise 953 into the power spectrum 952. In other words, because the unwanted frequency f2 is below the Nyquist frequency of ADC 852, there is no foldback of the unwanted frequency.

[0088] After the initial stage digital signal (d1) is low-pass filtered by a digital filter 908 having a transfer function H(z), the initial stage filtered digital signal (d h ) shows a reduction in the power of the unwanted frequency f2 (labeled “A H ”). In this example, the initial stage filtered digital signal (d h ) is further low-pass filtered, and the resulting initial stage further filtered signal (d g ) shows a further reduction in the power of the unwanted frequency f2 (labeled “A G ”), resulting in a total reduction in the power of the unwanted frequency f2 (marked as “A tot ”) is the sum of these two reductions (i.e., A tot =A H +A G , as shown in power spectrum 970).

[0089] The digital downsampler 912 can further filter the initial stage digital signal (d g ) is digitally downsampled to generate an initial downsampled digital signal (d m ). The initial stage downsampled digital signal (d m ) shows the power spectrum 958 at the effective Nyquist frequency of the downsampler (here f s / 2), so that the content at the unwanted frequency f2 is folded back to the vicinity of the desired frequency f1 (i.e., at f s -f2), but with much lower power compared to power spectrum 952. As shown in example power spectrum 958, the aliased unwanted content is not significantly above the noise floor.

[0090] For the analog path in the initial stage 901, the initial stage residual signal (v res ) shows the power spectrum 962 of the initial stage input analog signal (v i ) and the initial intermediate analog signal (v i* ), leaving what appears to be noise 953. This noise in power spectrum 962 represents the quantization error of initial stage 901, with a PSD of Fig. 9B The initial stage residual signal (v res ) is low-pass filtered, the initial filter analog signal (v h ) shows a reduction in power at higher frequencies.

[0091] The analog downsampler 906 can filter the initial stage analog signal (v h ) is downsampled to generate the initial downsampled analog signal (v m ). The initial stage downsampled digital signal (d m ) shows a power spectrum 968 that is greater than the effective Nyquist frequency of the downsampler (here f s / 2) of the frequency content is folded back into the frequency band of interest. The final stage 902 can quantize the initial stage downsampled analog signal (v m ) to generate a final stage digital signal (d2), the power spectrum 969 for the final stage digital signal (d2) has a similar shape to the power spectrum 968. The quantization error of the final stage 902 is not shown.

[0092] The decoder 804 combines the initial stage down-sampled digital signals (d m ) and the final digital signal (d2), the output digital signal d out The power spectrum 970 of shows a high signal-to-noise ratio (SNR) for the desired frequency f1. Some quantization noise may remain at higher frequencies, as shown in the power spectrum 970. For example, this may be due to a mismatch between aliasing filtering in the analog and digital paths of the pipeline ADC circuit (e.g., different attenuation of the analog and digital filters at higher frequencies).

[0093] Fig.10 According to certain aspects of the present disclosure Fig.9A 1 is a block diagram of an example pipeline ADC circuit 1000 of the pipeline ADC circuit 900. The pipeline ADC circuit 1000 combines aspects of both the SAR ADC and pipeline ADC circuits described above, wherein an analog FIR filter is implemented in the first stage to reduce aliasing. Fig.101000 is shown as a single-ended implementation, but it should be understood that the pipeline ADC circuit 1000 can be implemented as a fully differential circuit.

[0094] like Fig.10 As shown, pipeline ADC circuit 1000 includes a first stage 1050, a second stage 1052, and logic 1012. However, it should be understood that the pipeline ADC circuit may include more than two stages.

[0095] As shown, the first stage 1050 of the pipeline ADC circuit 1000 includes a pair of sampling and holding switches Sa1 and Sb1 (also referred to herein as a "first set of switches"), a pair of CDACs 1002a and 1002b (collectively referred to herein as "CDACs 1002"), a pair of quantizers 1003a and 1003b for coarse quantization (collectively referred to herein as "quantizers 1003"), a pair of amplifying switches Sa2 and Sb2 (also referred to herein as a "second set of switches"), an amplifier 1004, a feedback capacitive element Cf, and a reset switch Sf. Each of the CDACs 1002 may include, for example, a switch array of binary weighted capacitors. Each of the sampling and holding switches Sa1 and Sb1 may be controlled by a corresponding sampling clock signal ck_s1 and ck_s2. In addition, each of the sampling and holding switches Sa1 and Sb1 may be coupled between the input node 1001 of the pipeline ADC circuit 1000 and the output of the corresponding CDAC, which is also coupled to the input of the corresponding quantizer. For example, switch Sa1 is coupled at one end to CDAC 1002a (labeled "CDAC1") and quantizer 1003a (labeled "QzrA"), and switch Sb1 is coupled at one end to CDAC 1002b (labeled "CDAC2") and quantizer 1003b (labeled "QzrB").

[0096] Quantizer 1003 may be similar to Fig.9A ADC 852 or Figure 6 quantizer 603, and can be sampled at a rate (f s )High sampling rate (Mf s , such as 2f s ) operation. Therefore, Fig.10 Each of the quantizers 1003 may be implemented, for example, by a flash ADC, a SAR ADC, or any other suitable type of ADC. Each of the quantizers 1003 has a corresponding coarse digital output d cA or cB , the coarse digital output is coupled to the input of the corresponding CDAC. Therefore, CDAC1002 can be similar to Fig.9A DAC 854.

[0097] The output of CDAC 1002 can be coupled to the negative input of amplifier 1004 via an amplifying switch, which can be controlled via a control signal ck_amp. Fig.10 As shown, switch Sa2 may be coupled between the output of CDAC 1002a and the negative input of amplifier 1004, and switch Sb2 may be coupled between the output of CDAC 1002b and the negative input of amplifier 1004. Amplifier 1004 may be similar to an interstage amplifier of a pipeline ADC circuit (e.g., similar to Fig.9A 858 of the amplifier 1004), and can provide a certain gain. The positive input of the amplifier 1004 can be coupled to the reference potential node (e.g., electrically grounded) of the pipeline ADC circuit 1000. The feedback capacitive element Cf can be coupled between the output of the amplifier at node 1009 and the negative input of the amplifier, and the reset switch Sf can be coupled in parallel with the feedback capacitive element Cf. The reset switch Sf can be controlled by a control signal ckb_amp complementary to the control signal ck_amp of switches Sa2 and Sb2. In other words, when switches Sa2 and Sb2 are disconnected, the reset switch Sf can be closed to discharge the feedback capacitive element Cf, and when switches Sa2 and Sb2 are closed, the reset circuit Sf can be disconnected to allow the feedback capacitive element Cf to charge.

[0098] The second stage 1052 includes a quantizer 1010, which may represent, for example, one or more later stages of a pipeline ADC and may be similar to Fig.9A 914 of the pipelined ADC circuit 1000. Thus, the quantizer 1010 may be implemented as a SAR ADC, a flash ADC, or any other suitable type of ADC. The quantizer 1010 may be coupled to the output of the amplifier 1004 at node 1009 and receive the first stage output analog signal (e.g., from the amplifier 1004) as the final stage input analog signal. The quantizer 1010 may be implemented as a SAR ADC, a flash ADC, or any other suitable type of ADC. s ) converts the received analog signal into a final digital signal (e.g., the digitized residual, here labeled “d fine ”). In this way, later stage(s) of the pipeline ADC circuit do not waste power by operating at a higher sampling rate.

[0099] Logic 1012 may be similar to Fig. 8A and Fig.9A The logic 1012 may receive the coarse quantization d from the quantizers 1003a and 1003b, respectively. CA and d CB and the fine quantization d from the quantizer 1010 fine , and combine them to produce a digital output signal d outFor certain aspects, logic 1012 may implement additional digital signal processing, such as for coarse quantization d CA and d CB A digital filter (e.g., similar to Fig.9A digital filter 908 and / or digital filter 910).

[0100] During operation of the pipeline ADC circuit 1000, the sampling clock signals ck_s1 and ck_s2 may operate according to the higher sampling rate of the first stage 1050 to continuously sample the analog input signal (v i ) is sampled and the capacitors of CDAC 1002 are charged (e.g., CDAC1 is charged with charge Q1 and CDAC2 is charged with charge Q2). When it is time to amplify the sample with amplifier 1004, switches Sa2 and Sb2 may be closed (via ck_amp) and reset switch Sf may be opened (via ckb_amp), thereby charging the feedback capacitive element Cf with charge Qf, which is a proportional version of charges Q1 and Q2 (i.e., amplifier output α(Q1+Q2)). For two consecutive samples (V k and V k-1 , similar to Figure 6 SAR ADC circuit 600), the output can therefore be compared with C (V k +V k-1 ), where C is the capacitance of the feedback capacitive element Cf. This is roughly equivalent to having a transfer function H(z)=(1+z -1 ) / 2, which is a low pass filter with unity gain at low frequencies and attenuation at the sampling rate of the pipelined ADC circuit 1000. In this way, the pipelined ADC circuit 1000 can implement some of the functionality of the above circuit using an internal 2-tap FIR filter operating at a higher sampling rate in the first stage 1050 for aliasing suppression.

[0101] For the pipeline ADC circuit described herein, only a portion of the ADC circuit (eg, an initial stage) is operated at a higher rate for aliasing suppression, thereby saving power compared to an implementation where all stages are operated at a higher rate.

[0102] Example Transformation Operation

[0103] Fig.11 1 is a flow chart depicting example operations 1100 for signal conversion according to certain aspects of the present disclosure. Operation 1100 may be performed by an ADC circuit (e.g., Figure 3 SAR ADC circuit 300, Figure 6 SAR ADC circuit 600, Fig.9AThe pipeline ADC circuit 900 or Fig.10 ADC circuit 1000) is executed.

[0104] Operations 1100 may include, at block 1110, sampling the ADC circuit at a sampling rate (eg, f s ) to convert the analog signal to a digital signal. The conversion of block 1110 may include: at block 1112, operating a first circuit portion of the ADC circuit at a first clock rate equal to a sampling rate of the ADC circuit, and at block 1114, operating a first circuit portion of the ADC circuit at a second clock rate (e.g., 2f s or Mf s ) operates a second circuit portion of the ADC circuit. The second clock rate is higher than a sampling rate of the ADC circuit. For example, the second clock rate may be greater than or equal to twice the sampling rate of the ADC circuit. In another example, the second clock rate may be between one and two times the sampling rate of the ADC circuit.

[0105] According to certain aspects, operating the second circuit portion at block 1114 may involve operating an analog finite impulse response (FIR) filter (e.g., a multi-input comparator 400 with weighted transistors or a filter with a transfer function H(z)=(1+Z) in the second circuit portion of the ADC circuit at a second clock rate. -1 ) / 2 2-tap FIR filter).

[0106] According to certain aspects, the ADC circuit is a pipeline ADC (e.g., pipeline ADC circuit 900) having a plurality of stages (e.g., stages 802, 850, 901, and / or 902). In this case, the second circuit portion may include one or more initial stages (e.g., initial stage 901) of the plurality of stages of the pipeline ADC, and the first circuit portion may include one or more later stages (e.g., stage 850 or final stage 902) of the plurality of stages of the pipeline ADC. For certain aspects, one of the initial stages includes an ADC (e.g., ADC 852), a digital-to-analog converter (DAC) (e.g., DAC 854), a combiner (e.g., combiner 856), an analog filter (e.g., analog filter 904), and a first digital filter (e.g., digital filter 908). In this case, operating the second circuit portion may involve: operating the ADC at a second clock rate to input an analog signal (e.g., signal v i ) is converted into a level digital signal (e.g., signal d1); the DAC is operated at a second clock rate to convert the level digital signal into a level intermediate analog signal (e.g., signal v i* ); using a combiner to determine a stage residual signal (eg, signal v based on the difference between the stage input analog signal and the stage intermediate analog signal res); filtering the level residual signal with an analog filter to generate a level filtered residual signal (eg, signal v h ); and filtering the first digital filter on the digital signal to generate a first filtered digital signal (eg, signal d h For some aspects, operating the second circuit portion further comprises: downsampling the level filtered residual signal to generate a level downsampled residual signal (eg, signal v m ); the amplification stage downsamples the residual signal to generate a stage amplified residual signal (eg, signal v o ) to output to a subsequent stage in the pipeline ADC (e.g., one of stages 802b to 802n, stage 850, and final stage 902); and downsampling the stage filtered digital signal to generate a stage downsampled digital signal (e.g., signal d m In this case, the conversion of block 1110 may also include combining the stage downsampled digital signal from one of the initial stages with at least one or more stage digital signals (e.g., signal d2) from one or more later stages to generate a digital signal for output from the ADC circuit (e.g., signal d out ). The transfer function of the analog filter (eg, H(z)) may be similar to the transfer function of the first digital filter (eg, H(z)).

[0107] For certain aspects, one of the initial stages further includes a second digital filter (e.g., digital filter 910). In this case, the operation of the second circuit portion at block 1114 may also involve filtering the stage filtered digital signal with the second digital filter to generate a stage further filtered digital signal (e.g., signal d g ). For some aspects, operation 1100 may also include programming the second digital filter before filtering with the second digital filter. The second digital filter may have a higher order than the first digital filter (i.e., may be a high-order filter). In another case, the operation of the second circuit portion at block 1114 may involve bypassing the second digital filter.

[0108] According to certain aspects, one of the initial stages includes: an amplifier (e.g., amplifier 1004) having an output coupled to an output of one of the initial stages; a feedback capacitive element (e.g., feedback capacitive element Cf) coupled between the output of the amplifier and an input of the amplifier; a first set of switches (e.g., switches Sa1 and Sb1); a second set of switches (e.g., switches Sa2 and Sb2); a plurality of capacitive digital-to-analog converters (CDACs) (e.g., CDAC 1002) having outputs selectively coupled to an input of one of the initial stages (e.g., input node 1001) via the first set of switches and selectively coupled to an input of the amplifier via the second set of switches; and a plurality of quantizers (e.g., quantizer 1003) having inputs coupled to the outputs of the plurality of CDACs and selectively coupled to the input of one of the initial stages via the first set of switches, and having outputs coupled to the inputs of the plurality of CDACs. In this case, the operation of the second circuit portion at block 1114 may involve: sequentially sampling the analog signal using a first set of switches according to a second clock rate; sequentially converting the sampled analog signal into a plurality of coarse digital signals (e.g., dcA and dcB) using a plurality of quantizers according to the second clock rate; controlling the inputs of a plurality of CDACs using the plurality of coarse digital signals; closing the second set of switches to couple the remaining portion of the sampled analog signal on the plurality of CDACs to the input of the amplifier; and applying a finite impulse response (FIR) filter to the remaining portion of the sampled analog signal using the amplifier and a feedback capacitive element.

[0109] According to certain aspects, an ADC circuit includes a successive approximation register (SAR) ADC (e.g., SAR ADC circuit 300) having a plurality of capacitive digital-to-analog converters (CDACs) (e.g., CDAC 302) and a multi-input comparator (e.g., multi-input comparator 304). The multi-input comparator may have a plurality of inputs coupled to outputs of the plurality of CDACs. In this case, the second circuit portion may include the plurality of CDACs and the first circuit portion may include the multi-input comparator. For example, the plurality of CDACs may be arranged in a plurality of Mf s Operation (at each 1 / f s time interval), while the multiple-input comparator (and associated logic) can process multiple input samples at each 1 / f s For some aspects, the multiple inputs of a multiple-input comparator may have different weights (e.g., see Figure 4If so, the first circuit portion of the operation at block 1112 may involve: effectively applying a finite impulse response (FIR) filter to the multiple sampled input signals received by the multiple inputs of the multiple input comparator based on different weights. For some aspects, the conversion at block 1110 may also include performing a conversion based on the digital signal (e.g., d out ) to control multiple CDACs.

[0110] In the case of a SAR ADC, the operation of the second circuit portion at block 1114 may involve cycling through a plurality of switches (e.g., sample and hold switches S1, S2, ..., Sm) at a second clock rate, wherein one switch of the plurality of switches is cycled through per clock pulse at the second clock rate, wherein the plurality of switches are coupled to outputs of a plurality of CDACs. Thus, the digital signal may be a linearly weighted combination of different samples of the analog signal in the time domain based on the operation of the plurality of switches.

[0111] In the case of a SAR ADC, the second circuit portion of operation at block 1114 may involve sequentially sampling the analog signal using a plurality of switches (e.g., sample and hold switches S1, S2, ..., Sm) coupled to the outputs of the plurality of CDACs according to a second clock rate. For certain aspects, the first circuit portion of operation at block 1112 includes converting the sampled analog signals on the plurality of CDACs using a multi-input comparator and SAR logic (e.g., SAR logic 306) to generate a digital signal (e.g., d out ); and using the digital signal to control the inputs of the plurality of CDACs during the conversion of the sampled analog signal. For certain aspects, during the sequential sampling, at least one of the plurality of CDACs is inoperable.

[0112] According to certain aspects, the second circuit portion of the operation at block 1114 involves: sequentially sampling the analog signal using a plurality of switches (e.g., sample and hold switches S1, S2, ..., Sm) according to a second clock rate, the plurality of switches being coupled to the outputs of the CDACs; sequentially converting the sampled analog signal using a plurality of quantizers (e.g., quantizer 603) according to the second clock rate to a plurality of coarse digital signals (e.g., coarse quantization dc1, dc2, ..., dcm); and controlling the more significant bit inputs of the plurality of CDACs using the plurality of coarse digital signals. In this case, the first circuit portion of the operation at block 1112 may involve: converting the remaining portion of the sampled analog signal on the plurality of CDACs using a multi-input comparator and SAR logic (e.g., SAR logic 606) to generate fine digital signals (e.g., fine quantization dcm) at the first clock rate. fine ); and using a fine digital signal to control less significant bit inputs of multiple CDACs.

[0113] Example aspects

[0114] Implementation examples are described in the following numbered aspects:

[0115] Aspect 1: An analog-to-digital converter (ADC) circuit comprises: a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.

[0116] Aspect 2: The ADC circuit according to aspect 1, wherein the second circuit portion includes an analog finite impulse response (FIR) filter operating at the second clock rate.

[0117] Aspect 3: An ADC circuit according to Aspect 1 or 2, wherein the ADC circuit comprises a pipeline ADC having multiple stages, wherein the second circuit portion comprises one or more initial stages of the multiple stages of the pipeline ADC, and wherein the first circuit portion comprises one or more later stages of the multiple stages of the pipeline ADC.

[0118] Aspect 4: An ADC circuit according to Aspect 3, wherein one of the initial stages includes: an ADC configured to operate at the second clock rate; a digital-to-analog converter (DAC) configured to operate at the second clock rate and having an input coupled to the output of the ADC; a combiner having a first input coupled to the input of the ADC and a second input coupled to the output of the DAC; an analog filter having an input coupled to the output of the combiner; and a first digital filter having an input coupled to the output of the ADC.

[0119] Aspect 5: The ADC circuit according to Aspect 4, wherein the one of the initial stages further comprises: an analog downsampler having an input coupled to the output of the analog filter; and a digital downsampler having an input coupled to the output of the first digital filter.

[0120] Aspect 6: An ADC circuit according to Aspect 5, wherein: the pipeline ADC also includes a decoder coupled to the outputs of the multiple stages; the one of the initial stages also includes an amplifier having an input coupled to the output of the analog downsampler and having an output coupled to a subsequent stage of the multiple stages; and the output of the digital downsampler is coupled to the decoder.

[0121] Aspect 7: The ADC circuit according to any one of Aspects 4 to 6, wherein a transfer function of the analog filter is similar to a transfer function of the first digital filter.

[0122] Aspect 8: The ADC circuit according to any one of aspects 4 to 7, wherein the one of the initial stages further comprises a second digital filter having an input coupled to the output of the first digital filter.

[0123] Aspect 9: The ADC circuit according to Aspect 8, wherein the second digital filter is programmable.

[0124] Aspect 10: The ADC circuit according to aspect 8 or 9, wherein the second digital filter can be bypassed or can effectively have a unity transfer function.

[0125] Aspect 11: The ADC circuit according to any one of Aspects 8 to 10, wherein the second digital filter has a higher order than the first digital filter.

[0126] Aspect 12: An ADC circuit according to any one of Aspects 8 to 11, wherein the one of the initial stages further includes: an analog downsampler having an input coupled to the output of the analog filter; an amplifier having an input coupled to the output of the analog downsampler; and a digital downsampler having an input coupled to the output of the second digital filter, wherein the output of the amplifier is coupled to the analog output of the one of the initial stages, and wherein the output of the digital downsampler is coupled to the digital output of the one of the initial stages.

[0127] Aspect 13: An ADC circuit according to Aspect 3, wherein one of the initial stages includes: an amplifier having an output coupled to the output of the one of the initial stages; a feedback capacitive element coupled between the output of the amplifier and the input of the amplifier; a first group of switches; a second group of switches; a plurality of capacitive digital-to-analog converters (CDACs) having outputs selectively coupled to the input of the one of the initial stages via the first group of switches and selectively coupled to the input of the amplifier via the second group of switches; and a plurality of quantizers having inputs coupled to the outputs of the plurality of CDACs and selectively coupled to the input of the one of the initial stages via the first group of switches, and having outputs coupled to the inputs of the plurality of CDACs.

[0128] Aspect 14: The ADC circuit according to Aspect 13, wherein the one of the initial stages further comprises a switch coupled in parallel with the feedback capacitive element.

[0129] Aspect 15: An ADC circuit according to any one of Aspects 1 to 12, wherein: the ADC circuit includes a successive approximation register (SAR) ADC, the SAR ADC having a plurality of capacitive digital-to-analog converters (CDACs) and a multi-input comparator, the multi-input comparator having a plurality of inputs coupled to the outputs of the plurality of CDACs; the second circuit portion includes the plurality of CDACs; and the first circuit portion includes the multi-input comparator.

[0130] Aspect 16: The ADC circuit according to Aspect 15, wherein the multiple inputs of the multi-input comparator have different weights, and the different weights are implemented by input transistors of different sizes in the multi-input comparator.

[0131] Aspect 17: An ADC circuit according to Aspect 15 or 16, wherein the SAR ADC also includes logic having an input coupled to the output of the multi-input comparator, having an output coupled to the inputs of the multiple CDACs, and configured to generate a digital output signal at the output of the logic according to the sampling rate of the ADC circuit.

[0132] Aspect 18: An ADC circuit according to Aspect 17, wherein the digital output signal is a linearly weighted combination of different samples of the input voltage signal at the input of the SAR ADC in the time domain based on the operation of a plurality of switches, the plurality of switches being coupled to the outputs of the plurality of CDACs and being configured to be cycled through at the second clock rate, cycling through one switch of the plurality of switches per clock pulse at the second clock rate.

[0133] Aspect 19: An ADC circuit according to Aspect 15 or 16, wherein the outputs of the plurality of CDACs are selectively coupled to the input of the SAR ADC via a plurality of switches, the plurality of switches being configured to be cycled through at the second clock rate, cycling through one switch of the plurality of switches per clock pulse at the second clock rate.

[0134] Aspect 20: The ADC circuit according to aspect 19, wherein the SAR ADC further comprises a plurality of quantizers having inputs selectively coupled to the input of the SAR ADC via the plurality of switches and having outputs coupled to more significant bit inputs of the plurality of CDACs.

[0135] Aspect 21: An ADC circuit according to Aspect 20, wherein the SAR ADC further comprises logic having an input coupled to the output of the multi-input comparator, having a first output coupled to the less significant bit inputs of the plurality of CDACs, and configured to generate a digital output signal at a second output of the logic according to the sampling rate of the ADC circuit, the digital output signal being a weighted addition of a coarse quantization from one of the plurality of quantizers and a fine quantization based on the output signal from the multi-input comparator.

[0136] Aspect 22: The ADC circuit according to any one of the preceding aspects, wherein the second clock rate is twice the sampling rate of the ADC circuit.

[0137] Aspect 23: A signal conversion method, the method comprising using an analog-to-digital converter (ADC) circuit to convert an analog signal into a digital signal at a sampling rate of the ADC circuit, wherein the conversion comprises: operating a first circuit portion of the ADC circuit at a first clock rate equal to the sampling rate of the ADC circuit; and operating a second circuit portion of the ADC circuit at a second clock rate higher than the sampling rate of the ADC circuit.

[0138] Aspect 24: The method of aspect 23, wherein operating the second circuit portion comprises operating an analog finite impulse response (FIR) filter in the second circuit portion of the ADC circuit at the second clock rate.

[0139] Aspect 25: A method according to Aspect 23 or 24, wherein the ADC circuit includes a pipeline ADC having multiple stages, wherein the second circuit portion includes one or more initial stages of the multiple stages of the pipeline ADC, and wherein the first circuit portion includes one or more later stages of the multiple stages of the pipeline ADC.

[0140] Aspect 26: A method according to Aspect 25, wherein: one of the initial stages includes an ADC, a digital-to-analog converter (DAC), a combiner, an analog filter and a first digital filter; and operating the second circuit portion includes: operating the ADC at the second clock rate to convert the stage input analog signal into a stage digital signal; operating the DAC at the second clock rate to convert the stage digital signal into a stage intermediate analog signal; using the combiner, determining a stage residual signal based on the difference between the stage input analog signal and the stage intermediate analog signal; filtering the stage residual signal with the analog filter to generate a stage filtered residual signal; and filtering the stage digital signal with the first digital filter to generate a stage filtered digital signal.

[0141] Aspect 27: A method according to Aspect 26, wherein: operating the second circuit portion also includes: downsampling the stage filtering residual signal to generate a stage downsampled residual signal; amplifying the stage downsampled residual signal to generate a stage amplified residual signal for output to a subsequent stage in the pipeline ADC; and downsampling the stage filtering digital signal to generate a stage downsampled digital signal; and the conversion also includes: combining the stage downsampled digital signal from the one of the initial stages with at least one or more stage digital signals from the one or more later stages to generate the digital signal for output from the ADC circuit.

[0142] Aspect 28: The method according to aspect 26 or 27, wherein the transfer function of the analog filter is similar to the transfer function of the first digital filter.

[0143] Aspect 29: A method according to any one of Aspects 26 to 28, wherein the one of the initial stages also includes a second digital filter, and wherein operating the second circuit portion also includes: filtering the stage filtered digital signal with the second digital filter to generate a stage further filtered digital signal.

[0144] Aspect 30: The method according to Aspect 29 further includes: programming the second digital filter before filtering with the second digital filter.

[0145] Aspect 31: The method according to Aspect 29 or 30, wherein the second digital filter has a higher order than the first digital filter.

[0146] Aspect 32: The method according to any one of aspects 26 to 28, wherein the one of the initial stages further comprises a second digital filter, and wherein operating the second circuit portion further comprises bypassing the second digital filter.

[0147] Aspect 33: A method according to aspect 25, wherein: one of the initial stages comprises: an amplifier having an output coupled to the output of the one of the initial stages; a feedback capacitive element coupled between the output of the amplifier and the input of the amplifier; a first set of switches; a second set of switches; a plurality of capacitive digital-to-analog converters (CDACs) having outputs selectively coupled to the input of the one of the initial stages via the first set of switches and selectively coupled to the input of the amplifier via the second set of switches; and a plurality of quantizers having outputs coupled to the plurality of CDACs and selectively coupled to the one of the initial stages via the first set of switches. the input of the input of the stage and having an output coupled to the input of the plurality of CDACs; and operating the second circuit portion includes: sequentially sampling the analog signal using the first set of switches according to the second clock rate; sequentially converting the sampled analog signal using the plurality of quantizers according to the second clock rate to a plurality of coarse digital signals; controlling the inputs of the plurality of CDACs using the plurality of coarse digital signals; closing the second set of switches to couple a remaining portion of the sampled analog signal on the plurality of CDACs to the input of the amplifier; and applying a finite impulse response (FIR) filter to the remaining portion of the sampled analog signal using the amplifier and the feedback capacitive element.

[0148] Aspect 34: A method according to any one of Aspects 23 to 33, wherein: the ADC circuit includes a successive approximation register (SAR) ADC, the SAR ADC having a plurality of capacitive digital-to-analog converters (CDACs) and a multi-input comparator, the multi-input comparator having a plurality of inputs coupled to the outputs of the plurality of CDACs; the second circuit portion includes the plurality of CDACs; and the first circuit portion includes the multi-input comparator.

[0149] Aspect 35: A method according to Aspect 34, wherein the multiple inputs of the multi-input comparator have different weights, and wherein operating the first circuit portion includes effectively applying a finite impulse response (FIR) filter to multiple sampled input signals received by the multiple inputs of the multi-input comparator based on the different weights.

[0150] Aspect 36: The method according to aspect 34 or 35, wherein the converting further comprises: during the converting, controlling the plurality of CDACs based on the digital signal.

[0151] Aspect 37: A method according to any one of Aspects 34 to 36, wherein: operating the second circuit portion includes cycling through a plurality of switches at the second clock rate, wherein one switch of the plurality of switches is cycled through per clock pulse at the second clock rate; the plurality of switches are coupled to the outputs of the plurality of CDACs; and the digital signal is a linearly weighted combination of different samples of the analog signal in the time domain based on the operation of the plurality of switches.

[0152] Aspect 38: A method according to Aspect 34, wherein: operating the second circuit portion includes: sequentially sampling the analog signal using multiple switches coupled to the outputs of the multiple CDACs according to the second clock rate; and operating the first circuit portion includes: using the multi-input comparator and SAR logic to convert the sampled analog signals on the multiple CDACs to generate the digital signal of the first clock rate; and during the conversion of the sampled analog signals, using the digital signal to control the inputs of the multiple CDACs.

[0153] Aspect 39: The method of aspect 38, wherein during the sequential sampling, at least one CDAC of the plurality of CDACs is inoperable.

[0154] Aspect 40: A method according to aspect 34, wherein: operating the second circuit portion includes: sequentially sampling the analog signal using multiple switches according to the second clock rate, the multiple switches coupled to the output of the CDAC; sequentially converting the sampled analog signal into multiple coarse digital signals using multiple quantizers according to the second clock rate; and using the multiple coarse digital signals to control the more significant bit inputs of the multiple CDACs; and operating the first circuit portion includes: using the multi-input comparator and SAR logic to convert the remaining portion of the sampled analog signal on the multiple CDACs to generate a fine digital signal at the first clock rate; and using the fine digital signal to control the less significant bit inputs of the multiple CDACs.

[0155] Aspect 41: The method according to aspect 40, wherein the multi-input comparator is used to digitize the sampled analog signal for at least some initial conversions.

[0156] Aspect 42: The method according to any one of Aspects 23 to 41, wherein the second clock rate is greater than twice the sampling rate of the ADC circuit.

[0157] Other considerations

[0158] In this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed features, advantages, or modes of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other - even if object A and object C are not in direct physical contact with each other. For example, a first object can be coupled to a second object even if the first object has never been in direct physical contact with the second object. The terms "circuit" and "circuitry" are used broadly and are intended to include hardware implementations of electrical devices and conductors that, when connected and configured, are capable of performing the functions described in this disclosure, without limitation to the type of electronic circuits.

[0159] The apparatuses and methods described in the detailed description are illustrated in the drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using, for example, hardware.

[0160] One or more of the components, steps, features, and / or functions shown herein may be rearranged and / or combined into a single component, step, feature, or function, or implemented in several components, steps, or functions. Additional elements, components, steps, and / or functions may also be added without departing from the features disclosed herein. The devices, equipment, and / or components shown herein may be configured to perform one or more of the methods, features, or steps described herein.

[0161] It should be understood that the specific order or hierarchy of steps in the disclosed methods is an illustration of an exemplary process. Based on design preferences, it is understood that the specific order or hierarchy of steps in the methods can be rearranged. The accompanying method claims present the present elements of the various steps in a sample order, and unless specifically stated therein, are not intended to be limited to the specific order or hierarchy presented.

[0162] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be clear to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein unless otherwise specified, the reference to the element in the singular form does not mean "one and only one", but refers to "one or more". Unless otherwise specifically stated, the term "some" refers to one or more. The phrase "at least one of the list of items..." refers to any combination of these items, including a single member. For example, "at least one of a, b or c" is intended to cover at least: a, b, c, ab, ac, bc and abc, and any combination of multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc and ccc or any other order of a, b and c). All structural and functional equivalents of the elements of the various aspects described in this disclosure known to or later known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly cited in a claim. No claim element may be construed under 35 U.S.C. § 112(f) unless the element is recited using the phrase “means for” or, in the case of a method claim, the phrase “step for.”

[0163] It is to be understood that the claims are not limited to the precise configuration and components described above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An analog-to-digital converter (ADC) circuit, comprising: a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; as well as A second circuit portion is configured to operate at a second clock rate that is higher than the sampling rate of the ADC circuit.

2. The ADC circuit of claim 1, wherein the second circuit portion comprises an analog finite impulse response (FIR) filter operating at the second clock rate.

3. The ADC circuit of claim 1 , wherein the ADC circuit comprises a pipeline ADC having a plurality of stages, wherein the second circuit portion comprises one or more initial stages of the plurality of stages of the pipeline ADC, and wherein the first circuit portion comprises one or more later stages of the plurality of stages of the pipeline ADC.

4. The ADC circuit of claim 3, wherein one of the initial stages comprises: an ADC configured to operate at the second clock rate; a digital-to-analog converter (DAC) configured to operate at the second clock rate and having an input coupled to an output of the ADC; a combiner having a first input coupled to an input of the ADC and having a second input coupled to an output of the DAC; an analog filter having an input coupled to the output of the combiner; as well as A first digital filter has an input coupled to the output of the ADC.

5. The ADC circuit of claim 4, wherein the one of the initial stages further comprises: an analog downsampler having an input coupled to an output of the analog filter; as well as A digital downsampler has an input coupled to the output of the first digital filter.

6. The ADC circuit according to claim 5, wherein: The pipeline ADC further includes a decoder coupled to the outputs of the plurality of stages; The one of the initial stages further includes an amplifier having an input coupled to an output of the analog downsampler and having an output coupled to a subsequent stage of the plurality of stages; and An output of the digital downsampler is coupled to the decoder.

7. The ADC circuit of claim 4, wherein a transfer function of the analog filter is similar to a transfer function of the first digital filter.

8. The ADC circuit of claim 4, wherein the one of the initial stages further comprises a second digital filter having an input coupled to an output of the first digital filter.

9. The ADC circuit of claim 8, wherein the second digital filter is programmable.

10. The ADC circuit of claim 8, wherein the second digital filter can be bypassed or can effectively have a unity transfer function.

11. The ADC circuit of claim 8, wherein the second digital filter has a higher order than the first digital filter.

12. The ADC circuit of claim 8, wherein the one of the initial stages further comprises: an analog downsampler having an input coupled to an output of the analog filter; an amplifier having an input coupled to the output of the analog downsampler; as well as a digital downsampler having an input coupled to the output of the second digital filter, wherein the output of the amplifier is coupled to the analog output of the one of the initial stages, and wherein the output of the digital downsampler is coupled to the digital output of the one of the initial stages.

13. The ADC circuit of claim 3 , wherein one of the initial stages comprises: an amplifier having an output coupled to an output of said one of said initial stages; a feedback capacitive element coupled between the output of the amplifier and an input of the amplifier; The first set of switches; The second set of switches; a plurality of capacitive digital-to-analog converters (CDACs) having outputs, the outputs of the plurality of CDACs selectively coupled to the input of the one of the initial stages via the first set of switches and selectively coupled to the input of the amplifier via the second set of switches; as well as a plurality of quantizers having inputs coupled to the outputs of the plurality of CDACs and selectively coupled to the input of the one of the initial stages via the first set of switches, and having outputs, the inputs of the plurality of quantizers being coupled to the outputs of the plurality of CDACs and selectively coupled to the input of the one of the initial stages via the first set of switches, the outputs of the plurality of quantizers being coupled to the inputs of the plurality of CDACs.

14. The ADC circuit of claim 13, wherein the one of the initial stages further comprises a switch coupled in parallel with the feedback capacitive element.

15. The ADC circuit according to claim 1, wherein: The ADC circuit includes a successive approximation register (SAR) ADC having a plurality of capacitive digital-to-analog converters (CDACs) and a multi-input comparator having a plurality of inputs coupled to outputs of the plurality of CDACs; The second circuit portion includes the plurality of CDACs; and The first circuit portion includes the multi-input comparator. 16 . The ADC circuit of claim 15 , wherein the multiple inputs of the multi-input comparator have different weights, and the different weights are implemented by input transistors of different sizes in the multi-input comparator.

17. The ADC circuit of claim 15, wherein the SAR ADC further comprises logic having an input coupled to the output of the multi-input comparator, having an output coupled to the inputs of the plurality of CDACs, and configured to produce a digital output signal at the output of the logic according to the sampling rate of the ADC circuit.

18. The ADC circuit of claim 17, wherein the digital output signal is a linearly weighted combination of different samples of an input voltage signal at an input of the SAR ADC in the time domain based on operation of a plurality of switches, the plurality of switches being coupled to the outputs of the plurality of CDACs and configured to be cycled through at the second clock rate, one switch of the plurality of switches being cycled through per clock pulse at the second clock rate.

19. The ADC circuit of claim 15, wherein the outputs of the plurality of CDACs are selectively coupled to the input of the SAR ADC via a plurality of switches, the plurality of switches being configured to be cycled through at the second clock rate, one of the plurality of switches being cycled through per clock pulse at the second clock rate.

20. The ADC circuit of claim 19, wherein the SAR ADC further comprises a plurality of quantizers having inputs selectively coupled to the input of the SAR ADC via the plurality of switches and having outputs coupled to more significant bit inputs of the plurality of CDACs.

21. The ADC circuit of claim 20, wherein the SAR ADC further comprises logic having an input coupled to the output of the multi-input comparator, having a first output coupled to the less significant bit inputs of the plurality of CDACs, and configured to generate a digital output signal at a second output of the logic according to the sampling rate of the ADC circuit, the digital output signal being a weighted addition of a coarse quantization from one of the plurality of quantizers and a fine quantization based on an output signal from the multi-input comparator.

22. The ADC circuit of claim 1, wherein the second clock rate is twice the sampling rate of the ADC circuit.

23. A method of signal conversion, the method comprising converting an analog signal into a digital signal using an analog-to-digital converter (ADC) circuit at a sampling rate of the ADC circuit, wherein the converting comprises: operating a first circuit portion of the ADC circuit at a first clock rate equal to the sampling rate of the ADC circuit; as well as A second circuit portion of the ADC circuit is operated at a second clock rate that is higher than the sampling rate of the ADC circuit.

24. The method of claim 23, wherein operating the second circuit portion comprises: An analog finite impulse response (FIR) filter in the second circuit portion of the ADC circuit is operated at the second clock rate.

25. The method of claim 23, wherein the ADC circuit comprises a pipeline ADC having a plurality of stages, wherein the second circuit portion comprises one or more initial stages of the plurality of stages of the pipeline ADC, and wherein the first circuit portion comprises one or more later stages of the plurality of stages of the pipeline ADC.

26. The method of claim 25, wherein: One of the initial stages includes an ADC, a digital-to-analog converter (DAC), a combiner, an analog filter, and a first digital filter; and Operating the second circuit portion comprises: operating the ADC at the second clock rate to convert a stage input analog signal into a stage digital signal; operating the DAC at the second clock rate to convert the stage digital signal into a stage intermediate analog signal; determining, using the combiner, a stage residual signal based on a difference between the stage input analog signal and the stage intermediate analog signal; filtering the stage residual signal with the analog filter to generate a stage filtered residual signal; and The stage digital signal is filtered using the first digital filter to generate a stage filtered digital signal.

27. The method of claim 26, wherein: Operating the second circuit portion further comprises: Downsampling the level filtering residual signal to generate a level downsampled residual signal; amplifying the stage downsampled residual signal to generate a stage amplified residual signal for output to a subsequent stage in the pipeline ADC; and downsampling the stage filtered digital signal to generate a stage downsampled digital signal; and The converting further includes combining the stage downsampled digital signal from the one of the initial stages with at least one or more stage digital signals from the one or more later stages to generate the digital signal for output from the ADC circuit.

28. The method of claim 26, wherein a transfer function of the analog filter is similar to a transfer function of the first digital filter.

29. The method of claim 26, wherein the one of the initial stages further comprises a second digital filter, and wherein operating the second circuit portion further comprises: The stage filtered digital signal is filtered by the second digital filter to generate a stage further filtered digital signal.

30. The method of claim 29, further comprising: Prior to filtering with the second digital filter, the second digital filter is programmed.

31. The method of claim 29, wherein the second digital filter has a higher order than the first digital filter.

32. The method of claim 26, wherein the one of the initial stages further comprises a second digital filter, and wherein operating the second circuit portion further comprises bypassing the second digital filter.

33. The method of claim 25, wherein: One of the initial stages comprises: an amplifier having an output coupled to an output of said one of said initial stages; a feedback capacitive element coupled between the output of the amplifier and an input of the amplifier; The first set of switches; The second set of switches; a plurality of capacitive digital-to-analog converters (CDACs) having outputs, the outputs of the plurality of CDACs selectively coupled to the input of the one of the initial stages via the first set of switches and selectively coupled to the input of the amplifier via the second set of switches; and a plurality of quantizers having inputs and having outputs, the inputs of the plurality of quantizers being coupled to the outputs of the plurality of CDACs and selectively coupled to the input of the one of the initial stages via the first set of switches, the outputs of the plurality of quantizers being coupled to the inputs of the plurality of CDACs; and Operating the second circuit portion comprises: sequentially sampling the analog signal using the first set of switches according to the second clock rate; sequentially converting the sampled analog signal into a plurality of coarse digital signals using the plurality of quantizers according to the second clock rate; using the plurality of coarse digital signals to control inputs of the plurality of CDACs; closing the second set of switches to couple a remaining portion of the analog signal sampled on the plurality of CDACs to the input of the amplifier; and A finite impulse response (FIR) filter is applied to the remaining portion of the sampled analog signal using the amplifier and the feedback capacitive element.

34. The method of claim 23, wherein: The ADC circuit includes a successive approximation register (SAR) ADC having a plurality of capacitive digital-to-analog converters (CDACs) and a multi-input comparator having a plurality of inputs coupled to outputs of the plurality of CDACs; The second circuit portion includes the plurality of CDACs; and The first circuit portion includes the multi-input comparator.

35. A method according to claim 34, wherein the multiple inputs of the multi-input comparator have different weights, and wherein operating the first circuit portion includes effectively applying a finite impulse response (FIR) filter to multiple sampled input signals received by the multiple inputs of the multi-input comparator based on the different weights.

36. The method of claim 34, wherein the converting further comprises controlling the plurality of CDACs based on the digital signal during the converting.

37. The method of claim 34, wherein: Operating the second circuit portion includes cycling through a plurality of switches at the second clock rate, cycling through one switch of the plurality of switches per clock pulse at the second clock rate; The plurality of switches are coupled to outputs of the plurality of CDACs; and The digital signal is a linearly weighted combination of different samples of the analog signal in the time domain based on the operation of the plurality of switches.

38. The method of claim 34, wherein: Operating the second circuit portion includes sequentially sampling the analog signal using a plurality of switches coupled to outputs of the plurality of CDACs according to the second clock rate; and Operating the first circuit portion comprises: converting the sampled analog signals on the plurality of CDACs using the multi-input comparator and SAR logic to generate the digital signals at the first clock rate; as well as During the conversion of the sampled analog signal, the digital signal is used to control inputs of the plurality of CDACs.

39. The method of claim 38, wherein during said sequentially sampling, at least one CDAC of said plurality of CDACs is inoperable.

40. The method of claim 34, wherein: Operating the second circuit portion comprises: sequentially sampling the analog signal according to the second clock rate using a plurality of switches coupled to outputs of the CDAC; sequentially converting the sampled analog signal into a plurality of coarse digital signals using a plurality of quantizers according to the second clock rate; and using the plurality of coarse digital signals to control more significant bit inputs of the plurality of CDACs; and Operating the first circuit portion comprises: converting a remaining portion of the sampled analog signal on the plurality of CDACs using the multi-input comparator and SAR logic to generate a refined digital signal at the first clock rate; and The fine digital signal is used to control less significant bit inputs of the plurality of CDACs.

41. The method of claim 40, wherein the multiple-input comparator is used to digitize the sampled analog signal for at least some initial conversions.

42. The method of claim 23, wherein the second clock rate is greater than twice the sampling rate of the ADC circuit.

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