Cascaded integrated circuit aging device and method

Abstract

The invention belongs to the technical field of integrated circuit detection, and particularly discloses a cascaded integrated circuit aging device and method. The device is formed by sequentially cascading an upper computer, a driving module, a re-inspection module, an aging mother board, an aging test module, a first-stage aging daughter board, a second-stage aging daughter board and other modules, the upper computer controls the cascading modules to achieve output and re-inspection of aging signals, and the signals are introduced into the corresponding first-stage aging daughter board to age an integrated circuit. The device is not only suitable for the aging test of the integrated circuit, but also can use the aging test module in the device for the electrical parameter test link of the integrated circuit, thereby improving the efficiency of the electrical parameter test and the aging test in component screening, and saving the labor cost and the material cost in the integrated circuit detection process. In addition, the invention further provides an aging method based on the cascaded integrated circuit aging device, and accuracy and stability of the device in practical application are ensured.

Description

Technical Field

[0001] The present application belongs to the technical field of integrated circuit detection, and more specifically, relates to a cascade integrated circuit aging device and method. Background Art

[0002] In the process of integrated circuit manufacturing, due to factors such as unstable process conditions and changes in equipment performance, it is often difficult to fully achieve the expected reliability level. There are always some potential defects. These potential problems will be exposed as early failures under specific stress environments. Once defective components are used, the entire machine or equipment will malfunction, or the performance will not meet the requirements. Therefore, it is necessary to screen the components before assembly. The screening process includes electrical parameter testing and aging testing.

[0003] At present, the common practice for integrated circuit aging tests is to make different aging boards according to their packaging type and pin arrangement. However, there are many types of integrated circuits that need to be screened, the cycle for customizing aging boards is long, and the design and manufacturing costs of aging boards are high, especially the cost of aging sockets on the aging boards. As a result, the entire integrated circuit testing cycle is long and inefficient.

[0004] Therefore, how to better implement integrated circuit aging testing has become a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0005] In view of the defects of the prior art, the purpose of this application is to better implement integrated circuit aging testing, aiming to solve the problems of the existing integrated circuit aging testing, such as the long entire test cycle and low test efficiency.

[0006] To achieve the above objectives, in a first aspect, the present application provides a cascade integrated circuit aging device, comprising: A host computer, a drive module, a checkback module and a plurality of aging motherboards; each of the aging motherboards is provided with an aging test module, a primary aging daughter board and a secondary aging daughter board which are sequentially connected; the primary aging daughter board is used to set the integrated circuit to be tested; the secondary aging daughter board is used to set the peripheral functional circuit matching the integrated circuit to be tested; The host computer is connected to each of the aging motherboards through the driving module, and is used to control the driving module to input an aging driving signal to each of the aging motherboards, so as to introduce the aging driving signal to the corresponding primary aging daughter board through each of the aging test modules, and perform an aging test on each of the integrated circuits to be tested; The host computer is connected to each of the aging motherboards through the back-check module, and is used to control the back-check module to obtain the back-check signal generated by each of the integrated circuits to be tested after the aging test, and to detect each of the back-check signals.

[0007] Optionally, each of the aged mother boards includes a first board area and a second board area; The first board area is provided with a gold finger interface for introducing the aging drive signal, and a wiring interface for transmitting the aging drive signal to the aging test module; The second board area is used to set the aging test modules, and each of the aging test modules is connected to a plurality of the first-level aging sub-boards; each of the first-level aging sub-boards is provided with an aging seat for mounting the integrated circuit to be tested.

[0008] Optionally, the second board area is a hollow board structure, used to set the aging test module; the aging test module is a turntable structure, and each of the first-level aging sub-boards is set on the edge area of ​​the aging test module; The aging test module can be used in the integrated circuit electrical parameter test link. By rotating itself, the aging sockets on each of the first-level aging sub-boards are connected to the test head of the electrical parameter test system in turn, so as to perform electrical parameter tests on each aging socket one by one.

[0009] Optionally, the turntable structure is a circular disc structure, and a plurality of mounting portions are evenly arranged on an edge region of the circular disc structure, and the plurality of mounting portions are used to mount each of the primary aging sub-boards.

[0010] Optionally, brackets are provided on both sides of the edge of the hollow structure, and the brackets are provided with a waist-round hole structure; The oval hole structure is used to adjust the installation distance of the aging test module to adapt to the installation of aging test modules of different sizes.

[0011] Optionally, each of the primary aging daughter boards is provided with a plurality of pin sockets for connecting with the corresponding plurality of secondary aging daughter boards in a plug-in manner.

[0012] Optionally, the peripheral functional circuit includes at least a power supply circuit, a signal input and output circuit, and a protection circuit.

[0013] Optionally, each of the aging sockets is provided with a pin socket for plugging in the integrated circuit to be tested, so that the integrated circuit to be tested can be installed on the corresponding aging socket in a plug-in manner.

[0014] In a second aspect, the present application provides a cascade integrated circuit aging method applied to any of the aforementioned cascade integrated circuit aging devices, comprising: Calling the host computer to control the driving module to input an aging driving signal to each of the aging motherboards, so as to introduce the aging driving signal into the corresponding primary aging daughter board through each of the aging test modules, and perform an aging test on each of the integrated circuits to be tested; The host computer is called to control the back-check module to obtain the back-check signals generated by each of the integrated circuits to be tested after the aging test from each of the aging motherboards, and to detect each of the back-check signals.

[0015] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art: The present application provides a cascaded integrated circuit aging device and method, which realizes a deep modular design of the integrated circuit aging device by adopting a multi-module cascade method, combined with a multi-stage mother-and-child board structure consisting of an aging motherboard, a first-level aging daughter board, and a second-level aging daughter board. The aging device has certain universal characteristics, improves the efficiency of the integrated circuit aging test, and saves labor costs and material costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is one of the structural schematic diagrams of the cascade integrated circuit aging device provided in the embodiment of the present application; Figure 2 This is the second structural schematic diagram of the cascade integrated circuit aging device provided in the embodiment of the present application; Figure 3 It is a structural schematic diagram of the connection between the primary aging sub-board and the secondary aging sub-board provided in an embodiment of the present application; Figure 4 This is the third structural schematic diagram of the cascade integrated circuit aging device provided in the embodiment of the present application; Figure 5 This is the fourth structural schematic diagram of the cascade integrated circuit aging device provided in the embodiment of the present application; Figure 6 It is a flow chart of a cascade integrated circuit aging method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0018] The terms "first", "second", etc. in the specification and claims herein are used to distinguish different objects, rather than to describe a specific order of the objects. For example, the first board area and the second board area are used to distinguish the area ranges of different functions on the aging motherboard, rather than to describe a specific order of the board areas.

[0019] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0020] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more. For example, multiple first-level aging sub-boards refer to two or more first-level aging sub-boards; multiple mounting parts refer to two or more mounting parts, etc.

[0021] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0022] Figure 1 is one of the structural schematic diagrams of the cascade integrated circuit aging device provided in the embodiment of the present application, such as Figure 1 As shown, including: A host computer 5, a driving module 6, a checkback module 7 and a plurality of aging motherboards 1; each aging motherboard 1 is provided with an aging test module 2, a primary aging sub-board 3 and a secondary aging sub-board 4 which are sequentially connected; the primary aging sub-board 3 is used to set the integrated circuit to be tested; the secondary aging sub-board 4 is used to set the peripheral functional circuit matching the integrated circuit to be tested; The host computer 5 is connected to each aging motherboard 1 through the driving module 6, and is used to control the driving module 6 to input an aging driving signal to each aging motherboard 1, so as to introduce the aging driving signal to the corresponding primary aging daughter board 3 through each aging test module 2, and perform an aging test on each integrated circuit to be tested; The host computer 5 is connected to each aging motherboard 1 through the back-check module 7, and is used to control the back-check module 7 to obtain the back-check signal generated by each IC to be tested after the aging test, and to detect each back-check signal.

[0023] Specifically, the integrated circuit to be tested described in the embodiments of the present application may include chips, transistors, sensors and other integrated circuit devices to be tested.

[0024] In the embodiment of the present application, the cascade integrated circuit aging device can be composed of a host computer 5, a driving module 6, a recheck module 7, a plurality of aging motherboards 1, an aging test module 2, a primary aging daughter board 3, and a secondary aging daughter board 4 connected in sequence. Among them, the host computer 5 is used for aging data processing, human-computer interaction, etc., and is connected to the driving module 6 and the recheck module 7 through a communication bus, and is used to control the driving module 6 and the recheck module 7 to realize the driving and rechecking of the aging signal.

[0025] More specifically, in an embodiment of the present application, the host computer 5, the driving module 6 and the re-inspection module 7 can be installed outside the high-temperature aging box, and the aging test module 2, the first-level aging sub-board 3 and the second-level aging sub-board 4 are connected in sequence and connected to the corresponding aging motherboard 1. By installing each aging motherboard 1 in different aging test areas in the high-temperature aging box, the function of simultaneous aging in multiple areas can be achieved.

[0026] Specifically, by connecting the driving module 6 to each aging motherboard 1, the upper computer 5 controls the driving module 6 to output the aging driving signal to each aging motherboard 1 via the communication bus, and then introduces the aging driving signal to the corresponding first-level aging daughter board 3 through the aging test module 2 connected to the aging motherboard 1, so as to perform an aging test on the integrated circuit to be tested set thereon.

[0027] Meanwhile, during the implementation process, the back-check module 7 is connected to each aging motherboard 1. Therefore, during the aging test of each integrated circuit to be tested, the back-check signal in the aging test can be output through a specific interface on the aging motherboard 1. Then, the back-check module 7 can obtain the back-check signal generated by each integrated circuit to be tested after the aging test through the aging motherboard 1, and detect each obtained back-check signal, so as to realize the verification and inspection of the aging test results of each integrated circuit to be tested.

[0028] The cascaded integrated circuit aging device of the embodiment of the present application realizes a deep modular design of the integrated circuit aging device by adopting a multi-module cascade method, combined with a multi-level mother-and-child board structure consisting of an aging motherboard, a first-level aging daughter board, and a second-level aging daughter board. This makes the aging device have certain universal characteristics, improves the efficiency of the integrated circuit aging test, and saves labor costs and material costs.

[0029] Figure 2 This is the second structural diagram of the cascade integrated circuit aging device provided in the embodiment of the present application, such as Figure 2 As shown, each aging motherboard 1 includes a first board area 11 and a second board area 12; the first board area 11 is provided with a gold finger interface 111 for introducing an aging drive signal, and a cable interface 112 for transmitting the aging drive signal to the aging test module 2; the second board area 12 is used to set the aging test module 2, and each aging test module 2 is connected to a plurality of primary aging sub-boards 3; Each primary aging sub-board 3 is provided with an aging seat 31 for arranging the integrated circuit to be tested, and a connecting portion for connecting to the secondary aging sub-board 4 .

[0030] Specifically, in an embodiment of the present application, the aging motherboard 1 adopts a partitioned layout, including a first board area 11 and a second board area 12, and the first board area 11 is provided with a gold finger interface 111 and a cable interface 112; the aging test module 2 is arranged in the second board area 12, and each aging test module 2 is connected to a plurality of first-level aging sub-boards 3, wherein each first-level aging sub-board 3 can be provided with a plurality of connecting parts for installing and connecting the corresponding plurality of second-level aging sub-boards 4.

[0031] In the embodiment of the present application, an aging seat 31 is provided on each primary aging sub-board 3, and a special mounting portion is provided on the aging seat 31 for mounting the integrated circuit to be tested. A peripheral functional circuit is provided on each secondary aging sub-board 4; the peripheral functional circuit matches the integrated circuit to be tested mounted on the corresponding aging seat 31. Among them, the aging seat 31 is a device for testing the aging degree of integrated circuit products, which can simulate a long-term use environment and allow the integrated circuit to be tested mounted thereon to undergo aging tests under extreme temperature, humidity and other conditions.

[0032] Among them, the peripheral functional circuit is mainly used to cooperate with the aging socket 31 to realize the aging test of the integrated circuit to be tested. Specifically, the peripheral functional circuit includes but is not limited to a power supply circuit, a control circuit, an interface circuit, a signal input and output circuit, and a protection circuit. In the actual application process, it is necessary to design and configure the corresponding peripheral functional circuit according to the specific needs of the actual aging and the characteristics of the integrated circuit to be tested. Regarding the connection method between the primary aging sub-board 3 and the secondary aging sub-board 4, as an optional embodiment, each primary aging sub-board 3 is provided with a plurality of pin sockets for connecting with the corresponding plurality of secondary aging sub-boards 4 in a plug-in manner.

[0033] Specifically, in the embodiment of the present application, by considering the modular design of the aging socket and the peripheral functional circuit, the primary aging sub-board 3 is connected to the corresponding secondary aging sub-boards 4 in a plug-in manner.

[0034] In the embodiment of the present application, the primary aging sub-board 3 includes multiple groups of aging sockets 31 and pin sockets connected to the pins of the aging sockets 31 in a one-to-one correspondence, and can adapt to different secondary aging sub-boards 4.

[0035] Figure 3 Schematic diagram of the structure of the connection between the primary aging sub-board and the secondary aging sub-board provided in the embodiment of the present application, such as Figure 3As shown, in the embodiment of the present application, an aging seat 31 of a standard SMD package with a pin spacing of e=1.27mm and three groups of double-row 14pin (pin) pin seats are selected to form a primary aging sub-board 3, wherein the aging seat 31 is provided with a mounting portion for setting the integrated circuit 32 to be tested, and the three groups of pin seats can be respectively plugged with the corresponding three secondary aging sub-boards 4. The secondary aging sub-board 4 is connected to the primary aging sub-board 3 through multi-hole pins, and is symmetrically distributed on both sides of the aging seat 31. The secondary aging sub-boards 4 on the left and right sides of the aging seat 31 can realize the peripheral functional circuits required for the aging test, and the secondary aging sub-board 4 on the lower side of the aging seat 31 can realize the return connection of the output signal of the aging seat 31.

[0036] Among them, in this embodiment, chip capacitors with model specifications such as CC0805KRX7R9BB104, CC0805KRX7R9BB100, CC0805KRX7R9BB106, and chip resistors such as RC0805FR-0728KL, RC0805FR-070RL can be selected to form the peripheral functional circuit of the secondary aging sub-board 4; in addition, in order to ensure that the output signal of the aging socket 31 is used independently, an operational amplifier with model specifications of AD820 can be selected to form the return circuit of the secondary aging sub-board 4 to complete the normal return check of the output signal of the output pin.

[0037] The device of the embodiment of the present application, by separating the aging socket from the peripheral functional circuit and making a detachable connection by plugging, can not only greatly simplify the installation process of the aging daughter board, facilitate replacement and maintenance, and ensure stable and reliable circuit signal transmission, but also enhance the adaptability of the aging daughter board to different test environments by virtue of the impact resistance of the plug-in method, which is beneficial to improving the reliability of the integrated circuit aging test.

[0038] Further, in an embodiment of the present application, the aging motherboard 1 is a PCB circuit board of a certain specification size, and its circuit layout area is set to two board areas, namely the first board area 11 and the second board area 12. In the first board area 11, a gold finger interface 111 and a cable interface 112 are provided. Among them, the gold finger interface 111 can be designed as a signal input interface, which is used to connect with the drive module 6 that outputs the aging drive signal to introduce the aging drive signal for aging test; the cable interface 112 can be designed as a signal transfer interface and a signal output interface, which is connected with the aging test module 2, and the aging drive signal is transmitted to the aging test module 2 through the signal transfer interface; through the signal output interface, the aging test signal of the aging test module 2 can be output to the re-inspection module 7 for detection.

[0039] In addition, an aging test module 2 is provided in the second board area 12, and each primary aging sub-board 3 is connected to the aging test module 2. The aging test module 2, the primary aging sub-board 3 and the secondary aging sub-board are all PCB circuit boards of different specifications and sizes.

[0040] In the specific implementation process, by connecting the driving module 6 with the gold finger interface 111 on the aging motherboard 1, the upper computer 5 controls the driving module 6 via the communication bus to output the aging driving signal to the gold finger interface 111 on each aging motherboard 1, and then transmits it to the wiring interface 112 through the internal circuit. Through the signal transfer interface in the wiring interface 112, the aging driving signal can be further input into the aging socket 31 on each primary aging sub-board 3 in the aging test module 2, thereby driving each aging socket 31 to perform an aging test on the integrated circuit to be tested installed thereon.

[0041] In addition, by connecting the checkback module 7 to the signal output interface part in the cable interface 112 on the aging motherboard 1, during the aging test of the integrated circuit to be tested installed by each aging socket 31, the checkback signal in the aging test can be output through the signal output interface part in the cable interface 112, and then, the checkback module can obtain the checkback signal output by each aging socket 31 after the aging test through the cable interface 112, and detect each obtained checkback signal, so as to realize the verification and inspection of the aging test results of each integrated circuit to be tested.

[0042] In an embodiment of the present application, by cascading the aging motherboard 1, the aging test module 2, the first-level aging daughter board 3 and the second-level aging daughter board 4, the aging drive signal input by the gold finger interface 111 on the aging motherboard 1 can be led out to the pins of each aging socket 31, and the return check signal on the pin of the aging socket 31 can be output to the cable interface 112 of the aging motherboard 1. In addition, in the prior art, the design and manufacturing costs of the aging board are also relatively high, especially the cost of the aging seat on the aging board.

[0043] The device of the embodiment of the present application can reduce the number of times the screened components are installed and removed from the aging seat / test fixture through the modular cascade design in the cascade type integrated circuit aging device of the present application. There is no need to repeatedly replace the aging seat, and as many components as possible can be screened in a shorter time, thereby improving the efficiency of aging detection, saving screening costs, and reducing the probability of component pins being damaged during the installation and removal of the aging seat / test fixture.

[0044] In the prior art, the custom-made aging boards that take a long time to produce cannot be used for electrical parameter testing, which will further affect the efficiency of screening components before assembly.

[0045] Figure 4This is the third structural diagram of the cascade integrated circuit aging device provided in the embodiment of the present application, such as Figure 4 As shown, the second board area 12 is a hollow board structure, which is used to set the aging test module 2; the aging test module 2 is a turntable structure, and each primary aging sub-board 3 is set on the edge area of ​​the aging test module 2; The aging test module 2 is used to connect the aging sockets on each primary aging sub-board 3 to the test head 81 of the electrical parameter test system 8 in turn by rotating itself, so as to perform electrical parameter tests on each aging socket 31 on each aging test module 2 one by one.

[0046] Specifically, in the embodiment of the present application, the second board area 12 of the aging motherboard 1 can be designed as a hollow board structure to perfectly set the aging test module 2 inside the hollow board structure. At the same time, the aging test module 2 is designed as a turntable structure, and each primary aging sub-board 3 is set on the edge area of ​​the turntable structure, so as to facilitate the connection between the aging seat on the primary aging sub-board 3 and the test head 81 of the electrical parameter test system 8. Among them, the turntable structure of the aging test module 2 can be designed as a regular polygonal turntable structure, a circular turntable structure, etc.

[0047] For example, Figure 4 Two primary aging sub-boards 3 are arranged on the edge area of ​​the middle turntable structure. It is understandable that more primary aging sub-boards 3 can be arranged on the edge area of ​​the turntable structure according to actual test requirements.

[0048] In the actual implementation process, the center of the turntable structure can be fixed on the bracket next to the test head 81 of the electrical parameter test system 8, and the aging seat 31 on the first-level aging sub-board 3 set in the edge area of ​​the turntable is fixedly connected to the test head 81 for electrical parameter testing. After the test, the aging test module 2 is rotated by rotating the turntable structure, and the next aging seat 31 is fixedly connected to the test head 81. Similarly, by rotating and switching different aging seats 31, the aging seats 31 on each first-level aging sub-board 3 are connected to the test head 81 of the electrical parameter test system 8 in turn, so as to realize electrical parameter testing of each aging seat 31 one by one.

[0049] Figure 5 This is a fourth structural diagram of the cascade integrated circuit aging device provided in the embodiment of the present application, such as Figure 5 As shown, by adjusting the aging test modules 2 on each aging motherboard 1, it can be electrically connected to the test head 81 in the electrical parameter testing system 8 through its own rotation, thereby effectively realizing electrical parameter testing of several aging sockets 31 arranged on each aging test module 2.

[0050] It should be noted that the electrical parameter test of the burn-in socket mainly focuses on various parameters related to electrical performance, which are crucial to ensuring the reliability and durability of the integrated circuit products to be tested. The test content includes but is not limited to voltage testing, current testing, resistance testing, etc. Among them, the voltage test is used to test whether the voltage output by the burn-in socket is stable under different temperature, humidity and other conditions, and to verify whether the output voltage of the burn-in socket remains within the allowable error range after long-term operation; the current test is used to measure the current passing through the burn-in socket when simulating different environmental conditions, and to check whether the current exceeds the rated current of the burn-in socket to avoid overload and damage, etc.

[0051] The device of the embodiment of the present application adopts a cascaded method of multiple modules and designs the aging test module into a turntable structure. It is not only suitable for integrated circuit aging environment testing, but also the aging test module in the device can be used in the electrical parameter testing link, further improving the efficiency of electrical parameter testing and aging testing in component screening, realizing the integration of integrated circuit electrical parameter testing and aging testing, and further saving labor costs and material costs.

[0052] Continue to refer to Figure 4 Based on the contents of the above embodiments, as an optional embodiment, the turntable structure is a circular disc structure, and a plurality of mounting portions 21 (not all of which are marked in the figure) are evenly arranged on the edge area of ​​the circular disc structure, and the plurality of mounting portions 21 are used to install each primary aging sub-board 3.

[0053] Specifically, in the embodiment of the present application, the aging test module 2 of the turntable structure can be specifically designed as a disc structure, and according to the area of ​​the disc and the size of each primary aging sub-board 3, a plurality of mounting portions 21 can be evenly arranged on the edge area of ​​the disc structure.

[0054] Optionally, the mounting portion 21 can be fixedly connected to the primary aging sub-board 3 by welding connection, pin socket connection, etc., and this application does not make any specific limitation on this.

[0055] The device of the embodiment of the present application can install more aging sub-boards by designing the aging test module into a disc structure, thereby increasing the number of test aging sockets that can be accommodated on the aging test module. While realizing the integration of integrated circuit electrical parameter testing and aging testing, the test scale of the device can be further improved.

[0056] Continue to refer to Figure 3 Based on the content of the above embodiment, as an optional embodiment, brackets 121 are provided on both sides of the edge of the hollow structure, and a waist-round hole structure 122 is provided on the bracket; The oval hole structure 122 is used to adjust the installation distance of the aging test module 2 to adapt to the installation of aging test modules 2 of different sizes.

[0057] Specifically, in an embodiment of the present application, brackets 121 are arranged on both sides of the edges of the hollow structure of the second board area of ​​the aging motherboard 1, and a waist-shaped hole structure 122 is arranged on the bracket. Through the waist-shaped hole structure 122 on both sides, screws, bolts or other fasteners can be used to firmly fix the PCB board of the aging test module 2 on the bracket 121, thereby realizing the locking of the PCB board. The device of the embodiment of the present application fixes the aging test module by designing a bracket and a waist-shaped hole structure, providing a larger installation and adjustment space for the aging test module, so that the PCB board of the aging test module can be more easily aligned and fixed with the bracket, which is beneficial to improving the stability of the device during the aging test process, and can also adapt to the testing of aging test modules of different sizes.

[0058] Based on the contents of the above embodiments, as an optional embodiment, the peripheral functional circuit at least includes a power supply circuit, a signal input and output circuit, and a protection circuit.

[0059] Specifically, in an embodiment of the present application, the peripheral functional circuits integrated on the secondary aging sub-board 3 include at least a power supply circuit, a signal input and output circuit, and a protection circuit. That is to say, in addition to the integrated power supply circuit, signal input and output circuit, and protection circuit, the secondary aging sub-board 3 can also design and integrate other functional circuits, such as monitoring circuits, interface circuits, etc., according to actual test requirements.

[0060] Among them, in the embodiment of the present application, the power supply circuit can provide a stable operating voltage and current for the integrated circuit to be tested, which is the basis for ensuring the accuracy and reliability of the test, because an unstable power supply may cause deviations in the test results.

[0061] The signal input and output circuit can input the aging drive signal and the test signal into the IC under test through the pins of the aging socket, and receive its output signal. These signals may include digital signals, analog signals, and clock signals of specific frequencies. Through the signal input and output circuit, comprehensive testing of various functions of the IC under test can be achieved.

[0062] In order to protect the IC under test from damage during the test process, protection circuits are usually designed. These circuits can automatically cut off the power supply or adjust the test conditions in the event of excessive current, excessive voltage or abnormal temperature, thereby ensuring the safety of the test process.

[0063] In addition, in some embodiments, the peripheral functional circuit also includes an interface circuit, a monitoring circuit and a control circuit. Among them, the interface circuit can be used to connect the aging seat with external test equipment or systems, such as an oscilloscope, a signal generator, a data recorder, etc. Through the interface circuit, the transmission and sharing of test signal data and return signal data, as well as remote monitoring and analysis of test results can be realized; the monitoring circuit can be used to monitor the working state of the integrated circuit to be tested in real time, including parameters such as voltage, current, temperature and signal quality. These monitoring data can be used to evaluate the performance and reliability of the integrated circuit to be tested, and provide a basis for subsequent design and improvement; the control circuit can be used to control the working mode and test process of the aging seat.

[0064] These circuits may include microprocessors, programmable logic devices, etc., which can be programmed to implement complex test sequences and conditional controls.

[0065] It should be noted that different burn-in sockets and test requirements may correspond to different peripheral reference circuit designs. Therefore, in practical applications, it is necessary to design and select peripheral functional circuits based on specific test requirements and the characteristics of the integrated circuit to be integrated.

[0066] The device of the embodiment of the present application ensures that the aging test of the integrated circuit to be tested can run stably under specific environmental conditions by introducing peripheral functional circuits such as power supply circuits, signal input and output circuits, and protection circuits, and monitors performance changes or failures that may occur during long-term use, thereby improving the reliability and stability of the entire aging test.

[0067] Based on the content of the above embodiment, as an optional embodiment, the integrated circuit to be tested is mounted on the corresponding aging seat in a surface mount manner.

[0068] Specifically, in the embodiments of the present application, the contact area between the SMD packaged components and the circuit board will be larger, which helps to improve the reliability of the connection.

[0069] Furthermore, during the aging test, the integrated circuit may generate a lot of heat. By adopting the patch method, the heat can be more effectively transferred to the circuit board, thereby dissipating the heat through the circuit board.

[0070] In addition, the stable connection provided by the patch method can ensure the accurate transmission of the test signal in the aging test, thereby improving the accuracy of the test results. The device of the embodiment of the present application can improve connection reliability, heat dissipation performance, test accuracy and other aspects in the aging test by mounting the integrated circuit to be tested on the corresponding aging seat in a patch manner.

[0071] Based on the content of the above embodiment, as an optional embodiment, each aging socket is provided with a pin socket for plugging in the integrated circuit to be tested, so that the integrated circuit to be tested can be installed on the corresponding aging socket in a plug-in manner.

[0072] The device of the embodiment of the present application can improve the convenience of installation of the integrated circuit to be tested and facilitate replacement and maintenance by installing the integrated circuit to be tested on the corresponding aging socket in a plug-in manner; it allows convenient adjustment of test parameters during the test process, thereby improving the test flexibility of the device aging test; at the same time, the stable electrical contact through the plug-in method is conducive to further improving the accuracy of the device aging test results.

[0073] Optionally, the present application also provides an error correction method based on the aforementioned integrated circuit aging device to ensure the accuracy and stability of the device in practical applications. Specifically, in an embodiment of the present application, a corresponding error correction circuit is pre-set in the driving module and the checkback module, and the error correction method specifically includes the following steps: Step 1: Control the operation of the drive module and the check module, use a standard instrument to connect the cable interface on the aging motherboard to obtain the standard data of the aging test, and upload it to the host computer for data processing; Step 2: The expected values ​​of the driving and rechecking of the cascade integrated circuit aging device are associated with the standard values ​​measured by the external instrument through the host computer, and displayed in the host computer for data analysis.

[0074] Step three, for the associated data with small data deviation and regularity, linear fitting is performed using the error correction circuit in the corresponding driving module or back-check module, and error correction is performed on the hardware circuit in the operating device; for the associated data with large data deviation and randomness, the correction coefficient is calculated in sections using the calibration software preset by the host computer for error correction.

[0075] Among them, this embodiment uses an integrated dual-channel operational amplifier chip AD823 and metal film resistors with relatively good stability coefficient, voltage coefficient, heat resistance and noise index. The accuracy of the resistors is 1%. The precision resistors form a negative feedback circuit to achieve constant current output, providing a standard current source for the error correction module in this application.

[0076] The cascade integrated circuit aging method provided by the present invention is described below. The cascade integrated circuit aging method described below and the cascade integrated circuit aging device described above can be referred to each other.

[0077] Figure 6 is a flow chart of a cascade integrated circuit aging method provided in an embodiment of the present application, which can be applied to any of the aforementioned cascade integrated circuit aging devices, such as Figure 6 As shown, the method includes: Step S1, calling the host computer control driving module to input an aging driving signal to each aging motherboard, so as to introduce the aging driving signal to the corresponding primary aging daughter board through each aging test module, and perform an aging test on each integrated circuit to be tested; Step S2, calling the host computer to control the back-check module to obtain the back-check signals generated by each IC to be tested after the aging test from each aging motherboard, and testing each back-check signal.

[0078] It should be understood that the above method can be applied to the devices in the above embodiments, and its implementation principle and technical effects are similar to those described in the above device embodiments. The execution process of the method can refer to the execution process of the corresponding embodiment in the above device, which will not be repeated here.

[0079] The cascade integrated circuit aging method of the embodiment of the present application realizes a deep modular design of the integrated circuit aging device by adopting a multi-module cascade method, combined with a multi-level mother-and-child board structure consisting of an aging motherboard, a first-level aging daughter board, and a second-level aging daughter board. This makes the aging device have certain universal characteristics, improves the efficiency of the integrated circuit aging test, and saves labor costs and material costs.

[0080] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0081] It should be understood that expressions such as "including" and "may include" that may be used in the present application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In the present application, terms such as "including" and / or "having" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0082] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. Among them, "fixed connection" means that the two are connected to each other and the relative position relationship after the connection remains unchanged. "Rotational connection" means that the two are connected to each other and can rotate relative to each other after the connection. "Sliding connection" means that the two are connected to each other and can slide relative to each other after the connection. The directional terms mentioned in the embodiments of the present application, such as "upper", "lower", "outer", "inner", etc., are only reference to the directions of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0083] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A cascade integrated circuit aging device, characterized in that: include: It is composed of multiple modules connected in cascade, and is divided into: host computer, drive module, back-check module and multiple aging motherboards according to functional characteristics; Each of the aging motherboards is provided with an aging test module, a primary aging daughter board and a secondary aging daughter board which are connected in cascade in sequence; the primary aging daughter board is used to set the integrated circuit to be tested; the secondary aging daughter board is used to set the peripheral functional circuit matching the integrated circuit to be tested; The host computer is connected to each of the aging motherboards through the driving module, and is used to control the driving module to input an aging driving signal to each of the aging motherboards, so as to introduce the aging driving signal to the corresponding primary aging daughter board through each of the aging test modules, and perform an aging test on each of the integrated circuits to be tested; The host computer is connected to each of the aging motherboards through the back-check module, and is used to control the back-check module to obtain the back-check signal generated by each of the integrated circuits to be tested after the aging test, and to detect each of the back-check signals.

2. The cascade integrated circuit aging device according to claim 1, characterized in that: Each of the aged mother boards comprises a first board area and a second board area; The first board area is provided with a gold finger interface for introducing the aging drive signal, and a wiring interface for transmitting the aging drive signal to the aging test module; The second board area is used to set the aging test modules, and each of the aging test modules is connected to a plurality of the first-level aging sub-boards; each of the first-level aging sub-boards is provided with an aging seat for mounting the integrated circuit to be tested.

3. The cascade integrated circuit aging device according to claim 2, characterized in that: The second board area is a hollow board structure, used to set the aging test module; the aging test module is a turntable structure, and each of the first-level aging sub-boards is set on the edge area of ​​the aging test module; The aging test module can be used in the integrated circuit electrical parameter test link. By rotating itself, the aging sockets on each of the first-level aging sub-boards are connected to the test head of the electrical parameter test system in turn, so as to perform electrical parameter tests on each aging socket one by one.

4. The cascade integrated circuit aging device according to claim 3, characterized in that: The turntable structure is a circular disc structure, and a plurality of mounting parts are evenly arranged on the edge area of ​​the circular disc structure, and the plurality of mounting parts are used to mount each of the first-level aging sub-boards.

5. The cascade integrated circuit aging device according to claim 3, characterized in that: Brackets are arranged on both sides of the edge of the hollow structure, and a waist-round hole structure is arranged on the brackets; The oval hole structure is used to adjust the installation distance of the aging test module to adapt to the installation of aging test modules of different sizes.

6. The cascade integrated circuit aging device according to claim 2, characterized in that: Each of the first-level aging sub-boards is provided with a plurality of pin sockets for connecting with the corresponding plurality of second-level aging sub-boards in a plug-in manner.

7. The cascade integrated circuit aging device according to claim 2, characterized in that: The peripheral functional circuit at least includes a power supply circuit, a signal input and output circuit and a protection circuit.

8. The cascade integrated circuit aging device according to any one of claims 2 to 7, characterized in that: Each of the aging sockets is provided with a pin socket for plugging in the integrated circuit to be tested, so that the integrated circuit to be tested can be installed on the corresponding aging socket in a plug-in manner.

9. A cascade integrated circuit aging method applied to the cascade integrated circuit aging device according to any one of claims 1 to 8, characterized in that: include: Calling the host computer to control the driving module to input an aging driving signal to each of the aging motherboards, so as to introduce the aging driving signal into the corresponding primary aging daughter board through each of the aging test modules, and perform an aging test on each of the integrated circuits to be tested; The host computer is called to control the back-check module to obtain the back-check signals generated by each of the integrated circuits to be tested after the aging test from each of the aging motherboards, and to detect each of the back-check signals.

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