Minimum power supply voltage selection circuit and multi-power supply chip

Abstract

The embodiment of the invention provides a minimum power supply voltage selection circuit and a multi-power supply chip. The circuit comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a fifth switch tube, the source electrode of the first switch tube inputs a first voltage, and the drain electrode of the fourth switch tube inputs a second voltage; a grid electrode of the first switch tube is connected with a grid electrode and a source electrode of the second switch tube, a drain electrode of the first switch tube is connected with a grid electrode of the fourth switch tube, a source electrode of the fourth switch tube is connected with a drain electrode of the second switch tube, and minimum output voltage is led out to be input into an internal circuit; bias voltage is input into the grid electrode of the third switch tube and the grid electrode of the fifth switch tube, the grid electrodes of the third switch tube and the fifth switch tube are connected, the source electrodes are grounded, and the drain electrodes are respectively connected with the drain electrode of the first switch tube and the drain electrode of the second switch tube.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of electronic circuits, and in particular, to a minimum power supply voltage selection circuit and a multi-power supply chip. Background Art

[0002] A multi-power chip is a power management chip for electronic devices. It has multiple inputs and multiple outputs and can provide multiple stable output voltages to meet the power requirements of different components in electronic devices. How to provide stable power supply for electronic devices through power supply voltage selection circuits has become a key research direction.

[0003] The minimum power supply voltage selection circuit selects the minimum voltage output by comparing two or more input voltages. Currently, most circuits are designed to select the highest voltage comparison circuit from multiple power supplies in a multi-power supply chip, but not the lowest voltage circuit. Or, although the lowest voltage comparison circuit is set, the output of the lowest power supply voltage is inaccurate or cannot be loaded. When loaded, the level is inaccurate, which affects the circuit performance. Summary of the invention

[0004] In order to generate a minimum voltage that can carry a load and can adapt to various comparison conditions and process conditions, the embodiments described herein provide a minimum power supply voltage selection circuit and a multi-power supply chip.

[0005] According to a first aspect of the present disclosure, a minimum power supply voltage selection circuit is provided, comprising: a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a fifth switch tube; a first voltage is input to the source of the first switch tube, and a second voltage is input to the drain of the fourth switch tube; a gate of the first switch tube is connected to the gate and source of the second switch tube, a drain of the first switch tube is connected to the gate of the fourth switch tube, a source of the fourth switch tube is connected to the drain of the second switch tube, and a minimum output voltage is drawn out and input into an internal circuit; a bias voltage is input to the gate of the third switch tube and the gate of the fifth switch tube, the gates of the third switch tube and the fifth switch tube are connected, the sources are grounded, and the drains are respectively connected to the drain of the first switch tube and the drain of the second switch tube.

[0006] In some embodiments of the present disclosure, the width-to-length ratios of the third switch tube and the fifth switch tube are proportional, forming a bias current source for providing a proportional reference current for the first switch tube and the second switch tube.

[0007] In some embodiments of the present disclosure, the width-to-length ratio of the first switch tube and the second switch tube is proportional to the width-to-length ratio of the third switch tube and the fifth switch tube.

[0008] In some embodiments of the present disclosure, when the first voltage is higher than the second voltage, the first switch tube is turned on, the drain voltage of the first switch tube is equal to the first voltage, the fourth switch tube is turned on, and the minimum output voltage is equal to the second voltage.

[0009] In some embodiments of the present disclosure, when the second voltage is higher than the first voltage, the first switch tube is turned on, V min =V1-V gsMp1 +V gsMp2 , where V min is the minimum output voltage, V1 is the first voltage, V gsMp1 is the gate-source voltage of the first switch tube, V gsMp2 is the gate-source voltage of the second switch tube, the gate-source voltage of the first switch tube and the second switch tube are equal, V gsMp1 =V gsMp2 , so that the minimum output voltage is equal to the first voltage, that is, V min =V1.

[0010] In some embodiments of the present disclosure, the minimum output voltage port is connected to the internal circuit. When the first voltage is greater than the second voltage, the second voltage is used as the power supply potential of the internal circuit. When the first voltage is less than the second voltage, the first voltage is used as the power supply potential of the internal circuit.

[0011] In some embodiments of the present disclosure, the first switch tube and the second switch tube are PMOS tubes.

[0012] In some embodiments of the present disclosure, the third switch tube, the fourth switch tube and the fifth switch tube are NMOS tubes.

[0013] In the above circuit, the gate-source voltage of the first switch tube and the second switch tube directly affects their working state, thereby determining the minimum output voltage. The third switch tube and the fifth switch tube form a bias current source through a proportional width-to-length ratio. This provides a proportional reference current for the first switch tube and the second switch tube, thereby ensuring that their gate-source voltages can be maintained at the same level, avoiding excessive voltage differences, ensuring the stability of the circuit, and thus achieving precise control of the minimum voltage selection.

[0014] According to a second aspect of the present disclosure, a multi-power supply chip is provided, which includes the minimum power supply voltage selection circuit according to the first aspect of the present disclosure.

[0015] According to a third aspect of the present disclosure, an electronic device is provided, comprising the multi-power chip according to the second aspect of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0017] Figure 1 This is a circuit diagram for selecting the minimum power supply voltage using two switching tubes;

[0018] Figure 2 This is a schematic diagram of the minimum voltage output using two switching tubes;

[0019] Figure 3 This is a circuit diagram for selecting the minimum power supply voltage using a single NMOS tube;

[0020] Figure 4 This is a diagram of a voltage comparison circuit using an operational amplifier;

[0021] Figure 5 is a circuit structure diagram of a minimum power supply voltage selection circuit 100 according to an embodiment of the present disclosure;

[0022] Figure 6 It is a schematic diagram of the minimum power supply voltage load output result according to an embodiment of the present disclosure.

[0023] It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0026] The applicant found in the research that the common minimum power supply voltage selection circuit is as follows Figure 1As shown, two PN junctions or two switches are used to achieve low-level selection by comparing the input voltage. When the voltage on the opposite side (V1) is higher than the voltage on this side (V2), the gate-source voltage of the NMOS (Q2) on this side reaches the turn-on threshold, making the NMOS (Q2) on this side conduct, generating a low-level selection path. However, when the voltages on both sides tend to be consistent, Figure 2 As shown in the figure, when V1=V2, Vgs=Vds≈0V, and the nA-level current can pull Vmin down a lot, causing the NMOS to be unable to turn on effectively, making the minimum output voltage unable to operate with load, and the bias effect may cause the output voltage to be unstable, thereby increasing the deviation of the minimum output voltage and affecting the accuracy and stability of the entire circuit.

[0027] If only one NMOS (Q3) with a threshold voltage Vth≈0 is used to implement the minimum voltage selection circuit, as shown in Figure 3 As shown in the figure, when V1 is small, Vth=0, Vmin=V1; when V2 is small, Q3 is fully open, so Vmin=V2. However, the reality is that this NMOS can achieve Vth=0 at the tt process angle, but cannot achieve Vth=0V at other process angles, and has limited load capacity. In addition, it is affected by the bias effect and cannot meet the requirements of infinite impedance when the switch is turned off and very small impedance when turned on. Although it can carry load, it cannot achieve a small difference between Vmin and the two voltages.

[0028] Figure 4 This circuit uses an op amp as a voltage comparison circuit. For the minimum voltage output, the conduction of NMOS (Q4 or Q5) is controlled by the comparison result of the op amp. In this circuit structure, operational amplifiers A1, A2, and A3 will generate large static power consumption, and when the voltage difference is small, inaccurate voltage comparison will occur due to factors such as the op amp input offset voltage and input bias current.

[0029] In low-voltage power supply design, especially in applications where load conditions vary greatly, a stable and efficient power supply selection circuit is required to ensure that the minimum loadable voltage can be generated under various conditions. In order to generate a minimum loadable power supply voltage that adapts to multiple comparison conditions, an embodiment of the present disclosure proposes a minimum power supply voltage selection circuit that can select the lowest loadable voltage according to the size of the input voltage and can ensure that the circuit can work stably under different process conditions and load changes.

[0030] Figure 5 is a circuit structure diagram of a minimum power supply voltage selection circuit 100 according to an embodiment of the present disclosure. Figure 5As shown, the minimum power supply voltage selection circuit 100 includes: a first switch tube Mp1, a second switch tube Mp2, a third switch tube Mn1, a fourth switch tube Mn2 and a fifth switch tube Mn3. The source of the first switch tube Mp1 inputs the first voltage V1, the drain of the fourth switch tube Mn2 inputs the second voltage V2, the gate of the first switch tube Mp1 is connected to the gate and source of the second switch tube Mp2, the drain of the first switch tube Mp1 is connected to the drain of the third switch tube Mn1, the source of the fourth switch tube Mn2 is connected to the drain of the second switch tube Mp2, and the minimum output voltage Vmin is drawn out and input into the internal circuit.

[0031] The bias voltage Vbias is input to the gates of the third switch tube Mn1 and the fifth switch tube Mn3. The gates of the third switch tube Mn1 and the fifth switch tube Mn3 are connected, the source is grounded, and the drain is connected to the drain of the first switch tube Mp1 and the drain of the second switch tube Mp2 respectively. The third switch tube Mn1 and the fifth switch tube Mn3 form a current mirror and provide a proportional reference current for the first switch tube Mp1 and the second switch tube Mp2 as a bias current source.

[0032] In one embodiment of the present disclosure, the bias current source is implemented by a current mirror structure. In order to ensure the accuracy of the bias current source, the third switch tube Mn1 and the fifth switch tube Mn3 in the bias current source have a proportional width-to-length ratio (W / L), where W represents the width of the switch tube and L represents the length of the switch tube. The width-to-length ratio (W / L) determines the current transmission capability of the switch tube. The larger the width-to-length ratio, the greater the current that the switch tube can transmit. The bias voltage Vbias should be within a reasonable voltage range to avoid distortion in the saturation region or linear region. This design ensures current matching between multiple switch tubes and improves the accuracy, stability and power efficiency of the circuit.

[0033] In the embodiment of the present disclosure, the width-to-length ratio of the first switch tube Mp1 and the second switch tube Mp2 is proportional to the width-to-length ratio of the third switch tube Mn1 and the fifth switch tube Mn3, so that the current of the first switch tube Mp1 and the second switch tube Mp2 are accurately matched, ensuring that the two transistors can carry the same current, thereby making the gate-source voltage of the first switch tube Mp1 and the second switch tube Mp2 the same.

[0034] In the embodiment of the present disclosure, the first switch tube Mp1 and the second switch tube Mp2 are PMOS tubes, and the third switch tube Mn1, the fourth switch tube Mn2 and the fifth switch tube Mn3 are NMOS tubes.

[0035] exist Figure 5In the circuit shown, due to the linkage between the first switch tube Mp1 and the second switch tube Mp2, which voltage (V1 or V2) is smaller will be determined according to the input voltage. When the first voltage V1 is higher than the second voltage V2, the first switch tube Mp1 is turned on, the drain voltage of the first switch tube Mp1 is equal to the first voltage V1, and the fourth switch tube Mn2 is also turned on, so that the minimum output voltage Vmin is equal to the second voltage V2.

[0036] Specifically, when the input voltage V1 is relatively large, Mp1 is fully turned on. For a PMOS tube, it will be fully turned on when the gate-source voltage Vgs is large enough. When V1 is relatively large, the drain voltage of Mp1 is close to V1. In this case, since V1 is large, Mp1 is in the saturation region. When Mp1 is fully turned on, through the voltage condition connected to Mn2, Mn2 is fully turned on and the load current can flow. At this time, V min Controlled as V2.

[0037] When the second voltage V2 is higher than the first voltage V1, the first switch tube Mp1 is still turned on, but its on state is not completely saturated as before. At this time, there is a bias condition: V min =V1-V gsMp1 +V gsMp2 , where V min is the minimum output voltage, V1 is the first voltage, V gsMp1 is the gate-source voltage of the first switch tube Mp1, V gsMp2 is the gate-source voltage of the second switch tube Mp2.

[0038] Since the currents of Mp1 and Mp2 are matched, their gate-source voltages are the same. This means that in this state, VgsMp1 = VgsMp2 and the minimum output voltage V min is equal to the first voltage V1.

[0039] The purpose of the minimum power supply voltage selection circuit is to connect the minimum output voltage to the internal circuit to ensure that the circuit can operate stably at the minimum operating voltage. V1 and V2 can be input into the comparator. The function of the comparator is to monitor the magnitude relationship between the two voltages in real time. When the first voltage is greater than the second voltage, the second voltage is used as the power supply potential of the internal circuit. When the first voltage is less than the second voltage, the first voltage is used as the power supply potential of the internal circuit. Therefore, the circuit can dynamically select and adjust the minimum voltage. Through precise switch control, it is ensured that when the voltage selection is completed, the selected voltage will not be interfered by other factors (such as load changes), thereby ensuring the stability of the power supply voltage.

[0040] Figure 6 Schematic diagram of the minimum power supply voltage under load output result according to an embodiment of the present disclosure. Figure 6As shown, when V1 > V2, V2 serves as the internal power supply potential; when V1 < V2, the source terminal voltage of Mn2 will be clamped to V1, and V1 serves as the internal power supply potential. In the case of V1 = V2, the output minimum voltage does not fluctuate. The Vmin voltage can be stably output under different load conditions and allows for operation with a load.

[0041] Since the threshold voltage (Vth) of independent NMOS (especially native NMOS) may vary significantly under different process corners, this causes the circuit to be unable to fully turn off the switching transistors or operate stably at certain corners. Through the switching transistor and current matching mechanism, it can be ensured that the circuit can operate stably under different process and temperature conditions, thereby keeping Vmin at a relatively stable output. It can also avoid current flowing through an undesired conduction path when comparison cannot be made. By precisely controlling the conduction state of the switching transistor and current matching, it is possible to avoid unnecessary large current through regions during the comparison process of the minimum voltage selector and allow for operation with a load, which is crucial for the stability and reliability of the lowest voltage power supply in a multi-power system.

[0042] Embodiments of the present disclosure also provide a multi-power chip. The chip includes a minimum power supply voltage selection circuit according to the embodiments of the present disclosure. In addition, the multi-power chip may further include a maximum power supply voltage selection circuit.

[0043] Embodiments of the present disclosure also provide an electronic device. The electronic device includes a multi-power chip according to the embodiments of the present disclosure. The electronic device is, for example, a mobile device, an embedded system, a communication device, etc.

[0044] In summary, the small power supply voltage selection circuit according to the embodiments of the present disclosure not only avoids the inconsistency problem of the threshold voltage of NMOS under different process corners, but also improves the problems brought by the complete turn-off characteristics of the switching transistors, and avoids the mismatch problem between the ideally selected minimum power supply voltage and the actually selected minimum power supply voltage caused by the change of the threshold voltage. It can ensure that the circuit can operate stably under different process and temperature conditions, thereby keeping the minimum output voltage at a relatively stable output. By precisely controlling the conduction state of the switching transistor and current matching, it is possible to avoid unnecessary large current through regions during the comparison process of the minimum voltage selection circuit, thereby improving the efficiency and stability of the circuit. By dynamically selecting the minimum voltage, the circuit can operate stably at the lowest possible voltage, thereby minimizing power consumption and being applicable to devices in low-power, low-voltage operating environments.

[0045] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0046] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0047] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A minimum power supply voltage selection circuit, characterized in that: include: A first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a fifth switch tube; a first voltage is input to the source of the first switch tube, and a second voltage is input to the drain of the fourth switch tube; a gate of the first switch tube is connected to the gate and source of the second switch tube, a drain of the first switch tube is connected to the gate of the fourth switch tube, a source of the fourth switch tube is connected to the drain of the second switch tube, and a minimum output voltage is drawn out and input into an internal circuit; a bias voltage is input to the gate of the third switch tube and the gate of the fifth switch tube, the gates of the third switch tube and the fifth switch tube are connected, the sources are grounded, and the drains are respectively connected to the drain of the first switch tube and the drain of the second switch tube.

2. The minimum power supply voltage selection circuit according to claim 1, characterized in that: The width-to-length ratios of the third switch tube and the fifth switch tube are proportional, and they constitute a bias current source for providing a reference current for the first switch tube and the second switch tube.

3. The minimum power supply voltage selection circuit according to claim 1 or 2, characterized in that: The width-to-length ratio of the first switching tube to the second switching tube is proportional to the width-to-length ratio of the third switching tube to the fifth switching tube.

4. The minimum power supply voltage selection circuit according to claim 1, characterized in that: When the first voltage is higher than the second voltage, the first switch tube is turned on, the drain voltage of the first switch tube is equal to the first voltage, the fourth switch tube is turned on, and the minimum output voltage is equal to the second voltage.

5. The minimum power supply voltage selection circuit according to claim 1, characterized in that: When the second voltage is higher than the first voltage, the first switch is turned on, V min =V1-V gsMp1 +V gsMp2 , where V min is the minimum output voltage, V1 is the first voltage, V gsMp1 is the gate-source voltage of the first switch tube, V gsMp2 is the gate-source voltage of the second switch tube.

6. The minimum power supply voltage selection circuit according to claim 5, characterized in that: The gate-source voltages of the first switch tube and the second switch tube are equal, and the minimum output voltage is equal to the first voltage.

7. The minimum power supply voltage selection circuit according to claim 2, characterized in that: The minimum output voltage port is connected to an internal circuit. When the first voltage is greater than a second voltage, the second voltage is used as a power supply potential of the internal circuit. When the first voltage is less than the second voltage, the first voltage is used as a power supply potential of the internal circuit.

8. The minimum power supply voltage selection circuit according to claim 1, characterized in that: The first switch tube and the second switch tube are PMOS tubes.

9. The minimum power supply voltage selection circuit according to claim 1, characterized in that: The third switch tube, the fourth switch tube and the fifth switch tube are NMOS tubes.

10. A multi-power chip, characterized in that: The method comprises a minimum power supply voltage selection circuit according to any one of claims 1 to 9.

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