Low-power-consumption linear voltage stabilizing circuit and voltage stabilizing power supply

Abstract

The invention relates to a low-power-consumption linear voltage stabilizing circuit and a voltage stabilizing power supply. The low-power-consumption linear voltage stabilizing circuit comprises a depletion type field effect transistor, a voltage stabilizing circuit, a voltage stabilizing circuit and a voltage stabilizing circuit, the feedback circuit is connected in series with the depletion mode field effect transistor to form a first current branch and is used for generating feedback voltage according to the output voltage; and the control circuit is connected in series with the depletion type field effect transistor to form a second current branch and is used for generating a starting voltage not less than a starting threshold according to the feedback voltage when the power supply voltage is reduced to the output voltage so as to adjust the output voltage to be stable according to the starting voltage. The two current branches are adopted, so that the quiescent current can be further reduced, and the extreme low-power-consumption requirement is met. Meanwhile, a depletion mode field effect transistor is used as a power tube, and the power tube can still be normally started to work when the power supply voltage is low to the output voltage, so that enough high output voltage can be provided for a post-stage circuit to use in a scene that the power supply voltage is relatively low.

Description

Technical Field

[0001] The present invention relates to the field of power supply circuits, and in particular to a low-power linear voltage stabilization circuit and a voltage stabilization power supply. Background Art

[0002] For various electronic products with low power consumption standby requirements, a DC regulated power supply with low quiescent current is usually required to power the standby control circuit. The power consumption of the standby power supply directly affects the standby power consumption of the whole machine, so its quiescent current needs to be reduced as much as possible.

[0003] In the prior art, in order to meet the low power consumption requirement, the following deficiencies still exist in common voltage stabilization circuits: (1) The circuit has a large static current: The voltage regulator uses three current branches. Although it can reduce power consumption, due to the large number of current branches, the circuit itself consumes a large current, making it difficult to further reduce the static current and unable to meet the extreme low power consumption requirement. (2) Output voltage is limited: The voltage regulator of the prior art uses an enhancement field effect transistor (MOSFET) as a power tube. Due to the characteristics of the enhancement MOSFET, its output voltage can only reach the maximum power supply voltage minus the power tube gate-source voltage (Vgs, which is about 1V). This limitation results in the inability to provide a sufficiently high output voltage for the subsequent circuit in the scenario of low power supply voltage. (3) Dependence of static current on power supply voltage: In common standby power generation circuits, its static current is proportional to the power supply voltage. When the power supply voltage has a large variation range, the static current fluctuates accordingly, resulting in the inability to achieve stable and ultra-low standby power consumption within the entire power supply voltage range.

[0004] In view of the above problems, the present invention aims to provide solutions to overcome these technical defects. Summary of the invention

[0005] The present invention provides a low-power linear voltage-stabilizing circuit and a voltage-stabilizing power supply to solve at least one of the above-mentioned technical problems.

[0006] The technical solution of the present invention to solve the above technical problem is as follows: a low-power linear voltage stabilizing circuit, comprising: A depletion-type field effect transistor, comprising an input terminal, an output terminal and a control terminal, wherein the input terminal is connected to a power supply voltage, and the output terminal is used to output an output voltage; the depletion-type field effect transistor is provided with a start threshold, and the start threshold is less than zero; A feedback circuit, connected to the output terminal and connected in series with the depletion-type field effect transistor to form a first current branch, and used to generate a feedback voltage according to the output voltage; A control circuit is connected to the depletion-type field effect transistor and the feedback circuit, and is connected in series with the depletion-type field effect transistor to form a second current branch, and is used to generate a startup voltage that is not less than the startup threshold according to the feedback voltage when the supply voltage is reduced to the output voltage, and then adjust the output voltage to be stable according to the startup voltage.

[0007] Based on the above technical solution, the present invention can also be improved as follows.

[0008] Further, the feedback circuit includes a first resistor and a second resistor connected in series between the output terminal and the ground, and a feedback node, the feedback node is located between the first resistor and the second resistor, and is connected to the control circuit; The feedback voltage is generated by the first resistor and the second resistor, and is fed back to the control circuit through the feedback node according to a voltage division ratio.

[0009] Further, the feedback circuit comprises: A clamping subcircuit, connected to the output terminal, for performing a fixed voltage drop on the output voltage and generating a clamping current related to the output voltage; The sampling sub-circuit is connected to the clamping sub-circuit and the control circuit, and is used for sampling the clamping current to generate the feedback voltage.

[0010] Further, the clamping subcircuit includes a Zener diode; the sampling subcircuit includes a sampling MOS tube; The cathode of the Zener diode is connected to the output end, and the anode of the Zener diode is connected to the drain of the sampling MOS tube; the gate and drain of the sampling MOS tube are short-circuited, and the gate is connected to the control circuit, and the source of the sampling MOS tube is grounded.

[0011] Further, the clamping subcircuit includes a MOS tube cascade formed by a plurality of diodes connected in series, the gate and drain of the MOS tube cascade are short-circuited, the drain is connected to the output end, and the source is connected to the sampling subcircuit; The sampling subcircuit comprises a sampling MOS tube, the drain of the sampling MOS tube is connected to the source of the MOS tube cascade, the gate and the drain are short-circuited, the gate is connected to the control circuit, and the source of the sampling MOS tube is grounded.

[0012] Furthermore, the control circuit comprises: A control subcircuit, connected to the feedback circuit, for generating a pull-down current according to the feedback voltage and controlling the voltage of the control terminal of the depletion-type field effect transistor; A startup voltage generating subcircuit is connected to the control subcircuit and the depletion-type field effect transistor, and is used to generate the startup voltage not less than the startup threshold according to the pull-down current when the supply voltage is lower than the output voltage, and control the output voltage to be stable according to the startup voltage.

[0013] Furthermore, the control subcircuit comprises: An enhanced N-type field effect transistor, whose gate is connected to the feedback circuit, whose source is grounded, and whose drain is connected to the start-up voltage generating sub-circuit.

[0014] Furthermore, the startup voltage generating subcircuit includes: A pull-down resistor, one end of which is connected between the control end of the depletion-type field effect transistor and the drain of the enhancement-type N-type field effect transistor, and the other end of which is connected to the output end of the depletion-type field effect transistor, is used to generate the startup voltage not less than the startup threshold according to the pull-down current and the output voltage when the supply voltage is lower than the output voltage, and to control the output voltage to be stable according to the startup voltage.

[0015] Furthermore, the startup voltage generating subcircuit includes: A pull-down resistor, one end of which is connected between the control end of the depletion-type field effect transistor and the drain of the enhancement-type N-type field effect transistor, and the other end of which is connected to the input end of the depletion-type field effect transistor, is used to generate the startup voltage not less than the startup threshold according to the pull-down current and the supply voltage when the supply voltage is lower than the output voltage, and control the output voltage to be stable according to the startup voltage.

[0016] Based on the above-mentioned low-power linear voltage-stabilizing circuit, the present invention further provides a voltage-stabilizing power supply, which includes the above-mentioned low-power linear voltage-stabilizing circuit.

[0017] The beneficial effect of the present invention is that in a low-power linear voltage-stabilizing circuit and a voltage-stabilizing power supply of the present invention, only two current branches are required, namely, a first current branch formed by a feedback circuit and a depletion-type field-effect transistor in series and a second current branch formed by a control circuit and a depletion-type field-effect transistor in series. Compared with the three current branches in the prior art, the present invention uses two current branches to further reduce the current consumed by the circuit itself, thereby further reducing the static current, thereby meeting the extreme low power consumption requirements. At the same time, the present invention uses a depletion-type field-effect transistor as a power tube to support low power supply voltage requirements; since the start-up threshold of the depletion-type field-effect transistor is less than zero, when the power supply voltage is as low as the output voltage, the depletion-type field-effect transistor can still be turned on and work normally, and then in the scenario where the power supply voltage is low, the present invention can also provide a sufficiently high output voltage for use by the subsequent circuit. In addition, the present invention utilizes feedback regulation of the feedback circuit and the control circuit to effectively control the output voltage stability, and adjusting the feedback circuit can change the output voltage, so the load regulation rate is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A structural block diagram of a low power consumption linear voltage stabilizing circuit of the present invention; Figure 2 Another structural block diagram of a low power consumption linear voltage stabilizing circuit of the present invention; Figure 3 It is a schematic diagram of a depletion-type field effect transistor in a low-power linear voltage-stabilizing circuit of the present invention; Figure 4 A schematic diagram of a structure of a feedback circuit in a low-power linear voltage stabilization circuit of the present invention; Figure 5 A structural block diagram of a feedback circuit in a low-power linear voltage stabilization circuit of the present invention; Figure 6 for Figure 5 A specific structural diagram of the feedback circuit; Figure 7 for Figure 5 Another specific structural schematic diagram of the feedback circuit; Figure 8 A structural block diagram of a control circuit in a low-power linear voltage stabilizing circuit of the present invention; Fig. 9 Another structural block diagram of a control circuit in a low-power linear voltage stabilizing circuit of the present invention; Fig.10 for Figure 8 Specific structural diagram of the control circuit; Fig.11 for Fig. 9 Specific structural diagram of the control circuit; Fig.12This is a first circuit schematic diagram of a low-power linear voltage stabilizing circuit of the present invention; Fig.13 A second circuit schematic diagram of a low-power linear voltage stabilizing circuit of the present invention; Fig.14 A third circuit schematic diagram of a low power linear voltage stabilizing circuit of the present invention; Fig.15 This is a fourth circuit principle diagram of a low-power linear voltage stabilizing circuit of the present invention. DETAILED DESCRIPTION

[0019] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0020] like Figure 1 or Figure 2 As shown, a low power consumption linear voltage regulator circuit comprises: The depletion type field effect transistor 1 comprises an input terminal 11, an output terminal 12 and a control terminal 13. The input terminal 11 is connected to a power supply voltage The output terminal 12 is used to output the output voltage , the depletion-type field effect transistor 1 is provided with a start threshold, and the start threshold is less than zero; The feedback circuit 2 is connected to the output terminal 12 and is connected in series with the depletion-type field effect transistor 1 to form a first current branch for Generate feedback voltage ; The control circuit 3 is connected to the output terminal 12 or the input terminal 11 of the depletion-type field effect transistor 1, the control terminal 13 and the feedback circuit 2, and is connected in series with the depletion-type field effect transistor 1 to form a second current branch for Output voltages as low as When the feedback voltage Generate a starting voltage not less than the starting threshold , and then according to the starting voltage Regulate the output voltage Stablize.

[0021] Figure 1 In the low power consumption linear voltage regulator circuit shown, the control circuit 3 is connected to the output terminal 12; Figure 2 In the low power consumption linear voltage regulator circuit shown, the control circuit 3 is connected to the input terminal 11 .

[0022] In a low-power linear voltage stabilization circuit of the present invention, only two current branches are required, namely, a first current branch formed by a feedback circuit 2 and a depletion-type field effect transistor 1 in series, and a second current branch formed by a control circuit 3 and a depletion-type field effect transistor 1 in series. Compared with the three current branches in the prior art, the present invention uses two current branches to further reduce the current consumed by the circuit itself, thereby further reducing the static current, thereby meeting the extreme low power consumption requirements. At the same time, the present invention uses a depletion-type field effect transistor 1 as a power tube to support low supply voltage Requirements; Since the start threshold of the depletion-type field effect transistor 1 is less than zero, the supply voltage Output voltage as low as When the depletion-type field effect transistor 1 can still be turned on and work normally, In lower scenarios, the present invention can also provide a sufficiently high output voltage In addition, the present invention utilizes the feedback regulation of the feedback circuit 2 and the control circuit 3 to effectively control the output voltage. The output voltage can be changed by adjusting the feedback circuit 2, so the load regulation rate is better.

[0023] In some embodiments, Figure 3 As shown, the depletion-type field effect transistor 1 is specifically a depletion-type N-type field effect transistor MDN, whose drain is the input terminal 11 , whose source is the output terminal 12 , and whose gate is the control terminal 13 .

[0024] Specifically, the threshold voltage of the depletion-type N-type field effect transistor MDN is is the start threshold, and Compared with the enhancement type field effect transistor, the threshold voltage of the depletion type N-type field effect transistor MDN is less than zero, that is, the gate-source voltage of the depletion type N-type field effect transistor MDN is , it can still maintain the on state, this feature makes the supply voltage Output voltage as low as The depletion-type N-type field effect transistor MDN can still work. However, the enhancement-type field effect transistor has a gate-source voltage of Under the condition of the cut-off state (non-conducting), the circuit cannot work; therefore, in order to support the low supply voltage, the output voltage can be generated sufficiently high when the supply voltage is low. The present invention preferably uses a depletion type N-type field effect transistor MDN as a power tube to provide an output voltage for a load connected to the output terminal 12. and load current.

[0025] In some embodiments, Figure 4As shown, the feedback circuit 2 includes a first resistor R1 and a second resistor R2 connected in series between the output terminal 12 and the ground, and a feedback node, the feedback node is located between the first resistor R1 and the second resistor R2, and is connected to the control circuit 3; the feedback voltage is generated by the first resistor R1 and the second resistor R2 , and is fed back to the control circuit 3 through the feedback node according to the voltage division ratio.

[0026] Specifically, the first resistor R1 and the second resistor R2 form a voltage divider structure to divide the output voltage Feedback is given to the control circuit 3 according to the resistance ratio R2 / (R1+R2), so that the control circuit 3 can accurately adjust the output voltage Provide a stable basis.

[0027] If the output voltage The accuracy requirement is not high, and the feedback circuit 2 can also be used as follows Figure 5 The structure shown.

[0028] In other embodiments, Figure 5 As shown, the feedback circuit 2 includes: The clamping subcircuit 21 is connected to the output terminal 12 and is used to clamp the output voltage A fixed voltage drop is performed and an output voltage The associated clamping current; The sampling subcircuit 22 is connected to the clamping circuit 21 and the control circuit 3 and is used to sample the clamping current to generate the feedback voltage .

[0029] Specifically, the voltage drop of the clamping subcircuit 21 is fixed, so the current flowing through the clamping circuit 21 changes with the output voltage. The sampling subcircuit 22 samples the clamping current flowing through the clamping subcircuit 21 to obtain the sampling current, and converts the sampling current into a feedback voltage .

[0030] In some embodiments, Figure 6 As shown, the clamping sub-circuit 21 includes a Zener diode Dz, and the sampling sub-circuit 22 includes a sampling MOS tube MS; the cathode of the Zener diode Dz is connected to the output terminal 12, and the anode of the Zener diode Dz is connected to the drain of the sampling MOS tube MS; the gate and the drain of the sampling MOS tube MS are short-circuited, and the gate is connected to the control circuit 3, and the source of the sampling MOS tube MS is grounded.

[0031] Specifically, the clamping subcircuit 21 uses a Zener diode Dz with a fixed voltage drop, and the sampling subcircuit 22 uses a sampling MOS tube MS as a current sampling tube to sample the clamping current flowing through the Zener diode Dz. The voltage drop of the Zener diode Dz is weakly related to its own current, that is, ,in, is the fixed voltage drop of the Zener diode Dz, is the threshold voltage of the Zener diode Dz, is the clamping current of the Zener diode Dz; therefore, it can be approximately considered that the output voltage The current of the Zener diode Dz Weakly correlated; due to the output voltage The clamping current of the Zener diode Dz is approximately weakly correlated, so if the output voltage The accuracy requirement is not high, and the feedback circuit 2 can be used as follows Figure 6 The structure shown.

[0032] In other embodiments, Figure 7 As shown, the clamping subcircuit 21 includes a MOS tube cascade M formed by a plurality of diodes connected in series, the gate and drain of the MOS tube cascade M are short-circuited, the drain is connected to the output terminal 12, and the source is connected to the sampling subcircuit 22; The sampling subcircuit 22 includes a sampling MOS tube MS, the drain of the sampling MOS tube MS is connected to the source of the MOS tube cascade M, the gate and the drain are short-circuited, and the gate is connected to the control circuit 3, and the source of the sampling MOS tube MS is grounded.

[0033] Figure 7 In the example, a MOS tube cascade M formed by multiple series-connected diodes is used instead. Figure 6 The Zener diode Dz in the middle, that is, the voltage drop is relatively fixed. The gate and drain of the MOS tube cascade M are short-circuited to form a diode-connected MOS tube. The I / V characteristics of a diode-connected MOS tube are similar to those of a diode (the gate and drain are anodes, and the source is cathode); therefore, the voltage drop of the MOS tube cascade M is also related to its own clamping current, that is, ,in, is the fixed voltage drop of the MOS tube cascade M, is the threshold voltage of the MOS tube cascade M, is the clamping current of the MOS tube cascade M; therefore, it can be approximately considered that the output voltage Clamping current of cascaded MOS tube M Weakly correlated; due to the output voltage Clamping current of cascaded MOS tube M is approximately weakly correlated, so if the output voltage The accuracy requirement is not high, and the feedback circuit 2 can also be used as follows Figure 7 The structure shown.

[0034] In some embodiments, Figure 8 or Fig. 9 As shown, the control circuit 3 includes: The control subcircuit 31 is connected to the feedback circuit 2 and is used to control the feedback voltage according to the feedback voltage. Generate a pull-down current and control the voltage of the control terminal 13 of the depletion-type field effect transistor 1; The startup voltage generating sub-circuit 32 is connected to the control sub-circuit 31 and the depletion-type field effect transistor 1 and is used to generate a startup voltage at the supply voltage. Output voltages as low as When the pull-down current generates the starting voltage which is not less than the starting threshold value, , and according to the starting voltage Controlling the output voltage Stablize.

[0035] Figure 8 The start-up voltage generating sub-circuit 32 in the control circuit 3 shown is connected to the output terminal 12; Fig. 9 The starting voltage generating subcircuit 32 in the control circuit 3 shown is connected to the input terminal 11 .

[0036] The control circuit 3 controls the output voltage according to the feedback circuit 2. Feedback voltage obtained by feedback For output voltage Control to ensure the output voltage Specifically, when the output voltage When the target voltage is higher than the target voltage, the feedback circuit 2 will Feedback voltage obtained by feedback The pull-down current generated by the control subcircuit 31 increases, thereby increasing the startup voltage generated by the startup voltage generating subcircuit 32. Decrease; due to the threshold voltage of the depletion-type N-type field effect transistor MDN Less than zero, even if the starting voltage The gate-source voltage of the depletion-type N-type field effect transistor MDN decreases When the power supply voltage decreases, it can still maintain the on state. This characteristic makes the power supply voltage Output voltage as low as The depletion type N-type field effect transistor MDN can still work; due to the startup voltage generated by the startup voltage generating subcircuit 32 The gate voltage of the depletion-type N-type field effect transistor MDN decreases, which makes the gate-source voltage of the depletion-type N-type field effect transistor MDN This eventually causes the source-drain current of the depletion-type N-type field effect transistor MDN to decrease. decreases, thus making the output voltage When the output voltage The situation when the relative target voltage is lower than that when it is higher is opposite to that when the relative target voltage is higher, and will not be described in detail here.

[0037] In some embodiments, Fig.10 As shown, the control subcircuit 31 includes: The enhanced N-type field effect transistor MN has a gate connected to the feedback circuit 2 , a source connected to the ground, and a drain connected to the start-up voltage generating sub-circuit 32 .

[0038] against Figure 8 In the control circuit 3 shown, the starting voltage generating subcircuit 32 includes: A pull-down resistor Rpd has one end connected between the control end 13 of the depletion-type field effect transistor 1 and the drain of the enhancement-type N-type field effect transistor MN, and the other end connected to the output end 12 of the depletion-type field effect transistor 1, for Output voltages as low as When the pull-down current and the output voltage Generate the startup voltage not less than the startup threshold , and according to the starting voltage Controlling the output voltage Stablize.

[0039] The enhanced N-type field effect transistor MN is used as a control tube, which generates a pull-down current according to the gate voltage. The gate voltage of the enhanced N-type field effect transistor MN is controlled by the feedback circuit 2 to output the voltage. The enhanced N-type field effect transistor MN is provided according to the output voltage The pull-down current generated.

[0040] The pull-down resistor Rpd is connected to the control terminal 13 and the output terminal 12, that is, connected between the gate source of the depletion type N-type field effect transistor MDN, so that the static current of the low-power linear voltage regulator circuit of the present invention is proportional to the supply voltage. Specifically, the quiescent current is the current consumed by the circuit itself and not transmitted to the load. The quiescent current of the low-power linear voltage regulator circuit of the present invention consists of two parts, one is the current flowing to the feedback circuit 2, and the other is the current flowing to the control circuit 3. In a stable state, the current flowing to the feedback circuit 2 remains unchanged and is proportional to the supply voltage. The current flowing to the control circuit 3 is the current flowing through the pull-down resistor Rpd, which is equal to the gate-source voltage of the depletion-type N-type field effect transistor MDN divided by the pull-down resistor Rpd, and the gate-source voltage of the depletion-type N-type field effect transistor MDN is only related to the current of the depletion-type N-type field effect transistor MDN, and the current of the depletion-type N-type field effect transistor MDN is related to the supply voltage Therefore, the current flowing to the control circuit 3 is also related to the supply voltage Not related to supply voltage The feedback circuit 2 current is independent of the supply voltage The quiescent current is naturally related to the supply voltage. Therefore, when the supply voltage When there is a large variation range, the present invention can obtain stable standby power consumption in the entire range.

[0041] against Fig. 9 The control circuit 3 shown in FIG. When the variation range is small and the load current is large, the starting voltage generating sub-circuit 32 can also be used as follows Fig.11 The structure shown is used to increase the maximum current capability of the depletion-type N-type field effect transistor MDN.

[0042] In other embodiments, Fig.11 As shown, the startup voltage generating subcircuit 32 includes: A pull-down resistor Rpd has one end connected between the control end 13 of the depletion-type field effect transistor 1 and the drain of the enhancement-type N-type field effect transistor MN, and the other end connected to the input end 11 of the depletion-type field effect transistor 1, for Output voltages as low as When the pull-down current and the output voltage Generate the startup voltage not less than the startup threshold , and according to the starting voltage Controlling the output voltage Stablize.

[0043] exist Fig.11 In the structure shown, the pull-down resistor Rpd is connected between the gate and drain of the depletion-type N-type field effect transistor MDN. At this time, the current flowing through the pull-down resistor Rpd is equal to the supply voltage Subtract the starting voltage The difference is divided by the pull-down resistor Rpd, so the current flowing through the control circuit 3 is equal to the supply voltage related to the supply voltage, which makes the quiescent current also Although, the quiescent current is related to the supply voltage Related, but the above also states that the supply voltage The variation range is small, so the standby power consumption variation that can be obtained by the invention in the entire range is relatively small. The pull-down resistor Rpd connected between the gate and drain of the depletion-type N-type field effect transistor MDN can increase the maximum current capability of the depletion-type N-type field effect transistor MDN, thereby improving the maximum driving capability under the same device conditions.

[0044] The optimal low power consumption linear voltage regulator circuit formed by using some of the above embodiments is as follows: Fig.12 At this time: Source-drain current of depletion-type N-type field effect transistor MDN for: ; (1) in, It is a constant related to the characteristics of the depletion-type N-type field effect transistor MDN itself; is the gate-source voltage of the depletion-type N-type field effect transistor MDN, which is equal to Therefore, the source-drain current of the depletion-type N-type field effect transistor MDN is The transformed expression is: ; (2) Source-drain current of depletion-type N-type field effect transistor MDN is the total current of the low-power linear voltage regulator circuit. After passing through the depletion-type N-type field effect transistor MDN, the current is divided into three current branches. The first part flows to the load connected to the output terminal 12, which is called the load current; the second part is the current flowing to the first resistor R1 and the second resistor R2, and the third part is the current flowing to the pull-down resistor Rpd and the enhanced N-type field effect transistor MN; the current flowing to the first resistor R1 and the second resistor R2 and the current flowing to the pull-down resistor Rpd and the enhanced N-type field effect transistor MN are consumed by the circuit itself, so their sum is the static current; and then there is the following relationship: ; (3) in, represents the current flowing to the first resistor R1 and the second resistor R2, Represents the current flowing to the pull-down resistor Rpd and the enhanced N-type field effect transistor MN; Indicates load current; Indicates the total current of the low power linear voltage regulator circuit; represents the quiescent current, , it can be seen that the static current With supply voltage Not relevant.

[0045] Source-drain current of enhanced N-type field effect transistor MN for: ; (4) Among them, the source-drain current of the enhanced N-type field effect transistor MN It is also the current flowing through the pull-down resistor Rpd. ; It is a constant related to the characteristics of the enhanced N-type field effect transistor MN itself; is the threshold voltage of the enhanced N-type field effect transistor MN; is the voltage across the second resistor R2, and ; (5) The current flowing to the first resistor R1 and the second resistor R2, the current flowing to the pull-down resistor Rpd and the enhanced N-type field effect transistor MN, and the load current When both are small, When , according to equations (2) to (5), it can be deduced that: Combining equations (5) and (7), the output voltage can be derived : ; Combining equations (3), (5), (6) and (7), the static current can be derived : .

[0046] From this we can see that Fig.10 The output voltage of the low power linear voltage regulator circuit Very stable, quiescent current Very small, and quiescent current With supply voltage In addition, the output voltage can be adjusted by adjusting the resistance ratio of the first resistor R1 and the second resistor R2. Therefore, the output voltage of the present invention Adjustable, with good load regulation.

[0047] In addition, if Fig.12 As shown, the low power consumption linear voltage stabilizing circuit of the present invention has fewer active devices, only two, so the circuit structure is very simple and the power consumption is extremely low.

[0048] If the output voltage accuracy requirement is not high, you can use Fig.13 or Fig.14 The low power linear voltage regulator circuit shown.

[0049] exist Fig.13In the low-power linear voltage regulator circuit shown in FIG. 1 , the size ratio of the sampling MOS tube MS to the enhanced N-type field effect tube MN is N:1, then: in, is the gate-source voltage of the enhanced N-type field effect transistor MN.

[0050] At load current , when the pull-down resistor Rpd current and N are small, it satisfies When , according to equations (8) to (10), it can be deduced that: ; ; From this we can see that Fig.11 The output voltage of the low power linear voltage regulator circuit Very stable, quiescent current Very small, and quiescent current Also with the supply voltage In addition, by selecting a Zener diode Dz with a different fixed voltage drop, the output voltage can be changed. Therefore, the output voltage of the present invention Adjustable, with good load regulation.

[0051] Fig.14 The low power linear regulator circuit shown is Fig.13 The low power linear voltage regulator circuit shown has the same properties, except that a MOS tube M formed by multiple series diodes is cascaded instead of Fig.13 The Zener diode Dz in the embodiment will not be described in detail here. In addition, by selecting a plurality of diodes connected in series to form a MOS tube cascade M, different fixed voltage drops can be obtained, thereby changing the output voltage Therefore, the output voltage of the present invention Adjustable, with good load regulation.

[0052] For supply voltage When the variation range is small and the load current is large, the following can be used: Fig.15 The low power linear voltage regulator circuit shown in the figure, wherein the pull-down resistor Rpd is connected between the gate and drain of the depletion type N-type field effect transistor MDN to improve the maximum current capability of the depletion type N-type field effect transistor MDN.

[0053] exist Fig.15 In the low-power linear voltage regulator circuit shown, there is the following relationship: ; (11) ; (12) ; (13) According to equations (11) to (13), it can be deduced that: Fig.15 The quiescent current and supply voltage in the low power linear regulator circuit shown Related. Fig.15 The low power linear regulator circuit shown is Fig.12 Compared with the low power linear regulator circuit shown in the figure, the only difference is the quiescent current and supply voltage Related; although Fig.15 The low power linear regulator circuit shown has no Fig.12 The quiescent current in the low power linear regulator circuit shown is stable, but the supply voltage When the range of variation is small, Fig.15 The low power linear voltage regulator circuit shown has a smaller quiescent current variation range and relatively stable standby power consumption compared to the prior art. Fig.15 The maximum driving capability of the low power linear voltage regulator circuit shown is improved under the same device conditions.

[0054] Based on the above-mentioned low-power linear voltage-stabilizing circuit, the present invention further provides a voltage-stabilizing power supply, which includes the above-mentioned low-power linear voltage-stabilizing circuit.

[0055] The voltage-stabilized power supply of the present invention adopts the above-mentioned low-power linear voltage-stabilized circuit, so the voltage-stabilized power supply of the present invention has low static current and meets the extreme low power consumption requirements; at the same time, it supports low power supply voltage requirements, and when the power supply voltage is as low as the output voltage, it can also provide a sufficiently high output voltage for use by the subsequent circuit; in addition, it also has the advantage of better load regulation rate.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A low power linear voltage regulator circuit, characterized in that: include: A depletion-type field effect transistor, comprising an input terminal, an output terminal and a control terminal, wherein the input terminal is connected to a power supply voltage, and the output terminal is used to output an output voltage; The depletion-type field effect transistor is provided with a start-up threshold; A feedback circuit, connected to the output terminal and connected in series with the depletion-type field effect transistor to form a first current branch, and used to generate a feedback voltage according to the output voltage; A control circuit is connected to the depletion-type field effect transistor and the feedback circuit, and is connected in series with the depletion-type field effect transistor to form a second current branch, and is used to generate a startup voltage that is not less than the startup threshold according to the feedback voltage when the supply voltage is reduced to the output voltage, and then adjust the output voltage to be stable according to the startup voltage.

2. The low power consumption linear voltage regulator circuit according to claim 1, characterized in that: The feedback circuit includes a first resistor and a second resistor connected in series between the output terminal and the ground, and a feedback node; the feedback node is located between the first resistor and the second resistor and is connected to the control circuit; The feedback voltage is generated by the first resistor and the second resistor, and is fed back to the control circuit through the feedback node according to a voltage division ratio.

3. The low power consumption linear voltage regulator circuit according to claim 1, characterized in that: The feedback circuit comprises: A clamping subcircuit, connected to the output terminal, for performing a fixed voltage drop on the output voltage and generating a clamping current related to the output voltage; The sampling sub-circuit is connected to the clamping sub-circuit and the control circuit, and is used for sampling the clamping current to generate the feedback voltage.

4. The low power consumption linear voltage regulator circuit according to claim 3, characterized in that: The clamping subcircuit includes a Zener diode; the sampling subcircuit includes a sampling MOS tube; The cathode of the Zener diode is connected to the output end, and the anode of the Zener diode is connected to the drain of the sampling MOS tube; the gate and drain of the sampling MOS tube are short-circuited, and the gate is connected to the control circuit, and the source of the sampling MOS tube is grounded.

5. The low power consumption linear voltage regulator circuit according to claim 3, characterized in that: The clamping subcircuit comprises a MOS tube cascade formed by a plurality of diodes connected in series, the gate and drain of the MOS tube cascade are short-circuited, the drain is connected to the output end, and the source is connected to the sampling subcircuit; The sampling subcircuit comprises a sampling MOS tube, the drain of the sampling MOS tube is connected to the source of the MOS tube cascade, the gate and the drain are short-circuited, the gate is connected to the control circuit, and the source of the sampling MOS tube is grounded.

6. The low power consumption linear voltage regulator circuit according to claim 1, characterized in that: The control circuit comprises: A control subcircuit, connected to the feedback circuit, for generating a pull-down current according to the feedback voltage and controlling the voltage of the control terminal of the depletion-type field effect transistor; A startup voltage generating subcircuit is connected to the control subcircuit and the depletion-type field effect transistor, and is used to generate the startup voltage not less than the startup threshold according to the pull-down current when the supply voltage is lower than the output voltage, and control the output voltage to be stable according to the startup voltage.

7. The low power consumption linear voltage regulator circuit according to claim 6, characterized in that: The control subcircuit comprises: An enhanced N-type field effect transistor, whose gate is connected to the feedback circuit, whose source is grounded, and whose drain is connected to the start-up voltage generating sub-circuit.

8. The low power consumption linear voltage regulator circuit according to claim 7, characterized in that: The startup voltage generating subcircuit comprises: A pull-down resistor, one end of which is connected between the control end of the depletion-type field effect transistor and the drain of the enhancement-type N-type field effect transistor, and the other end of which is connected to the output end of the depletion-type field effect transistor, is used to generate the startup voltage not less than the startup threshold according to the pull-down current and the output voltage when the supply voltage is lower than the output voltage, and to control the output voltage to be stable according to the startup voltage.

9. The low power consumption linear voltage regulator circuit according to claim 7, characterized in that: The startup voltage generating subcircuit comprises: A pull-down resistor, one end of which is connected between the control end of the depletion-type field effect transistor and the drain of the enhancement-type N-type field effect transistor, and the other end of which is connected to the input end of the depletion-type field effect transistor, is used to generate the startup voltage not less than the startup threshold according to the pull-down current and the supply voltage when the supply voltage is lower than the output voltage, and control the output voltage to be stable according to the startup voltage.

10. A voltage-stabilized power supply, characterized in that: It comprises the low power consumption linear voltage regulator circuit as claimed in any one of claims 1 to 9.

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