A trigger control method based on FPGA parallel broadband DBI architecture

Abstract

This invention discloses a trigger control method based on an FPGA parallel broadband DBI architecture. The FPGA-based parallel DBI architecture includes a multiplexer, two subband decomposition filter groups, eight subband acquisition modules, processing card A, and processing card B. The trigger control method includes: S1. The input signal, after passing through the multiplexer, is input to the two subband decomposition filter groups; each subband decomposition filter group decomposes the input signal into four subband signals, each subband signal corresponding to a subband acquisition module; S2. Each subband signal enters the processing board through its corresponding subband acquisition module; S3. The trigger status of all subband paths is monitored in real time; S4. If a trigger signal is generated by any subband acquisition module, the subsequent processing board specifically controls the read / write control of the preceding subband acquisition module. This invention allows any channel to be selected as the trigger source, ensuring that the input waveform can be correctly triggered and stably displayed, and can stably trigger the waveform according to preset trigger conditions.

Description

Technical Field

[0001] This invention belongs to the technical field of broadband high-speed data acquisition and broadband high-speed digital oscilloscope, and relates to a trigger control method based on FPGA parallel broadband DBI architecture. Background Technology

[0002] Digital Bandwidth Interleaved (DBI) sampling technology has a wide range of applications in broadband high-speed data acquisition and broadband high-speed digital oscilloscope technology. The traditional DBI acquisition system multi-channel trigger architecture is a similar scheme that manages multiple channels on one processing board. Four channels correspond to four sub-bands. All four channels are on one processing board, and there is no switching of bandwidth acquisition mode or processing of transmission and interaction between channels. Determining the trigger source is simple and direct.

[0003] When a parallel processing board and a parallel multi-channel architecture are required, and accurate trigger response is needed for switching between full-bandwidth and half-bandwidth modes, the trigger control of the DBI sampling architecture becomes more complex. There is also inter-board signal transmission between multiple FPGAs and processing boards. If the signal transmission is unstable or the trigger control is inaccurate, the stitched waveform data will be distorted, and the acquired waveform cannot be displayed stably. Currently, there is no processing solution for mutual transmission, synchronization, effective trigger channel and effective trigger sub-band selection for parallel multi-FPGA multi-processing boards with multiple channels, and there is no triggering solution for accurate judgment and response to sub-band multiplexing under bandwidth channel acquisition mode switching. Furthermore, since the storage read / write enable signal and trigger signal in the parallel processing board and parallel multi-channel DBI sampling architecture need to be transmitted between various FPGAs, if asynchrony or metastability occurs during signal transmission, it will cause waveform distortion or jitter. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a trigger control method based on FPGA parallel broadband DBI architecture. By selecting any channel as the trigger source, the input waveform can be correctly triggered and displayed stably, and the waveform can be stably triggered according to the preset trigger conditions.

[0005] The objective of this invention is achieved through the following technical solution: a trigger control method based on an FPGA parallel broadband DBI architecture, wherein the FPGA parallel DBI architecture includes a multiplexer, two subband decomposition filter banks, eight subband acquisition modules, processing board A, and processing board B; each subband acquisition module includes an ADC acquisition card and an FPGA acquisition card; the trigger control method includes:

[0006] S1. After the input signal passes through the multiplexer, it is input to two subband decomposition filter groups respectively; each subband decomposition filter group decomposes the input signal into four subband signals, and each subband signal corresponds to a subband acquisition module;

[0007] S2. The four sub-band signals obtained by the first sub-band decomposition filter group are processed by the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and then enter the processing board A; the four sub-band signals obtained by the second sub-band decomposition filter group are processed by the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and then enter the processing board B.

[0008] S3. Each sub-band acquisition module's FPGA acquisition card is equipped with an independent trigger detection and judgment subsystem, which is used to monitor the trigger status of all sub-band paths in real time. For the input signal, when the FPGA acquisition card of each sub-band acquisition module detects that a trigger signal that meets the user's preset trigger conditions is generated, the trigger flag signal is activated, which determines that a trigger event has occurred in the sub-band acquisition module at this moment.

[0009] S4. If any trigger signal is generated by any sub-band acquisition module, it will send the generated trigger signal to the back-end processing board. The back-end processing board will collect the trigger signals of all front-end sub-band acquisition modules at the same time, and perform channel selection judgment on the trigger according to the user-preset channel acquisition mode and trigger source, select the valid trigger signal, and then generate a synchronization signal group sync_group to control the read and write of the corresponding sub-band acquisition module on the back-end processing board.

[0010] Preferably, the subsequent processing board refers to processing board A or processing board B, and both processing board A and processing board B are FPGA processing boards.

[0011] Preferably, either processing board A or processing board B includes a trigger communication synchronization processing module, a trigger channel selection and multi-subband trigger judgment module, and a trigger signal control processing module.

[0012] Preferably, step S4 includes:

[0013] S401. Trigger communication synchronization processing module, synchronously receives the trigger flag signals of each sub-band acquisition module, and transmits them to the trigger channel selection and multi-sub-band trigger judgment module;

[0014] S402. Trigger channel selection and multi-subband trigger judgment module, used to select a valid trigger flag signal and send it to the trigger signal control processing module;

[0015] (1) The trigger channel selection and multi-subband trigger judgment module divides the channels according to the channel acquisition mode; the channel acquisition mode includes full bandwidth mode 80GSPS and half bandwidth mode 40GSPS;

[0016] Let the eight sub-band signals be denoted as sub-band 1 to sub-band 8 respectively;

[0017] If the channel acquisition mode is full bandwidth mode 80GSPS, then:

[0018] Sub-bands 1-4 are combined into one channel;

[0019] Sub-bands 5-8 are combined into two channels;

[0020] If the channel acquisition mode is half bandwidth 40GSPS, then:

[0021] Sub-bands 1 and 2 are combined into one channel;

[0022] Sub-bands 3-4 are combined into two channels;

[0023] Sub-bands 5-6 are combined into a three-channel configuration;

[0024] Sub-bands 7-8 are combined into a four-channel configuration;

[0025] (2) The trigger channel selection and multi-subband trigger judgment module receives the channel acquisition mode and trigger source set by the user, and determines the subband where the trigger flag signal is valid based on this:

[0026] If the user sets the channel acquisition mode to full bandwidth mode 80GSPS and the trigger source is one channel, then the trigger flag signals of sub-bands 1 to 4 are valid.

[0027] If the user sets the channel acquisition mode to full bandwidth mode 80GSPS and the trigger source to two channels, then the trigger flag signals of sub-bands 5~8 are valid;

[0028] If the user sets the channel acquisition mode to half bandwidth 40GSPS and the trigger source is one channel, then the trigger flag signals of sub-band 1~2 are valid;

[0029] If the user sets the channel acquisition mode to half bandwidth 40GSPS and the trigger source to two channels, then the trigger flag signals of sub-band 3~4 are valid;

[0030] If the user sets the channel acquisition mode to half bandwidth 40GSPS and the trigger source to three channels, then the trigger flag signals of sub-band 5~6 are valid;

[0031] If the user sets the channel acquisition mode to half bandwidth 40GSPS and the trigger source to four channels, then the trigger flag signals of sub-band 7~8 are valid.

[0032] (3) When there is a valid trigger flag signal in the trigger flag signal of each sub-band acquisition module, the trigger channel selection and multi-sub-band trigger judgment module transmits the valid trigger flag signal to the trigger signal control processing module.

[0033] S403. After receiving a valid trigger flag signal, the trigger signal control processing module generates a synchronization control signal group sync_group to control the read and write operations of the corresponding sub-band acquisition module on the subsequent processing board.

[0034] Preferably, in step S4, when the channel acquisition mode is full bandwidth mode 80GSPS and the trigger source is a single channel, the subsequent processing board that finally receives the valid trigger signal is processing board A.

[0035] When the channel acquisition mode is half bandwidth 40GSPS and the trigger source is one channel or two channels, the final processing board that receives the valid trigger signal is processing board A.

[0036] At this time, the synchronization control signal group sync_group generated by processing board A needs to be synchronously transmitted to processing board B; processing board A and processing board B control the corresponding sub-band acquisition modules according to the same synchronization control signal group sync_group.

[0037] Preferably, in step S4, when the channel acquisition mode is full bandwidth mode 80GSPS and the trigger source is two channels, the subsequent processing board that finally receives the valid trigger signal is processing board B.

[0038] When the channel acquisition mode is half bandwidth 40GSPS and the trigger source is three or four channels, the final processing board that receives the valid trigger signal is processing board B.

[0039] At this time, the synchronization control signal group sync_group generated by processing board B needs to be synchronously transmitted to processing board A; processing board A and processing board B control the corresponding sub-band acquisition modules according to the same synchronization control signal group sync_group.

[0040] Preferably, the synchronization control signal group sync_group contains four identical control signals, each of which is a FIFO storage reset signal, write enable signal, or read enable signal in the FPGA acquisition card.

[0041] Preferably, in step S403, after receiving a valid trigger flag signal, the trigger signal control processing module generates a synchronization control signal group sync_group and then performs transmission synchronization control. After the transmission synchronization control is completed, the read / write control is then performed on the sub-band acquisition module corresponding to the subsequent processing board.

[0042] The transmission synchronization control process is as follows:

[0043] A1. The post-processing board sends test data to the FPGA acquisition card of each corresponding sub-band acquisition module. The test data includes the test sequence and the transmission time.

[0044] A2. Each sub-band acquisition module's FPGA acquisition card locally stores the same test sequence as the subsequent processing board. Before receiving test data, the FPGA acquisition card first delays the test data through a delay module, then receives it, and times the reception time. Based on the timing result and the transmission time of the test sequence, it calculates the transmission delay and compares the received test sequence with the locally stored test sequence.

[0045] If the test sequence received by each sub-band acquisition module is the same as the test sequence stored locally, proceed to step A3;

[0046] If there is a sub-band acquisition module that receives a test sequence that is different from the locally stored test sequence, then it is considered that metastability has occurred and the process returns to step A1.

[0047] A3. The FPGA acquisition card of each sub-band acquisition module transmits the calculated transmission delay to the host computer, which then adjusts the delay module to ensure that the transmission delay between the back-end processing board and the FPGA acquisition card of each sub-band acquisition module is the same. At this time, the transmission synchronization control is completed.

[0048] A4. The post-processing board sends a synchronization control signal group (sync_group) to the FPGA acquisition card of the corresponding sub-band acquisition module to achieve read / write control.

[0049] The beneficial effects of the present invention are: 1. The present invention can select any channel as the trigger source under different bandwidth modes and channel modes, can trigger correctly, and can simultaneously trigger other channels together.

[0050] 2. This invention solves the problems of trigger jitter caused by metastability during the transmission of inter-subband storage control signals, such as the inability to find a stable trigger point, severe waveform jitter, sudden flickering of waveforms at intervals, inability of multiple channels to stably associate triggers, and even severe waveform distortion after multi-subband waveform data splicing. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the overall architecture of the present invention;

[0052] Figure 2 Block diagram for triggering synchronous processing in a multi-subband, multi-FPGA parallel DBI architecture. Detailed Implementation

[0053] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0054] This invention selects a specific channel as the trigger source, ensuring not only stable triggering of that channel but also simultaneous triggering of other channels. From a user application perspective, selecting any channel as the trigger source guarantees that the input waveform will be correctly triggered and displayed stably.

[0055] Considering that in existing solutions, the selected trigger source channel does not have an input waveform, but other channels do, it should not trigger. There have been instances of incorrect channel triggering, which likely indicates an error in the valid trigger sub-band judgment (discussed below). This results in a situation where a channel that shouldn't trigger is actually triggering and refreshing the waveform. Alternatively, the channel source can trigger stably, while other channels, although triggering, are unstable with slight fluctuations; or, if waveforms are input to channels 1 and 3, but not to channels 2 and 4, triggering occurs when selecting channels 2 or 4, but not when selecting channel 3. Meanwhile, this invention can respond to input signals within a 20GHz frequency band and can stably trigger waveforms according to preset triggering conditions.

[0056] Edge triggering is the most basic and important triggering method in a digital oscilloscope acquisition triggering system. Here, we will use edge triggering to illustrate our acquisition triggering system solution. Other triggering methods, such as pulse width triggering, under-amplitude triggering, slope triggering, etc., can be obtained by changing the triggering condition settings.

[0057] The entire system is based on DBI (Digital Bandwidth Alternating) sampling technology, which divides the 20GHz frequency bandwidth into 4 frequency sub-bands. Each frequency sub-band has a sampling rate of 20GSPS and a frequency bandwidth of 5GHz, corresponding to a set of ADC+FPGA acquisition arrays. Each sub-band is based on TI (Time Alternating) sampling technology to implement the ADC sampling array, corresponding to one FPGA acquisition board.

[0058] like Figure 1 As shown, a trigger control method based on an FPGA parallel broadband DBI architecture is disclosed. The FPGA-based parallel DBI architecture includes a multiplexer, two subband decomposition filter banks, eight subband acquisition modules, processing board A, and processing board B. Each subband acquisition module includes an ADC acquisition card and an FPGA acquisition card. The trigger control method includes:

[0059] S1. After the input signal passes through the multiplexer, it is input to two subband decomposition filter groups respectively; each subband decomposition filter group decomposes the input signal into four subband signals, and each subband signal corresponds to a subband acquisition module;

[0060] S2. The four sub-band signals obtained by the first sub-band decomposition filter group are processed by the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and then enter the processing board A; the four sub-band signals obtained by the second sub-band decomposition filter group are processed by the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and then enter the processing board B.

[0061] In order to respond to all input signals within the full 20 GHz bandwidth and identify trigger points in waveforms within the full bandwidth, so as to ensure that we can capture waveform information of interest within the full bandwidth, we decompose the signal sub-band into four sub-bands and collect and trigger the data of each sub-band separately.

[0062] The entire system achieves a maximum sampling rate of 80Gsps and a frequency bandwidth of 20GHz. It can correctly acquire all input signals, trigger the capture of target signals, store them, and then display them.

[0063] like Figure 1 As shown, after the signal enters or exits from any channel, it is selected by a multiplexer and enters the subband decomposition filter group. The subband decomposition filter group decomposes the signal into four subband signals, corresponding to 0-5GHz, 5-10GHz, 10-15GHz, and 15-20GHz respectively; each subband corresponds to a set of ADC+FPGA subband acquisition modules with a sampling rate of 20GSPS.

[0064] The highest sampling rate of the entire system is 80GSPS. After the FPGA corresponding to each sub-band acquisition module receives 20GSPS of sampled data from the ADC output, it buffers the data for subsequent signal processing and performs trigger judgment on the data to capture trigger events.

[0065] S3. Each sub-band acquisition module's FPGA acquisition card is equipped with an independent trigger detection and judgment subsystem, which is used to monitor the trigger status of all sub-band paths in real time. For the input signal, when the FPGA acquisition card of each sub-band acquisition module detects that a trigger signal that meets the user's preset trigger conditions is generated, the trigger flag signal is activated, which determines that a trigger event has occurred in the sub-band acquisition module at this moment.

[0066] S4. If any trigger signal is generated by any sub-band acquisition module, it will send the generated trigger signal to the back-end processing board. The back-end processing board will collect the trigger signals of all front-end sub-band acquisition modules at the same time, and perform channel selection judgment on the trigger according to the user-preset channel acquisition mode and trigger source, select the valid trigger signal, and then generate a synchronization signal group sync_group to control the read and write of the corresponding sub-band acquisition module on the back-end processing board.

[0067] Different acquisition channel modes, such as 80GSPS and 40GSPS, have different sub-band combinations, resulting in different effective trigger selections.

[0068] The four sub-band acquisition modules at the front end generate four trigger signal paths, namely ACQ_TRIG1, ACQ_TRIG2, ACQ_TRIG3, and ACQ_TRIG4. The four sub-band trigger signals are input to the multi-sub-band trigger selection and judgment module. The trigger channel and the multi-sub-band trigger selection and judgment module will select a valid trigger signal based on the channel mode and trigger source selected by the current user, which is used to generate and output the final first-level trigger signal trig_out.

[0069] Classification:

[0070] The sampling mode is 80GSPS, with a bandwidth of 20GHz. Four sub-bands are combined into one channel, for a total of two channels.

[0071] Subbands 1, 2, 3, and 4 are combined into one channel; the trigger signals of subbands 1, 2, 3, and 4 are the effective subband trigger signals of one channel.

[0072] The 5678 sub-band combination forms a three-channel system; the trigger signals for sub-bands 5, 6, 7, and 8 are the effective sub-band trigger signals for the three channels.

[0073] The 40GSPS mode has a bandwidth of 10GHz, with two sub-bands combined into one channel, for a total of four channels.

[0074] Subbands 1 and 2 are combined into one channel, and the trigger signals of subbands 1 and 2 are the effective subband trigger signals of the first channel; subbands 3 and 4 are combined into two channels, and the trigger signals of subbands 3 and 4 are the effective subband trigger signals of the second channel.

[0075] Sub-bands 5 and 6 are combined to form a three-channel system. The trigger signals for sub-bands 5 and 6 are the effective sub-band trigger signals for the three-channel system.

[0076] Subbands 7 and 8 are combined to form a four-channel system. The trigger signals for subbands 7 and 8 are the effective subband trigger signals for the four-channel system.

[0077] like Figure 2As shown, the two processing boards receive trigger signals ACQ_TRIG1, ACQ_TRIG2, ACQ_TRIG3, and ACQ_TRIG4 and trigger position signals trig_loct1, trig_loct2, trig_loct3, and trig_loct4 from their respective front-end four acquisition cards. After trigger channel selection and multi-subband trigger selection processing, a valid trigger signal is generated. The trigger signal control processing module then generates read / write enable signals for the front-end storage FIFO. The storage read / write control signal generates a synchronous group of eight read / write enable signals, which are synchronously sent to each front-end ADC+FPGA sub-band acquisition module to control the data access of each sub-band. As can be seen from the figure, the trigger signal is transmitted through multiple boards and distributed to eight acquisition cards. Different transmission links may have different delays, instability, and transmission metastability. This leads to waveform asynchrony, which in turn causes errors in the waveform data of subsequent multi-subband data splicing or trigger instability.

[0078] A multi-subband synchronous transmission method was specially designed to ensure the synchronous control and stable transmission of signals between multiple subbands, thereby achieving stable waveform triggering.

[0079] After the software initiates data acquisition, it first sends a reset signal, then begins sending a write enable signal to start storage. The write enable signal is sent to processing board A via PCIe. On the processing board, the write enable signal is sent to the storage read / write control signal generation modules of both processing boards A and B. Simultaneously, it is sent to the trigger signal control processing module to control pre-triggering, post-triggering, trigger release, and read enable generation.

[0080] The storage read / write control signal generation module generates a FIFO storage reset and read / write synchronization control signal group, sync_groupx, where x=1,2,3,4, based on the received reset, write enable, and read enable signals. This signal group includes FIFO storage reset, write enable, and read enable. sync_groupx is simultaneously sent to the four preceding acquisition cards. Board B also receives a set of sync_groupx, then synchronously copies it four times, and sends each copy to the corresponding four preceding acquisition cards on Board B. Board B's sync_groupx and Board A's sync_groupx are synchronized from the same source.

[0081] The sync_groupx generated by the storage read / write control signal generation module of AB will be sent to their respective signal synchronization transmission modules simultaneously; the signal synchronization transmission module mainly completes the cross-clock domain synchronous transmission of signals, as well as the synchronous transmission control with the acquisition card;

[0082] Configure the transmission of test signals before the actual transmission of signals, and enter test mode;

[0083] During testing, the control signal receiving module receives the pattern sequence from the transmitting module, sends it to the IDEALY module for delay, and then performs timing and transmission delay calculations. Synchronization of the stored control signals within a single acquisition board is achieved by comparing the received signal and the local signal. Based on this, the same processing is performed on all acquisition boards in the acquisition system. Finally, the resulting synchronization flag signals (sync_status) are sent to the host computer for multi-channel inter-board synchronization determination. The FPGA acquisition cards of each sub-band acquisition module transmit the calculated transmission delay to the host computer, which adjusts the delay module to ensure that the transmission delay between the subsequent processing board and the FPGA acquisition cards of each sub-band acquisition module is the same. At this point, transmission synchronization control is complete.

[0084] Each acquisition board simultaneously receives storage control signals and trigger position synchronization signals sent from the processing board, including storage control signal groups and trigger fine positioning signals.

[0085] The processing board simultaneously receives trigger signals and trigger positioning signals from eight acquisition boards. The trigger signals undergo the aforementioned synchronous transmission control process; the trigger positioning signals require parallel-to-serial conversion before transmission, and are then sent back to each acquisition board via the signal synchronization transmission module. Each acquisition board stores the same accurate trigger position, facilitating subsequent software calculation of the data read position based on the trigger position.

[0086] This invention addresses the selection and judgment of multiple subbands and channels, particularly the interaction and combined control of multiple acquisition boards and processing boards. While the control logic is complex and transmission synchronization is challenging, it also offers advantages. A single processing board's FPGA resources and processing capabilities cannot handle the data transmission and signal processing of numerous front-end acquisition cards. Multiple processing boards reduce the performance resource requirements of each board, while parallel processing speeds are faster. Furthermore, it provides a method for future data acquisition, processing, and trigger control of more channels. Employing a parallel DBI multi-subband scheme, even without higher sampling rate and bandwidth ADCs, it enables high-speed, high-bandwidth acquisition systems using low-bandwidth, low-sampling-rate ADCs to achieve higher sampling rates and bandwidths. Trigger control in this architecture is also complex. This solution ensures stable acquisition of trigger waveforms in high-speed, high-bandwidth acquisition systems. Otherwise, unstable trigger control can distort the combined waveform data, making stable display of multi-channel waveforms impossible, which is crucial for high-bandwidth, high-sampling-rate oscilloscopes.

[0087] The above description represents preferred embodiments of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technical or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A trigger control method based on an FPGA parallel broadband DBI architecture, characterized in that: The FPGA-based parallel DBI architecture includes a multiplexer, two subband decomposition filter banks, eight subband acquisition modules, processing board A, and processing board B; each subband acquisition module includes an ADC acquisition card and an FPGA acquisition card; the trigger control method includes: S1. After the input signal passes through the multiplexer, it is input to two subband decomposition filter groups respectively; each subband decomposition filter group decomposes the input signal into four subband signals, and each subband signal corresponds to a subband acquisition module; S2. The four sub-band signals obtained by the first sub-band decomposition filter group are processed by the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and then enter the processing board A; the four sub-band signals obtained by the second sub-band decomposition filter group are processed by the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and then enter the processing board B. S3. Each sub-band acquisition module's FPGA acquisition card is equipped with an independent trigger detection and judgment subsystem, which is used to monitor the trigger status of all sub-band paths in real time. For the input signal, when the FPGA acquisition card of each sub-band acquisition module detects that a trigger signal that meets the user's preset trigger conditions is generated, the trigger flag signal is activated, which determines that a trigger event has occurred in the sub-band acquisition module at this moment. S4. If any trigger signal is generated by each sub-band acquisition module, the generated trigger signal will be sent to the back-end processing board. The back-end processing board will collect the trigger signals of all front-end sub-band acquisition modules at the same time, and perform channel selection judgment on the trigger according to the user-preset channel acquisition mode and trigger source, select the valid trigger signal, and then generate a synchronization signal group sync_group to control the read and write of the corresponding sub-band acquisition module of the back-end processing board. Both the processing board A and the processing board B include a trigger communication synchronization processing module, a trigger channel selection and multi-subband trigger judgment module, and a trigger signal control processing module. S4 includes: S401. Trigger communication synchronization processing module, synchronously receives the trigger flag signals of each sub-band acquisition module, and transmits them to the trigger channel selection and multi-sub-band trigger judgment module; S402. Trigger channel selection and multi-subband trigger judgment module, used to select a valid trigger flag signal and send it to the trigger signal control processing module; (1) The trigger channel selection and multi-subband trigger judgment module divides the channels according to the channel acquisition mode; the channel acquisition mode includes full bandwidth mode 80GSPS and half bandwidth mode 40GSPS; Let the eight sub-band signals be denoted as sub-band 1 to sub-band 8 respectively; If the channel acquisition mode is full bandwidth mode 80GSPS, then: Sub-bands 1-4 are combined into one channel; Sub-bands 5-8 are combined into two channels; If the channel acquisition mode is half bandwidth 40GSPS, then: Sub-bands 1 and 2 are combined into one channel; Sub-bands 3-4 are combined into two channels; Sub-bands 5-6 are combined into a three-channel configuration; Sub-bands 7-8 are combined into a four-channel configuration; (2) The trigger channel selection and multi-subband trigger judgment module receives the channel acquisition mode and trigger source set by the user, and determines the subband where the trigger flag signal is valid based on this: If the user sets the channel acquisition mode to full bandwidth mode 80GSPS and the trigger source is one channel, then the trigger flag signals of sub-bands 1 to 4 are valid. If the user sets the channel acquisition mode to full bandwidth mode 80GSPS and the trigger source to two channels, then the trigger flag signals of sub-bands 5~8 are valid; If the user sets the channel acquisition mode to half bandwidth 40GSPS and the trigger source is one channel, then the trigger flag signals of sub-band 1~2 are valid; If the user sets the channel acquisition mode to half bandwidth 40GSPS and the trigger source to two channels, then the trigger flag signals of sub-band 3~4 are valid; If the user sets the channel acquisition mode to half bandwidth 40GSPS and the trigger source to three channels, then the trigger flag signals of sub-band 5~6 are valid; If the user sets the channel acquisition mode to half bandwidth 40GSPS and the trigger source to four channels, then the trigger flag signals of sub-band 7~8 are valid. (3) When there is a valid trigger flag signal in the trigger flag signal of each sub-band acquisition module, the trigger channel selection and multi-sub-band trigger judgment module transmits the valid trigger flag signal to the trigger signal control processing module. S403. After receiving a valid trigger flag signal, the trigger signal control processing module generates a synchronization control signal group sync_group to perform read and write control on the corresponding sub-band acquisition module of the subsequent processing board. In S403, after receiving a valid trigger flag signal, the trigger signal control processing module generates a synchronization control signal group sync_group and then performs transmission synchronization control. After the transmission synchronization control is completed, the corresponding sub-band acquisition module of the subsequent processing board is read and written. The transmission synchronization control process is as follows: A1. The post-processing board sends test data to the FPGA acquisition card of each corresponding sub-band acquisition module. The test data includes the test sequence and the transmission time. A2. Each sub-band acquisition module's FPGA acquisition card locally stores the same test sequence as the subsequent processing board. Before receiving test data, the FPGA acquisition card first delays the test data through a delay module, then receives it, and times the reception time. Based on the timing result and the transmission time of the test sequence, it calculates the transmission delay and compares the received test sequence with the locally stored test sequence. If the test sequence received by each sub-band acquisition module is the same as the test sequence stored locally, proceed to step A3; If there is a sub-band acquisition module that receives a test sequence that is different from the locally stored test sequence, then it is considered that metastability has occurred and the process returns to step A1. A3. The FPGA acquisition card of each sub-band acquisition module transmits the calculated transmission delay to the host computer, which then adjusts the delay module to ensure that the transmission delay between the back-end processing board and the FPGA acquisition card of each sub-band acquisition module is the same. At this time, the transmission synchronization control is completed. A4. The post-processing board sends a synchronization control signal group (sync_group) to the FPGA acquisition card of the corresponding sub-band acquisition module to achieve read / write control.

2. The trigger control method based on FPGA parallel broadband DBI architecture according to claim 1, characterized in that: The subsequent processing board refers to processing board A or processing board B, both of which are FPGA processing boards.

3. The trigger control method based on FPGA parallel broadband DBI architecture according to claim 1, characterized in that: In step S4, when the channel acquisition mode is full bandwidth mode 80GSPS and the trigger source is one channel, the final processing board that receives the valid trigger signal is processing board A. When the channel acquisition mode is half bandwidth 40GSPS and the trigger source is one channel or two channels, the final processing board that receives the valid trigger signal is processing board A. At this time, the synchronization control signal group sync_group generated by processing board A needs to be synchronously transmitted to processing board B; processing board A and processing board B control the corresponding sub-band acquisition modules according to the same synchronization control signal group sync_group.

4. The trigger control method based on FPGA parallel broadband DBI architecture according to claim 1, characterized in that: In step S4, when the channel acquisition mode is full bandwidth mode 80GSPS and the trigger source is two channels, the final processing board that receives the valid trigger signal is processing board B. When the channel acquisition mode is half bandwidth 40GSPS and the trigger source is three or four channels, the final processing board that receives the valid trigger signal is processing board B. At this time, the synchronization control signal group sync_group generated by processing board B needs to be synchronously transmitted to processing board A; processing board A and processing board B control the corresponding sub-band acquisition modules according to the same synchronization control signal group sync_group.

5. A trigger control method based on an FPGA parallel broadband DBI architecture according to claim 3 or 4, characterized in that: The synchronization control signal group sync_group contains four identical control signals, each of which is a FIFO storage reset signal, write enable signal, or read enable signal in the FPGA acquisition card.

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