Power-on and power-off control circuit and multi-power system

Abstract

The invention provides a power-on and power-off control circuit and a multi-power-supply system, and relates to the field of power supply control, the circuit comprises a first control sub-circuit, the input end of the first control sub-circuit is connected with a first power supply, the output end of the first control sub-circuit is connected with a power utilization module, and the power supply end of the first control sub-circuit is connected with a second power supply; the first control sub-circuit is switched on to work under the condition that the second power supply is powered on, and the first control sub-circuit is used for controlling the power utilization module to work based on the output voltage of the first power supply. The reset signal is generated according to the size of the first power supply, whether the reset signal can be transmitted to the power utilization module or not is determined according to whether the second power supply is powered on or not, the power-on and power-off states of the first power supply can be known when the power utilization module receives the reset signal, and control over the power utilization module is achieved when the first power supply is powered on later and powered off first.

Description

Technical Field

[0001] The present application relates to the field of power supply control, and in particular to a power-on and power-off control circuit and a multi-power supply system. Background Art

[0002] The power-on and power-off timing can ensure that the chip starts and shuts down normally and stably, and has an important impact on the normal operation, stability and life of the chip. When powered on, each module needs to be connected to the power supply and signal in a certain order to ensure the overall stability and normal operation of the chip. When powered off, each module also needs to be shut down in a certain timing to avoid data loss and system crash. With the continuous development of electronic hardware systems, multiple power supply systems are used to power each module of the chip. The multi-power supply system requires a very complex timing to control the power on and off of each power supply in turn. For example, for a chip system with a storage module and a digital module, the power supply of the two is different, but the normal operation of the digital module requires the cooperation of the storage module. Therefore, in order to ensure the normal operation of the chip, the storage module and the digital module need to be powered on and off according to the specified timing. Once the power is not powered on and off according to the specified timing, it will cause the storage module timing error, causing the digital module and the core to work abnormally, and even affect the safety performance of the entire chip. Summary of the invention

[0003] The present application provides a power-on and power-off control circuit and a multi-power supply system to solve the power-on and power-off timing problem.

[0004] In a first aspect, the present application provides a power-on and power-off control circuit, the circuit comprising a first control subcircuit (201), the input end of the first control subcircuit (201) being connected to a first power source (101), the output end of the first control subcircuit (201) being connected to a power consumption module (301), and the power supply end of the first control subcircuit (201) being connected to a second power source (102);

[0005] The first control subcircuit (201) is turned on and operates when the second power supply (102) is powered on. The first control subcircuit (201) is used to control the operation of the power module (301) based on the output voltage of the first power supply (101).

[0006] In one embodiment, the power management module of the first power supply (101) includes a reset port (103), the reset port (103) is connected to the first power supply (101) through a first resistor (R1), and the reset port (103) outputs an external reset signal based on an output voltage of the first power supply (101);

[0007] The input end of the first control subcircuit (201) is connected to the reset port (103), and the first control subcircuit (201) is used to control the operation of the power module (301) according to an external reset signal.

[0008] In one embodiment, the first control subcircuit (201) comprises a voltage comparison module (2011), an input end of the voltage comparison module (2011) is connected to the reset port (103), and an output end of the voltage comparison module (2011) is connected to the power consumption module (301);

[0009] The voltage comparison module (2011) is turned on and operates when the second power supply (102) is powered on. The voltage comparison module (2011) is used to filter the external reset signal and output a reference reset signal. The reference reset signal is used to control the working state of the power consumption module (301).

[0010] In one embodiment, the voltage comparison module (2011) includes a trigger.

[0011] In one embodiment, the trigger is a Schmitt trigger.

[0012] In one embodiment, the first control subcircuit (201) further comprises an isolation module (2012), an input end of the isolation module (2012) is connected to the reset port (103), and an output end of the isolation module (2012) is connected to an input end of the voltage comparison module (2011);

[0013] The isolation module (2012) is used to isolate the reset port (103) and the power consumption module (301).

[0014] In one embodiment, the isolation module (2012) includes a second resistor (R2).

[0015] In one embodiment, the first control subcircuit (201) further comprises a voltage processing module (2013), the input end of the voltage processing module (2013) is connected to the output end of the voltage comparison module (2011), and the output end of the voltage processing module (2013) is connected to the power consumption module (301);

[0016] The voltage processing module (2013) is used to perform signal processing on the reference reset signal output by the voltage comparison module (2011), and output a target reset signal to drive the power consumption module (301).

[0017] In one embodiment, the voltage processing module (2013) includes a voltage conversion unit (1301), the input end of the voltage conversion unit (1301) is connected to the output end of the voltage comparison module (2011), and the output end of the voltage conversion unit (1301) is connected to the power consumption module (301);

[0018] The voltage conversion unit (1201) is used to convert the power domain of the reference reset signal from the first power domain to the second power domain, and output a first target reset signal to drive the power-consuming module (301).

[0019] In one embodiment, the voltage processing module (2013) further includes a drive processing unit (1302), the input end of the drive processing unit (1302) is connected to the output end of the voltage conversion unit (1301), and the output end of the drive processing unit (1302) is connected to the power consumption module (301);

[0020] The driving processing unit (1302) is used to perform signal amplification processing on the first target reset signal output by the voltage conversion unit (1301), and output a second target reset signal to drive the power module (301).

[0021] In one embodiment, the driver processing unit (1302) includes a buffer amplifier.

[0022] In one embodiment, the driving processing unit (1302) further includes a filtering subunit, the input end of the filtering subunit is connected to the output end of the buffer amplifier, and the output end of the filtering subunit is connected to the power consumption module (301).

[0023] In one embodiment, the filtering subunit comprises a low-pass filter (1001) and at least one trigger (1002); the low-pass filter (1001) and the at least one trigger (1002) are connected in sequence; the output end of the low-pass filter (1001) and the output end of the at least one trigger (1002) are connected to the power consumption module (301).

[0024] In one embodiment, the flip-flop is a D flip-flop.

[0025] In one embodiment, the power-on and power-off control circuit further includes a second control subcircuit (202), an input end of the second control subcircuit (202) is connected to the first power source (101), an output end of the second control subcircuit (202) is connected to the power consumption module (301), and a power supply end of the second control subcircuit (202) is connected to the first power source (101);

[0026] The second control subcircuit (202) is used to control the operation of the power module (301) based on the output voltage of the first power supply (101).

[0027] In one embodiment, the second control subcircuit (202) comprises a power-on reset module (2021), an input end and a power end of the power-on reset module (2021) are connected to the first power supply (101), and an output end of the power-on reset module (2021) is connected to the power consumption module (301);

[0028] The power-on reset module (2021) is used to send a power-on reset signal to the power-consuming module (301) based on the voltage boost process of the first power source (101).

[0029] In one embodiment, the second control subcircuit (202) further comprises a power-off reset module (2022), the input end and the power supply end of the power-off reset module (2022) are connected to the first power supply (101), and the output end of the power-off reset module (2022) is connected to the power consumption module (301);

[0030] The power-off reset module (2022) is used to send an undervoltage reset signal to the power consumption module (301) based on the voltage reduction process of the first power source (101).

[0031] In one embodiment, the second control subcircuit (202) is further configured to trigger a power-on reset signal or an undervoltage reset signal after a preset time period after detecting that the voltage of the first power supply (101) meets the triggering condition of the power-on reset signal or the undervoltage reset signal.

[0032] In a second aspect, the present application provides a multi-power supply system, the system comprising a first power supply (101), a second power supply (102) and a power management module (103), the power management module comprising an up and down power control circuit as in the embodiment of the first aspect.

[0033] The present application provides a power-on and power-off control circuit and a multi-power supply system, the circuit includes a first control subcircuit, the input end of the first control subcircuit is connected to the first power supply, the output end of the first control subcircuit is connected to the power module, and the power supply end of the first control subcircuit is connected to the second power supply; the first control subcircuit is turned on when the second power supply is powered on, and the first control subcircuit is used to control the power module to work based on the output voltage of the first power supply. A reset signal is generated by the size of the first power supply, and whether the reset signal can be transmitted to the power module is determined by whether the second power supply is powered on. When the power module receives the reset signal, the power-on and power-off status of the first power supply can be known, and the power module can be controlled when the first power supply is powered on later or powered off first. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0035] Figure 1 is a structural diagram of a multi-power supply system provided in one embodiment;

[0036] Figure 2 A schematic diagram of the power-on and power-off control timing provided in an embodiment Figure 1 ;

[0037] Figure 3 A schematic diagram of the structure of a power-on and power-off control circuit provided in an embodiment Figure 1 ;

[0038] Figure 4 A schematic diagram of the structure of a first control subcircuit provided in an embodiment Figure 1 ;

[0039] Figure 5 A schematic diagram of the structure of a first control subcircuit provided in an embodiment Figure 2 ;

[0040] Figure 6 A schematic diagram of the structure of a first control subcircuit provided in an embodiment Figure 3 ;

[0041] Figure 7 A schematic diagram of the structure of a first control subcircuit provided in an embodiment Figure 4 ;

[0042] Figure 8 A schematic diagram of the structure of a first control subcircuit provided in an embodiment Figure 5 ;

[0043] Fig. 9 A schematic diagram of the structure of a first control subcircuit provided in an embodiment Figure 6 ;

[0044] Fig.10 A schematic diagram of the structure of a filtering subunit provided in one embodiment;

[0045] Fig.11 A schematic diagram of the structure of a power-on and power-off control circuit provided in an embodiment Figure 2 ;

[0046] Fig.12 A schematic diagram of the structure of a power-on and power-off control circuit provided in an embodiment Figure 3 ;

[0047] Fig.13 A schematic diagram of the structure of a power-on and power-off control circuit provided in an embodiment Figure 4 ;

[0048] Fig.14 is a circuit diagram of a first control subcircuit provided in one embodiment;

[0049] Fig.15 A circuit diagram of a filter subunit provided in one embodiment;

[0050] Fig.16 A schematic diagram of the power-on and power-off control timing provided in an embodiment Figure 2 .

[0051] Reference numerals:

[0052] 101: first power supply; 102: second power supply; 103: reset port; 201: first control subcircuit; 2011: voltage comparison module; 2012: isolation module; 2013: voltage processing module; 1301: voltage conversion unit; 1302: drive processing unit; R1: first resistor; R2: second resistor; R3: third resistor; C: capacitor; 1001: low-pass filter; 1002: trigger; 202: second control subcircuit; 2021: power-on reset module; 2022: power-off reset module; 301: power consumption module.

[0053] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0054] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. It is understood that the terms "first", "second", etc. used in the present application can be used to describe various information or data in this article, but these elements are not limited by these terms. These terms are only used to distinguish the first information from another information. For example, without departing from the scope of the present application, the first action information can be referred to as the second action information, and similarly, the second action information can be referred to as the first action information. Both the first action information and the second action information are action information, but they are not the same action information.

[0056] First, the terms involved in this application are explained:

[0057] VCC: first power supply unit;

[0058] AVCC: analog module supply voltage;

[0059] IOVCC: port module power supply voltage;

[0060] VD11: second power supply unit;

[0061] VD33: the third power supply unit;

[0062] SARADC: Successive Approximation Analog-to-Digital Converter;

[0063] DSADC: Delta-Sigma Analog-to-Digital Converter;

[0064] CMP: Comparator;

[0065] PORT: port;

[0066] LDO: Low-dropout regulator, low-dropout linear regulator;

[0067] POR: Power-On Reset, power-on reset;

[0068] BOR: Brown-out Reset, undervoltage reset;

[0069] POR_N: POR reset pin;

[0070] BOR_N: BOR reset pin;

[0071] RST_N: external reset pin;

[0072] ESD: Electrostatic discharge;

[0073] MOS: metal oxide semiconductor field effect transistor;

[0074] Latch up: latch effect.

[0075] The power-on and power-off sequence ensures that the chip starts and shuts down normally and stably, and has an important impact on the normal operation, stability and life of the chip. When powering on, each module needs to be connected to the power supply and signal in a certain order to ensure the overall stability and normal operation of the chip. When powering off, each module also needs to be shut down in a certain sequence to avoid data loss and system crash.

[0076] With the continuous development of electronic hardware systems, multiple power supply systems are used to power various modules of the chip. Multiple power supply systems require a very complex timing sequence to control the power on and off of each power supply in turn. Figure 1 In the system shown, the multi-power system supplies power to each functional module of the chip, and the multi-power system includes:

[0077] The first power supply unit is used to supply power to analog modules (including but not limited to SARADC, DSADC and CMP) and PORT. For ease of description, this embodiment is represented by the symbol VCC.

[0078] The third power supply unit: input from the third power supply unit and generated after LDO. LDO outputs the third power supply unit and supplies power for the erase and write function of the storage module (including but not limited to the flash memory module FLASH module), which is represented by the symbol VD33 in this embodiment;

[0079] The second power supply unit: provides power to the digital module and the clock module, and provides power to the digital logic of the storage module (including but not limited to the FLASH module), which is represented by the symbol VD11 in this embodiment.

[0080] In the actual working process of the chip, VCC and VD11 have timing requirements. During the power-on process, VCC must be powered up to V VCC_Min (VCC minimum operating voltage), VD11 starts to power on. Figure 2 The timing diagram shown in the figure: During the VCC power-on process, the power-on reset POR provides a low level to keep the digital modules in reset state until the VCC power-on threshold V is detected. POR_N , the POR reset pin POR_N_VCC is pulled high, and the digital module starts working. During the power-off process, VD11 is powered down to V VD11_Min (the lowest voltage of analog circuit devices, digital modules cannot work) below, VCC starts to power down. Specifically: when the undervoltage threshold V of VCC is detected BOR_N , the BOR reset pin BOR_N_VCC is pulled low to reset the digital module.

[0081] In the above process, if the power is not turned on according to the above specified timing, that is, VD11 is powered on first and VCC is not powered on, since the POR circuit only detects the VCC signal, the POR reset is invalid and the digital module cannot be reset, which will cause the following risks:

[0082] (1) Timing error of storage module (including but not limited to FLASH module). If the user performs FLASH erase and write operation, VD11 is not powered on normally due to VCC not being input, which affects the FLASH data, so VCC must be powered on first.

[0083] (2) The digital module is working abnormally. The operation of the digital module requires the normal operation of the storage module. If there is a problem with the storage module, it will cause chip program errors, so VCC must be powered on first.

[0084] (3) If the voltage input is too large, the chip will be damaged. The chip power-on voltage detection needs to provide a reference voltage through a bandgap reference. The reference voltage is input by VCC, so VCC must be powered on first.

[0085] Similarly, if the power is not turned off according to the specified timing, that is, VCC is powered off first and VD11 is not powered off, since the BOR circuit only detects the VCC signal, when VCC is powered off to the undervoltage threshold V BOR_N Previously, BOR reset was invalid and could not reset the digital module, which would cause the following risks: The core would work abnormally. The core operating voltage is provided by VD11, so VD11 must be powered off first.

[0086] In the above solution, if the power is not turned on and off according to regulations, it will cause timing errors in the storage module, causing the digital module and the core to work abnormally, and even affecting the safety performance of the entire chip.

[0087] In view of the technical problems existing in the above solutions, the present application provides a power-on and power-off control circuit, such as Figure 3 As shown, the circuit includes a first control subcircuit 201, the input end of the first control subcircuit 201 is connected to the first power supply 101, the output end of the first control subcircuit 201 is connected to the power module 301, and the power supply end of the first control subcircuit 201 is connected to the second power supply 102;

[0088] The first control subcircuit 201 is turned on and operates when the second power supply 102 is powered on. The first control subcircuit 201 is used to control the operation of the power module 301 based on the output voltage of the first power supply 101 .

[0089] The output end of the first control subcircuit 201 is connected to the reset pin of the power module 301. In the circuit provided in this embodiment, the second power supply 102 provides power to the first control subcircuit 201 so that the first control subcircuit 201 can work. That is, the first control subcircuit 201 can receive the input of the first power supply 101 only when the second power supply 102 is powered on, and output the reset signal to control the power module 301 according to the output voltage of the first power supply 101.

[0090] Among them, the first power supply 101 is connected to the first control subcircuit 201. When the first power supply 101 has output, the first control subcircuit 201 detects and processes the output voltage of the first power supply 101, and sends a reset signal to the power module 301 according to the size of the output voltage of the first power supply 101, informing the power module 301 of the power-on and power-off status of the first power supply 101, thereby controlling the working state of the power module 301.

[0091] The power supply end of the power module 301 is connected to the second power supply 102. Only when the second power supply 102 is powered on can the power module 301 receive the reset signal sent by the first control subcircuit 201. When the second power supply 102 is powered on, the working state of the power module 301 is adjusted according to the reset signal received by the reset pin. For example, if the reset signal sent by the first control subcircuit 201 is low level effective, then when the reset signal is low level, the power module 301 is in the reset state. At this time, even if the second power supply 102 supplies power to the power module 301, the power module 301 is started but does not start working.

[0092] Similarly, when the first power supply 101 and the second power supply 102 are powered off, if the first power supply 101 is powered off first, a reset signal will be sent to the power module 301 to control the power module 301 to be in a reset state, and then the second power supply will not affect the normal operation of the power module 301 after it is powered off.

[0093] Specifically, in one embodiment, the first control subcircuit 201 has a voltage comparison function, and determines whether the first power supply 101 reaches the power-on threshold or drops to the undervoltage threshold by detecting and judging the voltage output by the first power supply 101, thereby outputting a reset signal to control the state of the power-using module 301. For example, the first control subcircuit 201 includes a voltage comparator, and when it is detected that the voltage output by the first power supply 101 is less than the first threshold, it outputs a low level, and the power-using module 301 is in a reset state, and when it is detected that the voltage output by the first power supply 101 is not less than the first threshold, it outputs a high level, and the power-using module 301 works normally.

[0094] In the circuit provided in the above embodiment, the circuit includes a first control subcircuit, the input end of the first control subcircuit is connected to the first power supply, the output end of the first control subcircuit is connected to the power module, and the power supply end of the first control subcircuit is connected to the second power supply; the first control subcircuit is turned on and works when the second power supply is powered on, and the first control subcircuit is used to control the power module to work based on the output voltage of the first power supply. A reset signal is generated by the size of the first power supply, and whether the reset signal can be transmitted to the power module is determined by whether the second power supply is powered on. When the power module receives the reset signal, the power-on and power-off status of the first power supply can be known, so as to realize the control of the power module when the first power supply is powered on later or powered off first.

[0095] In one embodiment, if Figure 4 As shown, the power management module of the first power supply 101 includes a reset port 103, the reset port 103 is connected to the first power supply 101 through a first resistor R1, and the reset port 103 outputs an external reset signal based on the output voltage of the first power supply 101;

[0096] An input end of the first control subcircuit 201 is connected to the reset port 103 , and the first control subcircuit 201 is used to control the operation of the power module 301 according to an external reset signal.

[0097] Among them, the power management module is used to realize functions such as power monitoring and power management. When the power management module detects that the power supply is unstable, it will send a reset signal to the external reset RST pin of the power-consuming module. The reset port 103 refers to the port on the power management module that outputs the reset signal to the outside. Under normal circumstances, for the power-consuming module 301, such as a digital module, a microcontroller, a processor, etc., there is an RST pin for receiving a reset signal. Taking a microcontroller as an example, its RST pin is usually connected to a power management module or a manual reset button. When the power supply voltage is unstable or the user presses the reset button, the RST pin will receive a reset signal, thereby resetting the microcontroller. During the reset process, the internal registers and status information of the microcontroller will be cleared, and the program counter will be set to the initial position, thereby ensuring that the microcontroller can start running from a known and stable state.

[0098] In the embodiment of the present application, the reset port 103 is a low-level reset pin, which is connected to the first power supply 101 through the first resistor R1, so that the reset port 103 outputs an external reset signal to the external reset pin of the power-consuming module 301 under the control of the first power supply 101. Specifically, the first resistor R1 can be a pull-up resistor, and the initial state of the reset port 103 is a low level, which is provided by the first power supply 101. Through the pull-up resistor, according to the power supply condition of the first power supply 101 to the reset port 103, that is, whether the first power supply 101 is powered on, the reset port 103 outputs a high / low level.

[0099] The resistance value of the first resistor R1 needs to be selected according to the specific needs of the system. A resistance value that is too large may cause the reset signal to rise too slowly, affecting the reset effect; a resistance value that is too small may increase power consumption. Usually, the resistance value of the first resistor R1 is selected between several hundred ohms and several thousand ohms.

[0100] In the circuit provided in the above embodiment, the control of the power-consuming module when the second power source is powered on first is achieved through the existing reset port without adding external pins and ports.

[0101] In one embodiment, if Figure 5 As shown, the first control subcircuit 201 includes a voltage comparison module 2011, the input end of the voltage comparison module 2011 is connected to the reset port 103, and the output end of the voltage comparison module 2011 is connected to the power module 301;

[0102] The voltage comparison module 2011 is turned on and works when the second power supply 102 is powered on. The voltage comparison module 2011 is used to filter the external reset signal and output a reference reset signal. The reference reset signal is used to control the working state of the power consumption module 301 .

[0103] It can be understood that the reset port 103 is connected to the first power supply 101 through the first resistor R1. The external reset signal output based on the size of the first power supply 101 will fluctuate due to the fluctuation of the first power supply 101. Therefore, the external reset signal directly output by the reset port 103 has a certain volatility, and the signal waveform is not very regular, which will cause the power module 301 to switch repeatedly between two states in a short period of time, affecting the normal operation and safety of the power module 301.

[0104] The external reset signal is filtered by the voltage comparison module 2011, and the irregular signal is outputted as high / low level through logic judgment, and the burr of the external reset signal is processed. The voltage comparison module 2011 can be a circuit with filtering effect, or any circuit or device with voltage comparison function, and the burr is removed by comparing the voltage, such as a voltage comparator, a trigger, etc. Among them, the trigger can be a Schmitt trigger. The Schmitt trigger can realize logic judgment of the irregular signal through the comparator, the burr of the initial input signal, and output stable high and low levels.

[0105] In the circuit provided by the above embodiment, the voltage comparison module performs signal processing on the external reset signal to remove signal glitches and improve the accuracy of the external reset signal.

[0106] In one embodiment, if Figure 6 As shown, the first control subcircuit 201 further includes an isolation module 2012, an input end of the isolation module 2012 is connected to the reset port 103, and an output end of the isolation module 2012 is connected to an input end of the voltage comparison module 2011;

[0107] The isolation module 2012 is used to isolate the reset port 103 from the power module 301 .

[0108] The isolation module 2012 is used to isolate the first power supply 101 from the circuit components in the first control subcircuit 201, and protect the circuit components in the first control subcircuit 201 and the safety of the power module 301. The isolation module 2012 can play the role of short circuit protection, overvoltage protection, undervoltage protection, and overcurrent protection. In a specific implementation scenario, a suitable isolation module 2012 is selected according to the actual situation of the first control subcircuit 201 and the power module 301.

[0109] For example, the isolation module 2012 includes a second resistor R2 . The second resistor R2 is used to block ESD current transients to prevent damage to components in the power-consuming module 301 .

[0110] In the circuit provided by the above embodiment, the safety of the first control subcircuit and the power-consuming module is protected by the isolation module.

[0111] In one embodiment, if Figure 7 As shown, the first control subcircuit 201 further includes a voltage processing module 2013, the input end of the voltage processing module 2013 is connected to the output end of the voltage comparison module 2011, and the output end of the voltage processing module 2013 is connected to the power consumption module 301;

[0112] The voltage processing module 2013 is used to perform signal processing on the reference reset signal output by the voltage comparison module 2011 , and output the reference reset signal to drive the power consumption module 301 .

[0113] The external reset signal is provided by the reset port 103, and the external reset signal provided is a signal within the power domain of the first power supply 101, while the power module 301 works within the power domain of the second power supply 102. Therefore, the external reset signal cannot directly drive the power module 301, and the external reset signal needs to be processed to obtain a reference reset signal that can drive the power module 301.

[0114] The processing of the external reset signal is completed by the voltage processing module 2013, which performs a series of processing on the external reset signal and then outputs a reference reset signal to drive the power module 301. The processing of the external reset signal by the voltage processing module 2013 includes but is not limited to the processing of the voltage domain, the processing of the voltage magnitude, and the processing of the driving duration.

[0115] In one embodiment, if Figure 8 As shown, the voltage processing module 2013 includes a voltage conversion unit 1301, the input end of the voltage conversion unit 1301 is connected to the output end of the voltage comparison module 2011, and the output end of the voltage conversion unit 1301 is connected to the power module 301;

[0116] The voltage conversion unit 1301 is used to convert the power domain of the reference reset signal from the first power domain to the second power domain, and output a first target reset signal to drive the first power-consuming module 301 .

[0117] The first power domain is the power domain corresponding to the first power supply 101, and the second power domain is the power domain corresponding to the second power supply 102. The power domain of the reference reset signal is converted from the first power domain to the second power domain by the voltage conversion unit, so that the output first target reset signal can drive the power module 301. The voltage conversion unit 1301 may include a DC-DC converter and an LDO (low dropout linear regulator).

[0118] The voltage conversion unit 1301 processes the reference reset signal only in the power domain of the signal. If the output first target reset signal is to be able to continuously and stably drive the power module 301, the signal needs to be processed in terms of driving capability.

[0119] In one embodiment, if Fig. 9 As shown, the voltage processing module 2013 further includes a driving processing unit 1302, the input end of the driving processing unit 1302 is connected to the output end of the voltage conversion unit 1301, and the output end of the driving processing unit 1302 is connected to the power module 301;

[0120] The driving processing unit 1302 is used to perform signal amplification processing on the first target signal output by the voltage conversion unit 1301 , and output a second target reset signal to drive the power module 301 .

[0121] The driving processing unit 1302 includes a buffer amplifier, which can amplify and output the voltage of the input first target reset signal, thereby improving the driving capability and driving duration of the output second target reset signal, while not changing the waveform characteristics of the first target reset signal.

[0122] The driving processing unit 1302 further includes a filtering subunit, wherein the input end of the filtering subunit is connected to the output end of the buffer amplifier, and the output end of the filtering subunit is connected to the power consumption module 301 .

[0123] The filter subunit is used to filter the signal output by the drive processing unit 1302. In one embodiment, Fig.10 As shown, the filtering subunit includes a low-pass filter 1001 and at least one trigger 1002; the low-pass filter 1001 and the at least one trigger 1002 are connected in sequence; the output end of the low-pass filter 1001 and the output end of the at least one trigger 1002 are connected to the power module 301.

[0124] The high frequency part of the signal is filtered out by the low-pass filter 1001, and then based on the characteristics of the trigger 1002, a plurality of triggers 1002 are connected in sequence, and the output ends of the plurality of triggers are connected to the power module 301, so as to provide a continuous second target reset signal to the power module 301. For example, Fig.11As shown, the filter subunit includes three triggers. If one trigger can keep the first target reset signal for t, then three triggers can keep the first target reset signal for 3t at most, and the generated second target reset signal is kept for 3t.

[0125] The trigger is a D trigger, and the output end of the D trigger is also connected to the power consumption module 301 through a frequency converter.

[0126] Exemplarily, a filtering subunit is provided, and the filtering subunit includes a low-pass filter and three D flip-flops. Specifically, the low-pass filter circuit is composed of a MOS tube, a third resistor R3, and a capacitor C. Among them, the MOS tube plays a role in amplifying and controlling the signal flow, and the third resistor R3 and the capacitor C form an RC low-pass filter for filtering high-frequency signals.

[0127] The three D flip-flops are respectively integrated with two inverters. This design does not affect the signal phase and enhances the signal driving capability. The D flip-flop is used for data transmission and delay circuits. When the clock signal rises and the input of the D flip-flop is high, the output is also high; if the input of the D flip-flop is low, the output is also low. The signal after MOS low-pass filtering is output from the three D flip-flops and can only be input to the power module 301 after passing through the NAND gate and the inverter. This design ensures that the output is continuously low / high to enter / release reset, preventing the signal from directly switching states when there are glitches.

[0128] The design of the driving processing unit ensures that a continuous and stable second target reset signal can be provided to the power-consuming module 301 .

[0129] In one embodiment, if Fig.11 As shown, the power-on and power-off control circuit further includes a second control subcircuit 202, the input end of the second control subcircuit 202 is connected to the first power supply 101, the output end of the second control subcircuit (202) is connected to the power consumption module (301), and the power supply end of the second control subcircuit (202) is connected to the first power supply (101);

[0130] The second control subcircuit (202) is used to control the operation of the power module (301) based on the output voltage of the first power supply (101).

[0131] exist Figure 3In the power-on and power-off control circuit shown, the reset signal provided by the first control subcircuit 201 is jointly determined by the size of the first power supply 101 and the second power supply 102. When the second power supply 102 is powered on, the first power supply 101 is powered on, and the first control subcircuit 201 provides a high level to use the power module 301 to work. When the first power supply 101 is not powered on, the first control subcircuit 201 provides a low level to use the power module 301 in a reset state. If the second power supply 102 is not powered on, the first control subcircuit 201 is in a non-working state. At this time, the power module 301 has no input signal and cannot control the working state of the power module 301. The power-off process is the same.

[0132] Therefore, when the first power source 101 is powered on first and the second power source 102 is powered on later, or the second power source 102 is powered off first, the second control subcircuit 202 provides a reset signal to the power-consuming module 301 to control the working state of the power-consuming module 301 .

[0133] It should be noted that since the usage scenarios of the reset signals provided by the first control subcircuit 201 and the second control subcircuit 202 are different and only one of the two situations will occur, there is no priority between the reset signals provided by the first control subcircuit 201 and the second control subcircuit 202.

[0134] In one embodiment, if Fig.12 As shown, the second control subcircuit 202 includes a power-on reset module 2021, the input end and the power end of the power-on reset module 2021 are connected to the first power supply 101, and the output end of the power-on reset module 2021 is connected to the power module 301;

[0135] The power-on reset module 2021 is used to send a power-on reset signal to the power-consuming module 301 based on the voltage boosting process of the first power source 101 .

[0136] The power-on reset module 2021 includes a POR circuit, which is used to provide a power-on reset signal to the power module 301. When the first power supply 101 is powered on, a low-level reset signal is provided to the power module 301, and after the first power supply 101 reaches the power-on threshold, a high-level signal is provided to start the power module 301 to work.

[0137] In one embodiment, if Fig.13 As shown, the second control subcircuit 202 further includes a power-off reset module 2022, the input end and the power end of the power-off reset module 2022 are connected to the first power supply 101, and the output end of the power-off reset module 2022 is connected to the power module 301;

[0138] The power-off reset module 2022 is used to send an undervoltage reset signal to the power-consuming module 301 based on the voltage reduction process of the first power source 101 .

[0139] The power-off reset module 2022 includes a BOR circuit, which is used to provide an undervoltage reset signal to the power module 301. When the first power supply 101 is powered off, a low-level reset signal is provided to the power module 301. When the power is turned off, the second power supply 102 is powered off first, and after the voltage of the first power supply 101 drops to the card threshold, a low-level signal is provided to put the power module 301 in a reset state.

[0140] In the circuit provided in the above embodiment, by adding a second control subcircuit and combining it with the first control subcircuit, the working state of the second power module can be controlled during any power-on and power-off sequence of the first power supply and the second power supply to ensure the safe operation of the second power module.

[0141] In one embodiment, the second control subcircuit 202 is further configured to trigger a power-on reset signal or a brown-out reset signal after a preset time period after detecting that the first power supply 101 meets the triggering condition of the power-on reset signal or the brown-out reset signal.

[0142] Among them, the triggering condition of the power-on reset signal or the undervoltage reset signal refers to the size of the first power supply 101 meeting the preset condition, such as when the power-on reset signal is on, the voltage of the first power supply 101 is not less than the power-on threshold. The setting of the preset time length is used to determine that the second power supply 102 reaches the working voltage. That is, taking the power-on process as an example, the first power supply 101 is powered on first, and the second power supply 102 is powered on later. After the voltage of the first power supply 101 reaches the corresponding power-on threshold, the power-on reset signal is pulled high after the preset time length is counted.

[0143] It should be noted that the preset duration is only a reference value. In actual applications, for example, to ensure the normal operation of the power module 301, after the preset duration, the voltage of the second power supply 102 needs to be detected. The power-on reset signal is adjusted only after the voltage of the second power supply 102 reaches the corresponding power-on threshold.

[0144] Similarly, when the voltage of the first power supply 101 reaches the corresponding undervoltage threshold, the undervoltage reset signal is adjusted after a preset time. The preset time of the power-off process and the preset time of the power-on process are two concepts, and the values ​​of the two can be the same or different.

[0145] In the circuit provided in the above embodiment, by setting a preset time length, during the power-on and power-off process of the first power supply, the reset signal is adjusted after ensuring that the first power supply is stable and the second power supply is successfully powered on. There is no need to immediately adjust the target reset signal when the first power supply reaches the corresponding power-on threshold or under-voltage threshold, thereby avoiding miscontrol caused by the instability of the first power supply.

[0146] An embodiment of the present application further provides a multi-power supply system, the system comprising a first power supply 101, a second power supply 102 and a power management module 103, the power management module comprising the power-on and power-off control circuits as mentioned in any of the above embodiments.

[0147] In order to better understand the solution of the embodiment of the present application, Figure 1 This application is explained in the context of an application scenario in which a multi-power system is used to power a chip.

[0148] exist Figure 1 In the multi-power supply system shown, in the power-on timing of the first power supply VCC output by the first power supply unit and the second power supply VD11 output by the second power supply unit, due to the relationship between the digital module and the storage module, VCC and VD11 have a strict power-on and power-off timing. The digital module is used as the power module 301, and through the ideas provided in the embodiments of the present application, a first control subcircuit is added between VCC, VD11 and the digital module to provide a reset signal for the RST_N pin of the digital module.

[0149] The structure and connection relationship of the first control subcircuit are as follows Fig.14 As shown, the isolation module of the first control sub-circuit includes a second resistor R2, the voltage comparison module includes a Schmitt trigger, and the voltage processing module includes a power domain conversion PowerShift, a buffer BUF, and a filter circuit Filter.

[0150] The RST_N port is connected to IOVCC through the first resistor R1 (40kΩ in this example). According to the power supply of RST_N by IOVCC, RST_N outputs an external reset signal (high / low level). After VD11 reaches the working voltage, it passes through the Schmitt trigger, power domain conversion, buffer, and then is filtered for a period of time before sending the high level to the digital module.

[0151] The second resistor R2 (500 kΩ in this example) is used to block ESD current transients to prevent damage to chip devices.

[0152] The function of the Schmitt trigger is to use the comparator to realize logic judgment and output high and low levels of irregular signal waveforms. It is used to process the glitches of the input signal. The Schmitt trigger is powered by VD11.

[0153] In the embodiment of the present application, the power domain conversion is implemented based on the MOS tube, and its function is to convert the IOVCC power domain (5V in this example) into the VD11 power domain (1.1V in this example), and to convert the signal ground from IOVSS to VSS11 to prevent immediate damage caused by latchup.

[0154] The function of the buffer is to amplify the voltage of the input signal and output it without changing its waveform characteristics, thereby enhancing the signal's driving capability and stability.

[0155] The filter circuit is used to ensure that the output is continuously low / high level before entering / releasing reset, to prevent direct switching of states when the signal has glitches.

[0156] Specifically, a filtering subunit is provided such as Fig.15 As shown, the filter subunit includes a MOS low-pass filter and three D flip-flops. The MOS low-pass filter circuit is composed of a MOS tube, a third resistor R3, and a capacitor C (RC = 0.5us in this example). The MOS tube plays a role in amplifying and controlling the signal flow, and the third resistor R3 and the capacitor C form an RC low-pass filter to filter out high-frequency signals.

[0157] The three D flip-flops are integrated with two inverters respectively. This design does not affect the signal phase and enhances the signal driving capability. The D flip-flop is used for data transmission and delay circuits. At the rising edge of the clock signal and if the D input is high, the output is also high; if the D input is low, the output is also low. The signal after MOS low-pass filtering is output from the three D flip-flops and can be input into the digital module after passing through the NAND gate and inverter. This design ensures that the output is continuously low / high to enter / release reset, preventing the signal from directly switching states when there are glitches.

[0158] In the above embodiment, the power on and off of the power supplies VCC, VD33 and VD11 are realized by the power-on reset signal POR_N_VCC, the undervoltage reset signal BOR_N_VCC and the external reset signal RST_N. The specific timing is as follows: Fig.16 As shown. Among them, V VCC_Typ is the typical value of VCC operating voltage, V VD33_Typ is the typical value of VD33 working voltage, V VD11_Typ It is the typical value of VD11 working voltage.

[0159] When VCC is powered on first and VD11 is powered on later, POR_N_VCC provides a power-on reset signal for the digital module. When VD11 is powered on first and VCC is powered on later, RST_N provides a power-on reset signal for the digital module. When VD11 is powered off first, BOR_N_VCC provides an undervoltage reset signal for the digital module. When VCC is powered off first, RST_N provides an undervoltage reset signal for the digital module.

[0160] In this example, the power domain of POR_N_VCC is 5V (POR_N_VCC is valid during the VCC power-on process) and 1.1V (sends the reset signal to the digital module). During the VCC power-on process, POR_N_VCC puts the digital module in reset state until the VCC power-on threshold V is detected.POR_N (This example is 1.82V, typical value), timing t POR_Delay (In this example, it is 15.6ms±50%. 15.6ms is the typical time for VD11 to reach the operating voltage, and the range of ±50% is the delay caused by clock deviation). After the VD11 voltage reaches 1.1V, POR_N_VCC is pulled high and the digital module starts working.

[0161] Similarly, the undervoltage threshold V of VCC is detected BOR_N (This example is 2.41V, the default value, the digital module is in reset state, and the analog circuit state is uncertain), timing t BOR_Delay (In this example, it is 110.9us, excluding the fluctuation of VCC output voltage), BOR_N_VCC is pulled low.

[0162] The working principle of RST_N is that during the power-on period (VD11 has reached the working voltage, but VCC has not yet been powered on), RST_N outputs a low level to reset the digital module. If RST_N is pulled high after both VCC and VD11 are powered on, the digital module starts to work. The same is true for the power-off process. RST_N must be pulled low to reset the digital module before VCC and VD11 start to power off in an unordered manner until VD11 is completely powered off.

[0163] In the present invention, the premise for RST_N to reset / release the digital module is that VD11 reaches the working voltage. If VCC is not powered on and VD11 does not reach the working voltage, the entire chip cannot work and cannot be reset. Until VD11 reaches the working voltage, RST_N reset is effective.

Claims

1. A power-on and power-off control circuit, characterized in that: The circuit comprises a first control subcircuit (201), an input end of the first control subcircuit (201) is connected to a first power source (101), an output end of the first control subcircuit (201) is connected to a power consumption module (301), and a power source end of the first control subcircuit (201) is connected to a second power source (102); The first control subcircuit (201) is turned on and operates when the second power supply (102) is powered on, and the first control subcircuit (201) is used to control the operation of the power consumption module (301) based on the output voltage of the first power supply (101).

2. The circuit according to claim 1, characterized in that The power management module of the first power supply (101) comprises a reset port (103), the reset port (103) is connected to the first power supply (101) via a first resistor (R1), and the reset port (103) outputs an external reset signal based on an output voltage of the first power supply (101); The input end of the first control subcircuit (201) is connected to the reset port (103), and the first control subcircuit (201) is used to control the operation of the power consumption module (301) according to the external reset signal.

3. The circuit according to claim 2, characterized in that The first control subcircuit (201) comprises a voltage comparison module (2011), an input end of the voltage comparison module (2011) is connected to the reset port (103), and an output end of the voltage comparison module (2011) is connected to the power consumption module (301); The voltage comparison module (2011) is turned on and operates when the second power supply (102) is powered on. The voltage comparison module (2011) is used to filter the external reset signal and output a reference reset signal. The reference reset signal is used to control the working state of the power consumption module (301).

4. The circuit according to claim 3, characterized in that The voltage comparison module (2011) comprises a trigger.

5. The circuit according to claim 4, characterized in that The trigger is a Schmitt trigger.

6. The circuit according to claim 3, characterized in that The first control subcircuit (201) further comprises an isolation module (2012), the input end of the isolation module (2012) being connected to the reset port (103), and the output end of the isolation module (2012) being connected to the input end of the voltage comparison module (2011); The isolation module (2012) is used to isolate the reset port (103) and the power consumption module (301).

7. The circuit according to claim 6, characterized in that The isolation module (2012) includes a second resistor (R2).

8. The circuit according to claim 6, characterized in that The first control subcircuit (201) further comprises a voltage processing module (2013), the input end of the voltage processing module (2013) being connected to the output end of the voltage comparison module (2011), and the output end of the voltage processing module (2013) being connected to the power consumption module (301); The voltage processing module (2013) is used to perform signal processing on the reference reset signal output by the voltage comparison module (2011), and output a target reset signal to drive the power consumption module (301).

9. The circuit according to claim 8, characterized in that The voltage processing module (2013) comprises a voltage conversion unit (1301), the input end of the voltage conversion unit (1301) is connected to the output end of the voltage comparison module (2011), and the output end of the voltage conversion unit (1301) is connected to the power consumption module (301); The voltage conversion unit (1301) is used to convert the power domain of the reference reset signal from the first power domain to the second power domain, and output a first target reset signal to drive the power consumption module (301).

10. The circuit according to claim 9, characterized in that The voltage processing module (2013) further comprises a drive processing unit (1302), the input end of the drive processing unit (1302) being connected to the output end of the voltage conversion unit (1301), and the output end of the drive processing unit (1302) being connected to the power consumption module (301); The driving processing unit (1302) is used to perform signal amplification processing on the first target reset signal output by the voltage conversion unit (1301), and output a second target reset signal to drive the power consumption module (301).

11. The circuit according to claim 10, characterized in that The driving processing unit (1302) includes a buffer amplifier.

12. The circuit according to claim 11, characterized in that The driving processing unit (1302) further comprises a filtering subunit, the input end of the filtering subunit is connected to the output end of the buffer amplifier, and the output end of the filtering subunit is connected to the power consumption module (301).

13. The circuit according to claim 12, characterized in that The filtering subunit comprises a low-pass filter (1001) and at least one trigger (1002); the low-pass filter (1001) and the at least one trigger (1002) are connected in sequence; the output end of the low-pass filter (1001) and the output end of the at least one trigger (1002) are connected to the power consumption module (301).

14. The circuit according to claim 13, characterized in that The trigger is a D trigger.

15. The circuit according to claim 1, characterized in that The power-on and power-off control circuit further comprises a second control subcircuit (202), the input end of the second control subcircuit (202) being connected to the first power source (101), the output end of the second control subcircuit (202) being connected to the power consumption module (301), and the power supply end of the second control subcircuit (202) being connected to the first power source (101); The second control subcircuit (202) is used to control the operation of the power consumption module (301) based on the output voltage of the first power supply (101).

16. The circuit according to claim 15, characterized in that The second control subcircuit (202) comprises a power-on reset module (2021), the input end and the power end of the power-on reset module (2021) are connected to the first power supply (101), and the output end of the power-on reset module (2021) is connected to the power consumption module (301); The power-on reset module (2021) is used to send a power-on reset signal to the power consumption module (301) based on the voltage boost process of the first power source (101).

17. The circuit according to claim 16, characterized in that The second control subcircuit (202) further comprises a power-off reset module (2022), wherein an input end and a power supply end of the power-off reset module (2022) are connected to the first power supply (101), and an output end of the power-off reset module (2022) is connected to the power consumption module (301); The power-off reset module (2022) is used to send an undervoltage reset signal to the power consumption module (301) based on the voltage reduction process of the first power source (101).

18. The circuit according to any one of claims 16 to 17, characterized in that: The second control subcircuit (202) is further configured to trigger the power-on reset signal or the undervoltage reset signal after a preset time period after detecting that the voltage of the first power supply (101) meets the triggering condition of the power-on reset signal or the undervoltage reset signal.

19. A multi-power system, characterized in that: The system comprises a first power supply (101), a second power supply (102) and a power management module (103), wherein the power management module comprises the power-on and power-off control circuit as claimed in claims 1-18.

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