Wafer-level chip layout method, device and medium based on affinity and symmetry

Abstract

The invention provides a wafer-level chip layout method, device and medium based on affinity and symmetry, which relate to the field of electronic automation design. According to the wafer-level chip design requirements, core particles are selected, core particle information is input, core particles that meet affinity constraints are divided into multiple core particle groups, and the layout within the group is initialized, and the layout within the group is optimized by using a simulated annealing algorithm to obtain multiple groups of core particle groups after the layout is completed; the multiple groups of core particle groups after the layout are completed are classified into multiple groups of symmetric core particle group pairs according to symmetric relationships, and the multiple groups of symmetric core particle group pairs and ungrouped core particle groups are initialized for layout using a sequence pair representation method, the multiple groups of symmetric core particle group pairs in the initialization layout meet the symmetry constraints, and then the simulated annealing algorithm is used to optimize the initialization layout and meet the symmetry constraints, and finally a chip module is formed; the chip module is tiled in a wafer layoutable area to complete the wafer layout, and the wafer-level chip after the layout has affinity and symmetry, and the layout efficiency is high.

Description

Technical Field

[0001] The present invention relates to the field of electronic automation design, and in particular to a wafer-level chip layout method, device and medium based on affinity and symmetry. Background Art

[0002] Chip layout is a key step in chip design. Its goal is to optimize the placement of various circuit modules within a limited chip area to meet design goals such as performance, power consumption, and area. The layout of wafer-level integrated chips is similar to that of traditional chips, and the layout method of traditional chips can be used as a reference.

[0003] At present, the automatic layout algorithms commonly used in traditional chips in the industry are based on heuristic algorithms such as simulated annealing, genetic algorithms, force-directed methods, and finding the optimal solution by simulating the physical derivation process, the genetic principle of natural selection, and simulating the forces in the physical system. Heuristic algorithms can handle multi-objective optimization problems and complex layout constraints; the minimum cut partitioning algorithm optimizes the layout by dividing the layout area into multiple sub-areas and minimizing the cross-area connections; the hierarchical layout algorithm handles the layout problem in layers, first optimizing the top-level layout and then gradually refining the bottom-level layout. This algorithm can effectively handle large-scale problems.

[0004] In recent years, AI technology has been introduced into the field of chip layout. For example, the AlphaChip model proposed by Google. This model achieves end-to-end chip layout optimization through reinforcement learning and graph neural network (GNN). This technology can generate layouts that are equivalent to or even better than human experts within 6 hours. It has been applied to Google's TPU design. However, this technology has been questioned by the academic community, and the experimental results are difficult to reproduce.

[0005] Disadvantages of existing technologies:

[0006] (1) The integration density of wafer-level chips is high, the problem scale is large, and the efficiency of heuristic chip layout algorithms is low.

[0007] (2) The constraints of traditional layout algorithm problem modeling cannot be directly applied to wafer-level chip layout design. Traditional algorithms need to be optimized based on the characteristics of wafer-level chip design. For example, wafer-level integrated chips need to consider the symmetry of the layout to improve signal integrity and anti-interference capabilities.

[0008] (3) Reinforcement learning-based layout algorithms require a large amount of training data and computing resources. Chip layout is different from traditional deep learning application scenarios. Due to commercial competition and other reasons, chip data is basically confidential. There are few public data sets for training models, and data acquisition is difficult. In addition, reinforcement learning models have weak generalization capabilities and poor stability, and their performance on prediction data is not as good as training data. Summary of the invention

[0009] In order to solve the above technical problems, the present invention provides a wafer-level chip layout method, device and medium based on affinity and symmetry. The laid-out chips have affinity and symmetry, and the layout efficiency is high.

[0010] To achieve the above technical purpose, the adopted technical solution is: a wafer-level chip layout method based on affinity and symmetry, comprising the following steps:

[0011] Step 1, selecting core particles according to wafer-level chip design requirements, dividing core particles that meet affinity constraints into a group through input wafer-level chip core particle information, dividing multiple groups of core particle groups, initializing the intra-group layout of each group of core particle groups, using the first simulated annealing algorithm to optimize the intra-group layout, and obtaining multiple groups of core particle groups after the layout is completed;

[0012] Step 2, classifying the multiple groups of core grains obtained in step 1 after the layout is completed into multiple groups of symmetric core grain pairs according to the symmetry relationship, using the sequence pair representation method to initialize the layout of the multiple groups of symmetric core grain pairs and the ungrouped core grain groups, the multiple groups of symmetric core grain pairs in the initial layout meet the symmetry constraints, and then using the second simulated annealing algorithm to optimize the initial layout, the multiple groups of symmetric core grain pairs in the optimization meet the symmetry constraints, and finally forming a chip module;

[0013] Step 3: Consider the chip module as the smallest layout unit and lay it out in the wafer layout area to complete the wafer layout.

[0014] Furthermore, affinity constraint means that when dividing the core groups, they are grouped according to the communication volume between the cores and the wafer-level chip design requirements. The interconnected cores in the same core group are arranged closely together without other cores in between.

[0015] Furthermore, the specific method for initializing the layout within each group of chiplets is: according to the port interconnection relationship in the wafer-level chip chiplet information, the interconnection of each chiplet in the same chiplet group is created, and the sequence pair representation is used to initialize the layout within each group of chiplets, with random positions.

[0016] Furthermore, after the layout is completed, the ports in the chiplet group that are not used for intra-group connection are all set as external interfaces, and the positions are the same as the original port position coordinates.

[0017] Furthermore, the first simulated annealing algorithm optimization is performed with the core particle layout area and the total length of the port connection between core particles as the optimization targets.

[0018] Furthermore, the symmetrical relationship means that the difference in length and width of a pair of core particle groups after layout is completed does not exceed 30%.

[0019] Furthermore, the symmetry constraint formula is described as follows:

[0020]

[0021] Among them, α is the sequence to positive sequence, β is the sequence to negative sequence, Represents one of the core groups in a symmetric core group pair ci The position in the α sequence, Represents the other core group in the symmetric core group pair cj The position in the α sequence, Represents one of the core groups in a symmetric core group pair ci The position in the β sequence, Represents the other core group in the symmetric core group pair cj Position in the beta sequence.

[0022] Furthermore, the second simulated annealing algorithm optimization is performed with the core particle group layout area and the total length of the port connection between the core particle groups as the optimization targets.

[0023] A wafer-level chip layout device based on affinity and symmetry, comprising:

[0024] The affinity coreparticle group layout module selects coreparticles according to the wafer-level chip design requirements, and divides the coreparticles that meet the affinity constraints into a group through the input wafer-level chip coreparticle information, divides multiple groups of coreparticle groups, initializes the intra-group layout of each group of coreparticle groups, and uses the first simulated annealing algorithm to optimize the intra-group layout to obtain multiple groups of coreparticle groups after the layout is completed;

[0025] A symmetric coregrain group layout module is used to classify the coregrain groups obtained by the affinity coregrain group layout module after the multiple groups of layout are completed into multiple groups of symmetric coregrain pairs according to the symmetry relationship, and initialize the layout of the multiple groups of symmetric coregrain pairs and ungrouped coregrain groups using a sequence pair representation method, and the multiple groups of symmetric coregrain pairs in the initial layout meet the symmetry constraints, and then use the second simulated annealing algorithm to optimize the initial layout, and the multiple groups of symmetric coregrain pairs in the optimization meet the symmetry constraints, and finally form a chip module;

[0026] The wafer architecture generation module is used to treat the chip module as the smallest layout unit and tile it into the wafer layout area to complete the wafer layout.

[0027] A storage medium stores a computer program, which implements the affinity- and symmetry-based wafer-level chip layout method when executed by a processor.

[0028] The beneficial effects of the present invention are as follows: the processing cost and design difficulty in traditional processes are constrained by the method. First, a minimum core particle group module composed of a variety of heterogeneous core particles is designed to reduce the scale of the optimization problem and improve the solution efficiency. Secondly, the symmetry of the wafer-level chip and the reasonable layout of the core particle group are considered. By establishing symmetry constraints suitable for wafer-level chips, the signal integrity and anti-interference capabilities are improved. Finally, the chip modules are tiled according to the size of the wafer-level chip, and a wafer-level chip layout plan is automatically generated. The plan meets the actual engineering design requirements and improves the layout efficiency. It has strong stability, provides design plans for engineers, and reduces chip design time and labor costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the method of this application;

[0030] Figure 2 This is a schematic diagram of the core particle model file;

[0031] Figure 3 To initialize the layout diagram within the group;

[0032] Figure 4 This is a schematic diagram of the symmetrical layout in step 2. DETAILED DESCRIPTION

[0033] The preferred embodiments of the invention are given below in conjunction with the accompanying drawings to explain the technical solution of the present invention in detail. Here, the corresponding drawings are given to explain the present invention in detail. It should be particularly noted that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not used to limit or restrict the present invention.

[0034] 1. Wafer-level chip core information:

[0035] (1) Core particle model file

[0036] The smallest layout unit of wafer-level chips is defined as a chiplet, which is a prefabricated small chip with specific functions.

[0037] First, the core particles are modeled. The physical interfaces of a group of core particles are modularized and abstracted, such as memory control modules, high-speed switching modules, etc. The locations of these modules are roughly divided to the edge of the chip to facilitate the subsequent calculation of the line length cost. Figure 2The following is a core model file, which is the input file of this method. NumModules is the number of modules; sizeX and sizeY are the physical dimensions of the chip in the X and Y directions; relativePos is the reference point, which is the lower left corner by default; 7, 8, 9, 10, 11, and 12 below modules are the port module information, mc1, mc2, rdio1, rdio2, rdio3, and rdio4 are the port names, and the two numbers behind are the X and Y coordinates of the port.

[0038] (2) Architecture description file

[0039] The architecture file must include the chip name, model, and port interconnection relationship between chiplets.

[0040] 2. Wafer-level chip layout method, device and medium based on affinity and symmetry:

[0041] like Figure 1 As shown, a wafer-level chip layout method based on affinity and symmetry includes the following steps:

[0042] Step 1. Select core particles according to the wafer-level chip design requirements. By inputting the wafer-level chip core particle information, the core particles that meet the affinity constraints are divided into a group, and multiple groups of core particle groups are divided. The intra-group layout of each group of core particles is initialized, and the intra-group layout is optimized using the first simulated annealing algorithm to obtain multiple groups of core particle groups after the layout is completed.

[0043] The specific implementation methods are: affinity layout based on simulated annealing;

[0044] Step 1.1, set up a chip group with affinity constraints, such as CPU and DDR. Affinity constraints mean that when dividing chip groups, they are grouped according to the communication volume between chiplets and wafer-level chip design requirements. The interconnected chiplets in the same chip group are laid out closely together, and no other chiplets can be separated in the middle. That is, the communication volume between chiplets in the same chip group is large, which meets the wafer-level chip design requirements. There are no other chiplets in the same group or in different groups between two interconnected chiplets. Figure 1 As shown, a chiplet group consisting of two DDRs and one CPU, a chiplet group consisting of two DDRs and two CPUs, a chiplet group consisting of one DDR and one CPU, and so on.

[0045] Step 1.2: Create interconnections between the corelets in the same corelet group according to the port interconnection relationship in the architecture description file. Figure 3 As shown, two DDRs are interconnected with one port of the CPU.

[0046] Step 1.3: Use the sequence pair representation method to initialize the layout within each group of core particles. The result of the layout of a core particle group is as follows: Figure 3 The interface interconnection is created on the far left.

[0047] Step 1.4: Use simulated annealing algorithm to optimize the layout. The optimization goal is:

[0048] Target=a*Area+b*Wirelength (1)

[0049] Where a and b are weight coefficients, and the sum of a and b is 1, indicating the priority of the optimization target. The values ​​of a and b need to be adjusted according to the actual application. Area is the layout area of ​​the core particle, and Wirelength is the total length of the port connection between the core particles. The total length of the port connection between the core particles is estimated using the Manhattan distance, and the specific formula is as follows. Where (x1, y1) and (x2, y2) are the interface position coordinates of the two interconnected core particles. The final result is as follows Figure 3 The middle layout is shown optimized.

[0050] Wirelength=|x1-x2|+|y1-y2| (2)

[0051] Step 1.5: Figure 3 The rightmost chip group is encapsulated. After the layout is completed, the chip groups with affinity are encapsulated as a whole, and the external interface positions are set. Ports that are not used for intra-group connections need to be set as external interfaces, and the positions are the same as the original port position coordinates to facilitate the connection between chip groups.

[0052] Step 2: Classify the multiple groups of core grains obtained in step 1 after the layout is completed into multiple groups of symmetric core grain pairs according to the symmetry relationship, use sequence pair representation to initialize the layout of the multiple groups of symmetric core grain pairs and ungrouped core grain groups, and the multiple groups of symmetric core grain pairs in the initialized layout meet the symmetry constraints. Then use the second simulated annealing algorithm to optimize the initialized layout, and the multiple groups of symmetric core grain pairs in the optimization meet the symmetry constraints, and finally form a chip module.

[0053] The specific implementation method is: symmetric layout based on simulated annealing;

[0054] Step 2.1, set symmetrical core particle pairs according to the symmetry relationship. The symmetry relationship refers to a pair of core particle groups with the same shape or similar shapes after the layout is completed. The same shape means that the length and width difference of a pair of core particle groups after the layout is completed is zero. The similar shape means that the length and width difference of a pair of core particle groups after the layout is completed does not exceed 30%. Figure 1 As shown in the figure, taking four core particle groups as an example, (c1, c2) represents a core particle pair with a symmetric relationship, and (c3, c4) represents a core particle pair with a symmetric relationship. Multiple symmetric core particle pairs are represented as (c1, c2), (c3, c4), and the chip c5 not in the brackets is not in the symmetric core particle group without symmetry constraints.

[0055] Step 2.2: Use sequence pair representation to initialize the layout of multiple symmetric core particle groups and ungrouped core particle groups as the initial solution of the simulated annealing algorithm. The initial solution must meet the symmetry constraint, which is expressed by formula (3). α is the sequence pair positive sequence, β is the sequence pair negative sequence, Represents one of the core groups in a symmetric core group pair ci The position in the α sequence, Represents the other core group in the symmetric core group pair cj The position in the α sequence, Represents one of the core groups in a symmetric core group pair ci The position in the β sequence, Represents the other core group in the symmetric core group pair cj The position in the β sequence. Formula 3 means a pair of symmetrical core particles, whose order of appearance in the positive and negative sequences is the same.

[0056] (3)

[0057] Taking (c1, c2) as an example, the symmetry constraint formula used is .

[0058] Step 2.3, use the second simulated annealing algorithm to optimize the layout. The layout is optimized with the core particle group layout area and the total length of the port connection between the core particle groups as the optimization target, and the optimization is performed according to formula (1) and (2). When perturbing, it is necessary to ensure that the symmetric core particle group pairs after each perturbation meet the symmetry constraints described in formula (3). The optimization process is as follows Figure 4 shown.

[0059] Step 2.4: After optimization, the chips after the second stage layout are packaged into modules and the third stage layout is carried out.

[0060] Step 3: Consider the chip module as the smallest layout unit and lay it out in the wafer layout area to complete the wafer layout.

[0061] A wafer-level chip layout device based on affinity and symmetry, comprising:

[0062] The affinity coreparticle group layout module selects coreparticles according to the wafer-level chip design requirements, and divides the coreparticles that meet the affinity constraints into a group through the input wafer-level chip coreparticle information, divides multiple groups of coreparticle groups, initializes the intra-group layout of each group of coreparticle groups, and uses the first simulated annealing algorithm to optimize the intra-group layout to obtain multiple groups of coreparticle groups after the layout is completed;

[0063] A symmetric coregrain group layout module is used to classify the coregrain groups obtained by the affinity coregrain group layout module after the multiple groups of layout are completed into multiple groups of symmetric coregrain pairs according to the symmetry relationship, and initialize the layout of the multiple groups of symmetric coregrain pairs and ungrouped coregrain groups using a sequence pair representation method, and the multiple groups of symmetric coregrain pairs in the initial layout meet the symmetry constraints, and then use the second simulated annealing algorithm to optimize the initial layout, and the multiple groups of symmetric coregrain pairs in the optimization meet the symmetry constraints, and finally form a chip module;

[0064] The wafer architecture generation module is used to treat the chip module as the smallest layout unit and tile it into the wafer layout area to complete the wafer layout.

[0065] A storage medium stores a computer program, which implements the affinity- and symmetry-based wafer-level chip layout method when executed by a processor.

[0066] The above are only preferred embodiments of the present invention and are not intended to limit or restrict the present invention. For researchers or technicians in this field, the present invention may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection declared by the present invention.

Claims

1. A wafer-level chip layout method based on affinity and symmetry, characterized in that: The following steps are involved: Step 1, selecting core particles according to wafer-level chip design requirements, dividing core particles that meet affinity constraints into a group through input wafer-level chip core particle information, dividing multiple groups of core particle groups, initializing the intra-group layout of each group of core particle groups, using the first simulated annealing algorithm to optimize the intra-group layout, and obtaining multiple groups of core particle groups after the layout is completed; Step 2, classifying the multiple groups of core grains obtained in step 1 after the layout is completed into multiple groups of symmetric core grain pairs according to the symmetry relationship, using the sequence pair representation method to initialize the layout of the multiple groups of symmetric core grain pairs and the ungrouped core grain groups, the multiple groups of symmetric core grain pairs in the initial layout meet the symmetry constraints, and then using the second simulated annealing algorithm to optimize the initial layout, the multiple groups of symmetric core grain pairs in the optimization meet the symmetry constraints, and finally forming a chip module; Step 3: Consider the chip module as the smallest layout unit and lay it out in the wafer layout area to complete the wafer layout.

2. The wafer-level chip layout method based on affinity and symmetry as claimed in claim 1, characterized in that: Affinity constraint means that when dividing the core groups, they are grouped according to the communication volume between the cores and the wafer-level chip design requirements. The interconnected cores in the same core group are laid out closely together without other cores in between.

3. The wafer-level chip layout method based on affinity and symmetry as claimed in claim 1, characterized in that: The specific method for initializing the layout within each group of core particles is: according to the port interconnection relationship in the wafer-level chip core particle information, the interconnection of each core particle in the same core particle group is created, and the sequence pair representation is used to initialize the layout within each group of core particles, with random positions.

4. The wafer-level chip layout method based on affinity and symmetry as claimed in claim 1, characterized in that: After the layout is completed, the ports in the core group that are not used for internal connection are set as external interfaces, and the positions are the same as the original port position coordinates.

5. The wafer-level chip layout method based on affinity and symmetry as claimed in claim 1, characterized in that: The first simulated annealing algorithm optimization is performed with the core particle layout area and the total length of the port connection between core particles as the optimization target.

6. The wafer-level chip layout method based on affinity and symmetry as claimed in claim 1, characterized in that: The symmetric relationship means that the length and width difference of a pair of core groups after layout is completed does not exceed 30%.

7. The wafer-level chip layout method based on affinity and symmetry as claimed in claim 1, characterized in that: The symmetry constraint formula is described as follows: , where α is the sequence to positive sequence, β is the sequence to negative sequence, Represents one of the core groups in a symmetric core group pair ci The position in the α sequence, Represents the other core particle group in the symmetric core particle group pair cj The position in the α sequence, Represents one of the core groups in a symmetric core group pair ci The position in the β sequence, Represents the other core particle group in the symmetric core particle group pair cj Position in the beta sequence.

8. The wafer-level chip layout method based on affinity and symmetry as claimed in claim 1, characterized in that: The second simulated annealing algorithm optimization is performed with the core particle group layout area and the total length of the port connection between core particle groups as the optimization target.

9. A wafer-level chip layout device based on affinity and symmetry, characterized in that: include: The affinity coreparticle group layout module selects coreparticles according to the wafer-level chip design requirements, and divides the coreparticles that meet the affinity constraints into a group through the input wafer-level chip coreparticle information, divides multiple groups of coreparticle groups, initializes the intra-group layout of each group of coreparticle groups, and uses the first simulated annealing algorithm to optimize the intra-group layout to obtain multiple groups of coreparticle groups after the layout is completed; A symmetric coregrain group layout module is used to classify the coregrain groups obtained by the affinity coregrain group layout module after the multiple groups of layout are completed into multiple groups of symmetric coregrain pairs according to the symmetry relationship, and use the sequence pair representation method to initialize the layout of the multiple groups of symmetric coregrain pairs and the ungrouped coregrain groups, and the multiple groups of symmetric coregrain pairs in the initial layout meet the symmetry constraints, and then use the second simulated annealing algorithm to optimize the initial layout, and the multiple groups of symmetric coregrain pairs in the optimization meet the symmetry constraints, and finally form a chip module; The wafer architecture generation module is used to treat the chip module as the smallest layout unit and tile it into the wafer layout area to complete the wafer layout.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the affinity-and-symmetry-based wafer-level chip layout method according to any one of claims 1 to 8 is implemented.

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