Voltage holding circuit and system on chip

Abstract

The application provides a voltage holding circuit and a system on chip. The voltage holding circuit comprises a charge pump, a trigger unit, a first switch unit and a voltage holding unit. The trigger unit is connected with the control end of the charge pump and the first switch unit respectively. The first end of the first switch unit is connected with the output end of the charge pump, and the second end of the first switch unit is connected with the voltage holding unit. The voltage holding unit is also used for connecting a DNW array of a memory. By controlling the working or resting of the charge pump, the input end voltage of the voltage holding unit is kept in a first target voltage interval, so that the voltage of the parasitic capacitance of the DNW array is kept in a second target voltage interval. When the read and write operations of the memory are needed, the power supply voltage of the electronic equipment can quickly raise the memory to the working voltage, so as to quickly respond to the read and write operations of the memory and guarantee the low power consumption in the standby mode.

Description

Technical Field

[0001] This invention relates to the field of electronic devices, and more specifically, to a voltage holding circuit and a system-on-a-chip. Background Technology

[0002] In standby mode (also known as sleep mode or standby mode), electronic devices reduce power consumption to extend battery life. Electronic devices typically contain flash memory (FLASH memory), and due to the operating characteristics of flash memory, it may not be able to perform read and write operations properly at lower voltages. When data needs to be read from the flash memory, to ensure reliable data access, the electronic device switches to read mode, in which case the power supply is sufficient to support the flash memory read operation.

[0003] Due to the characteristics of flash memory, when electronic devices switch from standby mode to read mode, especially when flash memory requires a voltage higher than the normal operating voltage VDD to perform operations, maintaining a sufficient voltage supply increases power consumption, which conflicts with the goal of saving energy in standby mode. Summary of the Invention

[0004] The purpose of this invention is to provide a voltage holding circuit and a system-on-a-chip to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, embodiments of the present invention provide a voltage holding circuit, the voltage holding circuit including a charge pump, a triggering unit, a first switching unit, and a voltage holding unit;

[0007] The triggering unit is connected to the control terminals of the charge pump and the first switching unit, respectively.

[0008] The first terminal of the first switching unit is connected to the output terminal of the charge pump, and the second terminal of the first switching unit is connected to the voltage holding unit;

[0009] The voltage holding unit is also used to connect the DNW array of the memory.

[0010] Optionally, the triggering unit is used to send a start signal to the charge pump when the first triggering condition is met, and control the first switching unit to switch to the closed state so that the charge pump charges the voltage holding unit and keeps the input voltage of the voltage holding unit within the first target voltage range.

[0011] The triggering unit is used to send a rest signal to the charge pump and control the first switching unit to switch to the off state when the second triggering condition is met.

[0012] The voltage holding unit is used to charge the DNW array so that the voltage of the parasitic capacitance of the DNW array is maintained within the second target voltage range.

[0013] Optionally, the triggering unit is used to detect the current voltage at the output terminal of the charge pump;

[0014] The triggering unit is used to determine that the first triggering condition is met when the current voltage is lower than the first voltage threshold.

[0015] The triggering unit is used to determine that the second triggering condition is met when the current voltage reaches the second voltage threshold.

[0016] Optionally, the triggering unit is used to record the start-up interval of the charge pump, and when the start-up interval is equal to a first time threshold, it is determined that the first triggering condition is met.

[0017] The triggering unit is used to record the continuous start-up duration of the charge pump. When the continuous start-up duration is equal to the second time threshold, it is determined that the second triggering condition is met.

[0018] Wherein, the start-up interval duration represents the time between the last time the charge pump entered the rest state and the current time, and the continuous start-up duration represents the time between the last time the charge pump entered the start-up state and the current time.

[0019] Optionally, the voltage holding unit includes a first capacitor and an NMOS transistor;

[0020] At the connection point between one pole of the first capacitor and the gate of the NMOS transistor, a terminal is led out as the input terminal of the voltage holding unit, which is used to connect to the second terminal of the first switching unit;

[0021] The other terminal of the first capacitor is grounded, the drain of the NMOS transistor is connected to the output terminal of the charge pump, and the source of the NMOS transistor is connected to the DNW array.

[0022] Optionally, the voltage holding circuit further includes a first resistor, a second resistor, and a second switching unit;

[0023] One end of the first resistor is connected to the second end of the first switching unit, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is grounded;

[0024] One end of the second switching unit is connected to a terminal block between the first resistor and the second resistor, and the other end of the second switching unit is connected to the input terminal of the voltage holding unit.

[0025] The triggering unit is connected to the control terminal of the second switching unit, and the triggering unit is used to control the state of the second switching unit to be consistent with that of the first switching unit.

[0026] Optionally, the voltage holding unit further includes a third switching unit;

[0027] The first end of the third switching unit is connected to the output end of the charge pump, and the second end of the third switching unit is connected to the drain of the NMOS transistor.

[0028] Optionally, when the electronic device in which the voltage holding circuit is deployed is in standby mode, the third switching unit is in a closed state;

[0029] When the electronic device is in working mode, the third switching unit is in the off state.

[0030] Secondly, embodiments of the present invention provide a system-on-a-chip, the system-on-a-chip including a memory and the voltage holding circuit described above.

[0031] Thirdly, embodiments of the present invention provide an electronic device including the above-described system-on-a-chip.

[0032] Compared to existing technologies, the present invention provides a voltage holding circuit and a system-on-a-chip. The voltage holding circuit includes a charge pump, a trigger unit, a first switching unit, and a voltage holding unit. The trigger unit is connected to the control terminals of the charge pump and the first switching unit. The first terminal of the first switching unit is connected to the output terminal of the charge pump, and the second terminal of the first switching unit is connected to the voltage holding unit. The voltage holding unit is also used to connect to a DNW array of memory. By controlling the charge pump to operate or rest, the input voltage of the voltage holding unit is kept within a first target voltage range, thereby keeping the voltage of the parasitic capacitance of the DNW array within a second target voltage range. When memory read / write operations are required, the power supply voltage of the electronic device can quickly boost the memory to its operating voltage, thereby quickly responding to memory read / write operations and ensuring low power consumption in standby mode.

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is one of the voltage holding circuits provided in the embodiments of the present invention.

[0036] Figure 2 This is a second voltage holding circuit provided in an embodiment of the present invention.

[0037] Figure 3 The third voltage holding circuit provided in the embodiments of the present invention.

[0038] In the diagram: 10 - charge pump; 20 - trigger unit; 30 - voltage holding unit; 40 - DNW array. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0041] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0042] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0043] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0044] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0045] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0046] To enable electronic devices to quickly respond to memory read and write operations with low power consumption in standby mode, this invention provides an optional implementation method. In standby mode, a voltage holding circuit keeps the parasitic capacitance of the memory's DNW (Deep N Well) array close to the memory's operating voltage. This allows the memory to be quickly boosted to the operating voltage when read and write operations are needed, thereby ensuring a rapid response to these operations. In this invention, the memory may be, but is not limited to, flash memory.

[0047] Because the S / D converter needs to see a negative voltage during memory cell operations, a conventional NMOS with PSUB as GND cannot be used. A separate NMOS with pwell and deep N well is required. A large memory array typically contains many memory cells, so the deep N well of many NMOS modules has a naturally large parasitic capacitance (and the parasitic PN junction between the Pwell and PSUB).

[0048] Please refer to Figure 1 , Figure 1 This is one of the voltage holding circuits provided in the embodiments of the present invention. The voltage holding circuit includes a charge pump 10, a trigger unit 20, a first switching unit K1, and a voltage holding unit 30.

[0049] The trigger unit 20 is connected to the control terminals of the charge pump 10 and the first switch unit K1, respectively.

[0050] The first terminal of the first switching unit K1 is connected to the output terminal (Vout) of the charge pump 10, and the second terminal of the first switching unit K1 is connected to the voltage holding unit 30.

[0051] The voltage holding unit 30 is also used to connect the DNW array 40 of the memory.

[0052] The triggering unit 20 is used to send a start signal to the charge pump 10 and control the first switch unit K1 to switch to the closed state when the first triggering condition is met, so that the charge pump 10 charges the voltage holding unit 30 and keeps the input voltage of the voltage holding unit 30 within the first target voltage range.

[0053] Optionally, the first trigger condition being met indicates that the input voltage of the voltage holding unit 30 has dropped to a third voltage threshold, which can be the lower limit of the first target voltage range.

[0054] The triggering unit 20 is used to send a rest signal to the charge pump 10 and control the first switching unit K1 to switch to the off state when the second triggering condition is met.

[0055] Optionally, the second trigger condition being met indicates that the input voltage (voltage at point A) of the voltage holding unit 30 rises to the fourth voltage threshold (the maximum value of the input voltage of the voltage holding unit 30), and the fourth voltage threshold can be the upper limit of the first target voltage range.

[0056] The voltage holding unit 30 is used to charge the DNW array 40 so that the voltage of the parasitic capacitance Cg of the DNW array 40 (the voltage at point B) is kept within the second target voltage range.

[0057] Optionally, the lower limit of the second target voltage range is higher than the supply voltage of the voltage source of the electronic device in standby mode. The input voltage of the voltage holding unit 30 (voltage at point A) and the voltage of the parasitic capacitance Cg of the DNW array 40 (voltage at point B) maintain a preset voltage difference. Therefore, when the input voltage of the voltage holding unit 30 is within the first target voltage range, the voltage of the parasitic capacitance Cg of the DNW array 40 (voltage at point B) can be guaranteed to remain within the second target voltage range.

[0058] In the voltage holding circuit provided in this embodiment of the invention, the charge pump 10 is triggered to operate by a first trigger condition, so that the input voltage of the voltage holding unit 30 is within a first target voltage range, thereby keeping the voltage of the parasitic capacitance Cg of the DNW array 40 within a second target voltage range. When memory read / write operations are required, the power supply voltage of the electronic device can quickly boost the memory to the operating voltage, thereby quickly responding to memory read / write operations.

[0059] Simultaneously, the charge pump 10 is triggered to stop working and enter a resting state by a second trigger condition, thereby ensuring low power consumption in standby mode. This allows the system to have high reliability and low power consumption in standby mode, performing limited operations only when necessary.

[0060] Based on the preceding text, this invention provides an optional implementation method for determining whether the rising trigger condition is met, as detailed below.

[0061] The trigger unit 20 is used to detect the current voltage at the output terminal of the charge pump 10.

[0062] It should be understood that in this embodiment of the invention, the trigger unit 20 can detect the current voltage at the output terminal of the charge pump 10, i.e., the voltage at point C in the figure.

[0063] The triggering unit 20 is used to determine that the first triggering condition is met when the current voltage is lower than the first voltage threshold.

[0064] It should be understood that when charge pump 10 stops working, the voltages at points A, B, and C shown in the diagram will all decrease, and these decreases are correlated. In optional scenarios, the output of the charge pump can also be connected to other component units, or multiple voltage holding circuits can share a single charge pump. Point C is located at the output of charge pump 10, where the voltage change is most pronounced and easier to monitor. Therefore, the current voltage at the output of charge pump 10 is detected, and the triggering condition is determined based on this.

[0065] It should be noted that if the current voltage at the output terminal of the charge pump 10 (voltage at point C) is lower than the first voltage threshold, then the input voltage at the voltage holding unit 30 (voltage at point A) has been reduced to the third voltage threshold, thus confirming that the first trigger condition is met.

[0066] The triggering unit 20 is used to determine that the second triggering condition is met when the current voltage reaches the second voltage threshold.

[0067] It should be noted that if the current voltage at the output terminal of the charge pump 10 (voltage at point C) reaches the second voltage threshold, then the input voltage at the voltage holding unit 30 (voltage at point A) has risen to the fourth voltage threshold, thus confirming that the second triggering condition is met.

[0068] The first voltage threshold may be, but is not limited to, 5.7V, and the second voltage threshold may be, but is not limited to, 6V.

[0069] Based on the preceding text, this invention provides an optional implementation method for determining whether the rising trigger condition is met, as detailed below.

[0070] The trigger unit 20 is used to record the start-up interval of the charge pump 10. When the start-up interval is equal to the first time threshold, the first trigger condition is determined to be met.

[0071] When the charge pump 10 stops working, the input voltage (voltage at point A) of the voltage holding unit 30 gradually decreases. When the start-up interval is equal to the first time threshold, the input voltage (voltage at point A) of the voltage holding unit 30 has decreased to the third voltage threshold, confirming that the first trigger condition is met.

[0072] The triggering unit 20 is used to record the continuous start-up duration of the charge pump 10. When the continuous start-up duration is equal to the second time threshold, the second triggering condition is determined to be met.

[0073] When the charge pump 10 starts working and enters the startup state, the input voltage (voltage at point A) of the voltage holding unit 30 rises rapidly. When the continuous startup duration equals the second time threshold, the input voltage (voltage at point A) of the voltage holding unit 30 has risen to the fourth voltage threshold, confirming that the second trigger condition is met.

[0074] The start-up interval duration represents the time between the last time the charge pump 10 entered the rest state and the current time, while the continuous start-up duration represents the time between the last time the charge pump 10 entered the start-up state and the current time.

[0075] Building upon the foregoing, this invention also provides an optional implementation method for achieving voltage maintenance. Please refer to [link / reference needed]. Figure 2 , Figure 2 This is a second voltage holding circuit provided in an embodiment of the present invention.

[0076] The voltage holding unit 30 includes a first capacitor C1 and an NMOS transistor M1.

[0077] A terminal is led out at the connection point between one pole of the first capacitor C1 and the gate of the NMOS transistor M1, serving as the input terminal of the voltage holding unit 30, for connecting to the second terminal of the first switching unit K1.

[0078] The other terminal of the first capacitor C1 is grounded, the drain of the NMOS transistor M1 is connected to the output terminal of the charge pump 10, and the source of the NMOS transistor M1 is connected to the DNW array 40.

[0079] During the one-time period when the first switching unit K1 and the second switching unit K2 are off, there will be a very small turn-off current at the gate of the NMOS transistor M1. The first capacitor C1 can ensure that the voltage at point A will not be too low during the one-time period when the first switching unit K1 and the second switching unit K2 are off, and will remain within a reasonable range.

[0080] In some scenarios, the voltage at the output of the charge pump 10 may exceed the first target voltage range corresponding to the voltage holding unit 30. In this case, regarding how to achieve voltage divider regulation, this embodiment of the invention also provides an optional implementation method; please refer to [link / reference needed]. Figure 2 .

[0081] The voltage holding circuit also includes a first resistor R1, a second resistor R2, and a second switching unit K2.

[0082] One end of the first resistor R1 is connected to the second end of the first switching unit K1, the other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

[0083] One end of the second switching unit K2 is connected to the lead-out terminal between the first resistor R1 and the second resistor R2, and the other end of the second switching unit K2 is connected to the input terminal of the voltage holding unit 30.

[0084] The trigger unit 20 is connected to the control terminal of the second switch unit K2, and the trigger unit 20 is used to control the second switch unit K2 to maintain the same state as the first switch unit K1.

[0085] That is, when the first switch unit K1 is closed, the second switch unit K2 is also closed, and when the first switch unit K1 is open, the second switch unit K2 is also open.

[0086] Building upon the foregoing, this invention provides an optional implementation method to further prevent false triggering of the voltage holding function. Please refer to [link / reference needed]. Figure 3 , Figure 3 The third voltage holding circuit provided in the embodiments of the present invention.

[0087] The voltage holding unit 30 also includes a third switching unit K3.

[0088] The first terminal of the third switching unit K3 is connected to the output terminal of the charge pump 10, and the second terminal of the third switching unit K3 is connected to the drain of the NMOS transistor M1.

[0089] The control terminal of the third switch unit K3 can be connected to the trigger unit 20 or other control units. Under the control of the trigger unit 20 or other control units, the third switch unit K3 can switch states.

[0090] When the electronic device with the voltage holding circuit is in standby mode, the third switch unit K3 is in the closed state.

[0091] When the electronic device is in working mode, the third switching unit K3 is in the off state.

[0092] This invention also provides a system-on-a-chip, which includes a memory and the voltage holding circuit described above.

[0093] This invention also provides an electronic device that includes the aforementioned system-on-a-chip. The electronic device may be, but is not limited to, portable sensing devices, mobile phones, computers, and server devices, etc.

[0094] In summary, the present invention provides a voltage holding circuit and a system-on-a-chip. The voltage holding circuit includes a charge pump, a trigger unit, a first switching unit, and a voltage holding unit. The trigger unit is connected to the control terminals of the charge pump and the first switching unit. The first terminal of the first switching unit is connected to the output terminal of the charge pump, and the second terminal of the first switching unit is connected to the voltage holding unit. The voltage holding unit is also used to connect to a DNW array of memory. By controlling the charge pump to operate or rest, the input voltage of the voltage holding unit is kept within a first target voltage range, thereby keeping the voltage of the parasitic capacitance of the DNW array within a second target voltage range. When memory read / write operations are required, the power supply voltage of the electronic device can quickly boost the memory to its operating voltage, thereby quickly responding to memory read / write operations and ensuring low power consumption in standby mode.

[0095] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0096] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A voltage holding circuit, characterized in that, The voltage holding circuit includes a charge pump, a trigger unit, a first switching unit, and a voltage holding unit; The triggering unit is connected to the control terminals of the charge pump and the first switching unit, respectively. The first terminal of the first switching unit is connected to the output terminal of the charge pump, and the second terminal of the first switching unit is connected to the voltage holding unit; The voltage holding unit is also used to connect to the DNW array of the memory; The voltage holding unit includes a first capacitor and an NMOS transistor; At the connection point between one pole of the first capacitor and the gate of the NMOS transistor, a terminal is led out as the input terminal of the voltage holding unit, which is used to connect to the second terminal of the first switching unit; The other terminal of the first capacitor is grounded, the drain of the NMOS transistor is connected to the output terminal of the charge pump, and the source of the NMOS transistor is connected to the DNW array. The voltage holding circuit further includes a first resistor, a second resistor, and a second switching unit; One end of the first resistor is connected to the second end of the first switching unit, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is grounded; One end of the second switching unit is connected to a terminal block between the first resistor and the second resistor, and the other end of the second switching unit is connected to the input terminal of the voltage holding unit. The triggering unit is connected to the control terminal of the second switching unit, and the triggering unit is used to control the state of the second switching unit to be consistent with that of the first switching unit.

2. The voltage holding circuit as described in claim 1, characterized in that, The triggering unit is used to send a start signal to the charge pump when the first triggering condition is met, and control the first switching unit to switch to the closed state so that the charge pump charges the voltage holding unit and keeps the input voltage of the voltage holding unit within the first target voltage range. The triggering unit is used to send a rest signal to the charge pump and control the first switching unit to switch to the off state when the second triggering condition is met. The voltage holding unit is used to charge the DNW array so that the voltage of the parasitic capacitance of the DNW array is maintained within the second target voltage range.

3. The voltage holding circuit as described in claim 2, characterized in that, The first trigger condition being met indicates that the input voltage of the voltage holding unit has dropped to a third voltage threshold, which is the lower limit of the first target voltage range; The second trigger condition being met indicates that the input voltage of the voltage holding unit rises to the fourth voltage threshold, which is the upper limit of the first target voltage range.

4. The voltage holding circuit as described in claim 2, characterized in that, The triggering unit is used to detect the current voltage at the output terminal of the charge pump; The triggering unit is used to determine that the first triggering condition is met when the current voltage is lower than the first voltage threshold. The triggering unit is used to determine that the second triggering condition is met when the current voltage reaches the second voltage threshold.

5. The voltage holding circuit as described in claim 2, characterized in that, The triggering unit is used to record the start-up interval of the charge pump. When the start-up interval is equal to a first time threshold, the first triggering condition is determined to be met. The triggering unit is used to record the continuous start-up duration of the charge pump. When the continuous start-up duration is equal to the second time threshold, it is determined that the second triggering condition is met. Wherein, the start-up interval duration represents the time between the last time the charge pump entered the rest state and the current time, and the continuous start-up duration represents the time between the last time the charge pump entered the start-up state and the current time.

6. The voltage holding circuit as described in claim 1, characterized in that, The voltage holding unit also includes a third switching unit; The first end of the third switching unit is connected to the output end of the charge pump, and the second end of the third switching unit is connected to the drain of the NMOS transistor.

7. The voltage holding circuit as described in claim 6, characterized in that, When the electronic device in which the voltage holding circuit is deployed is in standby mode, the third switching unit is in a closed state; When the electronic device is in working mode, the third switching unit is in the off state.

8. A system-on-a-chip, characterized in that, The system-on-chip includes a memory and a voltage holding circuit according to any one of claims 1-7.

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