Flash memory testing method

Abstract

The invention discloses a flash memory test method, which comprises the following steps: providing a flash memory, and performing enhanced erasure on a memory unit of the flash memory, namely applying enhanced erasure voltage VEE'greater than normal erasure voltage VEE on a word line of the memory unit to erase the memory unit; after erasing is completed, performing a 1 writing operation test on each storage unit of the flash memory; and if the '1' writing operation of a storage unit fails, removing the flash memory. By utilizing the scheme of the invention, the defective flash memory can be fully screened out in the yield test stage, so that the flash memory is prevented from flowing to the terminal user, and the reliability risk of causing the terminal failure is reduced. Moreover, through the test, the reliability of the flash memory can be further improved, and the user mode use failure of the flash memory terminal is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit manufacturing, and in particular to a flash memory testing method. Background Art

[0002] As a non-volatile memory, flash memory devices are widely used due to their convenience, high storage density, and high reliability. Existing flash memory devices are classified into split-gate structures, stacked-gate structures, or a combination thereof according to different cell structures. Among them, split-gate flash memory devices have the characteristics of high programming efficiency and no over-erasure effect, so they are widely used.

[0003] During the manufacturing process of split-gate flash memory, some memory cells may have abnormal morphology due to process environment defects. Figure 1 As shown, during the process of a split-gate flash memory, due to defects in the process environment, some storage cells will have abnormal morphology. The storage structure on the left side of the groove 10 includes a first floating gate 11 and a first word line 21, and the storage structure on the right side of the groove 10 includes a second floating gate 12 and a second word line 22. The first floating gate 11 has a normal morphology, and the position of the first floating gate 11 facing the first word line 21 has a sharp corner, and a longitudinal gap is formed between the first floating gate 11 and the first word line 21 from the sharp corner downward. A bit line is formed in the groove 10. The second floating gate 12 (in the red oval) has an abnormal morphology, and the position of the second floating gate 12 facing the second word line 22 has a sharp corner shape, but extends from the sharp corner to the inside of the second word line 22, and does not form the required longitudinal spacing with the second word line 22, but forms a lateral spacing.

[0004] Normally, such defective memory cells will be screened out and repaired during the chip erase / read function test process during the yield test, and can be shipped and used normally. Although the defective memory cell is repaired during the yield test, other rows in the storage array still share the bit line with the defective memory cell and are not completely independent. Although it is shipped as a normal sample and put on the terminal market, due to the different shapes and sizes of the defects, during the continuous use of the end user, the bit line of the defective memory cell has leakage due to this defect, causing the entire column of memory cells to fail when writing "1", which then becomes a terminal failure event. Summary of the invention

[0005] The embodiment of the present application provides a flash memory testing method to screen out flash memory with bit line and floating gate channel leakage defects during the yield testing stage to prevent it from being distributed to end users.

[0006] The present invention provides a flash memory testing method, the method comprising:

[0007] A flash memory is provided, the flash memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells arranged in a matrix, the memory cells being split-gate flash memory cells; each of the memory cells comprising a floating gate and a bit line; the memory cells in each column share the bit line;

[0008] Performing enhanced erasure on the storage cell of the flash memory, wherein the enhanced erasure refers to applying an enhanced erasure voltage VEE′ greater than a normal erasure voltage VEE on a word line of the storage cell to erase the storage cell;

[0009] After erasing is completed, a write "1" operation test is performed on each storage unit of the flash memory;

[0010] If a write "1" operation of a storage unit fails, the flash memory is discarded.

[0011] Optionally, 1.01VEE≤VEE′≤1.08VEE.

[0012] Optionally, a write "1" operation test is performed on the flash memory multiple times.

[0013] Optionally, the writing "1" operation test on the flash memory includes:

[0014] Applying voltages corresponding to a write "1" operation to the source region, the bit line, and the word line of the memory cell respectively;

[0015] Then, a read operation is performed on the storage unit to determine whether the storage bit state remains at "1";

[0016] If the storage bit state of a storage unit is "0", it is determined that the writing "1" operation of the storage unit fails.

[0017] Optionally, the voltage corresponding to the write “1” operation includes: source region voltage V S is 8.2V, the bit line voltage V B is 2.5V, the word line voltage V W is 1.6V.

[0018] Optionally, the method further comprises:

[0019] Before performing enhanced erasure on the storage unit of the flash memory, a first test is performed on the flash memory; the first test is a pre-baking test.

[0020] If the first test passes, a second test is performed, wherein the second test refers to a test after baking, and the second test at least includes a data retention capability test;

[0021] After the data retention capability test is passed, the step of performing enhanced erasing on the storage unit of the flash memory is performed.

[0022] Optionally, the split-gate flash memory unit includes two storage structures that share a common source region and are symmetrically distributed; the storage structure includes a drain region and the source region located in a substrate, the drain region is connected to the bit line, the floating gate and the word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on the side of the floating gate close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

[0023] Optionally, the method further comprises: if a plurality of storage cells in the same column fail to write "1" operations, determining that the storage cells have a problem of leakage of the bit line and the floating gate channel.

[0024] Alternatively, there is a problem of bit line and floating gate channel leakage caused by an abnormal floating gate.

[0025] Optionally, the abnormal floating gate includes: a situation where a required floating gate tip is not formed on a side of the floating gate close to the word line.

[0026] The flash memory testing method provided in the embodiment of the present application performs enhanced erasure on the flash memory in the CP test stage to increase the word line channel leakage of the storage unit with bit line and floating gate channel leakage problems, and then performs a write "1" operation test on the erased storage unit. If the write "1" operation of a storage unit fails, it indicates that the flash memory has potential defects, and it is thus eliminated. Using the scheme of the present application, defective flash memories can be fully screened out in the yield test stage to prevent them from flowing to end users, thereby reducing the reliability risk of causing terminal failure. Moreover, through this test, the reliability of the flash memory can be further improved to avoid failure of the flash memory in terminal user mode.

[0027] Furthermore, when performing a write "1" operation test, the problem and the flash memory defect corresponding to the problem can be roughly determined based on the distribution of write "1" operation failures. For example, if the write "1" operation fails for multiple storage cells in the same column, it can be determined that the storage cells in this column have a bit line and floating gate channel leakage problem, and this problem is usually caused by an abnormal floating gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of a split-gate flash memory having an unusual morphology;

[0029] Figure 2 This is a schematic diagram of the situation where a sector is judged as a failed sector during chip erase test;

[0030] Figure 3 It is a schematic diagram of the situation that the failed cells are gradually fully erased when erasing all sectors;

[0031] Figure 4is a flow chart of a flash memory testing method provided in an embodiment of the present application;

[0032] Figure 5 is a schematic diagram of a flash memory according to an embodiment of the present application;

[0033] Figure 6 It is a schematic diagram of the principle of the flash memory of the embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned purposes, features and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0035] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present application. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0036] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0037] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0038] CP (Chip Pobing) is for uncut wafers. It is necessary to use probes to contact the test pads on the wafer. One or more dies on the wafer can be tested at one time. CP testing generally includes three stages of testing, namely: CP1 tests the basic storage read and write functions and writes certain content into the storage chip; then the wafer is baked at high temperature and then CP2 is tested to detect whether the previously written data can be retained; finally, the CPE test of the logic function of the MCU (main control unit) is performed.

[0039] The CP1 test process mainly includes the following steps:

[0040] (1) Open / short test and leakage test

[0041] Among them, the open-short circuit test is mainly used to find out whether there is a short circuit between the pins of the chip, and whether there is a lack of bonding wires when the chip is packaged; the leakage current test is to detect the leakage current of the chip's input pins when voltage is applied.

[0042] (2) Chip erase / read function test

[0043] This test is mainly used to screen out chips that cannot complete basic erase, program, read and write operations. During the test, the chip performs erase and program operations on a single sector or the entire flash array at different operating voltages, and then reads the chip to determine whether it can pass the test.

[0044] In this process, the sectors where the failed cells with abnormal floating gate morphology are located will be judged as failed sectors during the chip erase test and counted as sectors to be repaired. Figure 2 shown.

[0045] (3) Programming crosstalk test

[0046] The crosstalk test simulates the stress condition of unselected cells during programming to detect whether their erased state is changed by accidental programming.

[0047] (4) Write the flag to NVR1 and erase the chip

[0048] In this process, all sectors will be erased, that is, the sectors counted as sectors to be repaired in the detection process of step (2) above will also be erased. During erasing, the high electric field between the word line and the floating gate induces the FN electron tunneling effect, causing electrons to be pulled out of the floating gate, such as Figure 3 This means that the above-mentioned failed cells will be gradually erased sufficiently, and the word line channel threshold voltage will become lower.

[0049] Through the above-mentioned erasing operation, the above-mentioned sectors to be repaired may be repaired and shipped as normal samples. However, due to the different shapes and sizes of defects, during the continuous use of the end user, the bit line of the defective storage unit may leak electricity, causing the entire column of storage units to fail when writing "1". This problem poses a great potential risk to terminal applications with high reliability requirements such as automotive applications.

[0050] The CP2 test is mainly to perform functional tests on the baked chip to detect its data retention ability. Generally, the CP2 test process mainly includes the following steps:

[0051] (1) Open / short test and leakage test

[0052] Similar to the corresponding steps in the CP1 test, the open-short circuit test is mainly used to find out whether there is a short circuit between the pins of the chip and whether there is a lack of bonding wires when the chip is packaged; the leakage current test is to detect the leakage current of the chip's input pins when voltage is applied.

[0053] (2) NVR1 verification

[0054] Used to verify that the flags written to NVR1 during the CP1 test are correct.

[0055] (3) Data retention and durability testing

[0056] Data retention refers to the ability of a memory cell to maintain its programmed state for an acceptable period of time.

[0057] The endurance test is to characterize the maximum number of P / E cycles that a memory cell can undergo without failure.

[0058] It should be noted that the above-mentioned test items and processes of CP1 and CP2 are just some conventional test items and processes. Depending on different manufacturers and products, there may be other test items and different test processes in the CP test phase, which is not limited in the embodiments of the present application.

[0059] In view of the problem that the bit lines of the storage cells of the sectors repaired in the CP1 test phase may have leakage, which may cause the entire column of storage cells to fail during the write "1" operation, an embodiment of the present application provides a flash memory testing method, which performs enhanced erasure on the flash memory before it flows into the end user, and after the enhanced erasure, performs a write "1" operation test on all storage cells to further screen out flash memory with certain defects to prevent it from flowing into the end user.

[0060] The flash memory testing method provided in the embodiment of the present application can be performed in the CP testing stage, and specifically can be performed in any stage after the above-mentioned CP2 data retention test.

[0061] It should be noted that for different types of flash memory produced by different manufacturers and the same manufacturer, the specific test items and processes of the first test (i.e., the CP1 test before baking) and the second test (i.e., the CP2 test after baking) may be different, and this embodiment of the application does not limit this.

[0062] For example, in a non-limiting embodiment, after providing the flash memory, a first test is performed first. The first test includes at least a chip erase / read function test. After the test is completed, a flag is written to NVR1 and the chip is erased. After the first test passes, the wafer is sent to an oven for high-temperature baking, and then a second test is performed. The second test includes at least an open-short circuit test, a data retention capability test, and a data durability test. After the test passes, the enhanced erase operation in the embodiment of the present application is performed.

[0063] For example, in another non-limiting embodiment, after providing the flash memory, a first test is performed first. After the first test passes, the wafer is sent to an oven for high-temperature baking, and then a second test is performed. During the second test, an open-short circuit test, an NVR1 verification, and a data retention capability test are performed in sequence. After the test passes, the enhanced erase operation and write "1" operation test in the embodiment of the present application are performed. After the test passes, a data durability test is performed.

[0064] like Figure 4 The figure shows a flow chart of a flash memory testing method provided in an embodiment of the present application.

[0065] The following is combined with Figure 5 and Figure 6 The execution process and principle of the flash memory testing method according to the embodiment of the present application are described in detail, wherein: Figure 5 is a schematic diagram of a flash memory according to an embodiment of the present application, Figure 6 It is a schematic diagram of the principle of the flash memory of the embodiment of the present application.

[0066] In step 401, a flash memory is provided, wherein the flash memory includes a memory cell array, wherein the memory cell array includes a plurality of memory cells arranged in a matrix, wherein the memory cells are split-gate flash memory cells; each of the memory cells includes a floating gate and a bit line; and the memory cells in each column share the bit line.

[0067] like Figure 5 and Figure 6 As shown, the flash memory includes a memory cell array, the memory cell array includes a plurality of memory cells A arranged in a matrix, and the memory cells are split-gate flash memory cells; each memory cell includes a floating gate 11 and a bit line 13; each column of memory cells shares a bit line 13. A plurality of split-gate flash memory cells arranged in parallel are formed on a semiconductor substrate. The material of the semiconductor substrate may be silicon, germanium, silicon germanium or silicon carbide, or may be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or may be other materials, such as III and V group compounds such as gallium arsenide.

[0068] In this embodiment, a split-gate flash memory unit includes two storage structures that share a source region 14 and are symmetrically distributed. Each split-gate flash memory unit includes a drain region 15 formed in a semiconductor substrate, a source region 14, and a source line (not shown) connected to the source region 14 formed on the semiconductor substrate, and the source line is located above the source region 14. Among them, the drain region 15 is connected to the bit line 13, and a word line 21 is formed between the source region 14 and the drain region 15. The two word lines 21 of the same split-gate flash memory unit are formed on both sides of the corresponding source line. A floating gate oxide layer, a floating gate 11, and a sidewall are formed on the semiconductor substrate between the source line and the word line 21, and a tunneling oxide layer is formed between the floating gate 11 and the word line 21. The material of the floating gate 11, the word line 21, and the source line can all be polysilicon. A floating gate tip is formed on the side of the floating gate 11 close to the word line 21. The storage structure on the left and the storage structure on the right are symmetrically distributed and share a source line. In this embodiment, the source region 14 and the drain region 15 are, for example, both N-type doped.

[0069] When programming the split-gate flash memory cell, the word line 21 serves as a control gate, a high voltage is applied to the source region 14, a voltage that can open the channel is applied to the word line 21, and a constant current is injected through the drain region 15. The source region 14 is at a high potential. Under the action of the high potential, on the one hand, hot electrons are generated in the channel, and on the other hand, the high potential is coupled to the floating gate 11, and the floating gate 11 generates a coupling voltage. Under the action of the coupling voltage, electrons are injected from the channel to the floating gate 11, thereby realizing programming. Programming is also called a write "0" operation.

[0070] In step 402, the memory cell of the flash memory is enhanced erased, wherein the enhanced erased refers to applying an enhanced erase voltage VEE′ greater than a normal erase voltage VEE to a word line of the memory cell to erase the memory cell.

[0071] The enhanced erasure voltage VEE′ is greater than the normal erasure voltage VEE. For example, in some embodiments, the enhanced erasure voltage VEE′ may satisfy the following condition: 1.01VEE≤VEE′≤1.08VEE.

[0072] For example, in a conventional CP test, the normal erase voltage VEE applied to the word line is 12V, and in the above-mentioned enhanced erase test, a high voltage of 12.5V is applied to the word line.

[0073] Also refer to Figure 5 and Figure 6 When the split-gate flash memory cell is enhanced erased, an enhanced erase voltage VEE' is applied to all word lines, and the tip of the floating gate reduces the channel voltage of the tunneling effect through the tip discharge principle, so that electrons can pass through the tunneling oxide layer from the tip of the floating gate 11 to the word line 21. After the memory cell is erased, the storage bit of the memory cell is in the "1" state; that is, all the memory cells of the flash memory are erased and set to "1".

[0074] Step 403, after erasing is completed, a write "1" operation test is performed on each storage unit of the flash memory.

[0075] If the write "1" operation of a storage unit fails, step 404 is executed to remove the flash memory; otherwise, the test passes and the test ends.

[0076] For flash memory, programming is also called writing "0" operation. Through programming, the state of the storage cell can be changed from "1" to "0". Specifically, by applying programming voltage to several storage cells that need to be programmed, the electrons of the corresponding storage cells enter the floating gate from the substrate channel to complete the programming. After programming, the state of the storage cell is "0".

[0077] In the embodiment of the present application, the write "1" operation refers to maintaining the storage bit of the memory cell in the "1" state after erasure. The principle is to apply a voltage to the memory cell that does not need to be programmed, so that the memory cell does not meet the programming conditions, the voltage of the channel is not turned on, and the electrons of the corresponding memory cell will not enter the floating gate 11 from the substrate, and the state of the memory cell is "1".

[0078] In the embodiment of the present application, the voltage corresponding to the write "1" operation is applied to the source region, the bit line, and the word line of the memory cell respectively. Exemplarily, the voltage application condition for the write "1" operation may include: the source region voltage V S is 8.2V, the bit line voltage V B is 2.5V, the word line voltage V W is 1.6 V. Then, a read operation is performed on the storage unit to determine whether the storage bit state is maintained as "1". If the storage bit state of a storage unit is "0", it is determined that the write "1" operation of the storage unit is invalid.

[0079] Step 404: remove the flash memory.

[0080] The following further combines Figure 5 and Figure 6 The principle of using the method of the present application to screen memory cells with bit line and floating gate channel leakage is described.

[0081] Reference Figure 5 and Figure 6 , the memory cell array includes a number of memory cells A arranged in a matrix. Assume that the floating gate of memory cell B is abnormal, for example, Figure 1 The abnormal situation shown.

[0082] When the memory cell B is first used, the source voltage V S and the bit line voltage V BThe voltage difference is smaller than the channel opening voltage, and the corresponding electrons of the memory cell will not enter the floating gate 11 from the substrate, and the storage bit of the memory cell is always in the "1" state.

[0083] During continuous use, the bit line 13 where the memory cell B is located leaks electricity, resulting in a suppression voltage, i.e., the bit line voltage V B is pulled low, and accordingly, the source voltage V S and the bit line voltage V B The voltage difference increases, when the source voltage V S and the bit line voltage V B When the voltage difference is greater than the channel turn-on voltage, electrons will enter the respective floating gates 11 from the substrate in the entire column of storage cells on the corresponding bit line 13, and then the entire column of storage cells will be programmed to "0", that is, the storage bit state of the entire column of storage cells will change from "1" to "0".

[0084] Therefore, the memory cell B with a floating gate defect will fail to write "1" in subsequent use due to leakage between the bit line 13 and the floating gate, and cannot be used normally.

[0085] By using the scheme of the present application, an enhanced erase voltage VEE′ is applied to all word lines. Since the enhanced erase voltage VEE′ is greater than the voltage VEE applied to the word line during the conventional erase test, the electrons in the floating gate 11 can pass through the tunneling oxide layer to enter the word line 21 as much as possible, thereby increasing the word line channel leakage of the storage unit with bit line and floating gate channel leakage problems.

[0086] For the flash memory that passes the above test, continue to perform the write "1" operation test. If the memory cell B has bit line and floating gate channel leakage defects, the storage bit of the memory cells in the entire column where the memory cell B is located cannot be maintained in the "1" state, that is, the corresponding entire column or most of the memory cells in the column fail to write "1", and the memory cells in the entire column where the memory cell B is located can be screened out to prevent them from flowing into the end user and bringing potential risks to the end user's application.

[0087] It should be noted that when performing the write "1" operation test, if one or a few storage units fail to write the "1" operation, it may be caused by other reasons. For this type of flash memory, the present application solution can also eliminate it in the yield testing stage, thereby fully ensuring the quality of the flash memory flowing to the end user.

[0088] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0089] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0090] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0091] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0092] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A flash memory testing method, characterized in that: The method comprises: A flash memory is provided, the flash memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells arranged in a matrix, the memory cells being split-gate flash memory cells; each of the memory cells comprising a floating gate and a bit line; the memory cells in each column share the bit line; Performing enhanced erasure on the storage cell of the flash memory, wherein the enhanced erasure refers to applying an enhanced erasure voltage VEE′ greater than a normal erasure voltage VEE on a word line of the storage cell to erase the storage cell; After erasing is completed, a write "1" operation test is performed on each storage unit of the flash memory; If a write "1" operation of a storage unit fails, the flash memory is discarded.

2. The flash memory testing method according to claim 1, characterized in that: 1.01VEE≤VEE′≤1.08VEE.

3. The flash memory testing method according to claim 1, characterized in that: Perform multiple write "1" operation tests on the flash memory.

4. The flash memory testing method according to claim 1, characterized in that: The writing "1" operation test on the flash memory comprises: Applying voltages corresponding to a write "1" operation to the source region, the bit line, and the word line of the memory cell respectively; Then, a read operation is performed on the storage unit to determine whether the storage bit state is maintained as "1"; If the storage bit state of a storage unit is "0", it is determined that the write "1" operation of the storage unit fails.

5. The flash memory testing method according to claim 4, characterized in that: The voltages corresponding to the write "1" operation include: source voltage V S is 8.2V, the bit line voltage V B is 2.5V, the word line voltage V W is 1.6V.

6. The flash memory testing method according to claim 1, characterized in that: The method further comprises: Before performing enhanced erasure on the storage unit of the flash memory, a first test is performed on the flash memory; the first test is a pre-baking test. If the first test passes, a second test is performed, wherein the second test refers to a test after baking, and the second test at least includes a data retention capability test; After the data retention capability test is passed, the step of performing enhanced erasing on the storage unit of the flash memory is performed.

7. The flash memory testing method according to any one of claims 1 to 6, characterized in that: The split-gate flash memory unit includes two storage structures that share a source region and are symmetrically distributed; the storage structure includes a drain region and the source region located in a substrate, the drain region is connected to the bit line, the floating gate and the word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on the side of the floating gate close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

8. The flash memory testing method according to claim 7, characterized in that: The method further comprises: If the write “1” operation fails in multiple memory cells in the same column, it is determined that the memory cells have leakage problems between the bit lines and the floating gate channels.

9. The flash memory testing method according to claim 8, characterized in that: There are problems with bit line and floating gate channel leakage caused by abnormal floating gate.

10. The flash memory testing method according to claim 9, characterized in that: The abnormal floating gate includes a situation where a required floating gate tip is not formed on a side of the floating gate close to the word line.

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