Focusing Ring and Its Preparation Method

Abstract

This application relates to a focusing ring and a preparation method thereof. The focusing ring includes: a first semiconductor material layer, the first semiconductor material layer includes a lower surface for contacting an electrostatic chuck and an upper surface facing an upper electrode and a wafer to be processed. The upper surface of the first semiconductor material layer includes a first surface and a second surface. The first surface is perpendicular to the thickness direction of the first semiconductor material layer. The distance between each position from the outside to the inside along the radial direction of the focusing ring in the second surface and the lower surface gradually decreases; a second semiconductor material layer, which is formed on the upper surface of the first semiconductor material layer by an epitaxial growth process. The crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface, and the second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer. Thus, the non-uniform deformation of the focusing ring is avoided from affecting the electric field at the edge of the wafer, and finally the non-uniform etching at the edge position of the wafer is avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a focus ring and a method for manufacturing the same. Background Art

[0002] The plasma etching process is one of the key processes in wafer processing. In a plasma etching chamber, a wafer is fixed by an electrostatic chuck, and under the action of an electric field between an upper electrode and a lower electrode, a specific structure is etched on the surface of the wafer. Currently, in this field, the diameter of the electrostatic chuck is usually set slightly smaller than the diameter of the wafer, and a focus ring is provided on the outer periphery of the electrostatic chuck to prevent the plasma from eroding the electrostatic chuck and ensure the electric field balance.

[0003] During actual use, the surface of the focus ring exposed to the plasma environment will also be etched by the plasma. As the loss degree of the focus ring deepens, the acting force of its balanced electric field gradually weakens. Moreover, the etching degree of each part of the focus ring surface is different, which makes the change degree of the electric field acting force of each part of the focus ring different, and the electric field at the edge position of the wafer is prone to distortion, resulting in uneven etching at the edge position of the wafer and even introducing other risks. Summary of the Invention

[0004] In view of this, embodiments of this application provide a focus ring and a method for manufacturing the same to solve the problems in the background art.

[0005] In a first aspect, embodiments of this application provide a focus ring applied to a semiconductor etching device. The semiconductor etching device includes an electrostatic chuck serving as a lower electrode and carrying a wafer to be processed, and an upper electrode corresponding to the electrostatic chuck. The focus ring is disposed on the outer periphery of the electrostatic chuck, and the focus ring includes:

[0006] A first semiconductor material layer, the first semiconductor material layer including a lower surface for contacting the electrostatic chuck and an upper surface facing the upper electrode and the wafer to be processed. The upper surface of the first semiconductor material layer includes a first surface and a second surface. The first surface is perpendicular to the thickness direction of the first semiconductor material layer, and the distance between each position of the second surface along the radial direction of the focus ring from the outside to the inside and the lower surface gradually decreases;

[0007] A second semiconductor material layer, formed on the upper surface of the first semiconductor material layer by an epitaxial growth process. The crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface, and the second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer.

[0008] In the above technical solution, a homogeneous epitaxial layer, i.e., a second semiconductor material layer, is epitaxially grown on the upper surface of the first semiconductor material layer. At this time, the surface of the focusing ring is the surface of the second semiconductor material layer, and the crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface. Then, the crystal orientation of the grains on the surface of the focusing ring is perpendicular to the surface of the focusing ring, and the grain size is the diameter of the cross section of the grain, i.e., the grains are evenly arranged and have the same grain size at various locations on the surface of the focusing ring. Thus, without changing the material of the focusing ring, the arrangement uniformity and grain size consistency of the grains on the surface of the focusing ring are improved, avoiding the problem of uneven arrangement and inconsistent grain size of grains at various locations on the surface when only the first semiconductor material layer is used as the focusing ring in the related art, thereby avoiding different etching consumption in actual use, and keeping the electric field at the edge of the wafer balanced to prevent uneven etching at the edge of the wafer.

[0009] In combination with the first aspect of the present application, in an optional implementation, the resistivity of the second semiconductor material layer is less than the resistivity of the first semiconductor material layer.

[0010] In the above technical solution, the resistivity of the second semiconductor material layer is lower than that of the first semiconductor material layer, and the conductivity of the second semiconductor material layer is better. In actual use, it is helpful to avoid the accumulation of charge on the surface of the focusing ring and reduce the risk of arcing.

[0011] In combination with the first aspect of the present application, in an optional embodiment, the thickness of the second semiconductor material layer is 5%-10% of the thickness of the focusing ring; wherein the thickness of the focusing ring is the sum of the thickness of the first semiconductor material layer and the thickness of the second semiconductor material layer, and the thickness of the first semiconductor material layer is the maximum value of the distance between the upper surface and the lower surface.

[0012] In the above technical solution, the thickness of the second semiconductor material layer is controlled to be 5%-10% of the thickness of the focusing ring. Within this range, the uniformity of grain arrangement and particle size consistency in the second semiconductor material layer are better, and the bonding with the first semiconductor material layer is better and is not easy to fall off.

[0013] In a second aspect, an embodiment of the present application provides a method for preparing a focusing ring, wherein the focusing ring is applied to a semiconductor etching device, wherein the semiconductor etching device includes an electrostatic chuck as a lower electrode and carrying a wafer to be processed, and an upper electrode arranged corresponding to the electrostatic chuck, wherein the focusing ring is arranged at the periphery of the electrostatic chuck, and the method includes:

[0014] providing a substrate;

[0015] Growing a layer of material to be processed on the surface of the substrate;

[0016] removing the substrate;

[0017] Remove a part of the to-be-processed material layer from the side of the to-be-processed material layer facing the substrate to form a first semiconductor material layer. The first semiconductor material layer is annular. The first semiconductor material layer includes a lower surface for contacting the electrostatic chuck and an upper surface facing the upper electrode and the to-be-processed wafer. The upper surface of the first semiconductor material layer includes a first surface and a second surface. The first surface is perpendicular to the thickness direction of the first semiconductor material layer. The distance between each position of the second surface from the outside to the inside along the radial direction of the first semiconductor material layer and the lower surface gradually decreases.

[0018] Epitaxially grow a second semiconductor material layer on the upper surface of the first semiconductor material layer to form a focusing ring. The crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface. The second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer.

[0019] In the above technical solution, by epitaxially growing a homoepitaxial layer, that is, a second semiconductor material layer, on the upper surface of the first semiconductor material layer, at this time, the surface of the focusing ring is the surface of the second semiconductor material layer. The crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface, so the crystal orientation of the grains at the surface of the focusing ring is perpendicular to the surface of the focusing ring, and the grain size of each grain is the diameter of the cross-section of the grain, that is, the arrangement of the grains at each position on the surface of the focusing ring is uniform and the grain size is consistent. Without changing the material of the focusing ring, the uniformity of the grain arrangement and the consistency of the grain size on the surface of the focusing ring are improved, avoiding the problem that the arrangement of the grains at each surface is uneven and the grain size is inconsistent as in the related art when only the first semiconductor material layer is used as the focusing ring. Subsequently, it can be avoided that different etching consumptions appear during actual use, the electric field at the edge of the wafer can be kept balanced, and the uneven etching at the edge position of the wafer can be prevented.

[0020] Combined with the second aspect of the present application, in an alternative embodiment, the growth conditions for growing the to-be-processed material layer include a first growth temperature; the growth conditions for growing the second semiconductor material layer include a second growth temperature; wherein, the second growth temperature is less than the first growth temperature.

[0021] In the above technical solution, controlling the growth temperature of the second semiconductor material layer to be less than the growth temperature of the first semiconductor material layer makes the grain size of the grown second semiconductor material layer smaller and the crystallinity better, which is beneficial to ensuring the uniformity of the grain arrangement and the consistency of the grain size at each position on the surface of the second semiconductor material layer, and is more beneficial to resisting etching damage and maintaining the electric field balance during actual use.

[0022] In combination with the second aspect of the present application, in an optional embodiment, the growth conditions for growing the material layer to be processed include a first growth pressure; the growth conditions for growing the second semiconductor material layer include a second growth pressure; wherein the second growth pressure is less than the first growth pressure.

[0023] In the above technical scheme, the growth pressure of the second semiconductor material layer is controlled to be lower than the growth pressure of the first semiconductor material layer, so that the grain size of the grown second semiconductor material layer is smaller and the crystallinity is better, which is beneficial to ensuring the uniformity of grain arrangement and consistency of grain size at various locations on the surface of the second semiconductor material layer, and is more beneficial to resisting etching damage and maintaining electric field balance during actual use.

[0024] In combination with the second aspect of the present application, in an optional embodiment, the growth conditions for growing the material layer to be processed include introducing a first doping gas; the growth conditions for growing the second semiconductor material layer include introducing a second doping gas; wherein the content of nitrogen atoms in the total doping amount of the second doping gas is greater than the content of nitrogen atoms in the total doping amount of the first doping gas.

[0025] In the above technical solution, the content of nitrogen atoms in the total doping amount of the second doping gas is controlled to be greater than the content of nitrogen atoms in the total doping amount of the first doping gas, which means that in the process of growing the second semiconductor material layer, the content of nitrogen atoms in the growth chamber is higher, and the increase in the nitrogen atom content reduces the resistivity of the grown material layer, that is, the resistivity of the second semiconductor material layer is less than that of the first semiconductor material layer, and the conductivity of the second semiconductor material layer is better. Therefore, in actual use, it is helpful to avoid the accumulation of charges on the surface of the focusing ring and reduce the risk of arcing.

[0026] In conjunction with the second aspect of the present application, in an optional implementation, the amount of the second doping gas introduced is greater than the amount of the first doping gas introduced.

[0027] In the above technical solution, the amount of doping gas introduced is increased when preparing the second semiconductor material layer, which is beneficial to increase the content of nitrogen atoms in the growth chamber, and then make the resistivity of the second semiconductor material layer smaller than the resistivity of the first semiconductor material layer, so as to avoid charge accumulation on the surface of the focusing ring and reduce the risk of arcing.

[0028] In conjunction with the second aspect of the present application, in an optional implementation, the nitrogen atomic composition of the second doping gas is greater than the nitrogen atomic composition of the first doping gas.

[0029] In the above technical solution, when growing the second semiconductor material layer, a doping gas different from that for growing the first semiconductor material layer is selected. The nitrogen atom component in the second doping gas is higher, so that the content of nitrogen atoms in the growth chamber increases, and then the resistivity of the second semiconductor material layer is made smaller than that of the first semiconductor material layer, so as to avoid charge accumulation on the surface of the focusing ring and reduce the risk of arcing.

[0030] In conjunction with the second aspect of the present application, in an optional implementation, before epitaxially growing the second semiconductor material layer on the upper surface of the first semiconductor material layer, the preparation method further includes: placing the first semiconductor material layer in a carrier, the carrier covering other surfaces of the first semiconductor material layer except the upper surface;

[0031] After epitaxially growing the second semiconductor material layer on the upper surface of the first semiconductor material layer, the preparation method further includes: removing the carrier.

[0032] In the above technical solution, before epitaxial growth, the first semiconductor material layer is placed in a carrier, and the carrier covers other surfaces except the upper surface, thereby preventing the second semiconductor material layer from growing on other surfaces of the first semiconductor material layer.

[0033] The focusing ring and the preparation method thereof provided in the embodiments of the present application have at least the following beneficial effects:

[0034] By epitaxially growing a homogeneous epitaxial layer, i.e., a second semiconductor material layer, on the upper surface of the first semiconductor material layer, the surface of the focusing ring is the surface of the second semiconductor material layer, and the crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface, then the crystal orientation of the grains on the surface of the focusing ring is perpendicular to the surface of the focusing ring, and the grain size is the diameter of the cross section of the grain, i.e., the arrangement of the grains on the surface of the focusing ring is uniform and the grain size is consistent. Thus, without changing the material of the focusing ring, the arrangement uniformity and grain size consistency of the grains on the surface of the focusing ring are improved, avoiding the problem of uneven arrangement and inconsistent grain size of the grains on the surface when only the first semiconductor material layer is used as the focusing ring in the related art, thereby avoiding different etching consumption in actual use, and keeping the electric field at the edge of the wafer balanced, avoiding uneven etching at the edge of the wafer;

[0035] By setting the resistivity of the second semiconductor material layer to be lower than that of the first semiconductor material layer, the conductivity of the second semiconductor material layer is better, which is helpful to avoid the accumulation of charges on the surface of the focusing ring and reduce the risk of arcing in actual use;

[0036] By controlling the thickness of the second semiconductor material layer to be 5%-10% of the thickness of the focus ring, within this range, the process time is controllable, which avoids affecting the production efficiency. The uniformity of the grain arrangement and the consistency of the particle size in the second semiconductor material layer are better, and the bonding property with the first semiconductor material layer is better, and it is not easy to fall off.

[0037] Additional aspects and advantages of the present application will be given in part in the following description, will become apparent in part from the following description, or will be understood through the practice of the present application. Brief Description of the Drawings

[0038] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation of the present application. In the drawings:

[0039] Figure 1 It is a schematic installation diagram of the focus ring and the wafer to be processed in the plasma etching chamber;

[0040] Figures 2 to 3 It is a schematic cross-sectional structure diagram of the focus ring in the preparation process of the related art;

[0041] Figure 4 For Figure 2 The electron microscope image of the structure shown;

[0042] Figure 5 For Figure 4 The partial enlarged view of the part of silicon carbide close to the graphite substrate in the electron microscope image shown;

[0043] Figure 6 For Figure 4 The partial enlarged view of the part of silicon carbide far from the graphite substrate in the electron microscope image shown;

[0044] Figure 7 It is a schematic cross-sectional structure diagram of the focus ring after plasma etching in the related art;

[0045] Figure 8 It is a schematic cross-sectional structure diagram of the focus ring provided by an optional embodiment of the present application;

[0046] Figure 9 It is a schematic cross-sectional structure diagram of the focus ring provided by another optional embodiment of the present application;

[0047] Figure 10 It is a schematic cross-sectional structure diagram of the focus ring provided by yet another optional embodiment of the present application;

[0048] Figure 11 It is a schematic flow diagram of the preparation method of the focus ring provided by the embodiment of the present application;

[0049] Figures 12 to 13 A schematic diagram of the cross-sectional structure of a focusing ring during the preparation process provided in an optional embodiment of the present application.

[0050] Description of reference numerals:

[0051] 1. Electrostatic chuck; 2. Wafer to be processed; 3. Focus ring; 4. Substrate; 5. Carrier; 21. Attachment; 30. Material layer to be processed; 31. First material layer; 32. First semiconductor material layer; 33. Second semiconductor material layer; 301. Step surface; 302. Lower surface; 303. Upper surface; 304. Outer surface; 305. Inner surface; 311. First step surface; 312. Second step surface; 313. Third step surface; 321. First surface; 322. Second surface; 323. Third surface; 313a. Inner side of lower step surface; 313b. Outer side of lower step surface; 401. Growth surface. DETAILED DESCRIPTION

[0052] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0053] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0054] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0055] When an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. Although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of this application, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when referring to the second element, component, region, layer, or part, it does not imply that there must be a first element, component, region, layer, or part in this application.

[0056] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. In addition to the orientation shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0057] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of this application. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0058] To fully understand this application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions of this application. The preferred embodiments of this application are described in detail below. However, in addition to these detailed descriptions, this application may have other embodiments.

[0059] Figure 1 Fig. shows a schematic installation diagram of a focus ring and a wafer to be processed in a plasma etching chamber. In the plasma etching apparatus, there is an electrostatic chuck 1 serving as a lower electrode, which is also used to fix the wafer 2 to be processed thereon, so as to prevent the wafer 2 to be processed from shifting during the process. The electrostatic chuck 1 can be made of metal, such as aluminum, aluminum alloy, etc. Corresponding to the electrostatic chuck 1, the plasma etching apparatus further includes an upper electrode (not shown in the figure). A gap is formed between the upper electrode and the electrostatic chuck 1. After being conducted, an electric field is generated in the gap, and the plasma etches the surface of the wafer 2 to be processed under the action of the electric field.

[0060] The electrostatic chuck 1 is usually designed as a cylindrical boss. The upper half of the cylindrical boss is close to the wafer 2 to be processed. The diameter of the cross-section of the upper half of the cylindrical boss is smaller than the diameter of the cross-section of the lower half of the cylindrical boss, and the diameter of the cross-section of the upper half of the cylindrical boss is slightly smaller than the diameter of the wafer 2 to be processed, so as to prevent the plasma from eroding the electrostatic chuck 1 and causing contamination in the etching chamber. Thus, the wafer 2 to be processed extends beyond the contact surface with the electrostatic chuck 1, and the wafer edge is located outside the electrostatic chuck 1, resulting in different electric fields at the wafer edge and the center. To ensure the uniformity of the electric fields at the wafer edge and the center, a focus ring 3 is usually arranged at the wafer edge position in the art. Please refer to Figure 1 , and the focus ring 3 is arranged on the lower half of the electrostatic chuck 1, and it surrounds the upper half of the electrostatic chuck 1. Thus, not only can the electric field uniformity be adjusted, but also the lower half of the electrostatic chuck 1 can be prevented from being etched by the plasma.

[0061] It should be noted that although the embodiments of the present application are specifically described by taking the plasma etching apparatus as an example, the semiconductor etching apparatus in the present application does not exclude other etching apparatuses including the electrostatic chuck 1, the upper electrode, and the focus ring 3 as described above. It should be understood that in the semiconductor etching process, the surface exposed to the etching environment is usually eroded, and the focus ring provided by the present application can be applied to any semiconductor etching apparatus in need.

[0062] However, the surface of the focus ring 3 exposed to the plasma environment will also be eroded by the plasma. As the use time increases, the focus ring 3 is continuously etched and consumed by the plasma and deforms, and the acting force on the electric field also changes. And the degree of etching and consumption of each part of the focus ring 3 may be different, and its non-uniform deformation causes the electric field at the wafer edge to change unevenly, which exacerbates the adverse impact on the etching effect.

[0063] Please refer to Figure 2 and Figure 3, in the related art, after a layer of material to be processed 30 is grown on a substrate 4, the layer of material to be processed 30 is processed to obtain a first material layer 31 with a preset shape, and the first material layer 31 is directly used as the focus ring. Then, the stepped surface 301 of the first material layer 31 is the surface of the focus ring. The first material layer 31 is annular, and it includes a lower surface 302 and a stepped surface 301 facing the upper electrode and the wafer to be processed 2. The stepped surface 301 includes a first stepped surface 311 and a second stepped surface 312. The first stepped surface 311 is perpendicular to the thickness direction of the first material layer 31, and the distance between each position of the second stepped surface 312 along the radial direction of the first material layer 31 from the outside to the inside and the lower surface 302 gradually decreases. Herein, the layer of material to be processed 30 can be understood as a rectangular material layer.

[0064] The crystal orientation of the grains in the layer of material to be processed 30 is the thickness direction of the layer of material to be processed 30, and the crystal orientation of the grains in the first material layer 31 obtained by processing is the thickness direction of the first material layer 31. The first stepped surface 311 is perpendicular to the thickness direction of the first material layer 31, so the first stepped surface 311 is perpendicular to the crystal orientation. In other words, the crystal orientation of the grains at the first stepped surface 311 is perpendicular to the first stepped surface 311, and the particle size of the grains at the first stepped surface 311 can be understood as the diameter of the cross-section of the grains; while the distance between each position of the second stepped surface 312 along the radial direction of the first material layer 31 from the outside to the inside and the lower surface 302 gradually decreases, and the second stepped surface 312 is not perpendicular to the crystal orientation. In other words, the crystal orientation of the grains at the second stepped surface 312 is not perpendicular to the second stepped surface 312, and the particle size of the grains is not the diameter of the cross-section of the grains. Therefore, the arrangement and particle size of the grains shown at the second stepped surface 312 are different from those at the first stepped surface 311.

[0065] In some focus rings, the second stepped surface 312 is an inclined surface. Then, the particle size of the grains at the second stepped surface 312 can be understood as the diameter of the inclined cross-section of the grains, which is obviously larger than the diameter of the cross-section of the grains. Therefore, the particle size of the grains at the second stepped surface 312 is different from the particle size of the grains at the other two positions, and the grains at the second stepped surface 312 are not perpendicular to the second stepped surface 312, and the grain arrangement is uneven and not compact; in some other focus rings, the second stepped surface 312 is a vertical surface. Specifically, the direction where the second stepped surface 312 is located is the thickness direction of the first material layer 31. Then, the particle size of the grains in the surface layer on the side of the second stepped surface 312 can be understood as the diameter of the longitudinal cross-section of the grains. Therefore, the same conclusion as above can be obtained.

[0066] Such as Figure 3As shown, the stepped surface 301 of the first material layer 31 may further include a third stepped surface 313. The third stepped surface 313 is perpendicular to the thickness direction of the first material layer 31. The distance between the first stepped surface 311 and the lower surface 302 is different from the distance between the third stepped surface 313 and the lower surface 302.

[0067] It can be understood that according to crystallography theory, during crystal growth, atomic stacking will preferentially occur on the crystal plane with the lowest crystal plane energy, thereby obtaining a dense structure. When the material of the substrate 4 is graphite and the material of the material layer 30 to be processed is silicon carbide, when growing a silicon carbide material layer on a graphite substrate, the grain arrangement near the growth interface is uniform, dense, and the grain size is small. As the growth continues, the grains compete with each other for growth, the grain size has a certain tendency to increase, and it is easy to occur that the grain arrangement is not dense. Figures 4 to 6 , showing the distribution of grains in the silicon carbide material layer at a magnification of 200 and a scale of 200 μm; the silicon carbide material layer is mainly composed of columnar grains with the

[111] crystal orientation stacked, and the grains near the substrate are arranged uniformly, densely, and have a small grain size. Towards the direction away from the substrate, the grain size gradually increases. Thus, the third stepped surface 313 is perpendicular to the thickness direction of the first material layer 31, the crystal orientation of the grains at the third stepped surface 313 is perpendicular to the third stepped surface 313, and the grain size of the grains at the third stepped surface 313 is also the diameter of the cross-section of the grains; however, due to the different heights of the first stepped surface 311 and the third stepped surface 313, the grain sizes and arrangements at different heights are different in themselves, thereby resulting in different grain sizes and arrangements of the grains at the first stepped surface 311 and the grains at the third stepped surface 313.

[0068] It can be seen that in the related art, taking the first material layer 31 as the focus ring, the stepped surface 301 of the first material layer 31 is the surface of the focus ring, and the grain arrangement on the surface of the focus ring 3 is uneven and the grain sizes are inconsistent. After performing the etching process, please refer to Figure 7 , the surface of the focus ring 3 shows different etching consumption amounts. The shaded part on the surface of the focus ring 3 in the figure is the etched consumption part. The etching consumption amount at the second stepped surface 312 is the largest. The uneven deformation of the surface of the focus ring 3 intensifies the electric field distortion, causing the problem of uneven etching at the edge of the wafer.

[0069] Based on this, an embodiment of the present application provides a focus ring. Please refer to Figure 1 , the focus ring is applied to a semiconductor etching device. The semiconductor etching device includes an electrostatic chuck 1 serving as a lower electrode and carrying a wafer 2 to be processed, and an upper electrode (not shown in the figure) corresponding to the electrostatic chuck 1. The focus ring 3 is arranged on the outer periphery of the electrostatic chuck 1. Please refer to Figures 8 to 10 , the focus ring includes:

[0070] The first semiconductor material layer 32, the first semiconductor material layer 32 includes a lower surface 302 for contacting the electrostatic chuck 1 and an upper surface 303 facing the upper electrode and the wafer to be processed. The upper surface 303 of the first semiconductor material layer 32 includes a first surface 321 and a second surface 322. The first surface 321 is perpendicular to the thickness direction of the first semiconductor material layer 32, and the distance between each position of the second surface 322 from the outside to the inside along the radial direction of the focus ring and the lower surface 302 gradually decreases;

[0071] The second semiconductor material layer 33, which is formed on the upper surface 303 of the first semiconductor material layer 32 by an epitaxial growth process. The crystal orientation of the grains in the second semiconductor material layer 33 is perpendicular to the upper surface 303, and the second semiconductor material layer 33 is a homoepitaxial layer of the first semiconductor material layer 32.

[0072] It can be understood that the second semiconductor material layer 33 is formed on the upper surface 303 of the first semiconductor material layer 32 by an epitaxial growth process. Therefore, the upper surface 303 of the first semiconductor material layer 32 is the growth surface of the second semiconductor material layer 33. According to the crystal growth principle, the grains in the second semiconductor material layer 33 are all perpendicular to their respective growth surfaces. The grain size of each part of the surface of the second semiconductor material layer 33 is the diameter of the cross-section of the grain. Therefore, the grain arrangement on its surface is uniform and the grain size is consistent; and the thickness of each part of the second semiconductor material layer 33 is the same. The upper surface 303 of the second semiconductor material layer 33 far from the first semiconductor material layer 32 is of the same shape as the upper surface 303 of the first semiconductor material layer 32. The grains on each part of the surface of the second semiconductor material layer 33 are basically in the same growth stage, which further ensures that the grain sizes are basically the same.

[0073] The crystal orientation of the grains in the first semiconductor material layer 32 is in the thickness direction of the first semiconductor material layer 32. The first surface 321 is perpendicular to the thickness direction of the first semiconductor material layer 32. Therefore, the crystal orientation of the grains at the first surface 321 is perpendicular to the first surface 321, and the grain size is the diameter of the cross-section of the grains. For the second surface 322, the distance between each position from the outside to the inside along the radial direction of the focusing ring and the lower surface 302 gradually decreases. The second surface 322 is not perpendicular to the thickness direction of the first semiconductor material layer 32. Obviously, the crystal orientation of the grains at the second surface 322 is not perpendicular to the second surface 322, and the grain size is not the diameter of the cross-section of the grains. Therefore, the arrangement and grain size of the grains at the first surface 321 are different from those at the second surface 322. It can be seen that the uniformity of the arrangement and the consistency of the grain size of the grains in the second semiconductor material layer 33 are higher than those of the grains in the surface layer on the upper surface 303 side of the first semiconductor material layer 32. This also makes the arrangement of the surface grains of the focusing ring exposed to the plasma etching environment uniform and the grain size consistent. Furthermore, during actual use, the etching consumption at each part of the focusing ring surface can be kept consistent, so that the electric field at the edge of the wafer remains balanced, avoiding uneven etching at the edge position of the wafer.

[0074] Optionally, as Figure 8 and Figure 9 shown, the upper surface 303 of the first semiconductor material layer 32 further includes a third surface 323. The third surface 323 is perpendicular to the thickness direction of the first semiconductor material layer 32. The distance between the third surface 323 and the first semiconductor material layer 32 is different from the distance between the first surface 321 and the first semiconductor material layer 32. It can be understood that Figure 8 and Figure 9 only schematically shows that the first surface 321, the second surface 322, and the third surface 323 are connected in sequence from the outside to the inside along the radial direction of the focusing ring. Among them, the first surface 321 faces the upper electrode, and the third surface 323 faces the upper electrode and the wafer to be processed. In some other embodiments, the first surface 321, the second surface 322, and the third surface 323 are connected in sequence from the inside to the outside along the radial direction of the focusing ring. Among them, the first surface 321 faces the upper electrode and the wafer to be processed, and the third surface 323 faces the upper electrode. This embodiment does not make any limitations in this regard.

[0075] Understandably, according to crystallography theory, during crystal growth, atomic stacking preferentially occurs on the crystal plane with the lowest surface energy, thereby obtaining a dense structure. That is to say, the grain size gradually increases in the direction away from the growth surface, and the grain arrangement gradually becomes loose. Thus, even if the third surface 323 is perpendicular to the thickness direction of the first semiconductor material layer 32, the grain size at the third surface 323 is also the cross-sectional diameter of the grains, and the grain orientation is perpendicular to the third surface 323. However, the first surface 321 and the third surface 323 are at different heights, and the grain size and arrangement at different heights are different, resulting in different grain sizes and arrangements at the first surface 321 and the third surface 323.

[0076] In an alternative embodiment, the second surface 322 can be an inclined surface. As Figure 8 shown, the angle between the second surface 322 and the first surface 321 is an obtuse angle, and the second surface 322 extends towards the lower surface 302. Please refer to Figure 9 . In another alternative embodiment, the second surface 322 can be an arc surface. Understandably, in some other embodiments, the second surface 322 can also be a vertical surface, the second surface 322 is perpendicular to the first surface 321, or rather, the direction of the plane where the second surface 322 is located is the thickness direction of the first semiconductor material layer 32.

[0077] In yet another alternative embodiment, please refer to Figure 10 . The second surface 322 extends towards the lower surface 302 until it connects to the lower surface 302, and the second surface 322 is an inclined surface. In this alternative embodiment, the longitudinal cross-sectional shape of the first semiconductor material layer 32 is a right trapezoid. Understandably, Figure 10 only the case where the second surface 322 is an inclined surface is described. In some other embodiments, the second surface 322 can also be an arc surface.

[0078] It should be noted that the first semiconductor material layer 32 is a ring structure with an inner diameter and an outer diameter. Therefore, the first semiconductor material layer 32 has an outer surface 304 corresponding to the outer diameter and an inner surface 305 corresponding to the inner diameter. Among these two, the outer surface 304 of the first semiconductor material layer 32 neither faces the upper electrode nor faces the wafer to be processed. Therefore, the outer surface 304 does not belong to a part of the upper surface 303. For example, Figures 8 to 10 in the embodiment shown, the direction of the plane where the outer surface 304 is located is perpendicular to the wafer to be processed and the upper electrode, and the outer surface 304 does not belong to the upper surface 303. And for the inner surface 305 of the first semiconductor material layer 32, in some embodiments, the distance between each position along the radial direction of the focus ring from the outside to the inside of the inner surface and the lower surface 302 gradually decreases. For example, Figure 10Another optional embodiment is shown, where the inner surface 305 faces the wafer to be processed, and the inner surface 305 is the second surface 322; in some other embodiments, the inner surface 305 faces neither the upper electrode nor the wafer to be processed. For example Figure 8 An optional embodiment shown or Figure 9 Another optional embodiment is shown, where the inner surface 305 faces the electrostatic chuck, i.e., the lower electrode. The direction of the plane where the inner surface 305 is located is perpendicular to the wafer to be processed and the upper electrode, and the inner surface 305 does not belong to the upper surface 303.

[0079] In some embodiments, the first semiconductor material layer 32 is a silicon carbide material layer. Since the second semiconductor material layer 33 is a homoepitaxial layer of the first semiconductor material layer 32, the second semiconductor material layer 33 is also a silicon carbide material layer. At this time, the focus ring is still a silicon carbide focus ring. Without changing the material of the focus ring, the arrangement and particle size of the grains on the surface of the focus ring can be improved, and the stress between the first semiconductor material layer 32 and the second semiconductor material layer 33 is small, and the bonding force is good, effectively avoiding the peeling off of the material layer in other processing procedures.

[0080] In this embodiment, the first semiconductor material layer 32 can be called the "focus ring body", and the second semiconductor material layer 33 can be called the "epitaxial layer". It can be understood that the first semiconductor material layer 32, as the main part of the focus ring, presents the basic shape of the focus ring, which is basically similar to the surface shape of the first material layer 31 used as the focus ring in the related art. The present application further processes on the basis of the first material layer 31 in the related art to obtain the second semiconductor material layer 33. The upper surface 303 of the second semiconductor material layer 33 far from the first semiconductor material layer 32 is of the same shape as the upper surface 303 of the first semiconductor material layer 32, and the second semiconductor material layer 33 is an epitaxial layer covering the focus ring body.

[0081] Optionally, the resistivity of the second semiconductor material layer 33 is less than that of the first semiconductor material layer 32. In this embodiment, the diameter of the inner edge of the first surface 321 of the first semiconductor material layer 32 is greater than the diameter of the wafer 2 to be processed, and the diameter of the outer edge of the third surface 323 is greater than the diameter of the wafer 2 to be processed. Therefore, only a part of the third surface 323 is covered by the wafer 2 to be processed. From the perspective of the entire focus ring 3, as Figure 7 shown, the inner side 313a of the lower step surface of the focus ring 3 is covered by the wafer 2 to be processed, and the outer side 313b of the lower step surface of the focus ring 3 is exposed outside the wafer 2 to be processed. Therefore, when performing the plasma etching process, the outer side 313b of the lower step surface is more easily etched, and the outer side 313b of the lower step surface shows a larger etching consumption relative to the inner side 313a of the lower step surface, presenting a larger etching groove in appearance (as Figure 7(as shown by the middle circle). The groove reflects the polymers generated by the plasma etching process, and the polymers accumulate at the edge of the wafer to form an attachment 21. Under a high-frequency electric field, arcs are likely to occur at the attachment 21 and the corners of the etching groove. Once an arc occurs, the entire wafer will fail. Therefore, by setting the resistivity of the second semiconductor material layer 33 to be less than that of the first semiconductor material layer 32, the conductivity of the surface of the focusing ring 3 is better. In actual use, it is beneficial to avoid the accumulation of charges on the surface of the focusing ring 3, especially to avoid the accumulation of charges at the corners of the etching groove, thereby reducing the risk of arc occurrence.

[0082] Optionally, the resistivity of the second semiconductor material layer 33 is 8% - 12% of the resistivity of the first semiconductor material layer 32. Further, the resistivity of the second semiconductor material layer 33 is 10% of the resistivity of the first semiconductor material layer 32. In this way, better effects can be achieved. In this embodiment, the resistivity of the first semiconductor material layer 32 is 0.1 Ω×cm, and the resistivity of the second semiconductor material layer 33 is 0.01 Ω×cm.

[0083] In some embodiments, the thickness of the second semiconductor material layer 33 is 5% - 10% of the thickness of the focusing ring; wherein, the thickness of the focusing ring is the sum of the thicknesses of the first semiconductor material layer 32 and the second semiconductor material layer 33, and the thickness of the first semiconductor material layer 32 is the maximum value of the distance between the upper surface 303 and the lower surface 302. It can be understood that if the thickness of the second semiconductor material layer 33 is too small, its bonding property with the first semiconductor material layer 32 is poor and it is likely to fall off during the processing; if the thickness of the second semiconductor material layer 33 is too large, it is difficult to control the uniformity of the arrangement of its internal grains and the consistency of the grain size. Therefore, the expected effects can be achieved within this range. In this embodiment, the thickness of the first semiconductor material layer 32 can be understood as the distance between the first surface 321 and the lower surface 302.

[0084] In this embodiment, the second semiconductor material layer 33 is a silicon carbide material layer, and the thickness of the second semiconductor material layer 33 is 0.5 mm. When the silicon carbide material has a thickness of 0.5 mm, the grain size is small and the arrangement is dense, and there is no situation of increasing grain size yet.

[0085] Optionally, the grain size of the grains in the second semiconductor material layer 33 is smaller than that of the grains in the first semiconductor material layer 32. Thus, the grain size of the grains on the surface of the focusing ring 3 is smaller, which can better resist the erosion of plasma. Specifically, the grain size of the grains in the second semiconductor material layer 33 is less than or equal to 3 μm. It can be understood that the first semiconductor material layer 32 is a silicon carbide material layer. In the first semiconductor material layer 32, the grain size of the grains near the growth surface 401 is 5 μm - 10 μm, and the grain size of the grains far from the growth surface 401 is greater than 10 μm. Controlling the grain size of the grains in the second semiconductor material layer 33 to be less than or equal to 3 μm can achieve the desired effect.

[0086] The embodiment of the present application also provides a method for manufacturing a focusing ring 3. Please refer to Figure 1 , the focusing ring 3 is applied to a semiconductor etching device. The semiconductor etching device includes an electrostatic chuck 1 serving as a lower electrode and carrying a wafer 2 to be processed, and an upper electrode (not shown in the figure) corresponding to the electrostatic chuck 1. The focusing ring 3 is disposed on the outer periphery of the electrostatic chuck 1. Please refer to Figure 11 , the manufacturing method includes:

[0087] Step S1: Provide a substrate;

[0088] Step S2: Grow a material layer to be processed on the surface of the substrate;

[0089] Step S3: Remove the substrate;

[0090] Step S4: Remove a part of the material layer to be processed from the side of the material layer to be processed facing the substrate to form a first semiconductor material layer. The first semiconductor material layer is annular. The first semiconductor material layer includes a lower surface for contacting the electrostatic chuck and an upper surface facing the upper electrode and the wafer to be processed. The upper surface of the first semiconductor material layer includes a first surface and a second surface. The first surface is perpendicular to the thickness direction of the first semiconductor material layer. The distance between each position of the second surface along the radial direction of the first semiconductor material layer from the outside to the inside and the lower surface gradually decreases;

[0091] Step S5: Epitaxially grow a second semiconductor material layer on the upper surface of the first semiconductor material layer to form a focusing ring. The crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface. The second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer.

[0092] Thus, by epitaxially growing a homoepitaxial layer, i.e., the second semiconductor material layer, on the upper surface of the first semiconductor material layer, the surface of the focusing ring is the surface of the second semiconductor material layer at this time. The crystal orientations of the grains in the second semiconductor material layer are perpendicular to the upper surface. Then, the crystal orientations of the grains at the surface of the focusing ring are all perpendicular to the surface of the focusing ring, and the grain size of each grain is the diameter of the cross-section of the grain, that is, the grain arrangement at each position on the surface of the focusing ring is uniform and the grain sizes are consistent. Without changing the material of the focusing ring, the uniformity of the grain arrangement and the consistency of the grain size on the surface of the focusing ring are improved, avoiding the problem that the grain arrangements at each surface are uneven and the grain sizes are inconsistent when only using the first semiconductor material layer as the focusing ring in the related art. Subsequently, the problem of different etching consumptions during actual use can be avoided, the electric field at the edge of the wafer can be kept balanced, and uneven etching at the edge position of the wafer can be avoided.

[0093] First, perform step S1: Provide a substrate 4.

[0094] The material of the substrate 4 may include graphite or sintered silicon carbide.

[0095] Please refer to Figure 2 , perform step S2: Grow a material layer to be processed 30 on the surface of the substrate 4. Optionally, the material of the material layer to be processed 30 is silicon carbide. Specifically, the material layer to be processed 30 may be a polycrystalline silicon carbide solid material layer. The process for growing the material layer to be processed 30 may include a chemical vapor deposition process.

[0096] Next, perform step S3: Remove the substrate 4.

[0097] The process for removing the substrate 4 may be any process that can be realized and is well-known to those skilled in the art, and will not be elaborated here.

[0098] Please refer to Figure 12 , perform step S4: Remove a part of the material layer to be processed 30 from the side of the material layer to be processed 30 facing the substrate 4 to form a first semiconductor material layer 32. The first semiconductor material layer 32 is annular. The first semiconductor material layer 32 includes a lower surface 302 for contacting the electrostatic chuck 1 and an upper surface 303 facing the upper electrode and the wafer to be processed 2. The upper surface 303 of the first semiconductor material layer 32 includes a first surface 321 and a second surface 322. The first surface 321 is perpendicular to the thickness direction of the first semiconductor material layer 32, and the distances between the positions of the second surface 322 along the radial direction of the first semiconductor material layer 32 from the outside to the inside and the lower surface 302 gradually decrease.

[0099] The crystal orientation of the grains in the first semiconductor material layer 32 is in the thickness direction of the first semiconductor material layer 32. The first surface 321 is perpendicular to the thickness direction of the first semiconductor material layer 32. Thus, the crystal orientation of the grains at the first surface 321 is perpendicular to the first surface 321, and the grain size is the diameter of the cross-section of the grains. For the second surface 322, the distance between each position from the outside to the inside along the radial direction of the focusing ring and the lower surface 302 gradually decreases. The second surface 322 is not perpendicular to the thickness direction of the first semiconductor material layer 32. Obviously, the crystal orientation of the grains at the second surface 322 is not perpendicular to the second surface 322, and the grain size is not the diameter of the cross-section of the grains. Therefore, the arrangement and size of the grains at the first surface 321 are different from those at the second surface 322.

[0100] It can be understood that according to crystallography theory, during crystal growth, atomic stacking will preferentially occur on the crystal plane with the lowest crystal plane energy, thereby obtaining a dense structure. Therefore, processing from the side of the material layer 30 to be processed facing the substrate 4 can make the grain size of the grains at the upper surface 303 of the first semiconductor material layer 32 smaller and the arrangement more compact.

[0101] Please refer to Figure 3 and Figure 12 , optionally, removing a part of the material layer 30 to be processed to form the first semiconductor material layer 32 includes: removing a part of the material layer 30 to be processed to form the first material layer 31. The first material layer 31 is annular and includes a lower surface 302 and a step surface 301 away from the lower surface 302. The step surface 301 includes a first step surface 311 and a second step surface 312. The first step surface 311 is perpendicular to the thickness direction of the first material layer 31. For the second step surface 312, the distance between each position from the outside to the inside along the radial direction of the first material layer 31 and the lower surface 302 gradually decreases; removing the first material layer 31 with a first thickness to form the first semiconductor material layer 32, and the upper surface 303 has the same shape as the step surface 301.

[0102] It should be noted that Figure 2 and Figure 3 are schematic cross-sectional structure diagrams of the focusing ring in the preparation process in the related art. In the related art, the directly processed first material layer 31 is used as the focusing ring. Based on this, the present application further processes the first material layer 31 to eliminate part of the thickness and obtain the first semiconductor material layer 32, avoiding a large impact on the thickness of the focusing ring 3 caused by the subsequent epitaxial growth of the second semiconductor material layer 33, changing the distance between the focusing ring 3 and the wafer 2 to be processed, and the distance between the focusing ring 3 and the wafer 2 to be processed will affect the electric field at the edge of the wafer, thereby affecting the etching effect at the edge of the wafer.

[0103] Specifically, the removal of the first material layer 31 having the first thickness may be achieved by using a CNC (Computer Numerical Control) machining center.

[0104] In some embodiments, please refer to Figure 13 Before executing step S4, the preparation method may further include: placing the first semiconductor material layer 32 in a carrier 5, wherein the carrier 5 covers other surfaces of the first semiconductor material layer 32 except the upper surface 303. Thus, the growth of material layers on other surfaces of the first semiconductor material layer 32 can be avoided.

[0105] The material of the carrier 5 may include graphite or sintered silicon carbide. Further, the material of the carrier 5 includes graphite. After the second semiconductor material layer 33 is grown, the carrier 5 needs to be removed. Graphite is easier to remove and has a lower material cost.

[0106] Please refer to the following Figure 8 , perform step S5: epitaxially grow a second semiconductor material layer 33 on the upper surface 303 of the first semiconductor material layer 32 to form a focus ring, the crystal orientation of the grains in the second semiconductor material layer 33 is perpendicular to the upper surface 303, and the second semiconductor material layer 33 is a homogeneous epitaxial layer of the first semiconductor material layer 32. At this time, the surface of the focus ring is the surface of the second semiconductor material layer 33, and the crystal orientation of the grains in the second semiconductor material layer 33 is perpendicular to the upper surface 303, then the crystal orientation of the grains at all locations on the focus ring surface is perpendicular to the focus ring surface, and the grain size is the diameter of the grain cross section, that is, the grains at all locations on the focus ring surface are evenly arranged and have the same grain size; and the thickness of the second semiconductor material layer 33 is consistent at all locations, the surface of the second semiconductor material layer 33 is the same shape as the upper surface 303 of the first semiconductor material layer 32, and the grains at all locations on the surface of the second semiconductor material layer 33 are basically in the same growth stage, which further ensures that the grain size is basically consistent.

[0107] In an optional embodiment where the first material layer 31 of the first thickness is removed, the thickness of the second semiconductor material layer 33 is equal to the first thickness. Thus, the thickness of the focus ring is kept consistent with the thickness of the first material layer 31, which is more conducive to ensuring that the distance between the focus ring 3 and the wafer 2 to be processed does not change.

[0108] In some embodiments, epitaxially growing a second semiconductor material layer 33 on the upper surface 303 of the first semiconductor material layer 32 to form the focus ring 3 may include: epitaxially growing a second semiconductor material (not shown in the figure) on the upper surface 303 of the first semiconductor material layer 32; removing the second semiconductor material of the second thickness to obtain the second semiconductor material layer 33 to form the focus ring. In this embodiment, the thickness of the second semiconductor material layer 33 is 0.5 mm, and the thickness of the second semiconductor material is greater than 1.2 mm.

[0109] Optionally, the thickness of the second semiconductor material layer 33 is 5%-10% of the thickness of the focus ring 3; wherein the thickness of the focus ring 3 is the sum of the thickness of the first semiconductor material layer 32 and the thickness of the second semiconductor material layer 33, and the thickness of the first semiconductor material layer 32 is the maximum value of the distance between the upper surface 303 and the lower surface 302. Within this range, the uniformity of grain arrangement and the consistency of grain size in the second semiconductor material layer 33 are better, and the bonding property with the first semiconductor material layer 32 is better, and it is not easy to fall off, and the process time for preparing the second semiconductor material layer 33 is controllable to avoid affecting the production efficiency. In actual preparation, the growth rate can be controlled to be reduced to obtain a second semiconductor material layer 33 with better crystal quality.

[0110] In this embodiment, the second semiconductor layer material layer is a silicon carbide material layer, and the thickness of the second semiconductor material layer 33 is 0.5 mm. When the silicon carbide material is 0.5 mm thick, the grain size is small and closely arranged, and the grain size has not changed, which is more conducive to ensuring the uniformity of grain arrangement and uniformity of grain size in the second semiconductor material layer 33.

[0111] Optionally, the particle size of the grains in the second semiconductor material layer 33 is smaller than the particle size of the grains in the first semiconductor material layer 32. As a result, the particle size of the grains on the surface of the focusing ring 3 is smaller, which can better resist plasma erosion. Specifically, the particle size of the grains in the second semiconductor material layer 33 is less than or equal to 3μm. It can be understood that the first semiconductor material layer 32 is a silicon carbide material layer. In the first semiconductor material layer 32, the particle size of the grains close to the growth surface 401 is 5μm-10μm, and the particle size of the grains away from the growth surface 401 is greater than 10μm. Controlling the particle size of the grains in the second semiconductor material layer 33 to be less than or equal to 3μm can achieve the desired effect.

[0112] The process of epitaxially growing the second semiconductor material layer 33 may include a chemical vapor deposition process.

[0113] Optionally, the growth conditions for growing the material layer to be processed include a first growth temperature; the growth conditions for growing the second semiconductor material layer include a second growth temperature; wherein the second growth temperature is lower than the first growth temperature. It can be understood that by controlling the growth temperature of the second semiconductor material layer to be lower than the growth temperature of the first semiconductor material layer, the second semiconductor material layer grows in a low temperature environment, so that the grain size of the grown second semiconductor material layer is smaller and the crystallinity is better, which is beneficial to ensure the uniformity of grain arrangement and grain size consistency at various locations on the surface of the second semiconductor material layer, and is more beneficial for the focusing ring to resist etching damage and maintain electric field balance during actual use.

[0114] Further, the difference between the second growth temperature and the first growth temperature ranges from 50°C to 100°C.

[0115] Optionally, the growth conditions for growing the material layer to be processed include a first growth pressure; the growth conditions for growing the second semiconductor material layer include a second growth pressure; wherein the second growth pressure is less than the first growth pressure. Thus, by controlling the growth pressure of the second semiconductor material layer to be less than the growth pressure of the first semiconductor material layer, the second semiconductor material layer grows under a low-pressure environment, so that the grain size of the grown second semiconductor material layer is smaller and the crystallinity is better, which is conducive to ensuring the uniformity of grain arrangement and grain size consistency at various locations on the surface of the second semiconductor material layer, and is more conducive to resisting etching damage and maintaining electric field balance in actual use.

[0116] It is understandable that the process for growing the material layer to be treated can be a normal pressure growth process, and the process for growing the second semiconductor material layer can be a low pressure growth process. It should be noted that the specific pressure ranges of normal pressure and low pressure here are generally known to those skilled in the art and will not be elaborated here.

[0117] In some embodiments, the second growth temperature is lower than the first growth temperature, and the second growth pressure is lower than the first growth pressure, so that the second semiconductor material layer grows in a low temperature and low pressure environment, and the crystal quality of the second semiconductor material layer is better, the grains are evenly arranged and the grain size is consistent.

[0118] Optionally, the growth conditions for growing the material layer to be processed include the introduction of a first doping gas; the growth conditions for growing the second semiconductor material layer include the introduction of a second doping gas; wherein the content of nitrogen atoms in the total doping amount of the second doping gas is greater than the content of nitrogen atoms in the total doping amount of the first doping gas. It can be understood that controlling the content of nitrogen atoms in the total doping amount of the second doping gas to be greater than the content of nitrogen atoms in the total doping amount of the first doping gas means that in the process of growing the second semiconductor material layer, the nitrogen atom content in the growth chamber is higher, and the increase in the nitrogen atom content reduces the resistivity of the grown material layer, that is, the resistivity of the second semiconductor material layer is less than that of the first semiconductor material layer, and the conductivity of the second semiconductor material layer is better. Therefore, in actual use, it is helpful to avoid the accumulation of charge on the surface of the focusing ring and reduce the risk of arcing.

[0119] Furthermore, the content of nitrogen atoms in the total doping amount of the second doping gas is 1.5 to 3 times the content of nitrogen atoms in the total doping amount of the first doping gas. Thus, the second semiconductor material layer with low resistivity can be better formed to achieve the expected effect.

[0120] Specifically, the flow rate of the second doping gas is greater than that of the first doping gas. By increasing the flow rate of the doping gas during the preparation of the second semiconductor material layer, the content of nitrogen atoms in the growth chamber is increased, and then the resistivity of the second semiconductor material layer is made smaller than that of the first semiconductor material layer.

[0121] Alternatively, specifically, the nitrogen atom component of the second doping gas is greater than that of the first doping gas. When growing the second semiconductor material layer, a doping gas different from that used for growing the first semiconductor material layer is selected. The second doping gas has a higher nitrogen atom component, increasing the content of nitrogen atoms in the growth chamber, and then making the resistivity of the second semiconductor material layer smaller than that of the first semiconductor material layer. For example, when growing the first semiconductor material layer, the doping gas is ammonia (NH3), and when growing the second semiconductor material layer, the doping gas is nitrogen (N2). Nitrogen contains 2 nitrogen atoms, while ammonia only has 1 nitrogen atom, so the nitrogen atom component of nitrogen is higher.

[0122] In some embodiments, the flow rate of the second doping gas is greater than that of the first doping gas, and the nitrogen atom component of the second doping gas is greater than that of the first doping gas. This can better achieve the desired effect.

[0123] In an optional specific embodiment, the epitaxial growth conditions for epitaxially growing the second semiconductor material layer 33 on the upper surface 303 of the first semiconductor material layer 32 include: the growth temperature ranges from 1290 °C to 1310 °C; the growth pressure ranges from 195 Torr to 205 Torr; the flow rate of the growth precursor ranges from 4.5 LPM to 5.5 LPM; the flow rate of the carrier gas ranges from 29 LPM to 31 LPM; the flow rate of the dilution gas ranges from 4.5 LPM to 5.5 LPM; the flow rate of the second doping gas ranges from 4.9 LPM to 5.1 LPM. It can be understood that by controlling the growth conditions, the grain size, grain arrangement, and resistivity of the second semiconductor material layer 33 can be adjusted.

[0124] The second semiconductor material layer 33 is a silicon carbide material layer. The growth precursor may include methyltrichlorosilane; the carrier gas may include hydrogen; the dilution gas may include argon; the second doping gas may include nitrogen.

[0125] Specifically, the first semiconductor material layer 32 is a silicon carbide material layer; the growth conditions for homoepitaxially growing the second semiconductor material layer 33 on the first semiconductor material layer 32 may include: the growth temperature is 1300 °C; the growth pressure is 200 Torr; the flow rate of monomethyltrichlorosilane introduced is 5 LPM; the flow rate of hydrogen introduced is 30 LPM; the flow rate of argon introduced is 5 LPM; the flow rate of nitrogen introduced is 5 LPM; the growth rate is 30 μm / h. Thus, the second semiconductor material layer 33 with closely distributed grains, a high proportion of

[111] crystal orientation, and a resistivity of 0.01 Ω×cm can be obtained.

[0126] After performing step S4, the preparation method may further include: removing the carrier 5.

[0127] It should be noted that the embodiments of the focusing ring and the preparation method of the focusing ring provided in this application belong to the same concept; among the technical features in the technical solutions recorded in each embodiment, they can be arbitrarily combined without conflict. However, it should be further noted that for the focusing ring provided in the embodiments of this application, the combination of its technical features can already solve the technical problems to be solved in this application; therefore, the focusing ring provided in the embodiments of this application may not be limited by the preparation method of the focusing ring provided in the embodiments of this application, and any focusing ring prepared by a preparation method that can form the structure of the focusing ring provided in the embodiments of this application is within the protection scope of this application.

[0128] It should be understood that the above embodiments are all exemplary and do not cover all possible implementation manners. Without departing from the scope of the present disclosure, various deformations and changes can also be made based on the above embodiments. Similarly, the technical features of the above embodiments can also be arbitrarily combined to form other embodiments of this application that may not be clearly described. Therefore, the above embodiments only represent several implementation manners of this application and do not limit the protection scope of the patent of this application.

Claims

1. A focusing ring is applied to a semiconductor etching device. The semiconductor etching device includes an electrostatic chuck serving as a lower electrode and for carrying a wafer to be processed, and an upper electrode arranged corresponding to the electrostatic chuck. The focusing ring is arranged on the outer periphery of the electrostatic chuck, and is characterized in that, The focusing ring includes: A first semiconductor material layer, the first semiconductor material layer including a lower surface for contacting the electrostatic chuck and an upper surface facing the upper electrode and the wafer to be processed. The upper surface of the first semiconductor material layer includes a first surface and a second surface. The first surface is perpendicular to the thickness direction of the first semiconductor material layer. The distance between each position of the second surface from the outside to the inside along the radial direction of the focusing ring and the lower surface gradually decreases; A second semiconductor material layer, formed only on the upper surface of the first semiconductor material layer by an epitaxial growth process. The crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface. The second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer. The particle size of the grains in the second semiconductor material layer is smaller than the particle size of the grains in the first semiconductor material layer. The thickness of the second semiconductor material layer is 5%-10% of the thickness of the focusing ring. Wherein, the thickness of the focusing ring is the sum of the thickness of the first semiconductor material layer and the thickness of the second semiconductor material layer, and the thickness of the first semiconductor material layer is the maximum value of the distance between the upper surface and the lower surface; 2. The focusing ring according to claim 1, wherein The resistivity of the second semiconductor material layer is less than the resistivity of the first semiconductor material layer.

3. A method for preparing a focusing ring, the focusing ring being applied to a semiconductor etching device, the semiconductor etching device including an electrostatic chuck serving as a lower electrode and for carrying a wafer to be processed, and an upper electrode disposed corresponding to the electrostatic chuck, the focusing ring being disposed on the outer periphery of the electrostatic chuck, characterized in that, The method includes: Providing a substrate; Growing a layer of material to be processed on the surface of the substrate; Removing the substrate; Removing a part of the layer of material to be processed from the side of the layer of material to be processed facing the substrate to form a first semiconductor material layer. The first semiconductor material layer is annular. The first semiconductor material layer includes a lower surface for contacting the electrostatic chuck and an upper surface facing the upper electrode and the wafer to be processed. The upper surface of the first semiconductor material layer includes a first surface and a second surface. The first surface is perpendicular to the thickness direction of the first semiconductor material layer. The distance between each position of the second surface from the outside to the inside along the radial direction of the first semiconductor material layer and the lower surface gradually decreases; Only growing a second semiconductor material layer epitaxially on the upper surface of the first semiconductor material layer to form a focusing ring. The crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface. The second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer. The particle size of the grains in the second semiconductor material layer is smaller than the particle size of the grains in the first semiconductor material layer. The thickness of the second semiconductor material layer is 5%-10% of the thickness of the focusing ring. Wherein, the thickness of the focusing ring is the sum of the thickness of the first semiconductor material layer and the thickness of the second semiconductor material layer, and the thickness of the first semiconductor material layer is the maximum value of the distance between the upper surface and the lower surface; 4. The method for preparing a focusing ring according to claim 3, wherein The growth conditions for growing the layer of material to be processed include a first growth temperature; the growth conditions for growing the second semiconductor material layer include a second growth temperature; wherein, the second growth temperature is less than the first growth temperature.

5. The preparation method of the focusing ring according to claim 3, characterized in that, The growth conditions for the layer of material to be grown include a first growth pressure; the growth conditions for the second semiconductor material layer include a second growth pressure; wherein, the second growth pressure is less than the first growth pressure.

6. The manufacturing method of the focusing ring according to claim 3, characterized in that, The growth conditions for the layer of material to be grown include introducing a first doping gas; the growth conditions for the second semiconductor material layer include introducing a second doping gas; wherein, the content of nitrogen atoms in the total doping amount of the second doping gas is greater than the content of nitrogen atoms in the total doping amount of the first doping gas.

7. The method for preparing a focusing ring according to claim 6, wherein, The introduction amount of the second doping gas is greater than the introduction amount of the first doping gas.

8. The method for preparing a focusing ring according to claim 6, wherein, The nitrogen atom component of the second doping gas is greater than the nitrogen atom component of the first doping gas.

9. The method for preparing a focusing ring according to claim 3, wherein Before epitaxially growing the second semiconductor material layer on the upper surface of the first semiconductor material layer, the preparation method further includes: placing the first semiconductor material layer in a carrier, and the carrier covers other surfaces of the first semiconductor material layer except the upper surface; After epitaxially growing the second semiconductor material layer on the upper surface of the first semiconductor material layer, the preparation method further includes: removing the carrier.

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