Preparation method of conductive contact hole and semiconductor device
By setting up a second interlayer dielectric layer with a first window during the preparation of the conductive contact hole, controlling the diameter of the second etching hole and ejecting the etch by-product, the problem of difficulty in controlling the bottom etching of the conductive contact hole and stopping the etching at the conductive contact hole is solved, and a higher process window and a more stable etching process are achieved.
Patent Information
- Application Number
- CN202311339107.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-16
- Publication Date
- 2025-04-18
AI Technical Summary
When preparing conductive contact holes, etching at the bottom of conductive contact holes is difficult to control, which easily leads to the problem of etching stop.
By providing a second interlayer dielectric layer with a first window between the first interlayer dielectric layer and the third interlayer dielectric layer, the diameter of the second etching hole formed by the second etching is controlled, and the minimum diameter of the first portion of the first etching hole formed after the first etching is greater than the diameter of the first window of the second interlayer dielectric layer to facilitate the discharge of etching by-products.
It reduces the control difficulty of etching at the bottom of the conductive contact hole, increases the process window during the second etching, and alleviates the problem of etching stop.
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Figure CN119852240A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a method for preparing a conductive contact hole and a semiconductor device. Background Art
[0002] In integrated circuits, a conductive contact hole is a structure used to connect front-end devices and back-end interconnect metals. With the continuous improvement of the integration of semiconductor devices, the miniaturization of semiconductor integrated devices is a general trend. Miniaturization includes the miniaturization of the volume of a single semiconductor device in an integrated device and the miniaturization of the connection between semiconductor devices. The miniaturization of semiconductor integrated devices has the advantages of excellent performance, low energy consumption, low cost, and expanded use scenarios.
[0003] Under the demand of semiconductor process miniaturization, the critical dimension (CD) of the conductive contact hole is also shrinking. The CD precision control requirement of the conductive contact hole on the active area is relatively high. Based on the process characteristics of etching the conductive contact hole with a high aspect ratio, it is more difficult to control it under a high aspect ratio. It is difficult to obtain a vertical conductive contact hole under the same etching conditions. For example, based on the existing etching process, when the aspect ratio of the conductive contact hole is about 9, after the conductive contact hole is formed, the size of the top and the bottom of the conductive contact hole differ by about 10nm, so the etching of the bottom of the conductive contact hole is difficult to control. In addition, in the etching process, the etching rate of patterns of different sizes is uneven, and the uneven rate will cause the CD deviation and etching depth between photolithography and etching to be different. This phenomenon is called the load effect. Due to the influence of the load effect, when etching conductive contact holes of different widths, although the etching is performed under the same etching conditions, each conductive contact hole cannot reach the bottom at the same time, which is easy to cause etching stop. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for preparing a conductive contact hole and a semiconductor device, so as to solve the problems in the prior art that, when preparing the conductive contact hole, the etching at the bottom of the conductive contact hole is difficult to control and etching stop is easy to occur.
[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a conductive contact hole, the method comprising the following steps:
[0006] Providing a substrate, on which a semiconductor structure is formed;
[0007] forming a first interlayer dielectric layer on the surface of the substrate, wherein the first interlayer dielectric layer covers the semiconductor structure;
[0008] forming a second interlayer dielectric layer having a first window on the surface of the first interlayer dielectric layer, wherein the first window penetrates the second interlayer dielectric layer;
[0009] forming a third interlayer dielectric layer on the surface of the second interlayer dielectric layer, and the third interlayer dielectric layer completely fills the first window;
[0010] Forming a first patterned photoresist layer on the third interlayer dielectric layer, wherein a second window is formed on the first patterned photoresist layer, and the second window is located directly above the first window, and the diameter of the second window is larger than the diameter of the first window;
[0011] Based on the second window, the third interlayer dielectric layer is etched until the surface of the first interlayer dielectric layer is exposed, thereby forming a first etched hole, wherein the first etched hole is composed of a first portion penetrating the third interlayer dielectric layer and the first window, and the minimum diameter of the first portion is larger than the diameter of the first window;
[0012] The first interlayer dielectric layer is etched based on the first etch hole, thereby forming a second etch hole penetrating the first interlayer dielectric layer, and the first etch hole and the second etch hole together constitute a conductive contact hole.
[0013] Optionally, the maximum aperture of the first part is larger than the aperture of the first window and is greater than 5% of the aperture of the first window.
[0014] Optionally, a minimum thickness of the first interlayer dielectric layer is greater than 30% of a total thickness of the second interlayer dielectric layer and the third interlayer dielectric layer.
[0015] Optionally, the method for forming the second interlayer dielectric layer having the first window includes:
[0016] forming a second interlayer dielectric layer on a surface of the first interlayer dielectric layer;
[0017] forming an anti-reflective coating and a photoresist layer in sequence on the second interlayer dielectric layer, and patterning the photoresist layer to form a second patterned photoresist layer;
[0018] Sequentially etching the anti-reflective coating and the second interlayer dielectric layer based on the second patterned photoresist layer;
[0019] The second patterned photoresist layer and the remaining anti-reflective coating are removed, so that the remaining second interlayer dielectric layer is formed into the second interlayer dielectric layer having the first window.
[0020] Optionally, the first etching hole and the second etching hole are formed by a plasma etching process.
[0021] Furthermore, the etching rate of the etching gas used in the plasma etching process on the third interlayer dielectric layer and the first interlayer dielectric layer is greater than the etching rate on the second interlayer dielectric layer.
[0022] Optionally, the substrate is a silicon substrate; the first interlayer dielectric layer is a silicon oxide layer; a silicon nitride layer is also formed between the first interlayer dielectric layer and the substrate; the second interlayer dielectric layer is a silicon nitride layer or a nitrogen-doped silicon carbide layer; and the third interlayer dielectric layer is a silicon oxide layer.
[0023] Furthermore, the semiconductor structure protrudes from the surface of the substrate, the silicon oxide layer is divided into a first silicon oxide layer in contact with the silicon nitride layer and a second silicon oxide layer away from the silicon nitride layer, and the first silicon oxide layer is formed by a HAPR process.
[0024] The present invention further provides a semiconductor device, comprising a conductive contact hole prepared by the method for preparing a conductive contact hole as described in any one of the above, comprising:
[0025] a substrate having a semiconductor structure formed thereon;
[0026] A first interlayer dielectric layer, formed on the substrate and covering the semiconductor structure;
[0027] A second interlayer dielectric layer having a first window, formed on a surface of the first interlayer dielectric layer, and the first window penetrates the second interlayer dielectric layer;
[0028] A third interlayer dielectric layer is formed on a surface of the second interlayer dielectric layer;
[0029] The conductive contact hole is composed of a first etched hole and a second etched hole that are connected, wherein the first etched hole is composed of a first part that penetrates the third interlayer dielectric layer and the first window, and the minimum diameter of the first part is larger than the diameter of the first window, and the second etched hole penetrates the first interlayer dielectric layer.
[0030] As described above, in the method for preparing a conductive contact hole of the present invention, a second interlayer dielectric layer having a first window is arranged between the first interlayer dielectric layer and the third interlayer dielectric layer, so that the diameter of the second etching hole formed by the second etching can be controlled by the size of the first window, so as to reduce the difficulty of controlling the etching at the bottom of the conductive contact hole; in addition, the minimum diameter of the first part of the first etching hole formed after the first etching is made larger than the diameter of the first window of the second interlayer dielectric layer, so that when etching to form the second etching hole, it is easy to discharge the etching by-products in the hole, and reduce the load effect caused by etching between different graphic areas and / or different wafers during the etching process, thereby increasing the process window during the second etching and alleviating the problem of etching stop. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figures 1 to 13 It is a schematic diagram of the cross-sectional structure after each step in the method for preparing a conductive contact hole of the present invention is completed.
[0032] Component number description
[0033] 10 Substrate
[0034] 100 Semiconductor Structure
[0035] 11. First interlayer dielectric layer
[0036] 110 Silicon nitride layer
[0037] 112 first silicon oxide layer
[0038] 113 Second silicon oxide layer
[0039] 12. A second interlayer dielectric layer having a first window
[0041] 120 First Window
[0042] 121 Second interlayer dielectric layer
[0043] 122 First anti-reflective coating
[0044] 123 Second patterned photoresist layer
[0045] 124 Etching Window
[0046] 13 Third interlayer dielectric layer
[0047] 130 First patterned photoresist layer
[0048] 131 Second Window
[0049] 132 APF membrane
[0050] 133 Second anti-reflective coating
[0051] 134 First Etched Hole
[0052] 135 Part 1
[0053] 136 Second Etched Hole
[0054] 14 Conductive contact holes DETAILED DESCRIPTION
[0055] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0056] It will be understood that the meanings of “on,” “over,” and “above” in the embodiments of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.
[0057] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0058] See also Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0059] This embodiment provides a method for preparing a conductive contact hole, and the method comprises the following steps:
[0060] S1. providing a substrate, on which a semiconductor structure is formed;
[0061] S2, forming a first interlayer dielectric layer on the surface of the substrate, wherein the first interlayer dielectric layer covers the semiconductor structure;
[0062] S3, forming a second interlayer dielectric layer having a first window on the surface of the first interlayer dielectric layer, and the first window penetrates the second interlayer dielectric layer;
[0063] S4, forming a third interlayer dielectric layer on the surface of the second interlayer dielectric layer, and the third interlayer dielectric layer fully fills the first window;
[0064] S5, forming a first patterned photoresist layer on the third interlayer dielectric layer, wherein a second window is formed on the first patterned photoresist layer, and the second window is located directly above the first window, and the diameter of the second window is larger than the diameter of the first window;
[0065] S6. Etching the third interlayer dielectric layer based on the second window until the surface of the first interlayer dielectric layer is exposed, thereby forming a first etched hole, wherein the first etched hole is composed of a first portion penetrating the third interlayer dielectric layer and the first window, and a minimum diameter of the first portion is larger than a diameter of the first window;
[0066] S7. Etching the first interlayer dielectric layer based on the first etched hole to form a second etched hole penetrating the first interlayer dielectric layer, wherein the first etched hole and the second etched hole together constitute a conductive contact hole.
[0067] In the method for preparing the conductive contact hole of the present embodiment, a second interlayer dielectric layer having a first window is arranged between the first interlayer dielectric layer and the third interlayer dielectric layer, so that the diameter of the second etched hole formed by the second etching can be controlled by the size of the first window, so as to reduce the difficulty of controlling the etching at the bottom of the conductive contact hole; in addition, the minimum diameter of the first part of the first etched hole formed after the first etching is made larger than the diameter of the first window of the second interlayer dielectric layer, so that when the second etched hole is formed by etching, it is easy to discharge the etching by-products in the hole, and the load effect caused by etching between different graphic areas and / or different wafers during the etching process is reduced, thereby increasing the process window during the second etching and alleviating the problem of etching stop.
[0068] The method for preparing the conductive contact hole of this embodiment is described in detail below with reference to the specific drawings.
[0069] like Figure 1 As shown, step S1 is first performed to provide a substrate 10 on which a semiconductor structure 100 is formed.
[0070] The material of the substrate 10 may be silicon, germanium, silicon germanium or silicon carbide, etc., or may be silicon on insulator (SOI) or germanium on insulator (GOI), or other semiconductor materials. In this embodiment, the material of the substrate 10 is preferably a silicon substrate, and further, it may be selected as an undoped silicon substrate, an N-type doped silicon substrate, or a P-type doped silicon substrate according to actual needs.
[0071] The semiconductor structure 100 formed on the substrate 10 may be a semiconductor structure 10 embedded in the substrate 10, or may be a semiconductor structure 10 partially or completely protruding from the surface of the substrate 10. For example, a trench gate transistor may be embedded in the substrate 10, while a planar gate transistor may partially protrude from the surface of the substrate 10. The specific structure depends on different semiconductor structures 100, and no excessive limitation is made here.
[0072] For ease of understanding, the figure only shows a part of the entire wafer where conductive contact holes need to be formed. Those skilled in the art will know that the required conductive contact holes will also be formed in other areas of the entire wafer at the same time. The diameter, depth, distribution of the conductive contact holes based on different connection positions are set according to actual needs.
[0073] like Figure 1 As shown, step S2 is then performed to form a first interlayer dielectric layer 11 on the surface of the substrate 10 , wherein the first interlayer dielectric layer 11 covers the semiconductor structure 100 .
[0074] As a specific example, the first interlayer dielectric layer 11 may be formed by using conventional deposition processes, such as CVD, ALD, etc., and then polished by using a CMP process to make its surface flat.
[0075] As an example, the minimum thickness of the first interlayer dielectric layer 11 is greater than 30% of the total thickness of the second interlayer dielectric layer and the third interlayer dielectric layer to be formed subsequently, so that when the first etching hole is formed by the subsequent first etching, the first interlayer dielectric layer 11 has sufficient margin, and the semiconductor structure 100 will not be damaged due to over-etching during the first etching. When the substrate 10 is selected as a silicon substrate, the first interlayer dielectric layer 11 is preferably a silicon oxide layer. In some embodiments, a silicon nitride layer 110 is also formed between the first interlayer dielectric layer 11 and the substrate 10, that is, the silicon nitride layer 110 is first formed on the surface of the substrate 10, and then a silicon oxide layer is formed on the surface of the silicon nitride layer 110, where the silicon nitride layer 110 is subsequently used as an etching stop layer when etching the first interlayer dielectric layer 11. When the semiconductor structure 100 on the substrate 10 protrudes from the surface of the substrate 10, the silicon oxide layer can be formed by two different deposition processes. The first HARP process is used to form the first silicon oxide layer 112 to completely fill the groove on the surface of the silicon nitride layer 110 and extend it outside the groove. The second conventional deposition process is used to form the second silicon oxide layer 113. Finally, the CMP process is used to grind the surface of the second silicon oxide layer 113 flat, so as to obtain the first interlayer dielectric layer 11 with a flat upper surface. Figure 1 shown.
[0076] like Figure 3 As shown, step S3 is then performed to form a second interlayer dielectric layer 12 having a first window 120 on the surface of the first interlayer dielectric layer 11 , and the first window 120 penetrates the second interlayer dielectric layer 12 having the first window.
[0077] As a specific example, Figure 2 and Figure 3 As shown, the method for forming the second interlayer dielectric layer 12 having the first window includes:
[0078] S31, forming a second interlayer dielectric layer 121 on the surface of the first interlayer dielectric layer 11; S32, sequentially forming an anti-reflective coating 122 and a photoresist layer 123 on the second interlayer dielectric layer 121, and patterning the photoresist layer to form a second patterned photoresist layer 123, wherein an etching window 124 is formed on the second patterned photoresist layer 123, and the etching window 124 will be subsequently transferred to the second interlayer dielectric material layer 121 by etching to form the first window 120;
[0079] S33, etching the anti-reflective coating 122 and the second interlayer dielectric layer 121 in sequence based on the second patterned photoresist layer 123;
[0080] S34, removing the second patterned photoresist layer 123 and the remaining anti-reflective coating layer 122, so that the remaining second interlayer dielectric layer 121 is formed into the second interlayer dielectric layer 12 having the first window, as shown in FIG. Figure 3 shown.
[0081] The purpose of selecting the material of the second interlayer dielectric layer 121 is to select a material with a relatively large selective etching ratio between the second interlayer dielectric layer 121 and the first interlayer dielectric layer 11 and the third interlayer dielectric layer 13, so that the second interlayer dielectric layer 12 with the first window will not be seriously damaged when the first interlayer dielectric layer 11 and the third interlayer dielectric layer 13 are subsequently etched. When the material of the first interlayer dielectric layer 11 is silicon oxide, the material of the second interlayer dielectric layer 12 is preferably silicon nitride or nitrogen-doped silicon carbide.
[0082] like Figure 4 As shown, step S4 is then performed to form a third interlayer dielectric layer 13 on the surface of the second interlayer dielectric layer 12 , and the third interlayer dielectric layer 13 fills the first window 120 .
[0083] The material selection of the third interlayer dielectric layer 13 should take into account a larger selective etching ratio with the second interlayer dielectric layer 12, so as to ensure that the second interlayer dielectric layer 12 will not be significantly affected when the third interlayer dielectric layer 13 is subsequently etched. When the material of the second interlayer dielectric layer 12 is silicon nitride or nitrogen-doped silicon carbide, the material of the third interlayer dielectric layer 13 is preferably silicon oxide.
[0084] As an example, the third interlayer dielectric layer 13 may be formed by using conventional deposition processes, such as CVD, ALD, etc., and then polished by using a CMP process to make its surface flat.
[0085] like Figure 5As shown, step S5 is then performed to form a first patterned photoresist layer 130 on the third interlayer dielectric layer 13, a second window 131 is formed on the first patterned photoresist layer 130, and the second window 131 is located directly above the first window 120, and the aperture D1 of the second window is larger than the aperture D2 of the first window.
[0086] The first patterned photoresist layer 130 is generally formed by coating, exposing, and developing processes.
[0087] As a specific example, the method for forming the first patterned photoresist layer 130 includes: first, forming an APF film 132, a second anti-reflective coating 133 and a photoresist layer in sequence on the surface of the third interlayer dielectric layer 13, and the APF film 132 and the second anti-reflective coating 133 are subsequently used as hard mask layers for etching the third interlayer dielectric layer 13; then, exposing and developing the photoresist layer to form the first patterned photoresist layer 130.
[0088] The second window 131 on the first patterned photoresist layer 130 serves as a process window for etching the second anti-reflective coating 133, the APF film 132 and the third interlayer dielectric layer 13, so the second window 131 is arranged to be located directly above the first window 120, and its aperture D1 is larger than the aperture D2 of the first window, providing a basis for the subsequent formation of a large-aperture first etching hole.
[0089] like Fig. 9 and Fig.10 As shown, step S6 is then performed, in which the third interlayer dielectric layer 13 is etched based on the second window etching 131 until the surface of the first interlayer dielectric layer 11 is exposed, thereby forming a first etching hole 134, wherein the first etching hole 134 is composed of a first portion 135 penetrating the third interlayer dielectric layer 13 and the first window 120, and the minimum aperture D3 of the first portion is larger than the aperture D2 of the first window.
[0090] like Fig. 9 As shown, the first portion 135 of the first etched hole 134 is a vertical hole, and the minimum diameter D3 of the first portion is the average diameter of the first portion; Fig.10 As shown, based on the load effect when etching holes, the holes formed by etching are generally inverted "V" shape, so the first part 135 is a hole that is wide at the top and narrow at the bottom. At this time, the minimum diameter D3 of the first part is basically the diameter size of the bottom area. The minimum diameter D3 of the first part formed based on the second window 131 is larger than the diameter D2 of the first window, which provides a larger process window for the subsequent second etching, so as to facilitate the discharge of etching by-products.
[0091] As a preferred example, the maximum aperture of the first portion is larger than the aperture D2 of the first window and is larger than 5% of the aperture D2 of the first window to ensure that the first etched hole 134 formed based on the second window 131 completely covers the first window 120 .
[0092] As a specific example, the process of forming the first etching hole 134 includes: Figures 5 to 7 As shown, based on the first patterned photoresist layer 130, the second anti-reflective coating 133 and the APF film 132 are sequentially etched; Figure 8 As shown, the first patterned photoresist layer 130 is then removed, for example, the first patterned photoresist layer 130 may be removed by ashing or other processes; as shown Fig. 9 As shown, the APF film 132 and the second anti-reflective coating 133 are then used as hard masks to etch the third interlayer dielectric layer 13 until the surface of the first interlayer dielectric layer 11 is exposed. Here, a highly directional plasma etching process is preferably used, and the etching gas used for etching is selected according to the materials of different layers.
[0093] like Figures 11 to 13 As shown, step S7 is finally performed, the first interlayer dielectric layer 11 is etched based on the first etched hole 134, so as to form a second etched hole 136 penetrating the first interlayer dielectric layer 11, and the first etched hole 134 and the second etched hole 136 together constitute a conductive contact hole 14. When a silicon nitride layer 110 is further provided between the substrate 10 and the first interlayer dielectric layer 11, the second etched hole 136 needs to penetrate the first interlayer dielectric layer 11 and the silicon nitride layer 110.
[0094] Here, it is also preferred to use a plasma etching process with strong directionality, and the etching gas used for etching is selected according to the materials of different layers. During the etching process, the APF film 132 and the second anti-reflection coating 133 are used as hard masks. After the etching is completed, the APF film 132 and the second anti-reflection coating 133 are removed, so as to obtain Fig.12 or Fig.13 The conductive contact hole 14 is shown. Fig.12 As shown, the second etched hole 136 can be a vertical hole; however, when the hole depth is deep, based on the load effect when etching the hole, the hole generally etched is quasi-inverted "V" shape, so the second etched hole 136 is a hole that is wide at the top and narrow at the bottom, such as Fig.13 shown.
[0095] During this etching process, since the size of the first window controls the aperture of the second etching hole 136 formed by this etching, the difficulty of controlling the etching at the bottom of the conductive contact hole can be effectively reduced; in addition, since the aperture of the first etching hole 134 above the second etching hole 136 is larger, it is easy to discharge the by-products in the hole during the etching process, thereby reducing the load effect caused by the etching between different graphic areas and / or different wafers during the etching process, thereby increasing the process window during this etching and alleviating the problem of etching stop.
[0096] Based on the above-mentioned method for preparing a conductive contact hole, this embodiment further provides a semiconductor device, the semiconductor device comprising a conductive contact hole prepared by the above-mentioned method for preparing a conductive contact hole, such as Figure 3 , Fig. 9 , Fig.10 , Fig.12 and Fig.13 As shown, including:
[0097] A substrate 10 having a semiconductor structure 100 formed thereon;
[0098] A first interlayer dielectric layer 11 is formed on the substrate 10 and covers the semiconductor structure 100;
[0099] A second interlayer dielectric layer 12 having a first window 120 is formed on the surface of the first interlayer dielectric layer 11, and the first window 120 penetrates the second interlayer dielectric layer 12;
[0100] A third interlayer dielectric layer 13, formed on the surface of the second interlayer dielectric layer 12;
[0101] The conductive contact hole 14 is composed of a connected first etching hole 134 and a second etching hole 136, wherein the first etching hole 134 is composed of a first part 135 penetrating the third interlayer dielectric layer 13 and the first window 120, and the minimum diameter D3 of the first part 135 is larger than the diameter D2 of the first window, and the second etching hole 136 penetrates the first interlayer dielectric layer 11.
[0102] In summary, the present invention provides a method for preparing a conductive contact hole and a semiconductor device, wherein the preparation method arranges a second interlayer dielectric layer having a first window between the first interlayer dielectric layer and the third interlayer dielectric layer, so that the caliber of the second etched hole formed by the second etching can be controlled by the size of the first window, so as to reduce the difficulty of controlling the etching at the bottom of the conductive contact hole; in addition, the minimum caliber of the first part of the first etched hole formed after the first etching is made larger than the caliber of the first window of the second interlayer dielectric layer, so that when the second etched hole is formed by etching, it is easy to discharge the etching byproducts in the hole, and the load effect generated by etching between different graphic areas and / or different wafers during the etching process is reduced, thereby increasing the process window during the second etching and alleviating the problem of etching stop. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0103] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a conductive contact hole, characterized in that: The preparation method comprises the following steps: Providing a substrate, on which a semiconductor structure is formed; forming a first interlayer dielectric layer on the surface of the substrate, wherein the first interlayer dielectric layer covers the semiconductor structure; forming a second interlayer dielectric layer having a first window on the surface of the first interlayer dielectric layer, wherein the first window penetrates the second interlayer dielectric layer; forming a third interlayer dielectric layer on the surface of the second interlayer dielectric layer, and the third interlayer dielectric layer completely fills the first window; Forming a first patterned photoresist layer on the third interlayer dielectric layer, wherein a second window is formed on the first patterned photoresist layer, and the second window is located directly above the first window, and the diameter of the second window is larger than the diameter of the first window; Based on the second window, the third interlayer dielectric layer is etched until the surface of the first interlayer dielectric layer is exposed, thereby forming a first etched hole, wherein the first etched hole is composed of a first portion penetrating the third interlayer dielectric layer and the first window, and the minimum diameter of the first portion is larger than the diameter of the first window; The first interlayer dielectric layer is etched based on the first etch hole, thereby forming a second etch hole penetrating the first interlayer dielectric layer, and the first etch hole and the second etch hole together constitute a conductive contact hole.
2. The method for preparing a conductive contact hole according to claim 1, characterized in that: The maximum diameter of the first part is larger than the diameter of the first window and is greater than 5% of the diameter of the first window.
3. The method for preparing a conductive contact hole according to claim 1, wherein: The minimum thickness of the first interlayer dielectric layer is greater than the height of the semiconductor structure formed on the substrate, and is greater than 30% of the total thickness of the second interlayer dielectric layer and the third interlayer dielectric layer.
4. The method for preparing a conductive contact hole according to claim 1, characterized in that: The method for forming the second interlayer dielectric layer having the first window includes: forming a second interlayer dielectric layer on a surface of the first interlayer dielectric layer; forming an anti-reflective coating and a photoresist layer in sequence on the second interlayer dielectric layer, and patterning the photoresist layer to form a second patterned photoresist layer; Sequentially etching the anti-reflective coating and the second interlayer dielectric layer based on the second patterned photoresist layer; The second patterned photoresist layer and the remaining anti-reflective coating are removed, so that the remaining second interlayer dielectric layer is formed into the second interlayer dielectric layer having the first window.
5. The method for preparing a conductive contact hole according to claim 1, wherein: The first etching hole and the second etching hole are formed by a plasma etching process.
6. The method for preparing a conductive contact hole according to claim 5, characterized in that: The etching rate of the etching gas used in the plasma etching process on the third interlayer dielectric layer and the first interlayer dielectric layer is greater than the etching rate on the second interlayer dielectric layer.
7. The method for preparing a conductive contact hole according to claim 1, characterized in that: The substrate is a silicon substrate; the first interlayer dielectric layer is a silicon oxide layer; a silicon nitride layer is also formed between the first interlayer dielectric layer and the substrate; the second interlayer dielectric layer is a silicon nitride layer or a nitrogen-doped silicon carbide layer; and the third interlayer dielectric layer is a silicon oxide layer.
8. The method for preparing a conductive contact hole according to claim 7, characterized in that: The semiconductor structure protrudes from the surface of the substrate, the silicon oxide layer is divided into a first silicon oxide layer in contact with the silicon nitride layer and a second silicon oxide layer away from the silicon nitride layer, and the first silicon oxide layer is formed by adopting a HAPR process.
9. A semiconductor device, characterized in that: The semiconductor device includes a conductive contact hole prepared by the method for preparing a conductive contact hole according to any one of claims 1 to 8, including: a substrate having a semiconductor structure formed thereon; A first interlayer dielectric layer, formed on the substrate and covering the semiconductor structure; A second interlayer dielectric layer having a first window, formed on a surface of the first interlayer dielectric layer, and the first window penetrates the second interlayer dielectric layer; A third interlayer dielectric layer is formed on a surface of the second interlayer dielectric layer; The conductive contact hole is composed of a first etched hole and a second etched hole that are connected, wherein the first etched hole is composed of a first part that penetrates the third interlayer dielectric layer and the first window, and the minimum diameter of the first part is larger than the diameter of the first window, and the second etched hole penetrates the first interlayer dielectric layer.