Chip bearing structure

Abstract

A chip bearing structure is defined with a chip bearing area and a wire bonding area, and comprises an insulating layer; the circuit layer is arranged on the insulating layer; the solder mask layer is arranged on the insulating layer and the circuit layer, and a plurality of openings are formed in the wire bonding area; the protection layer is arranged at the part, exposed out of the solder mask layer, of the circuit layer; wherein the area of the protective layer in each opening is less than 70000uM2. According to the chip bearing structure, the area of the circuit layer and the protection layer exposed out of the opening can be reduced, the delamination problem caused by poor binding force between materials of the protection layer and the circuit layer is greatly reduced, the reliability of the chip bearing structure is improved, and the service life of the chip bearing structure is prolonged.

Description

Technical Field

[0001] The present invention relates to a chip carrying structure, and in particular to a chip carrying structure which reduces the area of ​​a circuit layer exposed to a solder mask layer. Background Art

[0002] With the rapid and massive popularization of 3C products, various carrier substrates for carrying electronic components and chips have also been developed and applied in large quantities. In current technologies and applications, the circuit layer in the carrier substrate is mainly made of copper or its alloys. This is because copper not only has good conductivity, but also has many advantages such as easy access, low cost, and easy processing. However, since the copper element also has the characteristics of high chemical activity, it is easily oxidized when exposed to the atmospheric environment to form copper oxide with extremely poor conductivity. Therefore, most of the exposed surfaces of the copper circuits are covered with an anti-oxidation layer to isolate the atmospheric environment. Gold plating on the surface of the copper circuit has become a common process.

[0003] In addition, as electronic circuits are becoming increasingly complex, the carrier substrate usually has multiple circuit layers to separate different parts of the circuit into different circuit layers and connect the sub-circuits that need to be connected through conductive vias. For power or ground circuits that are used in almost every circuit layer, a dedicated layer is usually set up, and in order to make the wiring of other complex circuit layers easier, a continuous and large-area metal (copper) layer is often formed in the power and / or ground layer, especially the ground layer. And the ground layer is often set on the outermost layer of the carrier substrate.

[0004] Figure 1 This is a partial enlarged schematic diagram of the surface of an existing wire bonding substrate. Figure 1 As shown, a solder mask 11 is provided on the surface of the existing wire bonding substrate, and the wire bonding position is exposed in an opening 110 on the solder mask 11, on which a lead 12 is welded, and a continuously distributed metal grounding surface 13 is also exposed around the wire bonding position. In order to prevent the copper in the exposed grounding surface 13 from being oxidized, the surface is usually plated with gold. However, since gold has poor bonding strength with almost all materials, and various stresses often exist between the interfaces of different materials, the plated gold layer and the copper layer below it often delaminate, causing the circuit of the entire carrier substrate to fail to operate correctly, and the reliability and life of the electronic components containing the carrier substrate or even the products using the electronic components are reduced. Therefore, how to overcome the problems of the above-mentioned prior art has become a topic that the industry is eager to solve. Summary of the invention

[0005] In view of the various deficiencies of the above-mentioned prior art, the present invention provides a chip carrier structure, which is defined as a chip carrier area and a wiring area arranged around the chip carrier area, including: an insulating layer; a circuit layer, which is arranged on the insulating layer; a solder mask, which is arranged on the insulating layer and the circuit layer, and has a plurality of openings formed in the wiring area to expose part of the circuit layer and part of the insulating layer; and a protective layer, which is arranged on the circuit layer that exposes the solder mask layer; wherein the circuit layer in each of the openings is formed with at least one spacing portion to divide the circuit layer exposed in the opening into at least two blocks, so as to reduce the area of ​​the circuit layer exposed in the opening and the protective layer stacked thereon.

[0006] In the aforementioned chip carrier structure, at least one bonding finger area is disposed above the protection layer.

[0007] In the aforementioned chip carrying structure, the protection layer is made of gold.

[0008] In the aforementioned chip carrier structure, the circuit layer is made of copper or a copper-containing alloy.

[0009] In the aforementioned chip carrying structure, the area of ​​the protection layer is smaller than or equal to the area of ​​the circuit layer exposed by the opening.

[0010] In the aforementioned chip carrying structure, the thickness of the protection layer is smaller than the thickness of the circuit layer.

[0011] In the aforementioned chip carrier structure, the thickness of the protection layer is between 0.3um and 1.2um.

[0012] In the aforementioned chip carrier structure, the area of ​​the protection layer in each of the openings is less than 70000uM 2 .

[0013] In the aforementioned chip carrying structure, the width of the spacer is greater than or equal to a minimum line distance.

[0014] In the aforementioned chip carrying structure, the width of the spacer is greater than or equal to 100 um.

[0015] In the aforementioned chip carrier structure, the ratio of the area of ​​the protection layer exposed to the opening to the area of ​​the insulation layer exposed to the opening is less than or equal to 20%.

[0016] Through the implementation of the present invention, a spacer can be added to the circuit layer in the opening of the solder mask in the wiring area to divide the circuit layer into at least two blocks, etc., so as to reduce the area of ​​the circuit layer exposed in the opening and the protective layer stacked thereon, and greatly reduce the delamination problem caused by the poor bonding strength between the materials of the protective layer and the circuit layer, so as to improve the reliability and life of the chip supporting structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1It is a partial enlarged schematic diagram of the surface of a conventional wire bonding substrate.

[0018] Figure 2A It is a top view schematic diagram of the chip supporting structure of the present invention.

[0019] Figure 2B for Figure 2A A partial enlarged schematic diagram of .

[0020] Figure 2C for Figure 2B A partial cross-sectional schematic diagram of .

[0021] Figure 3 It is a schematic diagram of a semiconductor package using the chip carrying structure of the present invention.

[0022] Main component symbols

[0023] 11, 25 solder mask

[0024] 110, 251 Opening

[0025] 12 Lead

[0026] 13 Ground plane

[0027] 2 Semiconductor Package

[0028] 20 Chip carrying structure

[0029] 21 Chip carrying area

[0030] 22. Wire Area

[0031] 23 Insulation layer

[0032] 24 Circuit layer

[0033] 241 Interval

[0034] 26 Protective layer

[0035] 261 Welding finger area

[0036] 30 chips

[0037] 31. Welding wire

[0038] w Width. DETAILED DESCRIPTION

[0039] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and technical effects of the present invention from the contents disclosed in this specification.

[0040] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the technical effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0041] Figure 2A A schematic top view of a chip supporting structure of the present invention; Figure 2B for Figure 2A A partial enlarged schematic diagram of Figure 2C for Figure 2B A partial cross-sectional schematic diagram of the area shown in FIG. Figures 2A to 2C As shown, this embodiment provides a chip carrier structure 20, on the surface of which a chip carrier area 21 and a wiring area 22 are defined. The chip carrier structure 20 includes: an insulating layer 23; a circuit layer 24, which is disposed on the insulating layer 23; a solder mask 25, which is disposed on the insulating layer 23 and the circuit layer 24, and has a plurality of openings 251 formed in the wiring area 22; and a protective layer 26, which is stacked on the circuit layer 24 with the solder mask 25 exposed.

[0042] The insulating layer 23 may be a dielectric layer made of a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc.

[0043] The circuit layer 24 is disposed on the insulating layer 23, and can be a power circuit, a ground circuit, or circuits of various other functions, or any combination of the above circuits, which is not limited in this embodiment. In order to balance conductivity and cost, the circuit layer 24 in this embodiment is made of copper or a copper-containing alloy. In other embodiments, the circuit layer 24 can also be made of other different conductive materials, which is not limited to those shown in this embodiment.

[0044] In addition, in most current applications, the chip carrier structure 20 is often a multi-layer structure. Therefore, in this embodiment, in addition to the circuit layer 24 disposed on the surface of the insulating layer 23, one or more circuit layers (not shown) may also be disposed in the insulating layer 23, depending on the needs, and this embodiment has no particular limitation on this.

[0045] The solder mask 25 is disposed on the insulating layer 23 and the circuit layer 24 , and has a plurality of openings 251 formed at locations in the bonding area 22 where soldering is required to be performed later, so as to expose the circuit layer 24 and a portion of the insulating layer 23 at those locations.

[0046] The circuit layer 24 in this embodiment is made of copper. In addition to copper, other copper-containing alloys can also be used, depending on the requirements for electrical and mechanical properties, etc., and this embodiment has no special limitation on this. In order to prevent the circuit layer 24 exposed in each opening 251 from being oxidized after contacting the atmosphere, thereby deteriorating the conductivity of the circuit layer 24 at these positions, a protective layer 26 is formed on the part of the circuit layer 24 exposed in the opening 251 of the solder mask 25 in this embodiment. In this embodiment, the protective layer 26 is formed by gold plating on the circuit layer 24. In other words, the material of the protective layer 26 is made of gold, so as to prevent the part of the circuit layer 24 exposed in the opening 251 from being oxidized by the stability of gold. Since gold is also a conductive metal material, using gold to form the protective layer 26 can not only have the technical effect of anti-oxidation, but also still maintain the required conductivity.

[0047] At least one soldering finger area 261 is provided above the protective layer 26 in each opening 251. Each soldering finger area 261 is a position that is predetermined to be soldered or wired in subsequent applications. Since it is difficult to accurately control the shape and size of the soldering point regardless of soldering or wire bonding, at each soldering or wire bonding position, the area of ​​the circuit layer 24 or the protective layer 26 exposed in the opening 251 where it is located will be reserved to be slightly larger than the soldering finger area 261. In this embodiment, since the protective layer 26 is formed by gold plating, that is, gold must be plated on the circuit layer 24 and attached to the circuit layer 24, the area of ​​the protective layer 26 exposed in the opening 251 is larger than the area of ​​the soldering finger area 261 and at the same time is less than or equal to the area of ​​the circuit layer 24 exposed in the opening 251. Preferably, the area of ​​the protective layer 26 is equal to the area of ​​the circuit layer 24 exposed in the opening 251.

[0048] In addition, since gold has poor bonding strength with almost all materials, the protective layer 26 formed by gold plating has the risk of delamination from the circuit layer 24. For this reason, the area of ​​the protective layer 26 in this embodiment is limited as much as possible, for example, the ratio of the area of ​​the protective layer 26 exposed to the opening 251 to the area of ​​the insulating layer 23 exposed to the opening 251 is less than or equal to 20%. Preferably, the area of ​​the protective layer 26 corresponding to each solder finger area 261 in each opening 251 in the embodiment is less than 70000um. 2 .

[0049] Similarly, considering the risk of delamination of the protective layer 26 formed by gold plating, the thickness of the protective layer 26 is also limited in this embodiment. Figure 2C As shown, the thickness of the protective layer 26 in this embodiment is limited to be less than the thickness of the circuit layer 24. This is to prevent the mass of the protective layer 26 attached to each unit area of ​​the circuit layer 24 from being too high, thereby preventing the circuit layer 24 per unit area from being unable to bear the excessive pulling of the protective layer 26 above and delamination from the circuit layer 24. Preferably, the thickness of the protective layer 26 in this embodiment is between 0.3um and 1.2um.

[0050] Also, see Figure 2B , also in order to avoid the problem of delamination of the protective layer 26 formed by gold plating, the present embodiment may also form at least one spacer 241 on the circuit layer 24 exposed to the opening 251, so as to divide the circuit layer 24 exposed in the opening 251 into at least two blocks. Its function is to limit the area of ​​the circuit layer 24 in the opening 251 and the protective layer 26 attached thereto, so as to avoid a continuous and large area of ​​the circuit layer 24 and the protective layer 26 above it existing in the opening 251. When the area of ​​the circuit layer 24 and the protective layer 26 stacked thereon is reduced, the probability of delamination naturally decreases. This improves the reliability and life of the chip carrier structure 20 of the present embodiment.

[0051] In practice, each circuit layer 24 on a chip carrier structure has a minimum line spacing restriction when wiring, so as to avoid the wiring of the circuit being too close to each other, so that the potential difference, induced electric field, induced magnetic field and / or capacitance between adjacent wirings will cause signal distortion or interference in transmission. Therefore, this embodiment must also comply with these electrical characteristic restrictions when reducing the shrinkage of the circuit layer 24 and the protective layer 26. At the same time, if the area of ​​the circuit layer 24 and the protective layer 26 is reduced too little, the effect of preventing the delamination of the protective layer 26 is also limited. Therefore, in this embodiment, the width w of the spacer 241 is preferably greater than, or at least must be equal to, a minimum line spacing. Specifically, the width w of the spacer 241 in this embodiment is preferably greater than or equal to 100um.

[0052] In summary, the chip carrier structure 20 of the present embodiment reduces the area of ​​the circuit layer 24 exposed in the opening 251 by, for example, adding a spacer 241 to the circuit layer in the opening 251 of the solder mask 25 in the bonding area 22 to divide the circuit layer 24 into at least two blocks, thereby greatly reducing the delamination problem caused by the poor bonding strength between the protective layer 26 and the circuit layer 24 material, thereby improving the reliability and life of the chip carrier structure 20.

[0053] The chip supporting structure 20 obtained by this embodiment can be used, for example, Figure 3The semiconductor package 2 shown in FIG. 2 is a semiconductor package 2 in which a chip 30 is fixedly mounted on a chip carrier area 21 on a surface of a chip carrier structure 20, and a plurality of bonding wires 31 are connected to bonding finger areas 261 exposed in openings 251 of each solder mask area in the bonding area 22 by a bonding technique (see FIG. 2 ). Figure 2B ) and achieve electrical connection with the circuit layer 24 of the chip carrier structure 20 of the embodiment of the present invention. This makes the reliability and life of the semiconductor package 2 using the chip carrier structure 20 of the present invention also improved.

[0054] The above embodiments are only used to illustrate the principles and technical effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the inventive concept and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A chip carrier structure, comprising a chip carrier area and a bonding area around the chip carrier area, comprising: Insulation layer; A circuit layer is provided on the insulating layer; A solder mask layer is disposed on the insulating layer and the circuit layer, and a plurality of openings are formed in the wiring area to expose a portion of the circuit layer and a portion of the insulating layer; as well as A protective layer is stacked on the circuit layer where the opening of the solder mask is exposed; At least one spacer is formed on the circuit layer exposed outside each opening to divide the circuit layer exposed in the opening into at least two blocks to reduce the area of ​​the circuit layer exposed in the opening and the protection layer stacked on the circuit layer.

2. The chip carrier structure according to claim 1, wherein: At least one welding finger area is arranged above the protection layer.

3. The chip carrying structure according to claim 1, wherein: The protective layer consists of gold.

4. The chip carrying structure according to claim 1, wherein: The circuit layer is made of copper or a copper-containing alloy.

5. The chip carrying structure according to claim 1, wherein: The area of ​​the protection layer is smaller than or equal to the area of ​​the circuit layer exposed from the opening.

6. The chip carrying structure according to claim 1, wherein: The thickness of the protection layer is smaller than the thickness of the circuit layer.

7. The chip carrying structure according to claim 1, wherein: The thickness of the protective layer is between 0.3um and 1.2um.

8. The chip carrying structure according to claim 1, wherein: The area of ​​the protective layer in each opening is less than 70000um 2 .

9. The chip carrying structure according to claim 1, wherein: The width of the spacer is greater than or equal to a minimum line distance.

10. The chip supporting structure according to claim 1, wherein: The width of the spacer is greater than or equal to 100 um.

11. The chip supporting structure according to claim 1, wherein: The ratio of the area of ​​the protection layer exposed outside the opening to the area of ​​the insulation layer exposed outside the opening is less than or equal to 20%.

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