Miniaturized photoelectric co-packaged semiconductor device and packaging method thereof

Abstract

The invention relates to a miniaturized photoelectric co-packaged semiconductor device and a packaging method thereof.The miniaturized photoelectric co-packaged semiconductor device comprises a substrate 1, a metallization processing layer 2 is arranged on the upper surface layer of the substrate 1, a PI stacked structure 3 is arranged on the metallization processing layer 2, the PI stacked structure 3 is provided with a windowing part 301, and the windowing part 301 is provided with a window opening part 301. A semiconductor laser chip 4 is arranged at the windowing part 301; the surface layer of the PI laminated structure 3 is bonded with an interconnection circuit of a circuit element left after a copper layer is corroded and a radio frequency transmission line structure, and is distributed with a metallization area for interconnection of the semiconductor laser chip 4, the interconnection circuit and the radio frequency transmission line structure; and the metalized region is interconnected with the semiconductor laser chip 4 through a gold wire 5. According to the invention, the photoelectric co-packaging device with smaller size and higher intensity can be provided, high-frequency crosstalk can be reduced, and transmission loss can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of optical communication technology, and in particular to a miniaturized optoelectronic co-sealed semiconductor device and a packaging method thereof. Background Art

[0002] With the requirements for high-bandwidth computing, transmission, and storage in the 5G era, the number of channels on the board has also increased significantly. In the existing technology, a dedicated integrated circuit is usually used to control multiple optical transceiver modules to meet the requirements. In terms of packaging, it is also necessary to package the optical chip or optical module together with each circuit element to achieve optoelectronic co-sealing to increase the interconnection density.

[0003] In existing optoelectronic co-sealing devices, it is generally necessary to design components such as device tubes and soft belts. The density is not high enough and the size is not small enough, which gradually cannot meet the needs of miniaturization and integration. In addition, in the existing optoelectronic co-sealing process, the device packaging steps and packaging time are also relatively long. These traditional processes are a waste of time and material costs. In addition, the packaging performed by traditional processes may also have problems such as high-frequency crosstalk and large transmission loss.

[0004] In view of this, how to overcome the defects of the above-mentioned prior art and how to solve at least one of the above-mentioned technical problems is a difficult problem to be solved urgently in the field of this technology. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a miniaturized optoelectronic co-sealed semiconductor device and a packaging method thereof, which reduces the device tube shell, soft belt and other components in the traditional technology, thereby providing a smaller and more dense optoelectronic co-sealed device. In addition, by realizing the interconnection circuit of the circuit elements and the radio frequency transmission line structure on the PI stacking structure, it is possible to reduce high-frequency crosstalk and transmission loss. At the same time, the position of the radio frequency transmission line structure is raised by using the PI stacking structure, reducing the length of the gold wire from the radio frequency transmission line structure to the semiconductor laser chip, and reducing the influence of the parasitic inductance of the gold wire on the high-frequency signal. On the other hand, compared with the traditional packaging process, the packaging process provided by the present invention has reduced time cost and material cost, which is more conducive to the mass production of optoelectronic co-sealed devices.

[0006] The present invention is achieved in that:

[0007] In the first aspect, the present invention provides a miniaturized optoelectronic co-sealed semiconductor device, comprising a substrate 1, wherein a metallization treatment layer 2 is provided on the surface of the substrate 1, a PI stacking structure 3 is provided on the metallization treatment layer 2, the PI stacking structure 3 is provided with a window portion 301, and a semiconductor laser chip 4 is provided at the window portion 301; the surface of the PI stacking structure 3 is bonded with an interconnection circuit and a radio frequency transmission line structure of circuit elements remaining after the copper layer is corroded, and a metallization area for interconnecting the semiconductor laser chip 4 with the interconnection circuit and the radio frequency transmission line structure is distributed; the metallization area is interconnected with the semiconductor laser chip 4 through a gold wire 5.

[0008] In some embodiments, a thin film resistor is provided at a position of the metallization treatment layer 2 on the substrate 1 corresponding to the semiconductor laser chip 4, the thin film resistor is connected to the metallization treatment layer 2, and a gold-tin solder coating 6 is provided between the thin film resistor and the semiconductor laser chip 4; when current is passed through the thin film resistor, heat is generated to melt the gold-tin solder coating 6, and the semiconductor laser chip 4 is used for welding.

[0009] In some embodiments, the thin film resistor is a disposable resistor, which is only used to complete the welding of the semiconductor laser chip 4 .

[0010] In some embodiments, a V-groove structure 101 is provided on the substrate 1 . The V-groove structure 101 is located on one side of the semiconductor laser chip 4 and is used for mounting optical path components.

[0011] In some embodiments, the V-groove structure 101 includes a grid film layer 1011 of ultraviolet optical glue forming a V-groove shape; the production of the grid film layer 1011 of ultraviolet optical glue includes: using ultraviolet glue to coat the grid structure of a high-precision mold, and forming a grid structure of ultraviolet glue after coating, and the grid structure forms a V-groove shape; V-grooves of different sizes are obtained by adjusting the grid structure of the high-precision mold; after ultraviolet curing and thermal curing of the coated ultraviolet glue, a grid film layer 1011 of ultraviolet optical glue with a stable structure is obtained.

[0012] In some embodiments, the optical path elements include a front lens 7, an isolator 8, a collimator 9 and an optical fiber 10 which are arranged in sequence.

[0013] In some embodiments, the remaining circuit elements except the semiconductor laser chip 4 are mounted on the PI stacked structure 3 using SMT technology.

[0014] In some embodiments, the surface of the PI stacked structure 3 is covered with green oil 11 , and a circle of metallization structure 12 is provided on the surface of the green oil 11 , and a protective cover plate 13 is installed through the metallization structure 12 .

[0015] In some embodiments, the substrate 1 and the PI stacked structure 3 together form a gold finger area 14 on one side, and the gold finger area 14 is located outside the protective cover 13 .

[0016] In a second aspect, the present invention provides a packaging method for a miniaturized optoelectronic co-sealed semiconductor device, which is applied to the miniaturized optoelectronic co-sealed semiconductor device described in the first aspect, and the method comprises:

[0017] Processing a V-groove structure 101 for mounting optical path components on the substrate 1;

[0018] Performing metallization treatment on the upper surface of the substrate 1 to form a metallization treatment layer 2;

[0019] A PI stacked structure 3 is constructed on the metallization treatment layer 2, an interconnection circuit of circuit elements and a radio frequency transmission line structure are implemented on the PI stacked structure 3, and a window portion 301 is reserved;

[0020] The remaining circuit components except the semiconductor laser chip 4 are mounted on the PI stacked structure 3 by using the SMT process; the semiconductor laser chip 4 is mounted on the window portion 301;

[0021] The optical path components are coupled and fixed at the V-groove structure 101 , and finally the protective cover plate 13 is installed.

[0022] In some embodiments, mounting the semiconductor laser chip 4 on the window portion 301 specifically includes:

[0023] A thin film resistor and a gold-tin solder plating layer 6 are pre-arranged at the window portion 301;

[0024] The thin film resistor is energized to heat the gold-tin solder plating layer 6;

[0025] After the AuSn solder plating layer 6 is melted, the semiconductor laser chip 4 is mounted on the AuSn solder plating layer 6 .

[0026] Compared with the prior art, the beneficial effects of the present invention are: providing a miniaturized optoelectronic co-sealed semiconductor device and a packaging method thereof, reducing the device tube shell, soft belt and other components in the traditional technology, thereby providing a smaller and more dense optoelectronic co-sealed device. In addition, by realizing the interconnection circuit of the circuit elements and the radio frequency transmission line structure on the PI stacking structure, it is possible to reduce high-frequency crosstalk and transmission loss. At the same time, the position of the radio frequency transmission line structure is raised by using the PI stacking structure, reducing the length of the gold wire from the radio frequency transmission line structure to the semiconductor laser chip, and reducing the influence of the parasitic inductance of the gold wire on the high-frequency signal. On the other hand, compared with the traditional packaging process, the packaging process provided by the present invention has reduced time cost and material cost, which is more conducive to the mass production of optoelectronic co-sealed devices.

[0027] Furthermore, a thin film resistor and a gold-tin solder coating are pre-arranged at the window portion, and after the remaining circuit components except the semiconductor laser chip are installed, the thin film resistor is energized to heat the gold-tin solder coating, and then the semiconductor laser chip is mounted on the gold-tin solder coating. In this way, when installing the semiconductor laser chip, the heating temperature is concentrated at the location where the thin film resistor is set, which can avoid affecting the remaining installed circuit components. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A schematic diagram of a substrate of a miniaturized optoelectronic co-sealed semiconductor device provided by an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of a substrate and PI stacking structure provided in an embodiment of the present invention;

[0031] Figure 3 A cross-sectional view of a substrate and PI stacking structure provided in an embodiment of the present invention;

[0032] Figure 4 A schematic diagram of a grid film layer of a UV optical adhesive provided by an embodiment of the present invention;

[0033] Figure 5 A schematic diagram of a PI stacked structure provided in an embodiment of the present invention covered with green oil;

[0034] Figure 6 A schematic diagram of a miniaturized optoelectronic co-sealed semiconductor device provided by an embodiment of the present invention after a protective cover is installed;

[0035] Figure 7 A flow chart of a packaging method for a miniaturized optoelectronic co-sealed semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as open inclusion, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner, that is, although they may be carried in the embodiments or examples of the above terms due to reasons such as the order and position of appearance, it is not limited to that they can be carried in combination by one embodiment or example.

[0037] In the description of the present invention, the terms "inside", "outside", "longitudinal", "lateral", "up", "down", "left", "right", "top", "bottom" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and do not require that the present invention must be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present invention.

[0038] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several variations and improvements may be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0039] It should be noted that, if there is no conflict, the various features in the embodiments of the present invention can be combined with each other, all within the scope of protection of this application. Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by technicians in the technical field of the present invention. The terms and directions used in this specification are only for the purpose of describing specific implementation methods and are not intended to limit the present invention.

[0040] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] Example 1

[0042] refer to Figure 1 , Figure 2 and Figure 3As shown, embodiment 1 of the present invention provides a miniaturized optoelectronic co-sealed semiconductor device, including a substrate 1, a metallization treatment layer 2 is provided on the surface of the substrate 1, a PI stacking structure 3 is provided on the metallization treatment layer 2, the PI stacking structure 3 is provided with a window portion 301, and a semiconductor laser chip 4 is provided at the window portion 301; the surface of the PI stacking structure 3 is bonded with an interconnection circuit and a radio frequency transmission line structure of circuit elements left after the copper layer is corroded, and a metallization area for interconnecting the semiconductor laser chip 4 with the interconnection circuit and the radio frequency transmission line structure is distributed; the metallization area is interconnected with the semiconductor laser chip 4 through a gold wire 5. The PI stacking structure 3 uses polyimide (abbreviated as: PI) material for multi-layer circuit stacking, which can realize more miniaturized and lower-cost active device packaging.

[0043] In the above configuration, the substrate 1 uses aluminum nitride (ALN) or silicon as a substrate, for example, aluminum nitride is used, and the surface layer of the aluminum nitride is metallized to form a metallized layer 2. A PI stacked structure 3 is arranged on the metallized layer 2, and the surface layer of the structure is bonded with the interconnection circuit and RF transmission line structure of the electronic components left after the copper layer is corroded. The PI stacked structure 3 needs to open a window to expose the mounting part of the semiconductor laser chip 4, and is distributed with a metallized area for interconnecting the semiconductor laser chip 4 with the circuit, which is interconnected with the semiconductor laser chip 4 through a gold wire bonding process. At the same time, the interconnection structure of the electronic components is also connected to the gold finger area 14 at the edge of the substrate 1. Compared with the traditional process, the RF transmission line structure of this embodiment is wrapped by the stratum, which reduces high-frequency crosstalk and transmission loss. At the same time, the PI stacked structure 3 is used to lift the position of the RF link, reduce the length of the gold wire 5 of the gold wire interconnection from the RF link to the semiconductor laser chip 4, and reduce the influence of the parasitic inductance of the gold wire 5 on the high-frequency signal. At the same time, since the metallized part of the aluminum nitride layer is laid with a large area of ​​stratum, compared with the traditional technology of using hole filling or metallized hole to ground the chip, this design makes the chip grounded more fully and can obtain better bandwidth. In order to reduce the parasitic inductance of the gold wire in the gold wire interconnection structure, this embodiment uses the PI stacking structure 3 to construct a transmission line structure with a small height difference with the chip, reduce the length of the gold wire, thereby reducing the high-frequency parasitic inductance, so that the chip can obtain a higher bandwidth. This embodiment can make the substrate bandwidth from the traditional design 40G bandwidth to more than 67G bandwidth, and can achieve single-wave 200G high-frequency transmission.

[0044] In some embodiments, the metallization layer 2 on the substrate 1 is provided with a thin film resistor at a position corresponding to the semiconductor laser chip 4, the thin film resistor is connected to the metallization layer 2, and a gold-tin solder coating 6 is provided between the thin film resistor and the semiconductor laser chip 4; the thin film resistor can generate heat and melt the gold-tin solder coating 6 after current is passed through it, which is used to weld the semiconductor laser chip 4. In this embodiment, the remaining circuit elements except the semiconductor laser chip 4 are mounted on the PI stacked structure 3 using the surface mount technology (Surface Mounted Technology, abbreviated as: SMT) process. Specifically, electronic components such as resistors and capacitors can be reflow soldered; and for the optical chip, a high-resistance resistor current is provided by a current source, that is, the high-resistance resistor of the thin film resistor is heated to achieve heating of the substrate and melting of the gold-tin solder for mounting the active device optical chip. Through the above-mentioned settings, this embodiment integrates the semiconductor laser chip 4 and the electrical chip (other circuit elements) for control and calculation, and realizes the photoelectric co-sealing technology. The RF transmission loss of the entire system is reduced, and the transmission quality of the signal is improved.

[0045] Generally speaking, the remaining circuit elements are mounted first by the SMT process, and then the semiconductor laser chip 4 is mounted. In this mounting process, it is necessary to heat up the surface of the entire substrate 1 for welding operations. When the remaining circuit elements are mounted by the SMT process, when the semiconductor laser chip 4 is mounted, the welding points of the remaining circuit elements that have been mounted will melt again due to the temperature increase, which is prone to problems. Based on this, in this embodiment, a thin film resistor and a gold-tin solder coating 6 are set at the position corresponding to the need to mount the semiconductor laser chip 4. When the semiconductor laser chip 4 needs to be mounted, it is only necessary to energize the thin film resistor to heat the gold-tin solder coating 6, so that the gold-tin solder coating 6 melts, and then completes the mounting of the semiconductor laser chip 4. In this way, the heating range is limited to the thin film resistor area, and will not affect the remaining circuit elements that have been mounted in other places. It should also be noted that the above-mentioned thin film resistor is a disposable resistor, which is only used to complete the welding of the semiconductor laser chip 4. After the semiconductor laser chip 4 is welded and mounted, it is discarded and will not be used later.

[0046] refer to Figure 1 and Figure 2 As shown, in some embodiments, a V-groove structure 101 is provided on the substrate 1, and the V-groove structure 101 is located on one side of the semiconductor laser chip 4 and is used to install optical path components. If the substrate 1 is a silicon substrate, the V-groove structure 101 will be etched on the silicon substrate; if the substrate 1 is an aluminum nitride substrate, a multi-layer ceramic stacking structure can be used on the substrate to construct the V-groove structure 101. When the PI stacking structure 3 is provided, the V-groove structure 101 is not covered.

[0047] In some embodiments, the V-groove structure 101 includes a grid film layer 1011 of ultraviolet optical glue forming a V-groove shape; the production of the grid film layer 1011 of ultraviolet optical glue includes: using ultraviolet glue to coat the grid structure of a high-precision mold, and forming a grid structure of ultraviolet glue after coating, and the grid structure forms a V-groove shape; V-grooves of different sizes are obtained by adjusting the grid structure of the high-precision mold; after ultraviolet curing and thermal curing of the coated ultraviolet glue, a grid film layer 1011 of ultraviolet optical glue with a stable structure is obtained. The explanation for the above settings is as follows: In order to facilitate cost control and make the application more flexible, the V-groove structure 101 can also be replaced by a grid film layer of glue processed by a special process. Figure 4 As shown, the grid film layer 1011 of the ultraviolet optical glue is arranged on the substrate 1, and the optical path element 100 is arranged between the grid film layers 1011 of the ultraviolet optical glue; for the production of the grid film layer 1011 of the ultraviolet optical glue, the process of this embodiment adopts ultraviolet glue with low hardness and expansion coefficient, and is coated on a high-precision processed mold, and after the coating is completed, a Figure 4 The grid structure shown in the figure forms a certain V-groove shape. Different sizes of V-grooves can be obtained by adjusting the grid structure of the high-precision mold. After the coated glue is UV-cured and thermally cured, a structurally stable V-groove structure can be obtained, that is, the grid film layer 1011 of the UV optical glue. The invention of this process overcomes the disadvantage that V-grooves can only be processed on silicon substrates. It breaks the limitation of the V-groove angle by the silicon lattice structure. The process is simple and highly operable. At the same time, the cost is also greatly reduced.

[0048] refer to Figure 5 As shown, the V-groove structure 101 provides a support structure for the optical path element; in some embodiments, the optical path element includes a front lens 7, an isolator 8, a collimator 9 and an optical fiber 10 arranged in sequence. The light emitted by the semiconductor laser chip 4 is converted into collimated light through the front lens 7, and the collimated light passes through the isolator 8 and then converges to the optical fiber 10 through the collimator 9.

[0049] refer to Figure 5 and Figure 6 As shown, in some embodiments, the surface of the PI stacked structure 3 is covered with green oil 11, and a circle of metallization structure 12 is arranged on the surface of the green oil 11, and a protective cover plate 13 is installed through the metallization structure 12. Among them, the green oil 11 is a liquid photoresist, an acrylic acid oligomer, and a by-product of acetylene hydrogenation; the green oil can be used as a protective layer of the circuit board to prevent physical disconnection and short circuit. The protective cover plate 13 can be fixed on the metallization structure 12 by welding.

[0050] refer to Figure 6As shown, in some embodiments, the substrate 1 and the PI stacked structure 3 together form a gold finger area 14 on one side, and the gold finger area 14 is located outside the protective cover 13. Under the above settings, this embodiment has a pluggable gold finger structure to replace the soft tape or gold wire interconnection of traditional devices. The gold finger area 14 of the device can be directly connected to the high-frequency card holder on the mainboard to facilitate device replacement.

[0051] Under the configuration of this embodiment, the optoelectronic co-sealing of the device can be realized at the wafer level, which greatly reduces the device packaging steps and packaging time, while increasing the integration density on or between boards, increasing the packaging bandwidth of the optical active device, and reducing the power consumption of the active device. Compared with the existing mature packaging technology, this embodiment provides a smaller and more dense semi-airtight active device packaging technology, which reduces the device tube shell, soft belt, and other components in the traditional technology, and the size is equivalent to 1 / 2 or less of the traditional module size.

[0052] In summary, the embodiments of the present invention provide a miniaturized optoelectronic co-sealed semiconductor device, which reduces the device tube shell, soft tape and other components in the traditional technology, thereby providing an optoelectronic co-sealed device with smaller size and higher density. In addition, by realizing the interconnection circuit of the circuit elements and the RF transmission line structure on the PI stacking structure, it is possible to reduce high-frequency crosstalk and transmission loss. At the same time, the PI stacking structure is used to elevate the position of the RF transmission line structure, reduce the length of the gold wire from the RF transmission line structure to the semiconductor laser chip, and reduce the influence of the parasitic inductance of the gold wire on the high-frequency signal. On the other hand, compared with the traditional packaging process, the packaging process based on the miniaturized optoelectronic co-sealed semiconductor device has reduced time cost and material cost, which is more conducive to the mass production of optoelectronic co-sealed devices.

[0053] Furthermore, a thin film resistor and a gold-tin solder coating are pre-arranged at the window portion, and after the remaining circuit components except the semiconductor laser chip are installed, the thin film resistor is energized to heat the gold-tin solder coating, and then the semiconductor laser chip is mounted on the gold-tin solder coating. In this way, when installing the semiconductor laser chip, the heating temperature is concentrated at the location where the thin film resistor is set, which can avoid affecting the remaining installed circuit components.

[0054] Example 2

[0055] refer to Figure 7 As shown, this embodiment provides a packaging method for a miniaturized optoelectronic co-sealed semiconductor device, which is applied to the miniaturized optoelectronic co-sealed semiconductor device described in Example 1, and the method includes the following steps.

[0056] Step 100: Processing a V-groove structure 101 for mounting optical path components on a substrate 1. In this step, an aluminum nitride substrate is laminated under high pressure to form a structure with a V-groove, or a silicon substrate is processed into a V-groove structure by etching or other processes.

[0057] Step 200: metallizing the upper surface of the substrate 1 to form a metallized layer 2. In this step, after the metallized pattern is processed, a thin film resistor and gold-tin solder are pre-placed at the position where the semiconductor laser chip 4 is to be mounted.

[0058] Step 300: construct a PI stacking structure 3 on the metallization treatment layer 2, implement the interconnection circuit of the circuit elements and the radio frequency transmission line structure on the PI stacking structure 3, and reserve a window portion 301. In this step, a protective glue can be added first, and then the PI stacking structure is constructed to achieve high-frequency circuit matching and circuit element connection. The reserved window portion 301 is reserved at the position where the semiconductor laser chip 4 is to be installed.

[0059] Step 400: Mount the remaining circuit components except the semiconductor laser chip 4 on the PI stacked structure 3 using the SMT process; mount the semiconductor laser chip 4 on the window portion 301. In this step, the SMT reflow soldering and post-soldering cleaning of electronic chips such as resistors, capacitors, clock and data recovery (CDR) or optical digital signal processing (ODSP) can be performed first, and then the gold-tin solder of the semiconductor laser chip 4 is melted by applying current to achieve the mounting of the semiconductor laser chip 4.

[0060] Step 500: Couple and fix the optical path elements at the V-groove structure 101, and finally install the protective cover 13. In this step, the optical path elements include a front lens 7, an isolator 8, a collimator 9 and an optical fiber 10 arranged in sequence. The light emitted by the semiconductor laser chip 4 is converted into collimated light through the front lens 7. After the collimated light passes through the isolator 8, it is converged to the optical fiber 10 through the collimator 9. For the installation of the protective cover 13, the surface of the PI stacked structure 3 can be covered with green oil 11, and a circle of metallized structure 12 is set on the surface of the green oil 11. The protective cover 13 can be fixed on the metallized structure 12 by welding. The protective cover 13 mainly plays a role in dustproof and airtightness.

[0061] In some embodiments, mounting the semiconductor laser chip 4 on the window portion 301 specifically includes: pre-arranging a thin film resistor and a gold-tin solder coating 6 on the window portion 301; energizing the thin film resistor to heat the gold-tin solder coating 6; and mounting the semiconductor laser chip 4 on the gold-tin solder coating 6 after the gold-tin solder coating 6 melts. This processing method will not affect other components when mounting the semiconductor laser chip 4.

[0062] In summary, the embodiments of the present invention provide a miniaturized optoelectronic co-sealed semiconductor device, which reduces the device tube shell, soft tape and other components in the traditional technology, thereby providing an optoelectronic co-sealed device with smaller size and higher density. In addition, by realizing the interconnection circuit of the circuit elements and the RF transmission line structure on the PI stacking structure, it is possible to reduce high-frequency crosstalk and transmission loss. At the same time, the PI stacking structure is used to elevate the position of the RF transmission line structure, reduce the length of the gold wire from the RF transmission line structure to the semiconductor laser chip, and reduce the influence of the parasitic inductance of the gold wire on the high-frequency signal. On the other hand, compared with the traditional packaging process, the packaging process based on the miniaturized optoelectronic co-sealed semiconductor device has reduced time cost and material cost, which is more conducive to the mass production of optoelectronic co-sealed devices.

[0063] Furthermore, a thin film resistor and a gold-tin solder coating are pre-arranged at the window portion, and after the remaining circuit components except the semiconductor laser chip are installed, the thin film resistor is energized to heat the gold-tin solder coating, and then the semiconductor laser chip is mounted on the gold-tin solder coating. In this way, when installing the semiconductor laser chip, the heating temperature is concentrated at the location where the thin film resistor is set, which can avoid affecting the remaining installed circuit components.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Under the concept of the present invention, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A miniaturized optoelectronic co-sealed semiconductor device, characterized in that: The invention comprises a substrate (1), wherein a metallization treatment layer (2) is arranged on the surface of the substrate (1), a PI stacking structure (3) is arranged on the metallization treatment layer (2), the PI stacking structure (3) is provided with a window portion (301), and a semiconductor laser chip (4) is arranged at the window portion (301); the surface of the PI stacking structure (3) is bonded with an interconnection circuit and a radio frequency transmission line structure of circuit elements remaining after the copper layer is corroded, and a metallization area for interconnecting the semiconductor laser chip (4) with the interconnection circuit and the radio frequency transmission line structure is distributed; the metallization area is interconnected with the semiconductor laser chip (4) via a gold wire (5).

2. The miniaturized optoelectronic co-sealed semiconductor device according to claim 1, characterized in that: The metallized layer (2) on the substrate (1) is provided with a thin film resistor at a position corresponding to the semiconductor laser chip (4); the thin film resistor is connected to the metallized layer (2); a gold-tin solder coating (6) is provided between the thin film resistor and the semiconductor laser chip (4); when current is passed through the thin film resistor, heat is generated to melt the gold-tin solder coating (6) for soldering the semiconductor laser chip (4).

3. The miniaturized optoelectronic co-sealed semiconductor device according to claim 2, characterized in that: The thin film resistor is a disposable resistor and is only used to complete the welding of the semiconductor laser chip (4).

4. The miniaturized optoelectronic co-sealed semiconductor device according to claim 1, characterized in that: A V-groove structure (101) is provided on the substrate (1); the V-groove structure (101) is located on one side of the semiconductor laser chip (4) and is used for mounting optical path elements.

5. The miniaturized optoelectronic co-sealed semiconductor device according to claim 4, characterized in that: The V-groove structure (101) comprises a grid film layer (1011) of ultraviolet optical glue forming a V-groove shape; the production of the grid film layer (1011) of ultraviolet optical glue comprises: coating the grid structure of a high-precision mold with ultraviolet glue, forming a grid structure of the ultraviolet glue after coating, and the grid structure forming a V-groove shape; V-grooves of different sizes are obtained by adjusting the grid structure of the high-precision mold; and after ultraviolet curing and heat curing the coated ultraviolet glue, a grid film layer (1011) of ultraviolet optical glue with a stable structure is obtained.

6. The miniaturized optoelectronic co-sealed semiconductor device according to claim 3, characterized in that: The optical path element comprises a front lens (7), an isolator (8), a collimator (9) and an optical fiber (10) which are arranged in sequence.

7. The miniaturized optoelectronic co-sealed semiconductor device according to any one of claims 1 to 6, characterized in that: The remaining circuit elements except the semiconductor laser chip (4) are mounted on the PI stacked structure (3) using the SMT process.

8. The miniaturized optoelectronic co-sealed semiconductor device according to any one of claims 1 to 6, characterized in that: The surface of the PI stacked structure (3) is covered with green oil (11), and a circle of metallization structure (12) is arranged on the surface of the green oil (11), and a protective cover plate (13) is installed through the metallization structure (12); the substrate (1) and the PI stacked structure (3) together form a gold finger area (14) on one side, and the gold finger area (14) is located outside the protective cover plate (13).

9. A packaging method for a miniaturized optoelectronic co-sealed semiconductor device, applied to the miniaturized optoelectronic co-sealed semiconductor device according to any one of claims 1 to 8, characterized in that: include: Processing a V-groove structure (101) for mounting an optical path element on a substrate (1); Performing metallization treatment on the upper surface of the substrate (1) to form a metallization treatment layer (2); Constructing a PI stacked structure (3) on the metallization treatment layer (2), realizing an interconnection circuit of circuit elements and a radio frequency transmission line structure on the PI stacked structure (3), and reserving a window portion (301); Mounting the remaining circuit elements except the semiconductor laser chip (4) on the PI stacked structure (3) using the SMT process; mounting the semiconductor laser chip (4) on the window opening portion (301); The optical path elements are coupled and fixed at the V-groove structure (101), and finally the protective cover plate (13) is installed.

10. The packaging method of miniaturized optoelectronic co-sealed semiconductor device according to claim 9, characterized in that: The step of mounting the semiconductor laser chip (4) on the window opening portion (301) specifically comprises: Pre-arranging a thin film resistor and a gold-tin solder plating layer (6) at the window opening portion (301); Applying power to the thin film resistor to heat the gold-tin solder plating layer (6); After the gold-tin solder plating layer (6) is melted, the semiconductor laser chip (4) is mounted on the gold-tin solder plating layer (6).

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