Voltage generation circuit and electronic equipment

Abstract

The invention discloses a voltage generation circuit and electronic equipment. The voltage generation circuit comprises a first voltage conversion branch, a second voltage conversion branch and a third voltage conversion branch. The first voltage conversion branch is connected with an input power supply, and the first voltage conversion branch is configured to perform voltage conversion on the voltage of the input power supply to generate a first positive voltage. The second voltage conversion branch is connected with the first voltage conversion branch, and the second voltage conversion branch is configured to perform voltage conversion and phase inversion processing on the first positive voltage to generate a first negative voltage. And the third voltage conversion branch is connected with the first voltage conversion branch and the second voltage conversion branch, and the third voltage conversion branch is configured to convert the first positive voltage into a second positive voltage and adjust the second positive voltage based on the first negative voltage, and an adjustment result is used as an output voltage of the voltage generation circuit. In this way, the positive voltage or the negative voltage can be generated according to needs, and the practicability is high.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electronic circuits, and in particular to a voltage generating circuit and an electronic device. Background Art

[0002] With the development of the electronics industry, electronic components have an increasing demand for negative voltages. For example, the standard power supply in the telecommunications industry is -48V, which can prevent electrochemical corrosion of telephone lines and reduce system noise and interference. In another example, in the gate control voltage of a depletion-type field-effect transistor, the use of a negative voltage can speed up the discharge of the Miller capacitor and improve circuit performance. In another example, for dual-power-supply operational amplifiers, in circuit design, the use of a negative voltage can provide a power rail for the operational amplifier, allowing it to work normally under input / output conditions close to 0V.

[0003] However, the current structure for generating negative voltage can only generate negative voltage and cannot be applied to application scenarios that require both negative voltage and positive voltage. It has great limitations and poor practicality. Summary of the invention

[0004] The embodiments of the present application provide a voltage generating circuit and an electronic device, which can generate positive voltage or negative voltage as required and are highly practical.

[0005] In a first aspect, an embodiment of the present application provides a voltage generating circuit, comprising:

[0006] A first voltage conversion branch is connected to an input power source and is configured to perform voltage conversion on a voltage of the input power source to generate a first positive voltage;

[0007] a second voltage conversion branch, connected to the first voltage conversion branch, and configured to perform voltage conversion and inversion processing on the first positive voltage to generate a first negative voltage;

[0008] The third voltage conversion branch is connected to the first voltage conversion branch and the second voltage conversion branch respectively, and is configured to convert the first positive voltage into a second positive voltage, and adjust the second positive voltage based on the first negative voltage, so that the adjustment result is used as the output voltage of the voltage generating circuit.

[0009] In one or more embodiments, the first voltage conversion branch includes a first switch, a first inductor, a first capacitor, a first diode and a first resistor;

[0010] A first end of the first switch inputs a first pulse width modulation signal, a second end of the first switch is connected to the input power supply, a third end of the first switch is connected to the first end of the first inductor and the cathode of the first diode respectively, the first resistor is connected between the second end of the first inductor and the ground, the anode of the first diode is grounded, and the first capacitor is connected in parallel with the first resistor;

[0011] The first switch is configured to be controlled by the first pulse width modulation signal to be alternately turned on and off, and the voltage at the second end of the first inductor is the first positive voltage.

[0012] In one or more embodiments, the first switch is a PMOS tube;

[0013] The first end of the first switch is the gate of the PMOS tube, the second end of the first switch is the source of the PMOS tube, and the third end of the first switch is the drain of the PMOS tube.

[0014] In one or more embodiments, the second voltage conversion branch includes a second switch, a third switch, a second inductor, a second diode, a second capacitor and a second resistor;

[0015] A first end of the second switch inputs a second pulse width modulation signal, a second end of the second switch is connected to the first voltage conversion branch, a third end of the second switch is respectively connected to a first end of the second inductor and a third end of the third switch, a first end of the third switch inputs a first pulse width modulation signal, a second end of the third switch is respectively connected to a cathode of the second diode and the third voltage conversion branch, an anode of the second diode is respectively connected to a first end of the second capacitor and the third voltage conversion branch, a second end of the second inductor and a second end of the second capacitor are both grounded, and the second resistor is connected in parallel with the second capacitor;

[0016] The second switch is configured to be alternately turned on and off under the control of the second pulse width modulation signal, the third switch is configured to be alternately turned on and off under the control of the first pulse width modulation signal, the first pulse width modulation signal is complementary to the second pulse width modulation signal, and the voltage at the first end of the second capacitor is the first negative voltage.

[0017] In one or more embodiments, the second switch and the third switch are both PMOS tubes;

[0018] The first end of the second switch or the first end of the third switch is the gate of the PMOS tube, the second end of the second switch or the second end of the third switch is the source of the PMOS tube, and the third end of the second switch or the third end of the third switch is the drain of the PMOS tube.

[0019] In one or more embodiments, the third voltage conversion branch includes a fourth switch, a fifth switch, a third inductor, a third diode, a third capacitor and a third resistor;

[0020] The first end of the fourth switch inputs the first pulse width modulation signal, the second end of the fourth switch is connected to the first voltage conversion branch, the third end of the fourth switch is respectively connected to the first end of the third inductor and the cathode of the third diode, the first end of the fifth switch inputs the second pulse width modulation signal, the third end of the fifth switch is connected to the anode of the third diode, the second end of the fifth switch is connected to the second voltage conversion branch, the second end of the third inductor is connected to the first end of the third capacitor, the second end of the third capacitor is connected to the second voltage conversion branch, and the third resistor is connected in parallel with the third capacitor;

[0021] The fourth switch is configured to be controlled by the first pulse width modulation signal to be alternately turned on and off, the fifth switch is configured to be controlled by the second pulse width modulation signal to be alternately turned on and off, and the voltage at the first end of the third capacitor is the output voltage.

[0022] In one or more embodiments, the fourth switch and the fifth switch are both PMOS tubes;

[0023] The first end of the fourth switch or the first end of the fifth switch is the gate of the PMOS tube, the second end of the fourth switch or the second end of the fifth switch is the source of the PMOS tube, and the third end of the fourth switch or the third end of the fifth switch is the drain of the PMOS tube.

[0024] In one or more embodiments, the voltage generating circuit further includes a voltage detection branch and a controller;

[0025] The voltage detection branch is connected between the input power supply and the controller, and the voltage detection branch also inputs any one of the first positive voltage, the first negative voltage, and the output voltage. The voltage detection branch is configured to output a detection signal to the controller based on the voltage of the input power supply and the first positive voltage, or based on the voltage of the input power supply and the first negative voltage, or based on the voltage of the input power supply and the output voltage;

[0026] The controller is configured to adjust a first pulse width modulation signal and a second pulse width modulation signal based on the detection signal.

[0027] In one or more embodiments, the voltage detection branch includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first operational amplifier, and a second operational amplifier;

[0028] The fourth resistor and the fifth resistor are connected in series between the input power supply and the ground, the connection point between the fourth resistor and the fifth resistor is connected to the inverting input terminal of the first operational amplifier, the non-inverting input terminal of the first operational amplifier is respectively connected to the output terminal of the first operational amplifier and the controller, the first end of the sixth resistor inputs any one of the first positive voltage, the first negative voltage and the output voltage, the second end of the sixth resistor is connected to the inverting input terminal of the second operational amplifier, the first end of the seventh resistor inputs a preset reference voltage, the second end of the seventh resistor is connected to the non-inverting input terminal of the second operational amplifier, and the output terminal of the second operational amplifier is connected to the controller.

[0029] In a second aspect, an embodiment of the present application provides an electronic device, comprising the voltage generating circuit as described above.

[0030] The beneficial effect of the present application is that the voltage generation circuit of the embodiment of the present application includes a first voltage conversion branch, a second voltage conversion branch and a third voltage conversion branch. Among them, the first voltage conversion branch is connected to the input power supply, and the first voltage conversion branch is configured to convert the voltage of the input power supply to generate a first positive voltage. The second voltage conversion branch is connected to the first voltage conversion branch, and the second voltage conversion branch is configured to convert the first positive voltage and invert it to generate a first negative voltage. The third voltage conversion branch is connected to the first voltage conversion branch and the second voltage conversion branch respectively, and the third voltage conversion branch is configured to convert the first positive voltage into a second positive voltage, and adjust the second positive voltage based on the first negative voltage, so that the adjustment result is used as the output voltage of the voltage generation circuit. It can be seen that the output voltage can be adjusted by adjusting the first voltage conversion branch, the second voltage conversion branch and the third voltage conversion branch to adjust the first negative voltage, the second positive voltage and the result of adjusting the second positive voltage by the first negative voltage. In this case, the output voltage can be a positive voltage or a negative voltage. In summary, it is possible to generate a positive voltage or a negative voltage as needed, which is very practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] One or more embodiments are exemplarily described by the figures in the corresponding drawings, and these exemplary descriptions are not intended to limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements.

[0032] Figure 1 It is a schematic diagram of a circuit structure for generating a negative voltage in the related art;

[0033] Figure 2 Schematic diagram of the composition block diagram of the voltage generating circuit provided in the embodiment of the present application Figure 1 ;

[0034] Figure 3 is with Figure 2 The circuit structure corresponding to the block diagram shown in the figure Figure 1 ;

[0035] Figure 4 is with Figure 2 The circuit structure corresponding to the block diagram shown in the figure Figure 2 ;

[0036] Figure 5 is a schematic diagram of the corresponding relationship between the output voltage and the duty cycle of the first pulse width modulation signal provided in an embodiment of the present application;

[0037] Figure 6 Schematic diagram of the composition block diagram of the voltage generating circuit provided in the embodiment of the present application Figure 2 ;

[0038] Figure 7 is with Figure 6 The circuit structure schematic diagram corresponding to the composition block diagram of the voltage detection branch shown. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and in detail in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] It should be noted that, when an element is described as being “connected to” another element, it may be directly connected to the other element, or one or more intervening elements may exist therebetween.

[0041] In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as there is no structural conflict between them.

[0042] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a circuit structure for generating a negative voltage in the related art. Figure 1 As shown, the circuit structure for generating negative voltage includes a single chip computer UA1, a resistor RA1, a resistor RA2, a transistor QA1, a transistor QA2, a capacitor CA1, a capacitor CA2, a diode DA1 and a diode DA2.

[0043] Among them, the resistor RA1 is connected between the output end of the single-chip computer UA1 and the base of the transistor QA1, the emitter of the transistor QA1 inputs the positive voltage VC1, the collector of the transistor QA1 is connected to the collector of the transistor QA2, the resistor RA2 is connected between the output end of the single-chip computer UA1 and the base of the transistor QA2, the emitter of the transistor QA2 and the cathode of the diode DA1 are both grounded GND, the capacitor CA1 is connected between the collector of the transistor QA1 and the anode of the diode DA1, the cathode of the diode DA2 is connected to the anode of the diode DA1, the anode of the diode DA2 outputs the negative voltage VC2, and the capacitor CA2 is connected between the anode of the diode DA2 and the ground GND.

[0044] Specifically, the single chip computer UA1 outputs a pulse width modulation signal to control the transistors QA1 and QA2 to be alternately turned on and off, so as to realize the charging and discharging process of the capacitors CA1 and CA2, and further realize the output of the negative voltage VC2 at the anode of the diode DA2.

[0045] However, the above implementation can only generate negative voltage, and cannot be applied to application scenarios that require both negative voltage and positive voltage. It has great limitations and poor practicality.

[0046] Based on this, an embodiment of the present application provides a voltage generating circuit that can generate positive voltage or negative voltage as needed and is highly practical.

[0047] Please refer to Figure 2 , Figure 2 Schematic diagram of a block diagram of a voltage generating circuit provided in an embodiment of the present application. Figure 2 As shown, the voltage generating circuit 100 includes a first voltage conversion branch 10 , a second voltage conversion branch 20 and a third voltage conversion branch 30 .

[0048] The first voltage conversion branch 10 is connected to the input power source VI N, the second voltage conversion branch 20 is connected to the first voltage conversion branch 10, and the third voltage conversion branch 30 is connected to the first voltage conversion branch 10 and the second voltage conversion branch 20 respectively.

[0049] Specifically, the first voltage conversion branch 10 is configured to perform voltage conversion on the voltage of the input power supply VI N to generate a first positive voltage V1. The second voltage conversion branch 20 is configured to perform voltage conversion and inversion processing on the first positive voltage V1 to generate a first negative voltage V2. The third voltage conversion branch 30 is configured to convert the first positive voltage V1 into a second positive voltage (denoted as V3), and adjust the second positive voltage V3 based on the first negative voltage V2, so that the adjustment result is used as the output voltage VOUT of the voltage generating circuit 100.

[0050] It can be seen that the first voltage conversion branch 10, the second voltage conversion branch 20 and the third voltage conversion branch 30 can be adjusted to adjust the first negative voltage V2, the second positive voltage V3 and the result of the first negative voltage V2 adjusting the second positive voltage V3, thereby adjusting the size of the output voltage VOUT. For example, the first negative voltage V2 can be set to a larger value so that the result of the first negative voltage V2 adjusting the second positive voltage V3 is a negative voltage; for another example, the second positive voltage V3 can be set to a larger value so that the result of the first negative voltage V2 adjusting the second positive voltage V3 is a positive voltage. Thus, through the above process, the output voltage VOUT can be a positive voltage or a negative voltage, that is, in practical applications, the voltage generation circuit 100 can generate positive or negative voltages as needed, and is highly practical.

[0051] Please refer to Figure 3 , Figure 3 An example is shown with Figure 2 A circuit structure corresponding to the block diagram shown in FIG. Figure 3 As shown, the first voltage conversion branch 10 includes a first switch Q1, a first inductor L1, a first capacitor C1, a first diode D1 and a first resistor R1.

[0052] The first end of the first switch Q1 inputs the first pulse width modulation signal PWM1, the second end of the first switch Q1 is connected to the input power source VI N, the third end of the first switch Q1 is respectively connected to the first end of the first inductor L1 and the cathode of the first diode D1, the first resistor R1 is connected between the second end of the first inductor L1 and the ground GND, the anode of the first diode D1 is grounded GND, and the first capacitor C1 is connected in parallel with the first resistor R1.

[0053] The first switch Q1 is configured to be controlled by the first pulse width modulation signal PWM1 to be alternately turned on and off, and the voltage at the second end of the first inductor L1 is the first positive voltage V1. Pulse width modulation (PWM) is a technology used to adjust the amplitude and frequency of an output signal, encoding or adjusting the signal level by changing the width of the pulse; the pulse width modulation signal is usually composed of a series of rectangular pulses of equal amplitude but variable width, and the high level duration of each pulse is the duty cycle.

[0054] Specifically, when the first switch Q1 is turned on, the input power source VIN, the first switch Q1, the first inductor L1, and the first resistor R1 in parallel with the first capacitor C1 form a loop, and the voltage of the input power source VIN charges the first inductor L1 and the first capacitor C1.

[0055] When the first switch Q1 is turned off, due to the characteristics of the inductor (trying to keep the current unchanged), the inductor will generate a reverse electromotive force, causing the first diode D1 to be turned on. At this time, the combination of the first inductor L1, the first resistor R1 and the first capacitor C1 in parallel and the first diode D1 form a loop, and the energy in the first inductor L1 is consumed by the first resistor R1, and at the same time, the first capacitor C1 is charged to maintain the voltage on the first capacitor C1. Among them, the first resistor R1 is used as a load to enable the first voltage conversion branch 10 to operate normally when it is unloaded.

[0056] By repeatedly switching the first switch Q1 on and off alternately, the voltage at the first end of the first capacitor C1 can be maintained at the first positive voltage V1. According to the volt-second balance principle, the following formula (1) can be obtained:

[0057] V1=D 1 *VI N+VD1-VD1*D 1 (1).

[0058] Among them, D 1 is the duty cycle of the first pulse width modulation signal PWM1, and VD1 is the forward voltage drop of the first diode D1. In practical applications, the forward voltage drop of the first diode D1 is small and can be ignored. When the forward voltage drop of the first diode D1 is ignored, the following formula (2) can be obtained based on formula (1):

[0059] V1=D 1 *VI N (2).

[0060] Due to D 1 The value range of is (0,1], then from formula (2), it can be obtained that V1 is less than or equal to VIN, the voltage of the input power supply VIN is a positive voltage, and the first positive voltage V1 is a positive voltage less than or equal to the voltage of the input power supply VIN.

[0061] Among them, the first switch Q1 can be any controllable switch, such as a triode, a metal-oxide semiconductor field effect transistor (MOS tube), an insulated gate bipolar transistor (IGBT), an integrated gate-commutated thyristor (IGCT), a gate-turn-off thyristor (GTO), a silicon-controlled rectifier (SCR), a junction-gate field effect transistor (JFET), a MOS-controlled thyristor (MCT), etc.

[0062] For example, Figure 4 As shown, the first switch Q1 is a PMOS tube. The first end of the first switch Q1 is the gate of the PMOS tube, the second end of the first switch Q1 is the source of the PMOS tube, and the third end of the first switch Q2 is the drain of the PMOS tube.

[0063] Please refer back to Figure 3In some embodiments, the second voltage conversion branch 20 includes a second switch Q2, a third switch Q3, a second inductor L2, a second diode D2, a second capacitor C2 and a second resistor R2.

[0064] The first end of the second switch Q2 inputs the second pulse width modulation signal PWM2, the second end of the second switch Q2 is connected to the first voltage conversion branch 10, the third end of the second switch Q2 is respectively connected to the first end of the second inductor L2 and the third end of the third switch Q3, the first end of the third switch Q3 inputs the first pulse width modulation signal PWM1, the second end of the third switch Q3 is respectively connected to the cathode of the second diode D2 and the third voltage conversion branch 30, the anode of the second diode D2 is respectively connected to the first end of the second capacitor C2 and the third voltage conversion branch 30, the second end of the second inductor L2 and the second end of the second capacitor C2 are both grounded GND, and the second resistor R2 is connected in parallel with the second capacitor C2.

[0065] The second switch Q2 is configured to be controlled by the second pulse width modulation signal to be alternately turned on and off, the third switch Q3 is configured to be controlled by the first pulse width modulation signal to be alternately turned on and off, the first pulse width modulation signal PWM1 is complementary to the second pulse width modulation signal PWM2, and the voltage at the first end of the second capacitor C2 is the first negative voltage V2.

[0066] Specifically, when the second switch Q2 is turned on and the third switch Q3 is turned off, the first positive voltage V1 , the second switch Q2 , and the second inductor L2 form a loop, and the first positive voltage V1 charges the second inductor L2 .

[0067] When the second switch Q2 is turned off and the third switch Q3 is turned on, due to the characteristics of the inductor (trying to keep the current unchanged), the inductor will generate a reverse electromotive force, causing the second diode D2 to be turned on. At this time, the second inductor L2, the second resistor R2 and the second capacitor C2 are connected in parallel and the second diode D2 form a loop, and the energy in the second inductor L2 is consumed by the second resistor R2, and the second capacitor C2 is charged at the same time. At this time, since the second end of the second capacitor C2 is grounded GND and the voltage on the second capacitor C2 cannot change suddenly, the voltage at the first end of the second capacitor C2 will become a negative voltage. Among them, the second resistor R2 is used as a load to enable the second voltage conversion branch 20 to operate normally when it is unloaded.

[0068] By repeatedly turning on and off the second switch Q2 and the third switch Q3 alternately, the voltage at the first end of the second capacitor C2 can be kept at the first negative voltage V2. According to the volt-second balance principle, the following formula (3) can be obtained:

[0069] V2=V1*(D 2 / (D 2 -1))+VD2 (3).

[0070] Among them, D 2 is the duty cycle of the second pulse width modulation signal PWM2. Since the second pulse width modulation signal PWM2 is complementary to the first pulse width modulation signal PWM1, D 2 =1-D 1 VD2 is the forward voltage drop of the second diode D2. In practical applications, the forward voltage drop of the second diode D2 is small and can be ignored. When the forward voltage drop of the second diode D2 is ignored, the following formula (4) can be obtained based on formula (3):

[0071] V2=V1*(D 2 / (D 2 -1)) (4).

[0072] Due to D 2 The value range of is (0,1], then from formula (4) we can get V2 is a negative voltage.

[0073] Among them, the second switch Q2 and the third switch Q3 can be any controllable switches, such as triode, metal-oxide semiconductor field effect transistor (MOS tube), insulated gate bipolar transistor (IGBT), integrated gate commutated thyristor (IGCT), gate turn-off thyristor (GTO), silicon controlled rectifier (SCR), junction gate field effect transistor (JFET), MOS controlled thyristor (MCT), etc.

[0074] For example, Figure 4 As shown, the second switch Q2 and the third switch Q3 are both PMOS tubes. The first end of the second switch Q2 or the third switch Q3 is the gate of the PMOS tube, the second end of the second switch Q2 or the third switch Q3 is the source of the PMOS tube, and the third end of the second switch Q2 or the third switch Q3 is the drain of the PMOS tube.

[0075] Please refer back to Figure 3 In some embodiments, the third voltage conversion branch 30 includes a fourth switch Q4, a fifth switch Q5, a third inductor L3, a third diode D3, a third capacitor C3 and a third resistor R3.

[0076] Among them, the first end of the fourth switch Q4 inputs the first pulse width modulation signal PWM1, the second end of the fourth switch Q4 is connected to the first voltage conversion branch 10, the third end of the fourth switch Q4 is respectively connected to the first end of the third inductor L3 and the cathode of the third diode D3, the first end of the fifth switch Q5 inputs the second pulse width modulation signal PWM2, the third end of the fifth switch Q5 is connected to the anode of the third diode D3, the second end of the fifth switch Q5 is connected to the second voltage conversion branch 20, the second end of the third inductor L3 is connected to the first end of the third capacitor C3, the second end of the third capacitor C3 is connected to the second voltage conversion branch 20, and the third resistor R3 is connected in parallel with the third capacitor C3.

[0077] The fourth switch Q4 is controlled by the first pulse width modulation signal PWM1 to be alternately turned on and off, the fifth switch Q5 is controlled by the second pulse width modulation signal PWM2 to be alternately turned on and off, and the voltage at the first end of the third capacitor C3 is the output voltage VOUT.

[0078] Specifically, when the fourth switch Q4 is turned on and the fifth switch Q5 is turned off, the first positive voltage V1, the fourth switch Q4, the third inductor L3, and the third resistor R3 and the third capacitor C3 in parallel form a loop, and the first positive voltage V1 charges the third inductor L3 and the third capacitor C3.

[0079] When the fourth switch Q4 is turned off and the fifth switch Q5 is turned on, due to the characteristics of the inductor (trying to keep the current unchanged), the inductor will generate a reverse electromotive force, so that the third diode D3 is turned on. At this time, the combination of the third inductor L3, the third resistor R3 and the third capacitor C3 in parallel and the third diode D3 form a loop, and the energy in the third inductor L3 is consumed by the third resistor R3, and the third capacitor C3 is charged at the same time. At this time, first assume that the voltage at the second end of the third capacitor C3 is 0, then the voltage at the first end of the third capacitor C3 is the second positive voltage, and then, the voltage at the second end of the third capacitor C3 is set to the first negative voltage V2, which is equivalent to adjusting the second positive voltage based on the first negative voltage V2, and the adjustment result is the output voltage VOUT. Among them, the second resistor R2 is used as a load so that the second voltage conversion branch 20 can operate normally when it is unloaded.

[0080] By repeatedly turning on and off the fourth switch Q4 and the fifth switch Q5 alternately, the voltage at the first end of the third capacitor C3 can be kept at the output voltage VOUT. According to the volt-second balance principle, the following formula (5) can be obtained:

[0081] (V1-VOUT)=(VOUT-V2-VD2-VD3)(1-D 1 ) (5).

[0082] Wherein, VD3 is the conduction voltage drop of the third diode D3. In practical applications, the forward conduction voltage drop of the third diode D3 is small and can be ignored. When the forward conduction of the third diode D3 is ignored, the following formula (6) can be obtained based on formula (5):

[0083] VOUT=V2+V1*D 1 -V2*D 1 (6).

[0084] Substituting formula (2) and formula (4) into formula (6), we can get the following formula (7):

[0085] VOUT=(2*D 1 -1)VI N (7).

[0086] Due to D 1 The value range of is (0,1], then the corresponding range of VOUT is (-VI N,VI N]. The duty cycle D of the output voltage VOUT and the first pulse width modulation signal PWM1 1 The corresponding relationship between Figure 4 As shown, in Figure 4 In the figure, the horizontal axis is the duty cycle D1, the vertical axis is the output voltage VOUT, and the curve S1 is the output voltage VOUT and the duty cycle D 1 It can be seen that the output voltage VOUT and the duty cycle D 1 The corresponding relationship between them is a linear relationship, and it is only necessary to adjust the duty cycle D of the first pulse width modulation signal PWM1. 1 , the required positive or negative voltage can be generated, where the duty cycle D 1 When the duty cycle D is greater than 0.5, the output voltage VOUT is positive. 1 When it is less than 0.5, the output voltage VOUT is a negative voltage.

[0087] Among them, the fourth switch Q4 and the fifth switch Q5 can be any controllable switches, such as a triode, a metal-oxide semiconductor field effect transistor (MOS tube), an insulated gate bipolar transistor (IGBT), an integrated gate-commutated thyristor (IGCT), a gate-turn-off thyristor (GTO), a silicon-controlled rectifier (SCR), a junction-gate field effect transistor (JFET), a MOS-controlled thyristor (MCT), etc.

[0088] For example, Figure 4 As shown, the fourth switch Q4 and the fifth switch Q5 are both PMOS tubes. The first end of the fourth switch Q4 or the fifth switch Q5 is the gate of the PMOS tube, the second end of the fourth switch Q4 or the fifth switch Q5 is the source of the PMOS tube, and the third end of the fourth switch Q4 or the fifth switch Q5 is the drain of the PMOS tube.

[0089] In some embodiments, Figure 6 As shown, the voltage generating circuit 100 further includes a voltage detecting branch 40 and a controller 50 .

[0090] The voltage detection branch 40 is connected between the input power source VIN and the controller 50, and the voltage detection branch 40 also inputs any one of the first positive voltage V1, the first negative voltage V2 and the output voltage VOUT.

[0091] Specifically, the voltage detection branch 40 is configured to output a detection signal to the controller 50 based on the voltage of the input power supply VI N and the first positive voltage V1, or based on the voltage of the input power supply VI N and the first negative voltage V2, or based on the voltage of the input power supply VI N and the output voltage VOUT. The controller 50 is configured to adjust the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 based on the detection signal. Thus, the duty cycle D 1 The output voltage VOUT can be adjusted to obtain the required positive or negative voltage.

[0092] Please refer to Figure 7 , Figure 7 For Figure 6 The block diagram of the voltage detection branch shown in FIG. Figure 7 As shown, the voltage detection branch 40 includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first operational amplifier U1 and a second operational amplifier U2.

[0093] The fourth resistor R4 and the fifth resistor R5 are connected in series between the input power supply VI N and the ground GND, the connection point between the fourth resistor R4 and the fifth resistor R5 is connected to the inverting input terminal of the first operational amplifier U1, the non-inverting input terminal of the first operational amplifier U1 is respectively connected to the output terminal of the first operational amplifier U1 and the controller 50, the first end of the sixth resistor R6 inputs any one of the first positive voltage V1, the first negative voltage V2 and the output voltage VOUT, the second end of the sixth resistor R6 is connected to the inverting input terminal of the second operational amplifier U2, the first end of the seventh resistor R7 inputs the preset reference voltage VREF, the second end of the seventh resistor R7 is connected to the non-inverting input terminal of the second operational amplifier U2, and the output terminal of the second operational amplifier U2 is connected to the controller 50. The preset reference voltage VREF is a preset voltage, which can be set based on the actual application scenario, and the embodiment of the present application does not specifically limit this.

[0094] Specifically, the first operational amplifier U1 forms a voltage follower, and the voltage of the input power supply VI N is output through the voltage follower after being divided by the fourth resistor R4 and the fifth resistor R5, and is input to the controller 50, so that the controller 50 determines the voltage of the input power supply VI N. The difference between the preset reference voltage VREF and any one of the first positive voltage V1, the first negative voltage V2 and the output voltage VOUT is amplified by the second operational amplifier U2 and output, and is input to the controller 50, so that the controller determines the voltage of any one of the first positive voltage V1, the first negative voltage V2 and the output voltage VOUT. For example, the difference between the preset reference voltage VREF and the first positive voltage V1 is amplified by the second operational amplifier U2 and output, and is input to the controller 50, so that the controller determines the voltage of the first positive voltage V1. Among them, the detection signal output by the voltage detection branch 40 includes the signal output by the first operational amplifier U1 and the signal output by the second operational amplifier U2. After the controller 50 determines the voltage of the input power source VI N and the voltage of any one of the first positive voltage V1, the first negative voltage V2 and the output voltage VOUT, the controller 50 may determine the current duty cycle D 1 Is it the required duty cycle? If not, the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 can be adjusted accordingly to adjust the duty cycle D 1 The required duty cycle is obtained, thereby obtaining the required positive voltage or negative voltage.

[0095] An embodiment of the present application further provides an electronic device, which includes the voltage generating circuit 100 in any embodiment of the present application.

[0096] In some embodiments, the electronic device is a switching power supply.

[0097] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

[0098] The above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them. Under the idea of ​​the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. It should be understood by ordinary technicians in this field that they can still modify the technical solutions recorded in the above embodiments, or replace some of the technical features by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A voltage generating circuit, characterized in that: include: A first voltage conversion branch is connected to an input power source and is configured to perform voltage conversion on a voltage of the input power source to generate a first positive voltage; a second voltage conversion branch, connected to the first voltage conversion branch, and configured to perform voltage conversion and inversion processing on the first positive voltage to generate a first negative voltage; The third voltage conversion branch is connected to the first voltage conversion branch and the second voltage conversion branch respectively, and is configured to convert the first positive voltage into a second positive voltage, and adjust the second positive voltage based on the first negative voltage, so that the adjustment result is used as the output voltage of the voltage generating circuit.

2. The voltage generating circuit according to claim 1, characterized in that: The first voltage conversion branch includes a first switch, a first inductor, a first capacitor, a first diode and a first resistor; A first end of the first switch inputs a first pulse width modulation signal, a second end of the first switch is connected to the input power supply, a third end of the first switch is connected to the first end of the first inductor and the cathode of the first diode respectively, the first resistor is connected between the second end of the first inductor and the ground, the anode of the first diode is grounded, and the first capacitor is connected in parallel with the first resistor; The first switch is configured to be controlled by the first pulse width modulation signal to be alternately turned on and off, and the voltage at the second end of the first inductor is the first positive voltage.

3. The voltage generating circuit according to claim 2, characterized in that: The first switch is a PMOS tube; The first end of the first switch is the gate of the PMOS tube, the second end of the first switch is the source of the PMOS tube, and the third end of the first switch is the drain of the PMOS tube.

4. The voltage generating circuit according to claim 1, wherein: The second voltage conversion branch includes a second switch, a third switch, a second inductor, a second diode, a second capacitor and a second resistor; A first end of the second switch inputs a second pulse width modulation signal, a second end of the second switch is connected to the first voltage conversion branch, a third end of the second switch is respectively connected to a first end of the second inductor and a third end of the third switch, a first end of the third switch inputs a first pulse width modulation signal, a second end of the third switch is respectively connected to a cathode of the second diode and the third voltage conversion branch, an anode of the second diode is respectively connected to a first end of the second capacitor and the third voltage conversion branch, a second end of the second inductor and a second end of the second capacitor are both grounded, and the second resistor is connected in parallel with the second capacitor; The second switch is configured to be alternately turned on and off under the control of the second pulse width modulation signal, the third switch is configured to be alternately turned on and off under the control of the first pulse width modulation signal, the first pulse width modulation signal is complementary to the second pulse width modulation signal, and the voltage at the first end of the second capacitor is the first negative voltage.

5. The voltage generating circuit according to claim 4, characterized in that: The second switch and the third switch are both PMOS tubes; The first end of the second switch or the first end of the third switch is the gate of the PMOS tube, the second end of the second switch or the second end of the third switch is the source of the PMOS tube, and the third end of the second switch or the third end of the third switch is the drain of the PMOS tube.

6. The voltage generating circuit according to claim 1, characterized in that: The third voltage conversion branch includes a fourth switch, a fifth switch, a third inductor, a third diode, a third capacitor and a third resistor; The first end of the fourth switch inputs the first pulse width modulation signal, the second end of the fourth switch is connected to the first voltage conversion branch, the third end of the fourth switch is respectively connected to the first end of the third inductor and the cathode of the third diode, the first end of the fifth switch inputs the second pulse width modulation signal, the third end of the fifth switch is connected to the anode of the third diode, the second end of the fifth switch is connected to the second voltage conversion branch, the second end of the third inductor is connected to the first end of the third capacitor, the second end of the third capacitor is connected to the second voltage conversion branch, and the third resistor is connected in parallel with the third capacitor; The fourth switch is configured to be controlled by the first pulse width modulation signal to be alternately turned on and off, the fifth switch is configured to be controlled by the second pulse width modulation signal to be alternately turned on and off, and the voltage at the first end of the third capacitor is the output voltage.

7. The voltage generating circuit according to claim 6, characterized in that: The fourth switch and the fifth switch are both PMOS tubes; The first end of the fourth switch or the first end of the fifth switch is the gate of the PMOS tube, the second end of the fourth switch or the second end of the fifth switch is the source of the PMOS tube, and the third end of the fourth switch or the third end of the fifth switch is the drain of the PMOS tube.

8. The voltage generating circuit according to any one of claims 1 to 7, characterized in that: The voltage generating circuit also includes a voltage detection branch and a controller; The voltage detection branch is connected between the input power supply and the controller, and the voltage detection branch also inputs any one of the first positive voltage, the first negative voltage, and the output voltage. The voltage detection branch is configured to output a detection signal to the controller based on the voltage of the input power supply and the first positive voltage, or based on the voltage of the input power supply and the first negative voltage, or based on the voltage of the input power supply and the output voltage; The controller is configured to adjust a first pulse width modulation signal and a second pulse width modulation signal based on the detection signal.

9. The voltage generating circuit according to claim 8, characterized in that: The voltage detection branch includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first operational amplifier and a second operational amplifier; The fourth resistor and the fifth resistor are connected in series between the input power supply and the ground, the connection point between the fourth resistor and the fifth resistor is connected to the inverting input terminal of the first operational amplifier, the non-inverting input terminal of the first operational amplifier is respectively connected to the output terminal of the first operational amplifier and the controller, the first end of the sixth resistor inputs any one of the first positive voltage, the first negative voltage and the output voltage, the second end of the sixth resistor is connected to the inverting input terminal of the second operational amplifier, the first end of the seventh resistor inputs a preset reference voltage, the second end of the seventh resistor is connected to the non-inverting input terminal of the second operational amplifier, and the output terminal of the second operational amplifier is connected to the controller.

10. An electronic device, characterized in that: The method comprises a voltage generating circuit as claimed in any one of claims 1 to 9.

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