Switched mode power supply and control method and controller thereof

Abstract

A method of controlling a switched mode power supply (SMPS) to convert an input voltage to an output voltage based on a pulse width modulation (PWM) control signal, the SMPS, and a controller are provided. The method includes: generating an error signal based on a difference between an output voltage and a target output voltage; filtering the error signal to generate a filtered error signal; generating a feed-forward signal based on at least one feed-forward parameter related to at least one of the output voltage, the input voltage, an output power of the SMPS, or an output current corresponding to the output voltage; summing the feedforward signal and the filtered error signal to generate an integrator input signal; and applying a non-linear integration function to the integrator input signal to generate the PWM control signal.

Description

Technical Field

[0001] The present disclosure relates generally to the field of electronics, and in particular to voltage controllers using voltage feedback and power feed-forward. Background Art

[0002] Modern devices rely on power semiconductor devices for many functions in motor vehicles, consumer and industrial applications (e.g., driving motors or electric machines). For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), gallium nitride high electron mobility transistors (GaN HEMTs) and diodes have been used in a variety of applications, including but not limited to switches in power supplies and power converters.

[0003] A transistor typically includes a semiconductor structure configured to conduct a load current along a load current path between two load terminal structures of the transistor. In addition, the load current can be controlled by a control electrode (sometimes referred to as a gate electrode) of the transistor. For example, upon receiving a corresponding control signal from, for example, a gate driver, the control electrode can set its transistor to one of a conducting state or a blocking state. Thus, the semiconductor structure behaves like a switch having an on-state and an off-state (i.e., a conducting state and a blocking state, respectively).

[0004] A switch mode power supply (SMPS) is a power supply that uses semiconductor switching technology to provide a desired output voltage. An SMPS may include a power switch stage and a control circuit. The power switch stage may perform power conversion to convert an input voltage into an output voltage and generate an output current that may be used as a load current. For example, the power switch stage may include a transistor (e.g., a power switch) for performing power conversion. The input voltage may be a DC voltage provided from a DC supply or a rectified DC voltage from an AC supply that has been rectified using a diode bridge and some additional capacitor filtering. The control circuit may control the switching state of the transistor to regulate power conversion. For example, the control circuit may control the transistor to switch between an on state and an off state according to a duty cycle to regulate the output voltage to achieve a desired output voltage.

[0005] The converter topology of the SMPS and the switching scheme of the transistors implemented by the control circuit determine the power conversion. Possible converter topologies include buck converter topology, boost converter topology, buck-boost converter topology (e.g., including flyback converter topology and hybrid flyback converter topology), and boost power factor correction (PFC) converter topology. Other converter topologies may also be used. In addition, the converter topology may include a single stage or two or more stages. Summary of the invention

[0006] In some implementations, an SMPS configured to provide output power to a load includes: a power switch configured to receive a pulse width modulation (PWM) control signal to control the output power, wherein the SMPS is configured to convert an input voltage into an output voltage and generate an output current using the power switch; a controller configured to adjust the PWM control signal for controlling the output power, wherein the controller includes: an error generator configured to generate an error signal based on a difference between an output voltage and a target output voltage; a filter configured to generate a filtered error signal based on the error signal; a feedforward processing circuit configured to receive at least one feedforward parameter related to at least one of the output voltage, the output current, the output power, or the input voltage, and generate a feedforward signal based on the at least one feedforward parameter; a combiner configured to generate an integrator input signal based on a sum of the feedforward signal and the filtered error signal; and a nonlinear integrator configured to apply a nonlinear integration function to the integrator input signal to generate the PWM control signal.

[0007] In some implementations, a controller configured to control an SMPS based on a PWM control signal to convert an input voltage into an output voltage includes: an error generator configured to generate an error signal based on a difference between an output voltage and a target output voltage; a filter configured to generate a filtered error signal based on the error signal; a feedforward processing circuit configured to monitor a change in output current, a change in output voltage, or a change in input voltage corresponding to a change in load conditions, and to generate a feedforward signal based on the change in output current, the change in output voltage, or the change in input voltage; a combiner configured to generate an integrator input signal based on a sum of the feedforward signal and the filtered error signal; and a nonlinear integrator configured to apply a nonlinear integration function to the integrator input signal to generate a PWM control signal.

[0008] In some implementations, a method for controlling an SMPS based on a PWM control signal to convert an input voltage into an output voltage includes: generating an error signal based on a difference between an output voltage and a target output voltage; filtering the error signal to generate a filtered error signal; generating a feedforward signal based on at least one feedforward parameter related to at least one of the output voltage, the input voltage, an output power of the SMPS, or an output current corresponding to the output voltage; adding the feedforward signal and the filtered error signal to generate an integrator input signal; and applying a nonlinear integration function to the integrator input signal to generate the PWM control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Implementations are described herein with reference to the accompanying drawings.

[0010] Figure 1 A schematic block diagram of a SMPS according to one or more implementations is shown.

[0011] Figure 2 A schematic block diagram of a controller according to one or more implementations is shown.

[0012] Figure 3 A system diagram of a boost PFC converter according to one or more implementations is shown.

[0013] Figure 4 A system diagram of a power converter is shown in accordance with one or more implementations. DETAILED DESCRIPTION

[0014] In the following, the details are set forth to provide a more comprehensive description of example implementations. However, it will be apparent to those skilled in the art that these implementations may be practiced without these specific details. In other cases, well-known structures and devices are shown in block diagram form or schematic form rather than in detail to avoid obscuring the implementation. In addition, unless otherwise specifically stated, the features of the different implementations described below may be combined with each other.

[0015] In addition, equivalent or similar elements or elements having equivalent or similar functions are indicated by equivalent or similar reference numerals in the following description. Since the same elements or elements having equivalent functions are given the same reference numerals in the drawings, repeated descriptions of elements provided with the same reference numerals may be omitted. Therefore, the descriptions provided for elements having the same or similar reference numerals are interchangeable.

[0016] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe relationships between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0017] In the implementations described herein or shown in the accompanying drawings, any direct electrical connection or coupling (e.g., any connection or coupling without additional intermediate elements) may also be implemented by an indirect connection or coupling (e.g., a connection or coupling with one or more additional intermediate elements, and vice versa), as long as the general purpose of the connection or coupling is essentially maintained (e.g., transmitting a certain signal or transmitting certain information). Features from different implementations may be combined to form additional implementations. For example, unless otherwise stated, changes or modifications described with respect to one of the implementations may also apply to other implementations.

[0018] As used herein, the terms "substantially" and "approximately" mean "within reasonable tolerances of manufacturing and measurement." For example, the terms "substantially" and "approximately" may be used herein to illustrate small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in the industry without departing from aspects of the implementations described herein. For example, a resistor having an approximate resistance value may actually have a resistance within 5% of the approximate resistance value. As another example, a signal having an approximate signal value may actually have a signal value within 5% of the approximate signal value.

[0019] In the present disclosure, expressions including ordinal numbers such as "first", "second", etc. can modify various elements. However, such elements are not limited by such expressions. For example, such expressions do not limit the order and / or importance of elements. On the contrary, such expressions are only used for the purpose of distinguishing elements from other elements. For example, the first box and the second box indicate different boxes, although both the first box and the second box are boxes. For another example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can also be referred to as the first element.

[0020] The transistor may be referred to as a power switch or transistor switch, which may be used in an SMPS to convert an input voltage into an output voltage. The output voltage may be controlled using a feedback controller that adjusts a control parameter of the transistor based on at least one of the output voltage, the input voltage, the output current (e.g., the load current), or the output power (e.g., the product of the output current and the output voltage). For example, the feedback controller may adjust the on-time of the transistor to generate a target output voltage.

[0021] The feedback controller may have two nested control loops, including an inner current control loop and an outer voltage control loop. The inner current control loop should be much faster than the outer voltage control loop. While the upper limit of the inner current control loop is determined by the switching frequency, the outer voltage control loop may limit the load regulation performance. In most applications, it is not possible to implement an inner current control loop, where the control parameters can be expressed by simple formulas of output voltage, output current and / or input voltage, and is fast enough for adequate load regulation performance. The PFC controller may be an exception, where the load regulation is relatively slow in order to maintain unity power factor. However, in this case, the circuit design is complex and may be expensive.

[0022] In the case where the on-time is used as a control parameter, the feedback controller needs to know the inductance of the inductor used in the SMPS. However, due to manufacturing and production variations (e.g., high manufacturing tolerances), the inductance may vary by up to + / -20%. Therefore, the inductance may not be known with the accuracy level required for accurate and effective feedback control. The variation in inductance makes this feedback control difficult to implement in large-scale production because each inductor needs to be tested - a process that can be time-consuming and expensive to implement in large-scale. Other feedback control schemes may also need to know the component values ​​or other parameter values ​​of one or more circuit components of the SMPS to implement feedback control. However, similar to the inductance, the large manufacturing tolerances of one or more circuit components may make it difficult to implement feedback control schemes in large-scale production.

[0023] Some implementations described in the present disclosure relate to a feedback control scheme for an SMPS that is independent of known circuit component parameters for implementing the feedback control scheme. Therefore, the feedback control scheme can be implemented independently of the manufacturing tolerances of one or more circuit components of the SMPS. Therefore, the accuracy and efficiency of the feedback control of the SMPS can be improved. In addition, the feedback control scheme can be implemented in mass production without the additional cost associated with obtaining component values ​​for one or more circuit components. In some implementations, knowledge of the input voltage, the inductance of the inductor, the effective turns ratio of the transformer, the flyback voltage, and / or the switching frequency of the power switch may not be required for implementing the feedback control scheme. For example, for a boost PFC converter, neither the input voltage nor the inductance may be required to implement the feedback control scheme. For a discontinuous conduction mode (DCM) fixed frequency flyback converter with current control, neither the inductance nor the switching frequency may be required to implement the feedback control scheme. For a quasi-resonant flyback converter with current control, neither the effective turns ratio nor the input voltage and the flyback voltage may be required to implement the feedback control scheme.

[0024] In some implementations, the feedback control scheme may include generating a normalized feedforward signal derived from a set of feedforward rules that depend on the circuit topology of the SMPS. One or more feedforward parameters that are independent of all circuit parameters may be used to generate the normalized feedforward signal. For example, the normalized feedforward signal may be obtained based on at least one of the output voltage, input voltage, output current, or output power without knowing the component values ​​of one or more circuit components for the SMPS. In addition, the feedback control scheme may include a nonlinear integrator configured to apply a nonlinear integral function based on the normalized feedforward signal to generate a control signal for the transistor. The control signal may be a pulse width modulation (PWM) control signal that controls the on-time and / or duty cycle of the transistor.

[0025] Figure 1 A schematic block diagram of an SMPS 100 according to one or more implementations is shown. The SMPS 100 may be configured to provide an output power Pout to a load. For example, the SMPS 100 may convert an input voltage Vin into an output voltage Vout, and may generate an output current Iout. The output current Iout may correspond to a load current. The SMPS 100 may have a buck converter topology, a boost converter topology, a buck-boost converter topology (e.g., a flyback converter topology or a hybrid flyback converter topology), or a boost PFC converter topology. In this example, the SMPS 100 has a boost PFC converter topology.

[0026] The SMPS 100 may be coupled to an AC voltage source 102 that provides an AC voltage. The SMPS 100 may include a rectifier 104, an inductor 106, a diode 108, a capacitor 110, a power switch 112, a controller 114, and a zero-crossing detection (ZCD) winding 116 that may be magnetically coupled to the inductor 106 to form a transformer. The overall goal of a boost PFC converter is to quickly turn on and off the power switch 112 at a varying duty cycle to make the input AC current I AC is sinusoidal and has a similar voltage to the input voltage V AC Same phase.

[0027] The rectifier 104 (e.g., a diode bridge rectifier) ​​can convert the AC voltage to an input voltage Vin (e.g., a DC input voltage). The SMPS 100 can also include an input filter that can prevent damaging voltage transients and surges from entering the SMPS 100 and causing damage within the SMPS 100. Additionally or alternatively, the input filter can prevent any electromagnetic interference (EMI) generated within the SMPS 100 from being conducted to the AC voltage source 102.

[0028] Inductor 106, diode 108 and power switch 112 can be used to generate converter current Iconv. Capacitor 110 can store output voltage Vout, which can then be supplied to the load. For example, controller 114 can generate PWM control signal 118 to control output power Pout. In particular, PWM control signal 118 can control the on-time and / or duty cycle of power switch 112. Controller 114 can adjust PWM control signal 118 to control output voltage Vout. Therefore, PWM control signal 118 is used to adjust the conversion of input voltage Vin to output voltage Vout.

[0029] The controller 114 can cycle rapidly between the two states. The first state occurs when the power switch 112 is closed (e.g., the power switch 112 is in the on state). When in the first state, the inductor 106 can be excited by the input voltage Vin. Therefore, the inductor current may increase. At the same time, the diode 108 can become reverse biased (e.g., because the anode of the diode 108 is connected to the ground through the power switch 112), and energy is provided to the load by the capacitor 110 (e.g., the capacitor 110 is discharged).

[0030] The second state occurs when the power switch 112 is disconnected (e.g., the power switch 112 is in the off state). In the second state, the inductor 106 may be de-energized (e.g., the inductor current decreases) while the inductor 106 supplies energy to the load and recharges the capacitor 110. For example, when the power switch is turned off, the charging current Icap may begin to flow through the capacitor 110, and the capacitor 110 begins to charge. Here, the polarity of the inductor 106 may be reversed, which means that the left side of the inductor 106 may be negative. Thus, the two sources (input voltage Vin and inductor 106) are connected in series, resulting in a higher voltage charging the capacitor 110 through the diode 108, and a higher output voltage Vout is supplied to the load. The cycle between the first state and the second state may be performed in a manner that both maintains a constant output voltage Vout and controls the average value of the inductor current and thus controls the AC current I AC This is done by taking the average value of

[0031] Since the inductor current increases in the first state (on state) and decreases in the second state (off state), the on-time and off-time of the power switch 112 can determine the amount of time the inductor current increases and the amount of time the inductor current decreases. Therefore, by changing the on-time and off-time, the average value of the inductor current can be adjusted. For PFC, closed-loop control can be used to ensure that the output voltage Vout is maintained and the AC current I AC is sinusoidal and has a direct relationship with the AC voltage V AC Same phase.

[0032] The controller 114 may be an integrated circuit (IC) including a gate driver configured to drive the gate of the power switch 112 between switching states. For example, the controller 114 may receive one or more inputs as feedforward parameters, and based on these inputs, generate a PWM control signal 118 applied to the gate of the power switch 112. One or more inputs may include or may be related to a measurement of the output voltage Vout, a measurement of the input voltage Vin, a measurement of the output current Iout, and / or a measurement of the output power Pout. In some implementations, the controller 114 may receive a voltage Vzcd from the ZCD winding 116, and may detect a zero crossing of the voltage Vzcd that may be associated with a zero inductor current. The detected zero crossing may be used by the controller 114 for PFC. Therefore, the SMPS 100 may use the power switch 112 to convert the input voltage Vin into an output voltage Vout, and generate an output current Iout. The controller 114 may adjust the PWM control signal 118 based on one or more feedforward parameters to control the output voltage Vout (e.g., to maintain a constant output voltage Vout). The power switch 112 may receive a PWM control signal 118 to control the output voltage, the output current Iout, and / or the output power Pout.

[0033] As indicated above, Figure 1 Provided as examples only. Other examples may differ from those described in Figure 1 For example, in some implementations, the SMPS 100 may have a different converter topology. In some implementations, the controller 114 may be used to control a power switch provided in another type of power converter.

[0034] Figure 2 FIG. 2 shows a schematic block diagram of a controller 200 according to one or more implementations. The controller 200 may be implemented as a combination of Figure 1 The controller 200 may include an error generator 202, a filter 204, a feedforward processing circuit 206, a combiner 208, and a nonlinear integrator 210.

[0035] The error generator 202 may generate an error signal E based on a difference between the output voltage Vout and the target output voltage Vout*. For example, the error generator 202 may be a subtractor component configured to subtract the output voltage Vout from the target output voltage Vout* to generate the error signal E. The target output voltage Vout* may be an input variable provided to the controller 200 .

[0036] The filter 204 may receive the error signal E and generate a filtered error signal Y based on the error signal E. In some implementations, the filter 204 may be a linear filter having a substantially linear transfer function. Thus, the error signal E may be provided as an input to the linear transfer function, and the filtered error signal Y may be provided as an output of the linear transfer function. The linear transfer function may be "substantially" linear, meaning that the transfer function may not be completely linear to account for small nonlinearities that may occur, for example, due to production errors. The linear transfer function may select a certain frequency band to pass. For example, the linear transfer function may provide a low-pass filter function (e.g., to suppress AC line ripple).

[0037] The feedforward processing circuit 206 may receive at least one feedforward parameter related to at least one of the output voltage Vout, the output current Iout, the output power Pout, and the input voltage Vin, and generate a feedforward signal U based on the at least one feedforward parameter. Dff In some implementations, the feedforward processing circuit 206 may monitor changes in the output current Iout, the output voltage Vout, or the input voltage Vin corresponding to changes in the load condition of the load, and generate a feedforward signal U based on the changes in the output current, the output voltage, or the input voltage. Dff .

[0038] The combiner 208 can be based on the feedforward signal U Dff The sum of the filtered error signal Y generates the integrator input signal U D For example, the combiner 208 may be an adder configured to combine the feedforward signal U Dff and the filtered error signal Y to generate the integrator input signal U D .

[0039] The nonlinear integrator 210 may apply a nonlinear integration function to the integrator input signal U D , to generate a control signal U. The control signal U may correspond to the combination Figure 1 For example, the control signal U may be a PWM control signal that defines the on-time Ton and / or duty cycle of the power switch 112. Therefore, the controller 200 may generate the PWM control signal 118 applied to the gate of the power switch 112 based on the on-time defined by the control signal U. In some implementations, the control signal U may be a PWM control signal 118 generated according to the on-time.

[0040] In some implementations, the feedforward processing circuit 206 may be configured to generate a feedforward signal U Dff , so that the feedforward signal U Dffis zero during steady-state load conditions and deviates from zero during load changes under non-steady-state load conditions to minimize the filtered error signal Y during load changes. For example, the feedforward processing circuit 206 may generate a feedforward signal U having a non-zero value. Dff , to drive the filtered error signal Y towards zero during load changes. The feedforward signal U Dff It can represent the normalized feedforward value.

[0041] In some implementations, the feedforward processing circuit 206 may generate a feedforward signal U Dff , to drive the average value of the filtered error signal Y to a target error value. For example, the target error value may be zero, or may be some other set value. In some implementations, the feedforward processing circuit 206 may generate a feedforward signal U Dff , to minimize the filtered error signal Y during load changes. In some implementations, the feedforward processing circuit 206 can generate a feedforward signal U Dff , to minimize the magnitude and duration of the instantaneous deviation of the output voltage Vout from the target value during load changes. In some implementations, the feedforward signal U Dff The feedforward processing circuit 206 may monitor the relative load change or the relative change of the input voltage condition based on at least one feedforward parameter (e.g., Vout, Iout, Vin, and / or Pout), and generate the feedforward signal U based on the relative load change or the relative change of the input voltage condition. Dff .

[0042] The feedforward processing circuit 206 may include a first processing circuit 212 and a second processing circuit 214. The first processing circuit 212 may receive at least one feedforward parameter (e.g., Vout, Iout, Vin, and / or Pout) and generate an internal feedforward signal U based on a function of the at least one feedforward parameter. ff Thus, the first processing circuit 212 may include at least one processor or other processing component. The function may be based on an algorithm, transfer function, or mathematical formula corresponding to the converter topology of the SMPS 100. For example, for a boost converter topology, the function may be U ff =Pout / Vin. For a boost PFC converter topology, this function can be U ff =Pout / <Vin 2 >, where <Vin 2 >It's Vin 2 For a critical conduction mode boost PFC converter topology with on-time control, the function can be U ff =2L·Pout / <Vin2 >, where L is the inductance of the inductor 106. Therefore, the SMPS 100 may be a PFC boost converter configurable in a critical conduction mode, and during the critical conduction mode, the internal feedforward signal U ff can be proportional to the output power Pout of the SMPS 100. For a quasi-resonant flyback converter topology with current control, the function can be U ff =2N·Iout(Vin+Vr) / Vin, where N is the effective turns ratio of the transformer of the SMPS and Vr is the flyback voltage. Therefore, each function is specific to the converter topology of the SMPS 100, and other functions using one or more feed-forward parameters as input variables can be used for other types of converter topologies. In some implementations, the first processing circuit 212 can calculate the output power Pout (e.g., P=I·V) based on the output voltage Vout and the output current Iout measured by one or more sensors and / or sensing circuits.

[0043] The first processing circuit 212 may generate an internal feedforward signal U based on a function of at least one feedforward parameter ff , so that the internal feedforward signal U ff is proportional to the steady-state value of the control signal U (eg, proportional to the steady-state value of the PWM control signal 118). In addition, a feedforward signal U may be generated. Dff To normalize the internal feedforward signal U ff .

[0044] The second processing circuit 214 may include at least one processor or other processing component. For example, the second processing circuit 214 may include a delay element 216, a subtractor component 218, and a calculation circuit 220. The delay element 216 may receive the internal feedforward signal U ff , and the internal feedforward signal U ff The output of is delayed by a predetermined number of discrete time steps (eg, one or more discrete time steps) or samples. Thus, the delay element 216 may output the internal feedforward signal U ff The previous value U ff (n-1), where n is an integer greater than zero.

[0045] In some implementations, the controller 200 is a digital controller configured to operate in discrete time steps. For example, the first processing circuit 212 and the second processing circuit 214 can operate in discrete time steps based on a system clock. The first processing circuit 212 can be configured to update the internal feedforward signal U at each discrete time step. ff Therefore, the internal feedforward signal U ff The previous value U ff(n-1) can correspond to the previous discrete time step, and the internal feedforward signal U ff The updated value U ff (n) may correspond to the latest discrete time step.

[0046] The subtractor component 218 can be fed from the internal feedforward signal U ff The updated value U ff (n) minus the internal feedforward signal U ff The previous value U ff (n-1) to generate the internal feedforward signal U ff The difference ΔU ff Update value U ff (n) can represent the internal feedforward signal U ff The first processing circuit 212 may update the internal feedforward signal U at each clock cycle or each discrete time step. ff .

[0047] The calculation circuit 220 may include a divider configured to divide the difference ΔU ff Divided by the internal feedforward signal U ff The corresponding value is used to generate the feedforward signal U Dff For example, in some implementations, the calculation circuit 220 may calculate the difference ΔU ff Divide by the previous value U ff (n-1) to generate the feedforward signal U Dff In some implementations, the calculation circuit 220 can convert the difference ΔU ff Divided by the internal feedforward signal U ff Another previous sample (e.g., another previous value) of to generate the feedforward signal U Dff In some implementations, the calculation circuit 220 can convert the difference ΔU ff Divided by the internal feedforward signal U ff The average value of two or more previous samples of to generate the feedforward signal U Dff .

[0048] In some implementations, the feedforward processing circuit 206 may monitor a relative load change or a relative change in input voltage conditions based on at least one feedforward parameter, and the second processing circuit 214 may generate a feedforward signal U based on the relative load change or the relative change in input voltage conditions. Dff .

[0049] Therefore, the second processing circuit 214 can generate a feedforward signal U Dff, to drive the average value of the filtered error signal Y to the target error value, to minimize the filtered error signal Y during load changes, and / or to minimize the magnitude and duration of the instantaneous deviation of the output voltage Vout from the target value during load changes. The second processing circuit 214 can generate a feedforward signal U Dff , so that the feedforward signal U Dff is zero during steady-state load conditions and deviates from zero during load changes under non-steady-state load conditions to minimize the filtered error signal Y during load changes. In addition, due to the normalization of the internal feedforward signal by the second processing circuit 214, the first processing circuit 212 is used to calculate the internal feedforward signal U ff Any unknown measured gain error or any unknown circuit parameters can be offset.

[0050] For example, in the case of a critical conduction mode boost PFC converter topology with on-time control, the normalized function can be U Dff =ΔPout / Pout or U Dff =ΔIout / Iout. Normalized feedforward signal (eg, feedforward signal U Dff ) is not sensitive to the tolerance of the inductance L of the inductor 106 or the measurement error of the input voltage Vin, even if the first processing circuit 212 is using these parameters and signals. Instead, the real data of these parameters and signals can be replaced by any constant value.

[0051] Similarly, in the case of a quasi-resonant flyback converter topology with current control, the normalized function can be U Dff =ΔIout / Iout. Normalized feedforward signal (eg, feedforward signal U Dff ) is not sensitive to the tolerance of the effective turns ratio N, the measurement error of the input voltage Vin or the flyback voltage Vr, even if these parameters and signals are being used by the first processing circuit 212. Instead, the real data of these parameters and signals can be replaced by any constant values.

[0052] The nonlinear integrator 210 may include a multiplier 222, a combiner 224, and a delay element 226. The multiplier 222 may be configured to multiply the integrator input signal U D and the previous value U of the control signal U (eg, the PWM control signal 118). D (n-1) to generate the product value U P The delay element 226 may be arranged in the feedback path and may have an input coupled to the output of the combiner 224. The delay element 226 may receive the control signal U and delay the output of the control signal U by a predetermined number of discrete time steps or samples. Thus, the delay element 226 may delay the previous value U of the control signal U. D(n-1) is output to the input of multiplier 222 and the input of combiner 224. The combiner can be based on the product value U P and the previous value U of the control signal U D (n-1) to generate an updated value U D (n) control signal U.

[0053] As indicated above, Figure 2 Provided as examples. Other examples may differ from the Figure 2 As described. Figure 2 The number and arrangement of components shown are provided as examples. In practice, the controller 200 may include more Figure 2 The components shown may include more components, fewer components, different components, or components in a different arrangement. Figure 2 Two or more of the components shown may be implemented in a single component, or Figure 2 The single components shown may be implemented as multiple distributed components. Additionally or alternatively, one set of components (eg, one or more components) of the controller 200 may perform one or more functions described as being performed by another set of components of the controller 200.

[0054] Figure 3 A system diagram 300 of a boost PFC converter according to one or more implementations is shown. The system diagram 300 may be combined with Figure 1 1 is a representation of the SMPS 100 described herein. The system diagram includes a power switch stage 301 including an inductor 106, a diode 108, a capacitor 110, and a power switch 112; and a control circuit 302 including the circuitry of a controller 114 (e.g., controller 200). The power switch stage 301 is composed of a transfer function 303 (e.g., Vin) of a boost power conversion. 2 / (2LVout)) and a transfer function 304 (eg, 1 / Cs) of capacitor 110.

[0055] The first processing circuit 212 may include a current sensor 305 configured to sense the output current Iout and provide a sensor signal to a multiplier 306. The multiplier 306 may calculate the output power Pout based on the output current Iout and the output voltage Vout. Therefore, the first processing circuit 212 uses the output current Iout and the output voltage Vout as feedforward parameters. In some implementations, the output power Pout may be used as one of the feedforward parameters.

[0056] The second processing circuit 214 may generate a feedforward signal U based on the change ΔPout of the output power Pout. DffThe second processing circuit 214 may calculate the feedforward signal U in the continuous domain or the digital domain. Dff (P=Pout). For example, the feedforward signal U Dff can be equal to ΔPout / Pout. Therefore, the feedforward signal U Dff It can depend on the time derivative or rate of change of the output power Pout. For example, the feedforward signal U Dff It can be proportional to the time derivative or rate of change of the output power Pout. Therefore, the feedforward signal U Dff Can indicate relative changes in load conditions.

[0057] Feedforward signal U Dff can be combined with the filtered error signal Y to generate the integrator input signal U D . Integrator input signal U D can be integrated by a nonlinear integral function to generate a control signal U.

[0058] Therefore, the relative power change can be used to perform feed-forward compensation to avoid errors that may be caused by high manufacturing tolerances and / or uncertainties associated with absolute power measurements. In addition, due to the normalization of the internal feed-forward signal, any unknown measurement gain error or any unknown circuit parameter can be offset. Moreover, in a two-stage power converter, the output power Pout is known from the DC-DC stage. Therefore, the output power Pout from the DC-DC stage can be used as a feed-forward parameter.

[0059] As indicated above, Figure 3 Provided as examples. Other examples may differ from the Figure 3 As described.

[0060] Figure 4 A system diagram 400 of a power converter according to one or more implementations is shown. The power converter may have a converter topology, such as a converter topology of an SMPS. The system diagram 400 includes a power stage 401 and a control circuit 402, the control circuit 402 including circuitry of a controller 114 (e.g., controller 200). The power stage 401 may include at least one power switch and may be represented by a power stage transfer function. The first processing circuit 212 may receive an input voltage Vin, an output current Iout, and an output voltage Vout as feedforward parameters, and may generate an internal feedforward signal U based on a function of at least one of the feedforward parameters. ff The function may correspond to a converter topology of the power converter. In some implementations, the output power Pout may be used as one of the feedforward parameters.

[0061] The second processing circuit 214 may be configured based on the internal feedforward signal U ff Change of ΔU ffGenerate feedforward signal U Dff The second processing circuit 214 may calculate the feedforward signal U in the continuous domain or the digital domain. Dff For example, the feedforward signal U Dff Can be equal to ΔU ff / U ff Therefore, the feedforward signal U Dff can depend on the internal feedforward signal U ff The time derivative or rate of change of . For example, the feedforward signal U Dff Can be combined with the internal feedforward signal U ff The time derivative or rate of change of is proportional to . Therefore, the feedforward signal U Dff It can indicate relative changes in load conditions or relative changes in input voltage conditions.

[0062] Feedforward signal U Dff can be combined with the filtered error signal Y to generate the integrator input signal U D . Integrator input signal U D can be integrated by a nonlinear integral function to generate a control signal U.

[0063] Therefore, relative load changes or relative input changes can be used to perform feedforward compensation to avoid errors that may be caused by high manufacturing tolerances and / or uncertainties associated with absolute power measurements. In addition, due to the normalization of the internal feedforward signal, any unknown measurement gain error or any unknown circuit parameter can be offset. In addition, in a single-stage power converter, the output power Pout can be measured at the output of the single-stage power converter. In addition, in a two-stage power converter, the output power Pout is known from the DC-DC stage. Therefore, the output power Pout from the output of the single-stage power converter or the DC-DC stage of the two-stage power converter can be used as a feedforward parameter.

[0064] As indicated above, Figure 4 Provided as examples. Other examples may differ from the Figure 4 As described.

[0065] The following provides an overview of some aspects of the disclosure:

[0066] Aspect 1: An SMPS configured to provide output power to a load, comprising: a power switch (e.g., at least one power switch) configured to receive a PWM control signal to control the output power, wherein the SMPS is configured to use the power switch to convert an input voltage into an output voltage and generate an output current; a controller configured to adjust the PWM control signal for controlling the output power, wherein the controller comprises: an error generator configured to generate an error signal based on a difference between an output voltage and a target output voltage; a filter configured to generate a filtered error signal based on the error signal; a feedforward processing circuit configured to receive at least one feedforward parameter related to at least one of an output voltage, an output current, an output power, and an input voltage, and to generate a feedforward signal based on the at least one feedforward parameter; a combiner configured to generate an integrator input signal based on a sum of the feedforward signal and the filtered error signal; and a nonlinear integrator configured to apply a nonlinear integral function to the integrator input signal to generate a PWM control signal.

[0067] Aspect 2: The SMPS according to aspect 1, wherein the filter is a linear filter having a substantially linear transfer function.

[0068] Aspect 3: An SMPS according to any one of Aspects 1 to 2, wherein the feedforward processing circuit is configured to generate a feedforward signal such that the feedforward signal is zero during a steady-state load condition and deviates from zero during a load change under a non-steady-state load condition to minimize the filtered error signal during the load change.

[0069] Aspect 4: An SMPS according to any one of Aspects 1 to 3, wherein the feedforward processing circuit is configured to generate an internal feedforward signal based on a function of at least one feedforward parameter, the function corresponding to the topology of the SMPS, wherein the feedforward processing circuit is configured to subtract a previous value of the internal feedforward signal from an updated value of the internal feedforward signal to generate a difference value of the internal feedforward signal, and wherein the feedforward processing circuit is configured to divide the difference value by a value corresponding to the internal feedforward signal to generate the feedforward signal.

[0070] Aspect 5: The SMPS of aspect 4, wherein the SMPS is a power factor correction (PFC) boost converter configurable in critical conduction mode, and wherein, during critical conduction mode, the internal feedforward signal is configured to be proportional to the output power of the SMPS.

[0071] Aspect 6: The SMPS of aspect 4, wherein the feedforward processing circuit is configured to generate an internal feedforward signal proportional to a steady-state value of the PWM control signal.

[0072] Aspect 7: The SMPS according to any one of aspects 1 to 6, wherein the PWM control signal is an on-time of the power switch.

[0073] Aspect 8: An SMPS according to any one of Aspects 1 to 7, wherein the feedforward processing circuit is configured to monitor a relative load change or a relative change in an input voltage condition based on at least one feedforward parameter, and to generate a feedforward signal based on the relative load change or the relative change in the input voltage condition.

[0074] Aspect 9: A controller configured to control an SMPS based on a PWM control signal to convert an input voltage into an output voltage, the controller comprising: an error generator configured to generate an error signal based on a difference between an output voltage and a target output voltage; a filter configured to generate a filtered error signal based on the error signal; a feedforward processing circuit configured to monitor changes in output current, output voltage, or input voltage corresponding to changes in load conditions, and to generate a feedforward signal based on the changes in output current, output voltage, or input voltage; a combiner configured to generate an integrator input signal based on the sum of the feedforward signal and the filtered error signal; and a nonlinear integrator configured to apply a nonlinear integral function to the integrator input signal to generate a PWM control signal.

[0075] Aspect 10: The controller according to aspect 9, wherein the feedforward processing circuit is configured to generate a feedforward signal to drive an average value of the filtered error signal to a target error value.

[0076] Aspect 11: The controller of any one of aspects 9 to 10, wherein the feedforward processing circuit is configured to generate the feedforward signal to minimize the filtered error signal during load changes.

[0077] Aspect 12: The controller of any one of aspects 9 to 11, wherein the feedforward processing circuit is configured to generate the feedforward signal to minimize the magnitude and duration of a transient deviation of the output voltage from a target value during a load change.

[0078] Aspect 13: The controller according to any one of aspects 9 to 12, wherein the feedforward signal represents at least one of a relative change in load conditions or a relative change in input voltage conditions.

[0079] Aspect 14: A controller according to any one of Aspects 9 to 13, wherein the feedforward processing circuit is configured to receive at least one feedforward parameter, wherein the at least one feedforward parameter is related to at least one of an output voltage, an output current, an output power of the SMPS, and an input voltage, wherein the feedforward processing circuit is configured to generate an internal feedforward signal based on a function of the at least one feedforward parameter, the function corresponding to a topology of the SMPS, wherein the feedforward processing circuit is configured to subtract a previous value of the internal feedforward signal from an updated value of the internal feedforward signal to generate a difference value of the internal feedforward signal, and wherein the feedforward processing circuit is configured to divide the difference value by a value corresponding to the internal feedforward signal to generate the feedforward signal.

[0080] Aspect 15: A controller according to Aspect 14, wherein the controller is a digital controller configured to operate in discrete time steps, wherein the feedforward processing circuit is configured to update the internal feedforward signal at each discrete time step, and wherein a previous value of the internal feedforward signal corresponds to a previous discrete time step and an updated value of the internal feedforward signal corresponds to the latest discrete time step.

[0081] Aspect 16: The controller according to any one of aspects 9 to 15, wherein the feedforward processing circuit is configured to generate an internal feedforward signal proportional to a steady-state value of the PWM control signal.

[0082] Aspect 17: A controller according to any one of Aspects 9 to 16, wherein the nonlinear integrator includes: a multiplier configured to multiply the integrator input signal with a previous value of the PWM control signal to generate a product value; and a combiner configured to generate a PWM control signal with an updated value based on the sum of the product value and the previous value of the PWM control signal.

[0083] Aspect 18: A method for controlling an SMPS based on a PWM control signal to convert an input voltage into an output voltage, the method comprising: generating an error signal based on a difference between an output voltage and a target output voltage; filtering the error signal to generate a filtered error signal; generating a feedforward signal based on at least one feedforward parameter related to at least one of the output voltage, the input voltage, the output power of the SMPS, and an output current corresponding to the output voltage; adding the feedforward signal and the filtered error signal to generate an integrator input signal; and applying a nonlinear integral function to the integrator input signal to generate a PWM control signal.

[0084] Aspect 19: The method of aspect 18, wherein the feedforward signal is configured to be zero during steady-state load conditions and deviate from zero during load changes under non-steady-state load conditions to minimize the filtered error signal during load changes.

[0085] Aspect 20: The method according to any one of Aspects 18 to 19 further includes: generating an internal feedforward signal based on a function of at least one feedforward parameter, the function corresponding to the topology of the SMPS; subtracting a previous value of the internal feedforward signal from an updated value of the internal feedforward signal to generate a difference value of the internal feedforward signal; and dividing the difference value by a value corresponding to the internal feedforward signal to generate a feedforward signal.

[0086] Aspect 21: A system configured to perform one or more operations described in one or more of Aspects 1 to 20.

[0087] Aspect 22: An apparatus comprising means for performing one or more operations described in one or more of aspects 1 to 20.

[0088] Aspect 23: A non-transitory computer-readable medium storing an instruction set, the instruction set comprising one or more instructions, which, when executed by a device, causes the device to perform one or more operations described in one or more of Aspects 1 to 20.

[0089] Aspect 24: A computer program product comprising instructions or codes for performing one or more operations described in one or more of Aspects 1 to 20.

[0090] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the implementation.

[0091] As used herein, the term "component" is intended to be broadly interpreted as hardware, firmware, or a combination of hardware and software. The systems and / or methods described herein can be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods does not limit the implementation. Therefore, the operation and behavior of the systems and / or methods are described herein without reference to specific software codes, and it should be understood that software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0092] Any processing component can be implemented as a central processing unit (CPU) or other processor that reads and executes a software program from a non-transitory computer-readable recording medium such as a hard disk or a semiconductor memory device. For example, instructions can be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable logic arrays (FPLAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" used in this article refers to any of the aforementioned structures or any other structure suitable for implementing the technology described herein. The software can be stored on a non-transitory computer-readable medium, so that the non-transitory computer-readable medium includes a program code or a program algorithm stored thereon, which causes the processor to perform the steps of the method via a computer program when executed.

[0093] A controller including hardware may also perform one or more of the techniques of the present disclosure. A controller including one or more processors may use electrical signals and digital algorithms to perform its reception, analysis, and control functions, which may also include correction functions. Such hardware, software, and firmware may be implemented in the same device or in separate devices to support the various techniques described in the present disclosure.

[0094] Signal processing circuitry and / or signal conditioning circuitry may receive one or more signals (e.g., measurement signals) in the form of raw measurement data from one or more components, and may derive additional information from the measurement signals. As used herein, "signal conditioning" refers to manipulating an analog signal so that the signal meets the requirements of the next stage for further processing. Signal conditioning may include conversion from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other processing required to make the signal suitable for processing after conditioning.

[0095] Even if a particular feature combination is listed in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the implementation described herein. Many of these features can be combined in a manner not specifically listed in the claims and / or not disclosed in the specification. For example, the disclosure includes each dependent claim in the claim set combined with each other independent claim in the claim set and each combination of multiple claims in the claim set. As used herein, the phrase "at least one" in the list of items refers to any combination of these items, including a single member. As an example, "at least one of a, b or c" is intended to cover a, b, c, a and b, a and c, b and c and a, b and c, and any combination with multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c and c+c+c, or any other order of a, b and c).

[0096] In addition, it should be understood that the disclosure of multiple actions or functions disclosed in the specification or claims may not be interpreted as being in a specific order. Therefore, the disclosure of multiple actions or functions will not limit these actions or functions to a specific order, unless such actions or functions are not interchangeable due to technical reasons. In addition, in some implementations, a single action may include multiple sub-actions or may be decomposed into multiple sub-actions. Unless explicitly excluded, such sub-actions may be included and are part of the disclosure of the single action.

[0097] Unless explicitly described as such, any element, action or instruction used herein should not be interpreted as critical or necessary. In addition, as used herein, the article "a" and "an" are intended to include one or more projects, and can be used interchangeably with "one or more". In addition, as used herein, the article "the" is intended to include one or more projects quoted in combination with the article "the", and can be used interchangeably with "one or more". In the case of being intended to only one project, phrases "only one", "single" or similar language are used. In addition, as used herein, the term "has", "have", "having" etc. are intended to be open terms (for example, "having" A elements may also have B) that do not limit the elements modified. In addition, unless otherwise explicitly stated, the phrase "based on" is intended to mean "based at least in part". As used herein, the term "multiple" can be replaced with "a plurality of", and vice versa. Furthermore, as used herein, the term "or" when used in series is intended to be inclusive and may be used interchangeably with "and / or" unless expressly stated otherwise (eg, if used in conjunction with "either" or "only one").

Claims

1. A switch mode power supply (SMPS) configured to provide output power to a load, comprising: a power switch configured to receive a pulse width modulation (PWM) control signal to control the output power, wherein the SMPS is configured to convert an input voltage into an output voltage and generate an output current using the power switch; A controller configured to adjust the PWM control signal for controlling the output power, wherein the controller comprises: an error generator configured to generate an error signal based on a difference between the output voltage and a target output voltage; a filter configured to generate a filtered error signal based on the error signal; a feedforward processing circuit configured to receive at least one feedforward parameter related to at least one of the output voltage, the output current, the output power, and the input voltage, and to generate a feedforward signal based on the at least one feedforward parameter; a combiner configured to generate an integrator input signal based on a sum of the feedforward signal and the filtered error signal; and A non-linear integrator is configured to apply a non-linear integration function to the integrator input signal to generate the PWM control signal.

2. The SMPS according to claim 1, wherein: The filter is a linear filter with a linear transfer function.

3. The SMPS according to claim 1, wherein: The feedforward processing circuit is configured to generate the feedforward signal such that the feedforward signal is zero during steady-state load conditions and deviates from zero during load changes under non-steady-state load conditions to minimize the filtered error signal during the load changes.

4. The SMPS according to claim 1, wherein: The feedforward processing circuit is configured to generate an internal feedforward signal based on a function of the at least one feedforward parameter, the function corresponding to a topology of the SMPS, wherein the feedforward processing circuit is configured to subtract a previous value of the internal feedforward signal from an updated value of the internal feedforward signal to generate a difference value of the internal feedforward signal, and The feedforward processing circuit is configured to divide the difference by a value corresponding to the internal feedforward signal to generate the feedforward signal.

5. The SMPS according to claim 4, wherein: The SMPS is a configurable power factor corrected boost converter in critical conduction mode, and Wherein, during the critical conduction mode, the internal feed-forward signal is configured to be proportional to the output power of the SMPS.

6. The SMPS according to claim 4, wherein: The feedforward processing circuit is configured to generate the internal feedforward signal proportional to a steady-state value of the PWM control signal.

7. The SMPS according to claim 1, wherein: The PWM control signal is the on-time of the power switch.

8. The SMPS according to claim 1, wherein: The feedforward processing circuit is configured to monitor a relative load change or a relative change in input voltage conditions based on the at least one feedforward parameter and to generate the feedforward signal based on the relative load change or the relative change in the input voltage conditions.

9. A controller, the controller being configured to control a switch mode power supply (SMPS) to convert an input voltage into an output voltage based on a pulse width modulation (PWM) control signal, the controller comprising: an error generator configured to generate an error signal based on a difference between the output voltage and a target output voltage; a filter configured to generate a filtered error signal based on the error signal; a feedforward processing circuit configured to monitor a change in output current, a change in the output voltage, or a change in the input voltage corresponding to a change in a load condition, and to generate a feedforward signal based on the change in the output current, the change in the output voltage, or the change in the input voltage; a combiner configured to generate an integrator input signal based on a sum of the feedforward signal and the filtered error signal; as well as A non-linear integrator is configured to apply a non-linear integration function to the integrator input signal to generate the PWM control signal.

10. The controller according to claim 9, wherein: The feedforward processing circuit is configured to generate the feedforward signal to drive an average value of the filtered error signal to a target error value.

11. The controller according to claim 9, wherein: The feedforward processing circuit is configured to generate the feedforward signal to minimize the filtered error signal during load changes.

12. The controller according to claim 9, wherein: The feedforward processing circuit is configured to generate the feedforward signal to minimize the magnitude and duration of a transient deviation of the output voltage from a target value during a load change.

13. The controller according to claim 9, wherein: The feed-forward signal represents at least one of a relative change in load conditions and a relative change in input voltage conditions.

14. The controller according to claim 9, wherein: The feedforward processing circuit is configured to receive at least one feedforward parameter, the at least one feedforward parameter being related to at least one of the output voltage, the output current, the output power of the SMPS and the input voltage, wherein the feedforward processing circuit is configured to generate an internal feedforward signal based on a function of the at least one feedforward parameter, the function corresponding to the topology of the SMPS, wherein the feedforward processing circuit is configured to subtract a previous value of the internal feedforward signal from an updated value of the internal feedforward signal to generate a difference value of the internal feedforward signal, and The feedforward processing circuit is configured to divide the difference by a value corresponding to the internal feedforward signal to generate the feedforward signal.

15. The controller according to claim 14, wherein: The controller is a digital controller configured to operate in discrete time steps, wherein the feedforward processing circuit is configured to update the internal feedforward signal at each discrete time step, and Therein, the previous value of the internal feedforward signal corresponds to the previous discrete time step, and the updated value of the internal feedforward signal corresponds to the latest discrete time step.

16. The controller according to claim 9, wherein: The feedforward processing circuit is configured to generate an internal feedforward signal proportional to a steady-state value of the PWM control signal.

17. The controller according to claim 9, wherein: The nonlinear integrator comprises: a multiplier configured to multiply the integrator input signal by a previous value of the PWM control signal to generate a product value; and A combiner is configured to generate the PWM control signal having an updated value based on a sum of the product value and a previous value of the PWM control signal.

18. A method for controlling a switch mode power supply (SMPS) based on a pulse width modulation (PWM) control signal to convert an input voltage into an output voltage, the method comprising: generating an error signal based on a difference between the output voltage and a target output voltage; filtering the error signal to generate a filtered error signal; generating a feedforward signal based on at least one feedforward parameter related to at least one of the output voltage, the input voltage, an output power of the SMPS, and an output current corresponding to the output voltage; adding the feedforward signal and the filtered error signal to generate an integrator input signal; as well as A non-linear integration function is applied to the integrator input signal to generate the PWM control signal.

19. The method according to claim 18, wherein: The feed-forward signal is configured to be zero during steady-state load conditions and to deviate from zero during load changes under non-steady-state load conditions to minimize the filtered error signal during the load changes.

20. The method of claim 18, further comprising: generating an internal feedforward signal based on a function of the at least one feedforward parameter, the function corresponding to a topology of the SMPS; subtracting a previous value of the internal feedforward signal from an updated value of the internal feedforward signal to generate a difference value of the internal feedforward signal; as well as The difference is divided by a value corresponding to the internal feedforward signal to generate the feedforward signal.

Images