Multi-load constant power circuit

Abstract

The invention provides a multi-load constant power circuit, which relates to the technical field of circuits and comprises a load module, an MOS (Metal Oxide Semiconductor) tube, an output module and a pulse generation module, one end of the load module is used for accessing a constant current, and the other end of the load module is electrically connected with the MOS tube and the interface end of the output module; the control end of the MOS tube and output module is electrically connected with the output end of the pulse generation module; the input end of the pulse generation module is used for inputting a state control instruction and a clock signal; when the access states of a plurality of loads in the load module need to be adjusted, a trigger value provided by the state control instruction is adjusted, and the pulse generation module adjusts an output control signal according to the change of the trigger value. The MOS tube and output module adjusts the conduction degree and the conduction duration of branches where all loads in the load module are located according to the change of the control signal, so that the load module is driven by the constant current to work at constant power all the time.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a multi-load constant power circuit. Background Art

[0002] like Figure 1 As shown in the figure, the output of the constant current module is the positive power line and the negative power line, and the negative power line is regarded as the 0V reference point. In the circuit driven by the constant current module, there is more than one load (included in the load module), but the total power of the system needs to be kept constant. The most direct approach is to use some sliding rheostats (included in the current limiting module) and other devices with current limiting and voltage dividing properties to limit the current according to the characteristics of each part of the load to adjust the current allocated to each load. However, this approach will lead to some problems: first, part of the energy is wasted on the sliding rheostat, and second, when the system sometimes needs to disable some of the multiple loads, the resistance of the sliding rheostat connected in series with these loads to be disabled needs to be very large, and the resistance of the sliding rheostat connected in series with other loads needs to be adjusted. If the sliding rheostat is to be adjusted by the circuit (included in the control module), it is difficult to implement and the cost is high.

[0003] Therefore, there is a need for a multi-load constant power circuit suitable for a constant current module, which has low implementation difficulty, low cost, and can minimize energy waste. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a multi-load constant power circuit, comprising: a load module, a MOS tube and an output module, and a pulse generating module; One end of the load module is used to connect to the constant current, and the other end is electrically connected to the MOS tube and the interface end of the output module; The control end of the MOS tube and the output module is electrically connected to the output end of the pulse generating module; The input end of the pulse generating module is used to input state control instructions and clock signals; Among them, when it is necessary to adjust the access status of multiple loads inside the load module, the trigger value provided by the state control instruction is adjusted, the pulse generation module adjusts the output control signal according to the change of the trigger value, and the MOS tube and output module adjust the conduction degree and conduction time of the branch where each load in the load module is located according to the change of the control signal, so that the load module always operates at a constant power under the drive of the constant current.

[0005] In a possible implementation, the load module includes n loads; The first ends of the n loads are respectively used to access the constant current, and the second ends of the n loads are respectively electrically connected to the MOS tube and the n interfaces of the output module; Here, n is an integer greater than 1.

[0006] In a possible implementation, the MOS tube and output module includes n MOS tube units; The control ends of the n MOS tube units are electrically connected to the output end of the pulse generating module, the first ends of the n MOS tube units are electrically connected to the second ends of the n loads, and the second ends of the n MOS tube units are electrically connected to the ground. The n MOS tube units respectively adjust the conduction degree and conduction duration between their first and second ends according to the change of the control signal, so that the load module always works at a constant power under the drive of the constant current.

[0007] In a possible implementation, each of the control terminals of the n MOS tube units is provided with a delay module.

[0008] In a possible implementation, the effect of the delay module is: when the MOS tube unit of the branch needs to be turned on, the delay time is short or there is no delay; when the MOS tube unit of the branch needs to be turned off, the delay time is long.

[0009] In a possible implementation, the circuit where each of the delay modules is located is a driving branch, and its delay time is determined by the response time of other driving branches.

[0010] In a possible implementation, the pulse generating module is constructed based on a decoding module, a comparing module, a counting module, and a logic gate unit.

[0011] In a possible implementation, a filtering module is further provided in the pulse generating module.

[0012] In a possible implementation, the device further includes a control logic module electrically connected to the pulse generating module, and configured to provide the state control instruction to the pulse generating module.

[0013] In a possible implementation manner, a constant current module electrically connected to the load module is further included to provide the constant current.

[0014] The technical solution provided by the present invention has at least the following beneficial effects: By applying the contents of the present invention, a multi-load constant power circuit suitable for a constant current module can be obtained. The circuit can achieve a constant power effect when the constant current module carries multiple loads and the specific working load changes. It has low implementation difficulty and low cost, and can minimize energy waste. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1It is the constant power principle diagram of the current limiting module in the background technology; Figure 2 A circuit schematic diagram of a multi-load constant power circuit provided by an embodiment of the present invention; Figure 3 A first specific circuit schematic diagram of a multi-load constant power circuit provided by an embodiment of the present invention; Figure 4 A second specific circuit schematic diagram of a multi-load constant power circuit provided by an embodiment of the present invention; Figure 5 A third specific circuit schematic diagram of a multi-load constant power circuit provided by an embodiment of the present invention; Figure 6 A first internal circuit schematic diagram of a MOS tube and an output module provided by an embodiment of the present invention; Figure 7 A second internal circuit schematic diagram of a MOS tube and an output module provided by an embodiment of the present invention; Figure 8 A third internal circuit schematic diagram of the MOS tube and output module provided by an embodiment of the present invention; Fig. 9 A first timing diagram provided for an embodiment of the present invention; Fig.10 A second timing diagram provided for an embodiment of the present invention; Fig.11 A third timing diagram provided for an embodiment of the present invention; In the accompanying drawings, 10, load module; 11, MOS tube and output module; 12, pulse generation module; 13, test module; 14, control logic module; 15, constant current module; 101, first load; 102, second load; 103, third load; 111, first delay module; 112, second delay module; 113, third delay module; 114, first NMOS tube; 115, second NMOS tube; 116, third NMOS tube; 117, second NOT gate; 118, first AND gate; 119, second AND gate; 121, decoding module; 122, comparison module; 123, counting module; 124, OR gate; 125, first NOT gate; 126, filtering module. DETAILED DESCRIPTION

[0016] In order to deepen the understanding of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. The embodiments are only used to explain the present invention and do not limit the protection scope of the present invention.

[0017] Please refer to Figures 1 to 11 The present invention provides a multi-load constant power circuit, comprising: a load module 10, a MOS tube and output module 11, and a pulse generating module 12; One end of the load module 10 is used to connect to a constant current, and the other end thereof is electrically connected to the MOS tube and the interface end of the output module 11; The control end of the MOS tube and output module 11 is electrically connected to the output end of the pulse generating module 12; The input end of the pulse generating module 12 is used to input state control instructions and clock signals; Among them, when it is necessary to adjust the access status of multiple loads inside the load module 10, the trigger value provided by the state control instruction is adjusted, the pulse generation module 12 adjusts the output control signal according to the change of the trigger value, and the MOS tube and output module 11 adjusts the conduction degree and conduction time of the branch where each load in the load module 10 is located according to the change of the control signal, so that the load module 10 always operates at a constant power under the drive of the constant current.

[0018] In this embodiment, the power consumption of the multi-load constant power circuit except the load module 10 is negligible. The load module 10 includes multiple loads inside, and there are independent branches between each load, and the conduction of each branch is controlled by the MOS tube and the output module 11. Each load inside the load module 10 can be a light-emitting module (for example, a module based on a combination of light-emitting diodes in series and / or in parallel). The MOS tube and the output module 11 are mainly constructed based on MOS tubes, and play a role similar to a switch. Under the control of the pulse generating module 12, the conduction and cutoff (i.e., the degree of conduction) and the corresponding conduction time and cutoff time (i.e., the conduction duration) of the branches where each load in the load module 10 is located can be controlled based on the conduction state of its own MOS tube, so as to switch the access state of each load in the load module 10. The pulse generating module 12 can be constructed using a conventional digital logic circuit, or it can be constructed by a digital logic circuit and an analog circuit. It can be used to generate one or more signals, and the generated signal can contain one or more pulses in one cycle, which can be set according to actual needs. The state control instruction may include different trigger values ​​(such as 30, 60, etc.), which may be used to characterize the load switching time to be connected, and to control the total pulse width of the pulse within one cycle of the signal output by the pulse generating module 12, so that when the load connection demand inside the load module 10 changes, the system can still maintain constant power. The period of the clock signal may be 1 μs.

[0019] When the multi-load constant power circuit in the present application is working, the pulse generating module 12 processes the clock signal and the state control instruction after receiving the state control instruction (such as the trigger value is 30), and finally sends one or more signals containing one or more pulses in one cycle to the MOS tube and the output module 11.

[0020] It should be pointed out that in the present application, a specific situation in which the access status of each load inside the load module 10 needs to be adjusted is: assuming that the load module 10 includes two loads (load one and load two), in the initial state, load one works at the first voltage drop for the first working time, and load two works at the second voltage drop for the second working time, and the total working time of the two is a time period (for example, 100μs); after working for a period of time, the voltage drop of load one and load two changes. At this time, in order to keep the load module 10 at constant power, the working time of load one and load two needs to be adjusted. Another specific situation in which the access status of each load inside the load module 10 needs to be adjusted is: assuming that the load module 10 includes three loads (load one, load two, load three), in the initial state, load one and load two need to be connected to work together, and load three is not connected; at a certain moment, load one and load three need to be connected to work together, and load two is not connected according to actual application requirements. The load module 10 always works at a constant power when driven by a constant current, which means that in an ideal state, the total power of the load module 10 in any time period remains constant, rather than the total power being the same at any time.

[0021] In a possible implementation, the load module 10 includes n loads; The first ends of the n loads are respectively used to access the constant current, and the second ends of the n loads are respectively electrically connected to the MOS tube and the n interfaces of the output module 11; Here, n is an integer greater than 1.

[0022] In a specific implementation, n is 2, such as Figure 3 and Figure 4 , the load module 10 includes a first load 101 and a second load 102; the first ends of the first load 101 and the second load 102 are respectively used to access a constant current, and the second ends of each are respectively electrically connected to the first interface J1 and the second interface J2 of the MOS tube and the output module 11. In this embodiment, the first load 101 and the second load 102 can be conventional electrical devices, and their load voltage drops will change with changes in external conditions. For example: when the system just starts working, the voltage drop when a current of 0.2A flows through the first load 101 is 170V, and the voltage drop when a current of 0.2A flows through the second load 102 is 70V. After the system has been working for a period of time, the external conditions change (such as the temperature rises by 10 degrees), and the voltage drop when a current of 0.2A flows through the first load 101 becomes 120V, and the voltage drop when a current of 0.2A flows through the second load 102 becomes 60V.

[0023] In another specific implementation, n is 3, such as Figure 5, the load module 10 includes a first load 101, a second load 102, and a third load 103; the first ends of the first load 101, the second load 102, and the third load 103 are respectively used to access a constant current, and the second ends of each are respectively electrically connected to the first interface J1, the second interface J2, and the third interface J3 of the MOS tube and the output module 11. In this embodiment, the first load 101, the second load 102, and the third load 103 can be conventional light-emitting modules. The light-emitting module can be composed of light-emitting diodes connected in series and / or in parallel. The load characteristics of the first load 101, the second load 102, and the third load 103 are: the voltage drop of the first load 101 when a current of 60mA flows is 60V, the voltage drop of the second load 102 when a current of 60mA flows is 43V, and the voltage drop of the third load 103 when a current of 60mA flows is 29.9231V.

[0024] In a possible implementation, the MOS tube and output module 11 includes n MOS tube units; The control ends of the n MOS tube units are electrically connected to the output end of the pulse generating module 12, the first ends of the n MOS tube units are electrically connected to the second ends of the n loads, and the second ends of the n MOS tube units are electrically connected to the ground. The n MOS tube units adjust the conduction degree and conduction duration between their first and second ends respectively according to the change of the control signal, so that the load module 10 always works at a constant power under the drive of the constant current.

[0025] In a possible implementation, each of the control terminals of the n MOS tube units is provided with a delay module.

[0026] In a possible implementation, the effect of the delay module is: when the MOS tube unit of the branch needs to be turned on, the delay time is short or there is no delay; when the MOS tube unit of the branch needs to be turned off, the delay time is long.

[0027] In a possible implementation, the circuit where each of the delay modules is located is a driving branch, and its delay time is determined by the response time of other driving branches.

[0028] In this embodiment, the delay time of the delay module can be determined by the response time of other driving branches. Figure 6 and Figure 7 The delay time of the first delay module 111 is determined by the response time of the driving branch where the second delay module is located (i.e., the second driving branch). If the response time of the second driving branch is long, the delay time of the first delay module 111 is long; if the response time of the second driving branch is short, the delay time of the first delay module 111 is short.

[0029] In a first specific implementation, n is set to 2, such as Figure 3 and Figure 6 , the first MOS tube unit includes a first delay module 111 and a first NMOS tube 114, and the second MOS tube unit includes a second delay module 112, a second NMOS tube 115, and a second NOT gate 117; the input end of the first delay module 111 is electrically connected to the output end of the OR gate 124 and the input end of the second NOT gate 117, and its output end is electrically connected to the gate of the first NMOS tube 114; the input end of the second delay module 112 is electrically connected to the output end of the second NOT gate 117, and its output end is electrically connected to the gate of the second NMOS tube 115; the drains of the first NMOS tube 114 and the second NMOS tube 115 are electrically connected to the second ends of the first load 101 and the second load 102, respectively, and their respective sources are electrically connected to the ground. Furthermore, at any time in a working cycle, at most one of the first load 101 and the second load 102 is working. The working cycle can be understood as the first pulse signal (such as Fig. 9 ) cycle, in each cycle, only one load can work at the same time, so as to facilitate the calculation of the total power of the system in the cycle, reduce the amount of calculation and reduce the calculation complexity.

[0030] In this embodiment, Fig. 9 , the control signal includes a first pulse signal. The MOS tube and the output module 11 control the conduction time of the branch where the first load 101 and the second load 102 are located according to the first pulse signal, so that the load module 10 always works at a constant power under the drive of a constant current. The first pulse signal can be represented in the form of high and low levels. The period of the first pulse signal is 100μs. When the first pulse signal is at a high level, the first load 101 is connected, and when it is at a low level, the second load 102 is connected. When the first NMOS tube 114 and the second NMOS tube 115 are turned on, their conduction voltage drop is very small, and it is also ignored in subsequent calculations. The power consumption of the system other than the load module 10 is ignored. It is assumed that the voltage of the first load 101 and the second load 102 will change with changes in external conditions (such as temperature). The output current I of the constant current module 15 is 0.2A. The total power P of the load module 10 needs to be stabilized at 20W (within 1% error). The method of calculating the total power P of the system is as follows: P=(U1It1+U2It2) / T=(U1It1+U2It2) / (t1+t2)==20(W).

[0031] Among them, t1+t2=T, U1 is the voltage drop of the first load 101, U2 is the voltage drop of the second load 102, I is the current value of the constant current, t1 is the working time of the first load 101 in one cycle, t2 is the working time of the second load 102 in one cycle, and T is the period of the first pulse signal. According to the calculation method of the total system power P, it can be deduced that t 1= T*((P / I)-U2) / (U1-U2).

[0032] The control logic module 14 can be connected to the constant current module 15 through a voltage information line to monitor the voltage drop of the load module 10, or it can detect the voltage drop of the load module 10 through other detection modules and output the voltage drop information to the control logic module 14, which can be selected according to actual implementation needs.

[0033] When the system just starts working, the voltage drop U1 when the first load 101 flows through 0.2A current is 170V, and the voltage drop U2 when the second load 102 flows through 0.2A current is 70V. At this time, the control logic module 14 samples the positive power line voltage of 170V when the pulse generation module 12 outputs a high level, and the positive power line voltage is 70V when the pulse generation module 12 outputs a low level. In order to make the system enter a constant power 20W working state, the control logic module 14 outputs information for adjusting the pulse width (trigger value is 30), that is, its content is t1=30μs.

[0034] Calculation method: t1=T*((P / I)-U2) / (U1-U2)= 100*((20 / 0.2)-70) / (170-70) μs=30μs. Then, the pulse width output by the pulse generating module 12 is 30μs, and the system enters a constant power working state with a power of 20W.

[0035] After the system has been working for a period of time, the external conditions change (the temperature rises by 10 degrees), and the voltage drop U1 when the first load 101 flows through a current of 0.2A becomes 120V, and the voltage drop U2 when the second load 102 flows through a current of 0.2A becomes 60V. At this time, the control logic module 14 collects the positive power line voltage of 120V when the pulse generation module 12 outputs a high level, and collects the positive power line voltage of 60V when the pulse generation module 12 outputs a low level. Therefore, the control logic module 14 outputs the information of adjusting the pulse width (the trigger value is 67) at a certain moment in the cycle (for example, the 80μs of the cycle), that is, its content is t1=67μs.

[0036] Calculation method: t1=T*((P / I)-U2) / (U1-U2)= 100*((20 / 0.2)-60) / (120-60)μs≈67μs. Then, the pulse width output by the pulse generating module 12 is 67μs. After the power is temporarily reduced in the transition state, the system enters the constant power working state, and the power is 20.04W, which meets the requirement of error within 1%.

[0037] In a second specific implementation, n is set to 2, such as Figure 4 and Figure 7 , the first MOS tube unit includes a first delay module 111 and a first NMOS tube 114, and the second MOS tube unit includes a second delay module 112, a second NMOS tube 115, and a second NOT gate 117; the input end of the first delay module 111 is electrically connected to the output end of the OR gate 124, and its output end is electrically connected to the gate of the first NMOS tube 114; the input end of the second delay module 112 is electrically connected to the output end of the second NOT gate 117, and its output end is electrically connected to the gate of the second NMOS tube 115; the drains of the first NMOS tube 114 and the second NMOS tube 115 are electrically connected to the second ends of the first load 101 and the second load 102, respectively, and their respective sources are electrically connected to the ground; the input end of the second NOT gate 117 is electrically connected to the first output end of the decoding module 121. Furthermore, at any time in a working cycle, at most one of the first load 101 and the second load 102 is working. The working cycle can be understood as a first pulse signal (such as Fig.10 ) cycle, in each cycle, only one load can work at the same time, so as to facilitate the calculation of the total power of the system in the cycle, reduce the amount of calculation and reduce the calculation complexity.

[0038] In this embodiment, Fig.10 , the control signal includes a selection signal and a first pulse signal. The MOS tube and the output module 11 select the working load from the first load 101 and the second load 102 according to the selection signal, and control the conduction time of the branch where the selected load is located according to the first pulse signal, so that the load module 10 always works at a constant power under the drive of a constant current. Both the selection signal and the first pulse signal can be represented in the form of high and low levels. The period of the first pulse signal is 100μs. The selection signal and the first pulse signal are synchronization signals. When the selection signal is at a high level, only the first load 101 is connected, and when it is at a low level, only the second load 102 is connected.

[0039] In a third specific implementation manner, n is 3, such as Figure 5 and Figure 8The first MOS tube unit includes a first delay module 111 and a first NMOS tube 114, the second MOS tube unit includes a second delay module 112, a second NMOS tube 115, a second NOT gate 117, and a first AND gate 118, and the third MOS tube unit includes a third delay module 113, a third NMOS tube 116, and a second AND gate 119; the input end of the first delay module 111 is electrically connected to the output end of the OR gate 124, and the output end thereof is electrically connected to the gate of the first NMOS tube 114; the input end of the second delay module 112 is electrically connected to the output end of the first AND gate 118, and the output end thereof is electrically connected to the gate of the second NMOS tube 115; the input end of the third delay module 113 ... second NMOS tube 115; the input end of the third delay module 113 is electrically connected to the output end of the OR gate 124, and the output end thereof is electrically connected to the gate of the second NMOS tube 115; the input end of the third delay module 113 is electrically connected to the output end of the OR gate 124, and the output end thereof is electrically connected to the gate of the second NMOS tube 115; the input end of the third delay module 113 is electrically connected to the output end of the OR gate 124, and the output end thereof is electrically connected to the gate of the first NMOS tube 114. The output end of the second AND gate 119 is electrically connected, and its output end is electrically connected to the gate of the third NMOS tube 116; the drains of the first NMOS tube 114, the second NMOS tube 115, and the third NMOS tube 116 are electrically connected to the second ends of the first load 101, the second load 102, and the third load 103, respectively, and their respective sources are electrically connected to the ground; the input end of the second NOT gate 117 is connected to the first input end of the second AND gate 119 and then electrically connected to the first output end of the decoding module 121, and its output end is electrically connected to the first input end of the first AND gate 118; the second input end of the first AND gate 118 is connected to the second input end of the second AND gate 119 and then electrically connected to the output end of the first NOT gate 125. Furthermore, at any time within a working cycle, at most one load among the first load 101, the second load 102, and the third load 103 is working. The working cycle can be understood as the first pulse signal (such as Fig.11 ) cycle, in each cycle, only one load can work at the same time, so as to facilitate the calculation of the total power of the system in the cycle, reduce the amount of calculation and reduce the calculation complexity.

[0040] In this embodiment, Fig.11, the control signal includes a selection signal, a first pulse signal, and a second pulse signal. The levels of the first pulse signal and the second pulse signal are opposite. The MOS tube and the output module 11 select the working load from the first load 101, the second load 102, and the third load 103 according to the selection signal, and control the conduction time of the branch where the selected load is located according to the first pulse signal and the second pulse signal, so that the load module 10 always works at a constant power under the drive of a constant current. The selection signal, the first pulse signal, and the second pulse signal can all be represented in the form of high and low levels. The first pulse signal has two pulses, the initial pulse width of the main pulse is 30μs, the pulse width of the auxiliary pulse is 1us, and the period is 100μs. The second pulse signal corresponding to the first pulse signal also has two pulses, and the occurrence time of its high and low levels is opposite to the occurrence time of the high and low levels of the first pulse signal. The selection signal is at a low level, and the first load 101 and the second load 102 are allowed to be connected at this time. The voltage drop of the first load 101 when the current is 60mA is 60V, the voltage drop of the second load 102 when the current is 60mA is 43V, and the voltage drop of the third load 103 when the current is 60mA is 29.9231V. At this time: the first load 101 is connected when the first pulse signal is at a high level, and the first load 101 is not connected when the first pulse signal is at a low level; the second load 102 is connected when the second pulse signal is at a high level, and the second load 102 is not connected when the second pulse signal is at a low level. The method of calculating the total power P of the system is as follows: P=(U1It1+U2It2) / T=(U1It1+U2It2) / (t1+t2)=(60*0.06*0.000031+43*0.06*0.000069) / 0.0001=2.8962(W).

[0041] Among them, t1+t2=T, U1 is the voltage drop of the first load 101, U2 is the voltage drop of the second load 102, I is the current value of the constant current, t1 is the working time of the first load 101 in one cycle, t2 is the working time of the second load 102 in one cycle, and T is the period of the first pulse signal. It should be noted that the system needs to maintain the total power unchanged under different load combinations (the allowable error is less than 3%).

[0042] In this embodiment, Figure 6 , Figure 7 , Figure 8, the first delay module 111, the second delay module 112, and the third delay module 113 are all conventional modules with delay function, the first NMOS tube 114, the second NMOS tube 115, and the third NMOS tube 116 are all conventional NMOS tubes, the second NOT gate 117 is a conventional NOT gate, and the first AND gate 118 and the second AND gate 119 are all conventional AND gates. When the MOS tube and the output module 11 switch to different loads, the new load is first connected, and then the previous load is disconnected to prevent the constant current module 15 from having an excessively high voltage due to a temporary lack of load. This function is implemented by the first delay module 111, the second delay module 112, and the third delay module 113. The characteristics of these three modules are that there is no delay from low level to high level, and there is a delay from high level to low level. The switching (delay) time is very short and can be ignored when calculating power or other parameters.

[0043] In a possible implementation, it further includes a testing module 13; The n test points of the test module 13 are electrically connected to the n loads respectively, so as to verify that the n loads always operate at a constant power when driven by the constant current.

[0044] In a specific implementation, n is 3, such as Figure 5 and Fig.11 , the first pulse signal includes a main pulse and a secondary pulse, and the rising edge or falling edge of the secondary pulse is determined by the pulse width of the main pulse and the period of the first pulse signal; the test module 13 is electrically connected to the first load 101, the second load 102, and the third load 103, respectively, for monitoring the main pulse and the secondary pulse to verify that the first load 101, the second load 102, and the third load 103 always work at a constant power under the drive of the constant current. In this embodiment, the test module 13 is connected to the first load 101 through the first test point C1, connected to the second load 102 through the second test point C2, and connected to the third load 103 through the third test point C3. The pulse width of the main pulse can be set to not exceed 90μs. The test module 13 can monitor the conduction of the first load 101, the second load 102, and the third load 103 to verify whether the total power of the system remains unchanged. Further, one or more characteristics of the secondary pulse can be matched with the main pulse width, so that when the access state of the load branch pair changes, the load port current or voltage can be collected to obtain the information of the main pulse width of the next cycle. If the load module 10 has multiple loads, and the main pulse width information of the remaining loads can be deduced from the main pulse width information of one load, the circuit can be simplified so that only one load among the multiple loads has a periodic signal containing a secondary pulse.

[0045] In a possible implementation, the pulse generating module 12 is constructed based on a decoding module 121 , a comparing module 122 , a counting module 123 , and a logic gate unit.

[0046] In this embodiment, the decoding module 121, the comparison module 122, and the counting module 123 are all constructed by digital logic circuits, and the logic gate unit is constructed based on conventional logic gates. In a specific implementation, the counting cycle of the comparison module 122 is 100, that is, counting starts from 1, and restarts after counting to 100 (corresponding to the cycle of the first pulse signal 100 μs below). The counting cycle can be adjusted according to actual needs.

[0047] In a first specific embodiment, Figure 3 , the logic gate unit is constructed by an OR gate 124. The OR gate 124 is a conventional logic gate. The first input end of the decoding module 121 (having two output ends, the second output end and the third output end) is used to input a state control instruction, the second input end thereof is electrically connected to the first output end of the counting module 123, the second output end thereof is electrically connected to the first input end of the OR gate 124, and the third output end thereof is electrically connected to the first input end of the comparison module 122; the second input end of the comparison module 122 is electrically connected to the second output end of the counting module 123, and the output end thereof is electrically connected to the second input end of the OR gate 124; the input end of the counting module 123 is used to input a clock signal; the output end of the OR gate 124 is electrically connected to the MOS tube and the first control end 1C of the output module 11.

[0048] In a second specific embodiment, Figure 4 , the logic gate unit is constructed by an OR gate 124. The first input end of the decoding module 121 is used to input a state control instruction, the second input end thereof is electrically connected to the first output end of the counting module 123, the first output end thereof is electrically connected to the MOS tube and the selection end S of the output module 11, the second output end thereof is electrically connected to the first input end of the OR gate 124, and the third output end thereof is electrically connected to the first input end of the comparison module 122; the second input end of the comparison module 122 is electrically connected to the second output end of the counting module 123, and the output end thereof is electrically connected to the second input end of the OR gate 124; the input end of the counting module 123 is used to input a clock signal; the output end of the OR gate 124 is electrically connected to the first control end 1C of the MOS tube and the output module 11.

[0049] In a third specific embodiment, Figure 5, the logic gate unit is constructed by an OR gate 124 and a first NOT gate 125. The first NOT gate 125 is a conventional NOT gate. The first input end of the decoding module 121 is used to input a state control instruction, the second input end thereof is electrically connected to the first output end of the counting module 123, the first output end thereof is electrically connected to the selection end S of the MOS tube and the output module 11, the second output end thereof is electrically connected to the first input end of the OR gate 124, and the third output end thereof is electrically connected to the first input end of the comparison module 122; the second input end of the comparison module 122 is electrically connected to the second output end of the counting module 123, and the output end thereof is electrically connected to the second input end of the OR gate 124; the input end of the counting module 123 is used to input a clock signal; the output end of the OR gate 124 is electrically connected to the first control end 1C of the MOS tube and the output module 11, and the input end of the first NOT gate 125 respectively; the output end of the first NOT gate 125 is electrically connected to the second control end 2C of the MOS tube and the output module 11.

[0050] In a possible implementation, a filtering module 126 is further provided in the pulse generating module 12 .

[0051] In this embodiment, Figure 3 , Figure 4 , Figure 5 The comparison module 122 is connected to the second input terminal of the OR gate 124 through the filter module 126. The filter module 126 can be of conventional design and is used to eliminate the burr signal output by the comparison module 122. The pulse time error caused by the module can be ignored.

[0052] In a possible implementation, the device further includes a control logic module 14 electrically connected to the pulse generating module 12 and configured to provide the state control instruction to the pulse generating module 12 .

[0053] In this embodiment, the control logic module 14 is a conventional module, for example, it can be implemented based on a single chip. The values ​​communicated between the control logic module 14, the decoding module 121, the comparison module 122, and the counting module 123 are all integers (the decimal part of the number is removed to retain the integer).

[0054] In a possible implementation, a constant current module 15 electrically connected to the load module 10 is further included to provide the constant current.

[0055] In this embodiment, the constant current module 15 can adopt a conventional module for providing constant current, whose positive pole can be led out through the positive power line and connected to the positive pole of the load module 10, and whose negative pole can be led out through the negative power line and connected to the ground.

[0056] In a specific embodiment, Figure 5 , Figure 8 , Fig.11 , the constant current module 15 provides a constant current of 60mA for the system, the positive output is the positive power line, and the negative output is the negative power line. The negative power line can be regarded as a 0V reference point. When the multi-load constant power circuit of the present application is working, when the system needs to enable the first load 101 and the second load 102, you can refer to the following specific load enabling process. Assuming that the trigger value of the state control instruction is 30, it means that the first load 101 and the second load 102 need to be enabled, that is, connected; when the trigger value of the state control instruction is 60, it means that the first load 101 and the third load 103 need to be enabled, that is, connected. The specific process is as follows: like Figure 5 , Figure 8 , Fig.11 , the control logic module 14 sends a state control instruction to the decoding module 121, and the corresponding data value is 30 (that is, the trigger value is 30). After receiving the data value 30, the decoding module 121 outputs the data value 30 to the comparison module 122, and the comparison module 122 outputs a high level. The counting module 123 starts counting from 1, and when it counts to 31, the comparison module 122 outputs a low level. When the counting module 123 counts to (cycle + main pulse width) / 2=(100+30) / 2=65, the decoding module 121 outputs a 1μs wide pulse. The filtering module 126 is used to eliminate the burr signal output by the comparison module 122, and the pulse time error caused by this module is negligible. The signal output by the filtering module 126 to the OR gate 124 is a pulse signal starting from the beginning of the cycle and ending at the 30th μs in the cycle. The signal output by the decoding module 121 to the OR gate 124 is a pulse signal starting from the 65th μs in the cycle and ending at the 66th μs. The first pulse signal output by the OR gate 124 to the MOS tube and output module 11 is a cycle containing two high-level pulses, the main pulse width is 30μs, and the time when the auxiliary pulse rises is 65μs in the cycle. At this time, the selection signal is low. When the MOS tube and output module 11 receives the first pulse signal at a high level, the first load 101 is turned on. When the MOS tube and output module 11 receives the second pulse signal at a high level, the second load 102 is turned on. The test module 13 monitors the conduction information of the first load 101, and analyzes the information that the pulse rising edge appears at the 65μs of the cycle to obtain the main pulse width of the next cycle as (2*secondary pulse rising edge appearance time-cycle)=2*65-100=30μs.

[0057] When the system needs to enable the first load 101 and the third load 103 , the following is the process of modifying the load status.

[0058] Assume that at the 80 μs of the cycle, the control logic module 14 sends a state control instruction to the decoding module 121, and the corresponding data value is 60 (ie, the trigger value is 60). To maintain constant power, the total system power P = (U1It 1’+U3It3) / T,t 1’ +t3=T, so we can get t 1’ =(PT-U3IT) / ((U1-U3)I), U3 is the voltage drop of the third load 103, t 1’ is the working time of the first load 101 in one cycle after the modified load is connected (i.e., the total pulse width of the first pulse signal), and t3 is the working time of the third load 103 in one cycle after the modified load is connected. The total pulse width of the first pulse signal after the modified load is connected is calculated as follows: t 1’ =(PT-U3IT) / ((U1-U3)I)=(2.8962*0.0001-29.9231*0.06*0.0001) / ((60-29.9231)*0.06)=0.000061(s)=61(us).

[0059] Modify the total pulse width of the first pulse signal after the load is connected to subtract the secondary pulse width 1us to obtain the main pulse width PulseMain of 60us. In the second cycle, the decoding module 121 still outputs the data value 30 to the comparison module 122, and the path from the comparison module 122 to the filter module 126 still outputs a 30μs wide pulse to the OR gate 124, but the decoding module 121 outputs a 1μs wide high level pulse at (T+PulseMain) / 2=(100+60) / 2=80μs. The signal output by the OR gate 124 to the MOS tube and output module 11 is a cycle containing two high level pulses, the main pulse width is 30μs, and the time when the secondary pulse rising edge appears is the 80μs of the cycle. When the MOS tube and output module 11 receive the high level of the first pulse signal, the first load 101 is turned on. The test module 13 monitors the conduction information of the first load 101, and analyzes the information that the pulse rising edge appears at the 80 μs of the cycle, and the pulse width of the main pulse of the next cycle is (2*the time when the auxiliary pulse rising edge appears-T)=2*80-100=60 μs. Therefore, the test module 13 begins to prepare to detect the conduction data of the first load 101 corresponding to the pulse width of 60 μs and the conduction data of the third load 103 in the next cycle in detail when the next main pulse appears.

[0060] In the third cycle, similar to the above principle, the selection signal output by the decoding module 121 to the MOS tube and the output module 11 is at a high level. At this time, when the first pulse signal is at a high level, the first load 101 is connected, and when it is at a low level, the first load 101 is not connected; when the second pulse signal is at a high level, the third load 103 is connected, and when it is at a low level, the third load 103 is not connected. The decoding module 121 outputs a data value of 60 to the comparison module 122, and the first pulse signal output by the OR gate 124 to the MOS tube and the output module 11 is a signal containing two high-level pulses in one cycle, the main pulse width is 60μs, and the time when the rising edge of the secondary pulse occurs is the 80th μs of the cycle. When the main pulse appears, the test module 13 detects in detail the conduction data of the first load 101 corresponding to the pulse width of 60μs and the conduction data of the third load 103 in the next cycle for recording / calibration or other purposes. At this time, the total power P' of the system is calculated as follows: P'=(U1It1'+U3It3) / (t1+t3)=(60*0.06*0.000061+29.9231*0.06*0.000039) / 0.0001=2.8962(W).

[0061] It can be seen that P'=P, which indicates that the power of the system remains unchanged (allowing a maximum error of 3%) when the first load 101 and the second load 102 are enabled first and then the first load 101 and the third load 103 are enabled. The situation in the subsequent cycle is similar to the above situation.

[0062] The above embodiments should not limit the present invention in any way, and any technical solutions obtained by equivalent replacement or equivalent conversion shall fall within the protection scope of the present invention.

Claims

1. A multi-load constant power circuit, characterized in that: include: Load module, MOS tube and output module, pulse generation module; One end of the load module is used to connect to the constant current, and the other end is electrically connected to the MOS tube and the interface end of the output module; The control end of the MOS tube and the output module is electrically connected to the output end of the pulse generating module; The input end of the pulse generating module is used to input state control instructions and clock signals; Among them, when it is necessary to adjust the access status of multiple loads inside the load module, the trigger value provided by the state control instruction is adjusted, the pulse generation module adjusts the output control signal according to the change of the trigger value, and the MOS tube and output module adjust the conduction degree and conduction time of the branch where each load in the load module is located according to the change of the control signal, so that the load module always operates at a constant power under the drive of the constant current.

2. The multi-load constant power circuit according to claim 1, characterized in that: The load module includes n loads; The first ends of the n loads are respectively used to access the constant current, and the second ends of the n loads are respectively electrically connected to the MOS tube and the n interfaces of the output module; Here, n is an integer greater than 1.

3. The multi-load constant power circuit according to claim 2, characterized in that: The MOS tube and output module includes n MOS tube units; The control ends of the n MOS tube units are electrically connected to the output end of the pulse generating module, the first ends of the n MOS tube units are electrically connected to the second ends of the n loads, and the second ends of the n MOS tube units are electrically connected to the ground. The n MOS tube units respectively adjust the conduction degree and conduction duration between their first and second ends according to the change of the control signal, so that the load module always works at a constant power under the drive of the constant current.

4. The multi-load constant power circuit according to claim 3, characterized in that: The lines where the control ends of the n MOS tube units are located are respectively provided with delay modules.

5. The multi-load constant power circuit according to claim 4, characterized in that: The effect of the delay module is: when the MOS tube unit of the branch needs to be turned on, the delay time is short or there is no delay; when the MOS tube unit of the branch needs to be turned off, the delay time is long.

6. The multi-load constant power circuit according to claim 4, characterized in that: The circuit where each of the delay modules is located is a driving branch, and its delay time is determined by the response time of other driving branches.

7. The multi-load constant power circuit according to claim 2, characterized in that: The pulse generating module is constructed based on a decoding module, a comparing module, a counting module and a logic gate unit.

8. The multi-load constant power circuit according to claim 7, characterized in that: The pulse generating module is also provided with a filtering module.

9. The multi-load constant power circuit according to claim 1, characterized in that: It also includes a control logic module electrically connected to the pulse generating module, and is used to provide the state control instruction to the pulse generating module.

10. The multi-load constant power circuit according to claim 1, characterized in that: It also includes a constant current module electrically connected to the load module and used for providing the constant current.

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