Phase generation circuit based on double-ring structure, chip and automobile

Abstract

The invention relates to the technical field of automobile charging, and discloses a phase generation circuit based on a double-ring structure, a chip and an automobile, and the phase generation circuit comprises a phase-locked loop, a delay loop and a phase output circuit. The phase-locked loop is configured to generate a first control voltage according to a reference clock; the delay loop is connected with the phase-locked loop, and is configured to generate a second control voltage according to the reference clock, equally divide the period of the reference clock according to the first control voltage and the second control voltage, and generate a plurality of equally-spaced phases; the phase output circuit is connected with the delay ring and is configured to select a target phase output from a plurality of equally spaced phases. According to the first control voltage and the second control voltage, the period of the reference clock can be equally divided, and a plurality of equally-spaced phases are generated. By setting the parameters of the delay ring, the period of the reference clock can be changed, and the number of equal parts of the period of the reference clock is increased, so that higher-precision phase control is obtained.

Description

Technical Field

[0001] The present application relates to the field of automobile charging technology, for example, to a phase generation circuit, chip and automobile based on a dual-loop structure. Background Art

[0002] At present, with the popularity of electric vehicles, the demand for charging technology is growing. Charging efficiency and charging time are the focus of users, so the size of the charging current needs to be accurately controlled. Controlling the charging current can be achieved by adjusting the phase overlap time of the control signal of the charging power tube. This requires a set of sophisticated phase control mechanisms.

[0003] In the related art, the phase generating circuit adopts a single-loop structure based on a phase-locked loop, and generates a stable output signal by locking the phase and frequency of the input signal.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The single-loop structure may have limitations in the accuracy and flexibility of phase control, especially in application scenarios that require high-precision phase control, and cannot generate high-precision phase control.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a phase generation circuit, chip and vehicle based on a dual-loop structure to obtain higher-precision phase control.

[0009] In some embodiments, a phase generation circuit based on a dual-loop structure includes: a phase-locked loop, a delay loop, and a phase output circuit; the phase-locked loop is configured to generate a first control voltage based on a reference clock; the delay loop is connected to the phase-locked loop, and is configured to generate a second control voltage based on the reference clock, and to divide the period of the reference clock into equal parts based on the first control voltage and the second control voltage to generate multiple equally spaced phases; the phase output circuit is connected to the delay loop, and is configured to select a target phase output from multiple equally spaced phases.

[0010] Optionally, the phase-locked loop includes: a first phase frequency detector, a first charge pump, a loop filter and a voltage-controlled oscillator; the first phase frequency detector is connected to the voltage-controlled oscillator and is configured to generate a first phase error according to the phase of a reference clock and the phase of a first output clock output by the voltage-controlled oscillator; the first charge pump is connected to the first phase frequency detector and is configured to generate a first charge and discharge current according to the first phase error; the loop filter is connected to the first charge pump and is configured to generate a first control voltage according to the first charge and discharge current; the voltage-controlled oscillator is connected to the loop filter and is configured to adjust the first output clock according to the first control voltage so that the frequency of the first output clock is locked to the frequency of the reference clock.

[0011] Optionally, the loop filter includes: a first capacitor, a second capacitor and a resistor; the first end of the first capacitor and the first end of the second capacitor are connected to the first charge pump; the second end of the first capacitor is grounded; the second end of the second capacitor is connected to the first end of the resistor; and the second end of the resistor is grounded.

[0012] Optionally, the delay loop includes: a second phase frequency detector, a second charge pump and a voltage-controlled delay line; the second phase frequency detector is connected to the voltage-controlled delay line and is configured to generate a second phase error according to the phase of the reference clock and the phase of the second output clock output by the voltage-controlled delay line; the second charge pump is connected to the second phase frequency detector and is configured to generate a second charge and discharge current according to the second phase error, and to generate a second control voltage according to the second charge and discharge current; the voltage-controlled delay line is connected to both the second charge pump and the loop filter, and is configured to adjust the second output clock according to the first control voltage and the second control voltage, so that the delay of the second output clock is locked to a period of a reference clock and prevent the second output clock from being locked to a harmonic of the reference clock; when the delay of the second output clock is exactly equal to the period of a reference clock, the voltage-controlled delay line divides the period of a reference clock into equal parts to generate multiple equally spaced phases.

[0013] Optionally, the voltage-controlled delay line includes 32 delay units; the voltage-controlled delay line equally divides a period of a reference clock according to the delay units to generate 32 equally spaced phases.

[0014] Optionally, the phase output circuit includes: 8 phase output branches; all phase output branches are connected to the voltage-controlled delay line and are configured to select one phase from 32 equally spaced phases generated by the voltage-controlled delay line as the target phase output.

[0015] Optionally, each phase output branch includes: 32 multiplexers; the 32 multiplexers are respectively connected to 32 equally spaced phases generated by the voltage-controlled delay line, and one phase is selected from the 32 equally spaced phases as the target phase output.

[0016] Optionally, the phase generating circuit also includes: a trigger circuit; the trigger circuit is connected to the phase output circuit, and the target phase output by the phase output circuit serves as a sampling clock of the trigger circuit; the trigger circuit samples the external input PWM signal of the trigger circuit according to the sampling clock, and at the same time, the trigger circuit sets the PWM signal to a delayed preset phase.

[0017] In some embodiments, the chip includes a phase generation circuit based on a dual-ring structure as described above.

[0018] In some embodiments, a car includes a chip as described above.

[0019] The phase generation circuit, chip and automobile based on the dual-ring structure provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] The phase generation circuit provided by the embodiment of the present disclosure has a dual-loop structure composed of a phase-locked loop and a delay loop, wherein the phase-locked loop is configured to generate a first control voltage to ensure that the basic frequency of the system is locked, and the delay loop is configured to generate a second control voltage to achieve a finer phase adjustment. This dual-loop structure can better resist external interference and improve the stability of the system. According to the first control voltage and the second control voltage, the period of the reference clock can be divided equally to generate a plurality of equally spaced phases. By setting the parameters of the delay loop, the period of the reference clock can be changed, and the number of equally spaced periods of the reference clock can be increased, thereby obtaining a more precise phase control. In addition, the phase output circuit can select any one of a plurality of equally spaced phases as output as needed, providing a high degree of flexibility.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is a circuit block diagram of a phase generating circuit based on a dual-loop structure provided by an embodiment of the present disclosure;

[0024] Figure 2 is a circuit block diagram of a phase-locked loop in a phase generation circuit based on a dual-loop structure provided by an embodiment of the present disclosure;

[0025] Figure 3 is a circuit block diagram of a delay loop in a phase generation circuit based on a dual-loop structure provided by an embodiment of the present disclosure;

[0026] Figure 4 is a circuit block diagram of a phase output circuit in a phase generation circuit based on a dual-loop structure provided by an embodiment of the present disclosure;

[0027] Figure 5 is a circuit block diagram of another phase generating circuit based on a dual-ring structure provided by an embodiment of the present disclosure;

[0028] Figure 6 It is a circuit block diagram of another phase generation circuit based on a dual-ring structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0030] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0031] Unless otherwise stated, the term "plurality" means two or more.

[0032] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0033] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0034] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0035] Combination Figure 1 As shown, an embodiment of the present disclosure provides a phase generation circuit based on a dual-loop structure, including: a phase-locked loop 10 , a delay loop 20 and a phase output circuit 30 .

[0036] The phase-locked loop 10 is configured to generate a first control voltage according to a reference clock. The delay loop 20 is connected to the phase-locked loop 10 and configured to generate a second control voltage according to the reference clock, and to divide the period of the reference clock into equal parts according to the first control voltage and the second control voltage to generate a plurality of equally spaced phases. The phase output circuit 30 is connected to the delay loop 20 and configured to select a target phase output from a plurality of equally spaced phases.

[0037] The phase generation circuit provided in the embodiment of the present disclosure has a dual-loop structure composed of a phase-locked loop 10 and a delay loop 20, wherein the phase-locked loop 10 is configured to generate a first control voltage to ensure that the basic frequency of the system is locked, and the delay loop 20 is configured to generate a second control voltage to achieve a finer phase adjustment. This dual-loop structure can better resist external interference and improve the stability of the system. According to the first control voltage and the second control voltage, the period of the reference clock can be divided equally to generate a plurality of equally spaced phases. By setting the parameters of the delay loop 20, the period of the reference clock can be changed, and the number of equally spaced periods of the reference clock can be increased, thereby obtaining a more precise phase control. In addition, the phase output circuit 30 can select any one of a plurality of equally spaced phases as output as needed, providing a high degree of flexibility, so that it can adapt to different application scenarios, such as different charging current control requirements.

[0038] Optionally, combined Figure 2 and Figure 6 As shown, the phase-locked loop 10 includes: a first phase frequency detector PFD1, a first charge pump CP1, a loop filter LF and a voltage-controlled oscillator VCO. The first phase frequency detector PFD1 is connected to the voltage-controlled oscillator VCO, and is configured to generate a first phase error according to the phase of the reference clock and the phase of the first output clock output by the voltage-controlled oscillator VCO. The first charge pump CP1 is connected to the first phase frequency detector PFD1, and is configured to generate a first charge-discharge current according to the first phase error. The loop filter LF is connected to the first charge pump CP1, and is configured to generate a first control voltage V1 according to the first charge-discharge current. The voltage-controlled oscillator VCO is connected to the loop filter LF, and is configured to adjust the first output clock according to the first control voltage V1, so that the frequency of the first output clock is locked to the frequency of the reference clock.

[0039] In this embodiment, the phase-locked loop 10 is used as a phase negative feedback system, and the first phase frequency detector PFD1 is a key component in the phase-locked loop 10, which is used to compare the phase and frequency differences between the reference clock and the first output clock output by the voltage-controlled oscillator VCO. When the phases of the reference clock and the first output clock are inconsistent, the first phase frequency detector PFD1 will generate a first phase error to reflect the phase difference between the two clocks. The first charge pump CP1 receives the first phase error from the first phase frequency detector PFD1, and generates a first charge and discharge current of corresponding magnitude and direction according to this signal. If the first phase frequency detector PFD1 detects a phase error, the first charge pump CP1 will provide a control current proportional to the phase error to the loop filter LF to adjust the output frequency of the voltage-controlled oscillator VCO. The loop filter LF can convert the output of the first charge pump CP1 into a stable first control voltage V1 for controlling the oscillation frequency of the voltage-controlled oscillator VCO. The output frequency of the voltage-controlled oscillator VCO can be adjusted by the input control voltage. When the first control voltage V1 provided by the loop filter LF changes, the voltage controlled oscillator VCO adjusts the output frequency to reduce the phase error between the reference clock and the first output clock.

[0040] In a specific embodiment, through a negative feedback mechanism, when the frequency of the first output clock deviates from the reference frequency due to various factors such as fluctuations in process, voltage, and temperature, the first phase frequency detector PFD1 will detect the phase error and adjust the voltage-controlled oscillator VCO through the first charge pump CP1 and the loop filter LF until the frequency of the first output clock output by the voltage-controlled oscillator VCO matches the frequency of the reference clock, at which time the phase-locked loop 10 reaches a locked state.

[0041] Optionally, combined Figure 2 and Figure 6 As shown, the loop filter LF includes: a first capacitor C1, a second capacitor C2 and a resistor R. The first end of the first capacitor C1 and the first end of the second capacitor C2 are connected to the first charge pump CP1; the second end of the first capacitor C1 is grounded; the second end of the second capacitor C2 is connected to the first end of the resistor R; and the second end of the resistor R is grounded.

[0042] In this embodiment, the loop filter LF is composed of a resistor and capacitor string connected in parallel with a capacitor to form a low-pass filter for smoothing the control current generated by the first charge pump CP1 to reduce noise and rapid changes.

[0043] Optionally, combined Figure 3 and Figure 6As shown, the delay loop 20 includes: a second phase frequency detector PFD2, a second charge pump CP2 and a voltage-controlled delay line VCDL. The second phase frequency detector PFD2 is connected to the voltage-controlled delay line VCDL and is configured to generate a second phase error according to the phase of the reference clock and the phase of the second output clock output by the voltage-controlled delay line VCDL. The second charge pump CP2 is connected to the second phase frequency detector PFD2 and is configured to generate a second charge-discharge current according to the second phase error, and to generate a second control voltage V2 according to the second charge-discharge current. The voltage-controlled delay line VCDL is connected to both the second charge pump CP2 and the loop filter LF and is configured to adjust the second output clock according to the first control voltage V1 and the second control voltage V2, so that the delay of the second output clock is locked to a period of a reference clock, and prevent the second output clock from being locked to the harmonic of the reference clock. In the case where the delay of the second output clock is exactly equal to the period of a reference clock, taking the voltage-controlled delay line VCDL dividing the period of a reference clock into 32 equal parts as an example, 32 equally spaced phases (X1, X2, ..., X32) will be generated.

[0044] In this embodiment, the delay loop 20 also acts as a phase negative feedback system. The second phase frequency detector PFD2 is a key component in the delay loop 20, which is used to compare the phase and frequency difference between the reference clock and the second output clock output by the voltage-controlled delay line VCDL. When the phases of the reference clock and the second output clock are inconsistent, the second phase frequency detector PFD2 will generate a second phase error to reflect the phase difference between the two clocks. The second charge pump CP2 receives the second phase error from the second phase frequency detector PFD2 and generates a second charge and discharge current of corresponding magnitude and direction and a second control voltage V2. If the second phase frequency detector PFD2 detects the second phase error, the second charge pump CP2 will generate a second control current proportional to the phase error according to the second phase error to adjust the delay of the voltage-controlled delay line VCDL. The voltage-controlled delay line VCDL is a variable delay circuit whose output delay can be adjusted according to the input control voltage. When the control current provided by the charge pump changes, the voltage-controlled delay line VCDL adjusts its output delay so that the delay of the second output clock is locked to a period of a reference clock.

[0045] In a specific embodiment, through a negative feedback mechanism, when the delay of the second output clock deviates from a cycle of the reference clock due to various factors such as fluctuations in process, voltage, and temperature, the second phase frequency detector PFD2 will detect a second phase error and adjust the voltage-controlled delay line VCDL through the second charge pump CP2 until the delay of the second output clock matches the cycle of a reference clock. At this time, the rising edge of the reference clock and the rising edge of the second output clock are aligned, and the delay loop 20 reaches a locked state. In addition, in order to prevent the second output clock from being locked to the harmonic of the reference clock, the first control voltage V1 of the phase-locked loop 10 is connected to the voltage-controlled delay line VCDL to provide a stable reference for the voltage-controlled delay line VCDL, helping the delay loop 20 to lock to the base frequency more accurately, ensuring that the delay of the voltage-controlled delay line VCDL accurately matches the cycle of a reference clock, thereby avoiding interference from harmonic frequencies. After the delay of the second output clock is locked to the cycle of a reference clock, the voltage-controlled delay line VCDL can divide the cycle of a reference clock into equal parts, thereby generating multiple equally spaced phases.

[0046] Optionally, the voltage-controlled delay line VCDL includes 32 delay units; the voltage-controlled delay line VCDL equally divides a period of a reference clock according to the delay units to generate 32 equally spaced phases.

[0047] In this embodiment, the voltage-controlled delay line VCDL is composed of 32 delay units connected in series, each delay unit can be adjusted to generate a specific delay amount, and the delay amounts of all delay units are added together to obtain the delay of the second output clock output by the voltage-controlled delay line VCDL. In the case where the delay of the second output clock is exactly equal to the period of a reference clock, each delay unit is precisely adjusted so that each delay unit generates the same delay amount, that is, the delay amount generated by each delay unit is one thirty-second of a reference clock period. At this time, according to the output of each delay unit, 32 equally spaced phases generated by equally dividing a reference clock period can be obtained.

[0048] In a specific embodiment, if the period of a reference clock is 5ns and it needs to be divided into 32 equal parts, each delay unit will be responsible for generating a delay of about 156.25ps, so that 32 equally spaced phases with adjacent phases of 156.25ps can be obtained according to the outputs of all delay units. By changing the number of equal divisions of the reference clock period, phase control with different precisions can be obtained, which can be used to select specific timing points to meet various application requirements, such as data sampling, signal synchronization, etc.

[0049] Optionally, combined Figure 4 and Figure 6As shown, the phase output circuit 30 includes: 8 phase output branches (Z1, Z2, ..., Z8). All phase output branches are connected to the voltage-controlled delay line VCDL and are configured to select one phase as the target phase output (Y1, Y2, ..., Y8) from the 32 equally spaced phases (X1, X2, ..., X32) generated by the voltage-controlled delay line VCDL.

[0050] In this embodiment, the phase output circuit 30 includes 8 phase output branches, each of which can select one phase from 32 equally spaced phases as a target phase output. Therefore, the 8 phase output branches can output 8 different target phases simultaneously.

[0051] Optionally, each phase output branch includes: 32 multiplexers (MUXi01, MUXi02, ..., MUXi32, i=1, 2, ..., 8). The 32 multiplexers are respectively connected to 32 equally spaced phases generated by the voltage-controlled delay line VCDL, and one phase is selected from the 32 equally spaced phases as the target phase output.

[0052] In this embodiment, 32 multiplexers are used as a group as a phase output branch. For 8 phase output branches, 8 groups of multiplexers need to be set, and each group includes 32 multiplexers. The phase output branch uses 32 multiplexers to select a target phase from 32 equally spaced phases. The 32 multiplexers can select a phase from 32 equally spaced phases as the target phase for output.

[0053] Optionally, combined Figure 5 and Figure 6 As shown, the phase generating circuit further includes: a trigger circuit 40. The trigger circuit 40 is connected to the phase output circuit 30, and the target phase output by the phase output circuit 30 is used as a sampling clock of the trigger circuit 40; the trigger circuit 40 samples the external input PWM signal of the trigger circuit 40 according to the sampling clock, and at the same time, the trigger circuit 40 sets the PWM signal to a delayed preset phase.

[0054] In this embodiment, the trigger circuit 40 includes a trigger (D1, D2, ..., D8). For the phase output circuit 30 including 8 phase output branches, a trigger can be set in each phase output branch. With a PWM (Pulse Width Modulation) signal as the external input signal of the trigger, the target phase (Y1, Y2, ..., Y8) output by each phase output branch is used as the sampling clock (C1, C2, ..., C8) of the trigger circuit, and the 8 PWM signals (P1, P2, ..., P8) can be delayed at different phases at the same time. According to the preset phase required for delay, the delay loop 20 is controlled to divide the cycle of the reference clock into 32 equal parts, and the target phase required for output in the phase output branch is used as the sampling clock of the trigger circuit. The trigger circuit 40 samples the external input PWM signal of the trigger circuit 40 according to the sampling clock. At the same time, the trigger circuit 40 sets the PWM signal to the delayed preset phase, thereby realizing the function of accurately delaying the PWM signal by the preset phase.

[0055] An embodiment of the present disclosure provides a chip, including the phase generation circuit based on the dual-ring structure as described above.

[0056] According to the phase generation circuit, the chip provided by the embodiment of the present disclosure can generate a higher precision target phase. When the chip is applied to electric vehicle charging, the phase overlap time of the control signal of the charging power tube can be adjusted to control the charging current and improve the charging efficiency. In addition, the chip provided by the embodiment of the present disclosure can also be extended to multiple fields such as communication, signal processing, and precision measurement, and has a wide range of application prospects.

[0057] An embodiment of the present disclosure provides a car, comprising the chip as described above.

[0058] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

Claims

1. A phase generating circuit based on a dual-loop structure, characterized in that: include: Phase-locked loop, delay loop and phase output circuit; The phase-locked loop is configured to generate a first control voltage according to a reference clock; The delay loop is connected to the phase-locked loop and is configured to generate a second control voltage according to the reference clock, and to divide the period of the reference clock into equal parts according to the first control voltage and the second control voltage to generate a plurality of equally spaced phases; The phase output circuit is connected to the delay loop and is configured to select a target phase output from a plurality of equally spaced phases.

2. The phase generating circuit according to claim 1, characterized in that: The phase-locked loop includes: A first phase frequency detector, a first charge pump, a loop filter and a voltage controlled oscillator; The first phase frequency detector is connected to the voltage controlled oscillator and is configured to generate a first phase error according to the phase of the reference clock and the phase of the first output clock output by the voltage controlled oscillator; The first charge pump is connected to the first phase frequency detector and is configured to generate a first charge and discharge current according to the first phase error; The loop filter is connected to the first charge pump and is configured to generate a first control voltage according to the first charge and discharge current; The voltage controlled oscillator is connected to the loop filter and is configured to adjust the first output clock according to the first control voltage so that the frequency of the first output clock is locked to the frequency of the reference clock.

3. The phase generating circuit according to claim 2, characterized in that: The loop filter comprises: a first capacitor, a second capacitor and a resistor; The first end of the first capacitor and the first end of the second capacitor are connected to the first charge pump; the second end of the first capacitor is grounded; the second end of the second capacitor is connected to the first end of the resistor; and the second end of the resistor is grounded.

4. The phase generating circuit according to claim 2, characterized in that: The delay loop includes: a second frequency detector, a second charge pump and a voltage-controlled delay line; The second phase frequency detector is connected to the voltage-controlled delay line and is configured to generate a second phase error according to the phase of the reference clock and the phase of the second output clock output by the voltage-controlled delay line; The second charge pump is connected to the second phase frequency detector and is configured to generate a second charge and discharge current according to the second phase error and generate a second control voltage according to the second charge and discharge current; The voltage-controlled delay line is connected to both the second charge pump and the loop filter, and is configured to adjust the second output clock according to the first control voltage and the second control voltage, so that the delay of the second output clock is locked to a period of a reference clock, and prevent the second output clock from being locked to a harmonic of the reference clock; When the delay of the second output clock is exactly equal to the period of a reference clock, the voltage-controlled delay line divides the period of a reference clock into equal parts to generate a plurality of equally spaced phases.

5. The phase generating circuit according to claim 4, characterized in that: The voltage-controlled delay line includes 32 delay units; the voltage-controlled delay line equally divides a period of a reference clock according to the delay units to generate 32 equally spaced phases.

6. The phase generating circuit according to claim 5, characterized in that: The phase output circuit includes: 8 phase output branches; All phase output branches are connected to the voltage-controlled delay line and are configured to select one phase from 32 equally spaced phases generated by the voltage-controlled delay line as a target phase output.

7. The phase generating circuit according to claim 6, characterized in that: Each phase output branch includes: 32 multiplexers; The 32 multiplexers are respectively connected to the 32 equally spaced phases generated by the voltage-controlled delay line, and one phase is selected from the 32 equally spaced phases as a target phase output.

8. The phase generating circuit according to any one of claims 1 to 7, characterized in that: Also includes: Trigger circuit; The trigger circuit is connected to the phase output circuit, and the target phase output by the phase output circuit serves as a sampling clock of the trigger circuit; The trigger circuit samples the external input PWM signal of the trigger circuit according to the sampling clock, and at the same time, the trigger circuit sets the PWM signal to delay a preset phase.

9. A chip, characterized in that: It comprises a phase generating circuit based on a dual-ring structure as claimed in any one of claims 1 to 8.

10. An automobile, characterized in that: Comprising the chip as claimed in claim 9.

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