Initial control voltage generation circuit and phase-locked loop circuit

Abstract

The invention relates to an initial control voltage generation circuit and a phase-locked loop circuit. An initial control voltage generation circuit for a voltage controlled oscillator (VCO) includes a resistor coupled between a supply voltage terminal and an output node outputting an initial control voltage; and a pass gate resistor coupled between the output node and a ground voltage terminal. The pass gate resistor includes a P-channel MOS (PMOS) transistor and an N-channel MOS (NMOS) transistor coupled in parallel between the output node and a ground voltage terminal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Application No. 10-2023-0138083, filed on October 16, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to an initial control voltage generating circuit for a voltage controlled oscillator (VCO) and a phase locked loop (PLL) circuit having the initial control voltage generating circuit. Background Art

[0004] PLL receives a reference frequency signal and can generate output signals with multiple frequencies higher than the reference frequency signal using the reference frequency signal. Electronic devices are designed to operate based on a clock signal with a specific frequency, so PLL is used in such electronic devices. Until the frequency of the output frequency signal of the PLL is locked to the target frequency, the electronic device can operate normally. Therefore, as the locking speed of the PLL increases, the operating speed of the electronic device can also be increased. Summary of the invention

[0005] According to an embodiment of the present disclosure, an initial control voltage generating circuit, which is used for a voltage-controlled oscillator (VCO), may include: a resistor coupled between a power supply voltage terminal and an output node that outputs an initial control voltage; and a transmission gate resistor coupled between the output node and a ground voltage terminal.

[0006] A phase-locked loop (PLL) circuit according to an embodiment of the present disclosure may include: a phase frequency detector configured to receive a reference signal and a feedback signal, and output a rising signal or a falling signal based on a phase difference between the reference signal and the feedback signal; a charge pump configured to output a control voltage based on the rising signal or the falling signal; a voltage-controlled oscillator (VCO) configured to generate and output an output signal having a first frequency corresponding to the control voltage; a frequency divider configured to generate a feedback signal having a second frequency and transmit the feedback signal to the phase frequency detector; and an initial control voltage generating circuit configured to generate an initial control voltage during an initialization period and provide the initial control voltage to the VCO. The initial control voltage generating circuit may include: a resistor coupled between a power supply voltage terminal and an output node outputting the initial control voltage; and a transmission gate resistor coupled between the output node and a ground voltage terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] With reference to the accompanying drawings, certain features of the disclosed technology are described through various embodiments, in which:

[0008] Figure 1 An initial control voltage generating circuit for a VCO according to an embodiment of the present disclosure is shown.

[0009] Figure 2 The embodiment according to the present disclosure is shown Figure 1 An initial control signal generating circuit of an initial control voltage generating circuit.

[0010] Figure 3 The present invention is shown in Figure 2 The timing diagram of the input signal, power-off signal and reset signal of the initial control signal generating circuit.

[0011] Figure 4 The present invention is shown in Figure 2 A circuit diagram of an initialization operation of an initial control signal generating circuit.

[0012] Figure 5 The present invention is shown in Figure 1 A circuit diagram of an initialization operation of an initial control voltage generating circuit.

[0013] Figure 6 FIG. 1 is a diagram showing that when both the power-down signal and the reset signal have a high level according to an embodiment of the present disclosure Figure 2 A circuit diagram of the operation of the initial control signal generating circuit.

[0014] Figure 7 FIG. 1 is a diagram showing that when both the power-down signal and the reset signal have a high level according to an embodiment of the present disclosure Figure 1 Schematic diagram of the operation of the initial control voltage generating circuit.

[0015] Figure 8 is a diagram showing that when both the power-down signal and the reset signal have a low level according to an embodiment of the present disclosure Figure 2 Schematic diagram of the operation of the initial control signal generating circuit.

[0016] Fig. 9 is a block diagram showing a PLL circuit including an initial control voltage generating circuit according to an embodiment of the present disclosure.

[0017] Fig.10 The present invention is shown in Fig. 9 Block diagram of the VCO included in the PLL circuit. DETAILED DESCRIPTION

[0018] In the description of the embodiments of the present disclosure, descriptions such as "first" and "second" are intended to distinguish between elements and are not used to limit the elements themselves or to indicate a particular order. A component "connected" or "coupled" to another component may mean that one component is electrically or mechanically connected to another component, whether directly connected or connected through one or more intermediate elements. The term "predetermined" means that the value of the parameter is predetermined when the parameter is used in a process or algorithm. The value of the parameter can be set at the beginning of the process or algorithm, or during the period during which the process or algorithm is executed, depending on the embodiment.

[0019] "Logical high level" and "logical low level" are used to describe the logic level of a signal. A signal having a "logical high level" is distinguished from a signal having a "logical low level". For example, when a signal having a first voltage corresponds to a "logical high level", a signal having a second voltage may correspond to a "logical low level". According to an embodiment, the "logical high level" may be set to a higher voltage than the "logical low level", but the embodiments of the present disclosure are not limited thereto. For example, the "logical high level" may be set to a lower voltage than the "logical low level".

[0020] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0021] Figure 1 An initial control voltage generating circuit 100 for a VCO according to an embodiment of the present disclosure is shown.

[0022] See also Figure 1, the initial control voltage generating circuit 100 includes a voltage dividing circuit 110, a switch circuit 120 and an initial control signal generating circuit 130. The voltage dividing circuit 110 includes a resistor 111 having a first resistance value R and a transmission gate resistor 112. The voltage dividing circuit 110 outputs a voltage dividing voltage V_DIV at an output node NO. The voltage dividing voltage V_DIV is generated by dividing the power supply voltage VDD by the resistor 111 and the transmission gate resistor 112. The switch circuit 120 includes a first switch, a second switch and a third switch. The first switch may be implemented as a first transmission gate switch 121. The second switch may be implemented as a second transmission gate switch 122. The third switch may be implemented as a third transmission gate switch 123. The switch circuit 120 performs a switching operation in which the power supply voltage VDD and the ground voltage are applied to the voltage dividing circuit 110 based on the initial control signal (or the first initial control signal) INIT and the initial control negation signal (or the second initial control signal) INIT_B as complementary signals. Specifically, the switch circuit 120 connects the power supply voltage terminal to the resistor 111 of the voltage divider circuit 110 or disconnects the power supply voltage terminal from the resistor 111 of the voltage divider circuit 110 based on the first initial control signal INIT and the second initial control signal INIT_B. The switch circuit 120 also connects the ground voltage terminal to the transmission gate resistor 112 of the voltage divider circuit 110 or disconnects the ground voltage terminal from the transmission gate resistor 112 of the voltage divider circuit 110 based on the first initial control signal INIT and the second initial control signal INIT_B. When the power supply voltage terminal and the ground voltage terminal are connected to the resistor 111 and the transmission gate resistor 112 of the voltage divider circuit 110, respectively, the switch circuit 120 applies the power supply voltage VDD to the resistor 111 through the second transmission gate switch 122, and applies the ground voltage to the transmission gate resistor 112 through the third transmission gate switch 123. In addition, the switch circuit 120 performs a switching operation of outputting the divided voltage V_DIV output from the voltage divider circuit 110 as the control voltage V_CTRL from the initial control voltage generating circuit 100 based on the first reset signal RST and the second reset signal RST_B which are complementary signals. Specifically, the switch circuit 120 connects or disconnects the output node NO of the voltage divider circuit 110 with the output terminal of the initial control voltage generating circuit 100 based on the first reset signal RST and the second reset signal RST_B. When the output node NO is connected to the output terminal of the initial control voltage generating circuit 100, the switch circuit 120 transfers the divided voltage V_DIV to output the control voltage V_CTRL at the output terminal. Hereinafter, the control voltage V_CTRL output from the initial control voltage generating circuit 100 may also be referred to as the term "initial control voltage".

[0023] More specifically, the resistor 111 of the voltage divider circuit 110 is coupled to the output terminal of the second transmission gate switch 122 of the switch circuit 120 and the output node NO of the voltage divider circuit 110. The output node NO is coupled to the output line of the output control voltage V_CTRL of the voltage divider circuit 110. The transmission gate resistor 112 of the voltage divider circuit 110 has a structure in which a P-channel MOS transistor (hereinafter referred to as "PMOS transistor") and an N-channel MOS transistor (hereinafter referred to as "NMOS transistor") are coupled in parallel. In an embodiment, the source of the PMOS transistor and the source of the NMOS transistor constitute the input terminal of the transmission gate resistor 112, and the drain of the PMOS transistor and the drain of the NMOS transistor constitute the output terminal of the transmission gate resistor 112. The input terminal of the transmission gate resistor 112 is coupled to the output node NO. The output terminal of the transmission gate resistor 112 is coupled to the output terminal of the third transmission gate switch 123 of the switch circuit 120. The gate of the PMOS transistor of the transmission gate resistor 112 is coupled to the ground voltage terminal to which the ground voltage is applied. The gate of the NMOS transistor of the transmission gate resistor 112 is coupled to a power supply voltage terminal to which the power supply voltage VDD is applied.

[0024] The first transmission gate switch 121, the second transmission gate switch 122, and the third transmission gate switch 123 of the switch circuit 120, like the transmission gate resistor 112, each has a structure in which a PMOS transistor and an NMOS transistor are coupled in parallel. In one embodiment, the source of the PMOS transistor and the source of the NMOS transistor of each of the first transmission gate switch 121, the second transmission gate switch 122, and the third transmission gate switch 123 constitute an input terminal of each of the first transmission gate switch 121, the second transmission gate switch 122, and the third transmission gate switch 123. The drain of the PMOS transistor and the drain of the NMOS transistor of each of the first transmission gate switch 121, the second transmission gate switch 122, and the third transmission gate switch 123 constitute an output terminal of each of the first transmission gate switch 121, the second transmission gate switch 122, and the third transmission gate switch 123.

[0025] An input terminal of the first transmission gate switch 121 is coupled to an output node NO of the voltage divider circuit 110. An output terminal of the first transmission gate switch 121 is coupled to an output line of the initial control voltage generating circuit 100. A reset signal (or a first reset signal) RST is applied to a gate of an NMOS transistor of the first transmission gate switch 121. A reset negation signal (or a second reset signal) RST_B is applied to a gate of a PMOS transistor of the first transmission gate switch 121. The first and second reset signals RST and RST_B are complementary signals. An input terminal of the second transmission gate switch 122 is coupled to a power supply voltage terminal. An output terminal of the second transmission gate switch 122 is coupled to a resistor 111 of the voltage divider circuit 110. An initial control signal INIT is applied to a gate of an NMOS transistor of the second transmission gate switch 122. An initial control negation signal INIT_B is applied to a gate of a PMOS transistor of the second transmission gate switch 122. An input terminal of the third transmission gate switch 123 is coupled to a ground voltage terminal. The output terminal of the third transmission gate switch 123 is coupled to the output terminal of the transmission gate resistor 112 of the voltage dividing circuit 110. The initial control signal INIT is applied to the gate of the NMOS transistor of the third transmission gate switch 123. The initial control bar signal INIT_B is applied to the gate of the PMOS transistor of the third transmission gate switch 123.

[0026] The initial control signal generating circuit 130 receives the power-down signal PD and the reset signal RST. The power-down signal PD and the reset signal RST may have a first logic level (e.g., a high level) or a second logic level (e.g., a low level). The initial control signal generating circuit 130 outputs an initial control signal INIT and an initial control negation signal INIT_B. The initial control signal generating circuit 130 transmits the initial control signal INIT to the gate of the NMOS transistor of the second transmission gate switch 122 and the gate of the NMOS transistor of the third transmission gate switch 123. The initial control signal generating circuit 130 transmits the initial control negation signal INIT_B to the gate of the PMOS transistor of the second transmission gate switch 122 and the gate of the PMOS transistor of the third transmission gate switch 123.

[0027] Figure 2 The embodiment according to the present disclosure is shown Figure 1 The initial control voltage generating circuit 100 and the initial control signal generating circuit 130 .

[0028] See also Figure 2, the initial control signal generating circuit 130 includes a first inverter 131, a NAND gate 132, and a second inverter 133. The first inverter 131 receives a power-off signal PD (or a first power-off signal). The first inverter 131 outputs a power-off inverted signal (or a second power-off signal) PD_B. For example, the second power-off signal PD_B is an inverted version of the first power-off signal PD, so that the first power-off signal PD and the second power-off signal PD_B become complementary signals. The power-off inverted signal PD_B has a logic level that is inverted from the logic level of the power-off signal PD. The NAND gate 132 receives the power-off inverted signal PD_B output from the first inverter 131 through a first input terminal. The NAND gate 132 receives a reset signal RST through a second input terminal. The NAND gate 132 performs a NAND operation on the power-off inverted signal PD_B and the reset signal RST. The NAND gate 132 outputs the signal generated as a result of the NAND operation as the initial control inverted signal INIT_B through an output terminal. The second inverter 133 receives as an input the initial control bar signal INIT_B output from the NAND gate 132. The second inverter 133 outputs the initial control signal INIT having a logic level inverted from that of the initial control bar signal INIT_B.

[0029] Figure 3 is a timing diagram showing a power-down signal PD and a reset signal RST, the power-down signal PD and the reset signal RST are Figure 2 The initial control signal generating circuit 130 is inputted with the signal. Figure 3 In FIG. 8 , the horizontal axis represents time, and the vertical axis represents logic levels of the power-down signal PD and the reset signal RST.

[0030] See also Figure 3 , when the power is turned on at the first time point T1, the logic level of the power-down signal PD changes from a high level to a low level. On the other hand, the logic level of the reset signal RST remains at a high level. At the second time point T2, that is, after a specific time interval (e.g., the time interval (or initialization period) INITIALIZATION required to perform the initialization operation) has passed since the first time point T1, the logic level of the reset signal RST changes from a high level to a low level. At the third time point T3 when the power is turned off, the logic level of the power-down signal PD and the logic level of the reset signal RST both change from a low level to a high level. In this example, the initialization operation refers to the operation in which the control voltage V_CTRL changes from Figure 1 The initial control voltage generating circuit 100 outputs and is transmitted to the VCO. The initialization operation is performed during the period when the logic level of the power-down signal PD is low and the logic level of the reset signal RST is high. In other words, the initialization operation is performed during the period when the power-down signal PD is low and the logic level of the reset signal RST is high. Figure 3When the initialization operation is not performed, that is, when both the power-down signal PD and the reset signal RST are at a high level or at a low level, Figure 1 Initially, the control voltage generating circuit 100 does not output the control voltage V_CTRL.

[0031] Figure 4 To illustrate the embodiment of the present disclosure Figure 2 FIG. 1 is a circuit diagram of the initialization operation of the initial control signal generating circuit 130. Figure 4 In, with Figure 2 Like reference numerals denote like components.

[0032] See also Figure 4 , when the initialization operation is being performed (i.e. Figure 3 The first inverter 131 outputs a high-level power-down inverting signal PD_B, and transmits the high-level power-down inverting signal PD_B to the first input terminal of the NAND gate 132. The NAND gate 132 outputs a low-level initial control inverting signal INIT_B by performing a NAND operation on the high-level power-down inverting signal PD_B and the high-level reset signal RST. The second inverter 133, which receives the low-level initial control inverting signal INIT_B from the NAND gate 132, outputs a high-level initial control signal INIT.

[0033] Figure 5 is shown as shown Figure 1 FIG. 1 is a schematic diagram of the initialization operation of the initial control voltage generating circuit 100. Figure 5 In, with Figure 1 The same reference numerals in the drawings represent the same components.

[0034] See also Figure 5, a high-level reset signal RST and a low-level reset negation signal RST_B are input to the gate of the NMOS transistor and the gate of the PMOS transistor of the first transmission gate switch 121, respectively. Therefore, the first transmission gate switch 121 is turned on (or turned on). The high-level initial control signal INIT output from the initial control signal generating circuit 130 is input to the gate of the NMOS transistor of the second transmission gate switch 122 and the gate of the NMOS transistor of the third transmission gate switch 123. The low-level initial control negation signal INIT_B output from the initial control signal generating circuit 130 is input to the gate of the PMOS transistor of the second transmission gate switch 122 and the gate of the PMOS transistor of the third transmission gate switch 123. Therefore, the second transmission gate switch 122 and the third transmission gate switch 123 are also turned on.

[0035] When the second transmission gate switch 122 is turned on, the power supply voltage VDD is applied to the resistor 111 of the voltage divider circuit 110. When the third transmission gate switch 123 is turned on, the ground voltage is applied to the output terminal of the transmission gate resistor 112 of the voltage divider circuit 110. When the power supply voltage VDD and the ground voltage are applied to the gate of the NMOS transistor and the gate of the PMOS transistor of the transmission gate resistor 112, respectively, the transmission gate resistor 112 remains turned on, so that the transmission gate resistor 112 acts as a resistor with an on-resistance value. The power supply voltage VDD is divided by the resistor 111 and the transmission gate resistor 112, so that the divided voltage V_DIV is generated at the output node NO. When the transmission gate resistor 112 is made to have an on-resistance value substantially the same as the resistance value R of the resistor 111, the divided voltage V_DIV at the output node NO is approximately half of the power supply voltage VDD, that is, VDD / 2. When the first transmission gate switch 121 is turned on, the divided voltage V_DIV at the output node NO is output as the control voltage V_CTRL through the output terminal of the first transmission gate switch 121 and provided to the VCO. Since the value of the control voltage V_CTRL output from the initial control voltage generating circuit 100 is VDD / 2 instead of 0V, the locking time interval (i.e., the time interval for the control voltage V_CTRL to reach the final value from the initial value) is shortened. Here, the final value means that the value of the control voltage V_CTRL remains substantially unchanged.

[0036] In some embodiments, the PMOS transistor and the NMOS transistor constituting the transmission gate resistor 112 may have a pair of transistor corners, including any one of TT (typical / typical), FF (fast / fast), and SS (slow / slow). When the pair of transistor corners is TT, the PMOS transistor and the NMOS transistor of the transmission gate resistor 112 both have a target threshold voltage. Here, the target threshold voltage refers to the threshold voltage of the PMOS transistor and the NMOS transistor that make the transmission gate resistor 112 have an on-resistance value substantially equal to the resistance value of the resistor 111 of the voltage divider circuit 110. For example, the on-resistance value may be in the range of about 95% to about 105%, about 97% to about 103%, or about 99% to about 101% of the resistance value of the resistor 111. When the pair of transistor corners is FF, the PMOS transistor and the NMOS transistor of the transmission gate resistor 112 both have a threshold voltage lower than the target threshold voltage. In this case, the transmission gate resistor 112 has an on-resistance value lower than the resistance value of the resistor 111 of the voltage divider circuit 110. When a pair of transistor corners is SS, both the PMOS transistor and the NMOS transistor of the transmission gate resistor 112 have a threshold voltage higher than the target threshold voltage. In this case, the on-resistance value of the transmission gate resistor 112 is higher than the resistance value of the resistor 111 of the voltage divider circuit 110.

[0037] As reference Figure 3 As described above, it takes a certain time interval for the control voltage V_CTRL input to the VCO from the initial control voltage generating circuit 100 to reach the final value from the initial value output from the initial control voltage generating circuit 100. When a pair of transistor angles is FF, the final value has a value less than VDD / 2, and when a pair of transistor angles is SS, the final value has a value greater than VDD / 2. When a pair of transistor angles is FF, the on-resistance values ​​of the PMOS transistor and the NMOS transistor of the transmission gate resistor 112 are less than the resistance value of the resistor 111, so the initial value of the control voltage V_CTRL output from the initial control voltage generating circuit 100 is also less than VDD / 2. Therefore, the time interval required for the control voltage V_CTRL to reach the final value is shorter than the case where the initial value is VDD / 2. Similarly, when a pair of transistor angles is SS, the on-resistance values ​​of the PMOS transistor and the NMOS transistor of the transmission gate resistor 112 are greater than the resistance value of the resistor 111, so the initial value of the control voltage V_CTRL output from the initial control voltage generating circuit 100 is also greater than VDD / 2. As a result, the time interval required for the control voltage V_CTRL to reach the final value is shorter than the case where the initial value of the control voltage V_CTRL is VDD / 2.

[0038] Figure 6 To illustrate the embodiment of the present disclosure, when the power-down signal PD and the reset signal RST are both at high level, Figure 2 1 is a circuit diagram of the operation of the initial control signal generating circuit 130. Figure 7 To illustrate the embodiment of the present disclosure, when the power-down signal PD and the reset signal RST are both at high level, Figure 1 FIG. 1 is a schematic diagram of the operation of the initial control voltage generating circuit 100. Figure 6 In, with Figure 2 The same reference numerals in the drawings represent the same components; Figure 7 In, with Figure 1 The same reference numerals in the drawings represent the same components.

[0039] First, if Figure 6 As shown, in the time interval before the initialization operation is performed (for example, see Figure 3 , before the first time point T1 or after the third time point T3), the high-level power-down signal PD is input to the first inverter 131, and the high-level reset signal RST is input to the second input terminal of the NAND gate 132. The first inverter 131 outputs a low-level power-down negation signal PD_B, and transmits the low-level power-down negation signal PD_B to the first input terminal of the NAND gate 132. The NAND gate 132 performs a NAND operation on the low-level power-down negation signal PD_B and the high-level reset signal RST to output a high-level initial control signal negation INIT_B. The second inverter 133, which receives the high-level initial control negation signal INIT_B from the NAND gate 132, outputs a low-level initial control signal INIT.

[0040] Next, if Figure 7 As shown, a high-level reset signal RST and a low-level reset negation signal RST_B are respectively input to the gate of the NMOS transistor and the gate of the PMOS transistor of the first transmission gate switch 121. Therefore, the first transmission gate switch 121 is turned on (or turned on). The low-level initial control signal INIT output from the initial control signal generating circuit 130 is input to the gate of the NMOS transistor of the second transmission gate switch 122 and the gate of the NMOS transistor of the third transmission gate switch 123. The high-level initial control negation signal INIT_B output from the initial control signal generating circuit 130 is input to the gate of the PMOS transistor of the second transmission gate switch 122 and the gate of the PMOS transistor of the third transmission gate switch 123. Therefore, the second transmission gate switch 122 and the third transmission gate switch 123 are also closed (or turned off).

[0041] Since the second transmission gate switch 122 is turned off, the resistor 111 of the voltage divider circuit 110 is disconnected from the power supply voltage VDD terminal. Since the third transmission gate switch 123 is turned off, the output terminal of the transmission gate resistor 112 of the voltage divider circuit 110 is disconnected from the ground voltage terminal. Since the power supply voltage VDD and the ground voltage are applied to the gate of the NMOS transistor and the gate of the PMOS transistor of the transmission gate resistor 112, respectively, the transmission gate resistor 112 remains turned on, but since one terminal of the resistor 111 and the input terminal of the transmission gate resistor 112 are both in a floating state, no voltage is applied to the output node NO. Therefore, the control voltage V_CTRL is not output through the output terminal of the first transmission gate switch 121.

[0042] Figure 8 1 is a diagram showing that when the power-down signal PD and the reset signal RST are both at low level according to an embodiment of the present disclosure Figure 2 A circuit diagram of the operation of the initial control signal generating circuit 130. Figure 8 In, with Figure 2 The same reference numerals in the drawings represent the same components.

[0043] See also Figure 8 , after the initialization operation is completed and before the power is turned off again (for example Figure 3 In the time interval from the second time point T2 to the third time point T3 in the control circuit 130, the low-level power-down signal PD is input to the first inverter 131, and the low-level reset signal RST is input to the second input terminal of the NAND gate 132. The first inverter 131 outputs a high-level power-down inversion signal PD_B, and transmits the high-level power-down inversion signal PD_B to the first input terminal of the NAND gate 132. The NAND gate 132 outputs a high-level initial control inversion signal INIT_B by performing a NAND operation on the high-level power-down inversion signal PD_B and the low-level reset signal RST. The second inverter 133, which receives the high-level initial control inversion signal INIT_B from the NAND gate 132, outputs a low-level initial control signal INIT. Since the initial control signal generating circuit 130 outputs a low-level initial control signal INIT and a high-level initial control inversion signal INIT_B, Figure 1 The operation of the initial control voltage generating circuit 100 is referenced Figure 7 Same as described.

[0044] Fig. 9 is a block diagram showing a PLL circuit 200 including an initial control voltage generating circuit 260 according to an embodiment of the present disclosure. For example, Figure 1 The initial control voltage generating circuit 100 in FIG. 1 can be suitably used as the initial control voltage generating circuit 260 .

[0045] See also Fig. 9 , the PLL circuit 200 may include a phase frequency detector PFD 210, a charge pump 220, a loop filter 230, a VCO 240, a frequency divider 250, and an initial control voltage generating circuit 260. The PLL circuit 200 receives a reference signal REF, and outputs an output signal OUT having a constant frequency based on the reference signal REF. The VCO 240 of the PLL circuit 200 generates an output signal OUT based on a control voltage V_CTRL provided by the initial control voltage generating circuit 260 during an initialization time interval when the power-down signal PD is at a low level and the reset signal RST is at a high level. After the initialization time interval, the VCO 240 generates an output signal OUT based on the control voltage V_CTRL provided by the charge pump 220 and the loop filter 230. The initial control voltage generating circuit 260 may be connected to the reference signal REF. Figures 1 to 8 The initial control voltage generating circuit 100 described above is configured identically. Figures 1 to 8 The described initialization process is applicable to the PLL circuit 200 .

[0046] The phase frequency detector 210 receives a reference signal REF and a feedback signal FB as inputs. In one example, the reference signal REF may be provided by a crystal oscillator. The phase frequency detector 210 detects the phase difference between the reference signal REF and the feedback signal FB, and transmits the detected phase difference to the charge pump 220. In one example, the phase frequency detector 210 outputs an up signal UP or a down signal DN in the form of a pulse during each cycle of the reference signal REF based on the phase difference between the reference signal REF and the feedback signal FB. For example, when the phase of the reference signal REF leads the phase of the feedback signal FB, the phase frequency detector 210 outputs an up signal UP. The width of the up signal UP may be proportional to the phase difference. When the phase of the reference signal REF lags behind the phase of the feedback signal FB, the phase frequency detector 210 outputs a down signal DN. The width of the down signal DN may also be proportional to the phase difference.

[0047] The charge pump 220 outputs a control voltage V_CTRL based on an up signal UP or a down signal DN provided by the phase frequency detector 210. In one example, when an up signal UP is sent from the phase frequency detector 210, the charge pump 220 outputs a control voltage V_CTRL, which is increased by an amplitude corresponding to the amount of charge corresponding to the pulse width of the up signal UP. When a down signal DN is sent from the phase frequency detector 210, the charge pump 220 outputs a control voltage V_CTRL, which is reduced by an amplitude corresponding to the amount of charge corresponding to the pulse width of the down signal DN. In one example, the charge pump 220 can be configured to include a first current source, a second current source, a first switch, and a second switch.

[0048] The loop filter 230 is located between the charge pump 220 and the VCO 240. In one example, the loop filter 230 may be configured as a low pass filter, including a resistor 231 and capacitors 232 and 233. The capacitors 232 and 233 of the loop filter 230 may accumulate the charge provided by the charge pump 220, or discharge the accumulated charge to the charge pump 220. Such accumulation or discharge of the charge in the loop filter 230 is achieved by the operation of the charge pump 220 in response to the up signal UP or the down signal DN output from the phase frequency detector 210. For example, when the up signal UP is provided to the charge pump 220, the charge pump 220 pushes the charge corresponding to the pulse width of the up signal UP, and the charge pushed from the charge pump 220 is charged to the capacitor of the loop filter 230. When the down signal DN is provided to the charge pump 220, the charge pump 220 attracts the charge corresponding to the pulse width of the down signal DN, and the charge accumulated in the capacitor of the loop filter 230 is released to the charge pump 220. On the other hand, since the loop filter 230 is configured as a low-pass filter, harmonics and noise of the control voltage V_CTRL may be substantially removed by the loop filter 230 .

[0049] The VCO 240 receives the control voltage V_CTRL from the initial control voltage generating circuit 260 during the initialization period, and receives the control voltage V_CTRL from the charge pump 220 during the normal operation period after the initialization period. The VCO 240 generates and outputs the output signal OUT based on the control voltage V_CTRL from the initial control voltage generating circuit 260 or the control voltage V_CTRL from the charge pump 220. In one example, the VCO 240 may be configured as a ring oscillator structure. In another example, the VCO 240 may include a structure including an inductor-capacitor (LC) tank.

[0050] The frequency divider 250 receives as input the output signal OUT from the VCO 240. The frequency divider 250 generates a feedback signal FB having a frequency of 1 / M of the output signal OUT, and transmits the feedback signal FB to the phase frequency detector 210. In one example, the frequency of the output signal OUT can be changed by changing the multiplication factor (ie, "M") of the frequency divider 250.

[0051] Fig.10 The present invention is shown in Fig. 9 Schematic diagram of VCO 240 included in PLL circuit 200. In this example, VCO 240 is a current starved ring oscillator structure, but the embodiments of the present disclosure are not limited thereto. For example, VCO 240 may include any other type, such as a structure including an LC tank.

[0052] refer to Fig.10 , VCO 240 may include a bias circuit 241, a current mirror circuit 242, and an inverter chain circuit 243. The bias circuit 241 may include an NMOS transistor NM coupled to the current mirror circuit 242 and a ground voltage. The control voltage V_CTRL is applied to the gate of the NMOS transistor NM. The drain and source of the NMOS transistor NM are coupled to the current mirror circuit 242 and the ground voltage terminal, respectively. Although not shown, a resistor may be provided between the source and the ground voltage terminal of the NMOS transistor NM. The NMOS transistor NM provides a current linearly proportional to the control voltage V_CTRL applied to the gate to the current mirror circuit 242.

[0053] The current mirror circuit 242 may include a first PMOS transistor PM1 and a second PMOS transistor PM2, whose gates are coupled to each other. The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are coupled to the power supply voltage VDD. The drain of the first PMOS transistor PM1 is coupled to the drain of the NMOS transistor NM, the gate of the first PMOS transistor PM1, and the gate of the second PMOS transistor PM2. The drain of the second PMOS transistor PM2 is coupled to the inverter chain circuit 243. The current mirror circuit 242 mirrors the current provided by the bias circuit 241 and provides the mirrored current to the inverter chain circuit 243.

[0054] The inverter chain circuit 243 includes a plurality of inverters, for example, three inverters INV, which are combined in a chain structure. In one example, the number of inverters may be an odd number. The inverters form a loop, i.e., the output of the last inverter (i.e., the third inverter INV) is fed back to the input of the first inverter INV. The source of the PMOS transistor of each inverter INV in the inverter chain circuit 243 is coupled to the drain of the second PMOS transistor PM2 of the current mirror circuit 242. The source of the NMOS transistor of each inverter INV in the inverter chain circuit 243 is coupled to the ground voltage. The output signal OUT from the VCO 240 is output from the last inverter (i.e., the third inverter INV) in the inverter chain circuit 243. The inverter INV constituting the inverter chain circuit 243 may work as an oscillator to generate a periodically repeated pulse signal. The inverter chain circuit 243 has a variable delay time according to the amount of current provided by the current mirror circuit 242. For example, as the amount of current provided by the current mirror circuit 242 increases, the delay time of the inverter INV may decrease. On the other hand, when the amount of current provided by the current mirror circuit 242 decreases, the delay time of the inverter INV may increase.

[0055] The concepts have been disclosed in conjunction with some of the embodiments described above. Various modifications, additions and substitutions may be made.

Claims

1. An initial control voltage generating circuit, the initial control voltage generating circuit is used to generate an initial control voltage and provide the initial control voltage to a VCO, the VCO refers to a voltage controlled oscillator, the initial control voltage generating circuit comprises: a resistor coupled between a power supply voltage terminal and an output node outputting the initial control voltage; as well as A transmission gate resistor is coupled between the output node and a ground voltage terminal.

2. The initial control voltage generating circuit according to claim 1, in, The transmission gate resistor includes a PMOS transistor and an NMOS transistor coupled in parallel between the output node and the ground voltage terminal, the PMOS transistor refers to a P-channel type MOS transistor, and the NMOS transistor refers to an N-channel type MOS transistor, and The PMOS transistor and the NMOS transistor have a pair of transistor corners, and the pair of transistor corners includes any one of TT, FF and SS, TT refers to typical / typical, FF refers to fast / fast, and SS refers to slow / slow.

3. The initial control voltage generating circuit according to claim 2, in, When the PMOS transistor and the NMOS transistor have a TT transistor angle, an on-resistance value of the transmission gate resistor is substantially equal to a resistance value of the resistor.

4. The initial control voltage generating circuit according to claim 2, in, When the PMOS transistor and the NMOS transistor have an FF transistor corner, an on-resistance value of the transmission gate resistor is smaller than a resistance value of the resistor.

5. The initial control voltage generating circuit according to claim 2, in, When the PMOS transistor and the NMOS transistor have an SS transistor corner, an on-resistance value of the transmission gate resistor is greater than a resistance value of the resistor.

6. The initial control voltage generating circuit according to claim 2, in, The gate of the PMOS transistor is coupled to the ground voltage terminal, and Wherein, the gate of the NMOS transistor is coupled to the power supply voltage terminal.

7. The initial control voltage generating circuit according to claim 1, further comprising an initial control signal generating circuit, wherein the initial control signal generating circuit generates a first initial control signal and a second initial control signal based on a power-off signal and a reset signal, wherein the first initial control signal and the second initial control signal are complementary signals. in, At a first time point of power-on, the power-down signal changes from a first logic level to a second logic level, and Wherein, at a second time point after an initialization period from the first time point, the reset signal changes from the first logic level to the second logic level.

8. The initial control voltage generating circuit according to claim 7, wherein: The initial control signal generating circuit comprises: A first inverter, which receives the power-off signal and outputs an inverted power-off signal; a NAND gate, which: performs a NAND operation on the inverted power-off signal and the reset signal, and outputs the second initial control signal; and The second inverter receives the second initial control signal and outputs the first initial control signal.

9. The initial control voltage generating circuit according to claim 7, further comprising: a first switch through which the initial control voltage from the output node is provided; a second switch that connects or disconnects the resistor and the power supply voltage terminal; as well as a third switch that connects or disconnects the transmission gate resistor and the ground voltage terminal.

10. The initial control voltage generating circuit according to claim 9, in, The first switch, the second switch and the third switch are respectively a first transmission gate switch, a second transmission gate switch and a third transmission gate switch, Wherein, when the reset signal has the first logic level, the first transmission gate switch is turned on, and When the power-off signal has the second logic level and the reset signal has the first logic level, the second transmission gate switch and the third transmission gate switch are turned on.

11. A PLL circuit, PLL refers to a phase-locked loop, the PLL circuit comprising: a phase frequency detector that receives a reference signal and a feedback signal and outputs an up signal or a down signal based on a phase difference between the reference signal and the feedback signal; a charge pump that outputs a control voltage based on the rising signal or the falling signal; A VCO that generates and outputs an output signal having a first frequency corresponding to the control voltage, the VCO being a voltage controlled oscillator; a frequency divider generating the feedback signal having a second frequency and transmitting the feedback signal to the phase frequency detector; as well as an initial control voltage generating circuit that generates an initial control voltage during an initialization period and provides the initial control voltage to the VCO, Wherein, the initial control voltage generating circuit comprises: a resistor coupled between a power supply voltage terminal and an output node outputting the initial control voltage; and A transmission gate resistor is coupled between the output node and a ground voltage terminal.

12. The PLL circuit according to claim 11, wherein: The transmission gate resistor includes a PMOS transistor and an NMOS transistor coupled in parallel between the output node and the ground voltage terminal, the PMOS transistor refers to a P-channel MOS transistor, and the NMOS transistor refers to an N-channel MOS transistor, and The PMOS transistor and the NMOS transistor have a pair of transistor corners, and the pair of transistor corners includes any one of TT, FF and SS, TT refers to typical / typical, FF refers to fast / fast, and SS refers to slow / slow.

13. The PLL circuit according to claim 12, in, When the PMOS transistor and the NMOS transistor have a TT transistor angle, an on-resistance value of the transmission gate resistor is substantially equal to a resistance value of the resistor.

14. The PLL circuit according to claim 12, in, When the PMOS transistor and the NMOS transistor have an FF transistor corner, an on-resistance value of the transmission gate resistor is smaller than a resistance value of the resistor.

15. The PLL circuit according to claim 12, in, When the PMOS transistor and the NMOS transistor have an SS transistor corner, an on-resistance value of the transmission gate resistor is greater than a resistance value of the resistor.

16. The PLL circuit according to claim 12, in, The gate of the PMOS transistor is coupled to the ground voltage terminal, and Wherein, the gate of the NMOS transistor is coupled to the power supply voltage terminal.

17. The PLL circuit according to claim 11, wherein: The initial control voltage generating circuit further includes an initial control signal generating circuit, wherein the initial control signal generating circuit generates a first initial control signal and a second initial control signal based on a power-off signal and a reset signal, wherein the first initial control signal and the second initial control signal are complementary signals. Wherein, at a first time point of power-on, the power-off signal changes from a first logic level to a second logic level, and Wherein, at a second time point after an initialization period from the first time point, the reset signal changes from the first logic level to the second logic level.

18. The PLL circuit according to claim 17, wherein: The initial control signal generating circuit comprises: A first inverter, which receives the power-off signal and outputs an inverted power-off signal; a NAND gate, which: performs a NAND operation on the inverted power-off signal and the reset signal, and outputs the second initial control signal; and The second inverter receives the second initial control signal and outputs the first initial control signal.

19. The PLL circuit according to claim 17, wherein: The initial control voltage generating circuit further includes: a first switch through which the initial control voltage from the output node is provided; a second switch that connects or disconnects the resistor and the power supply voltage terminal; and a third switch that connects or disconnects the transmission gate resistor and the ground voltage terminal.

20. The PLL circuit according to claim 19, in, The first switch, the second switch and the third switch are respectively a first transmission gate switch, a second transmission gate switch and a third transmission gate switch, Wherein, when the reset signal has the first logic level, the first transmission gate switch is turned on, and When the power-off signal has the second logic level and the reset signal has the first logic level, the second transmission gate switch and the third transmission gate switch are turned on.

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