Storage vertical device based on two-dimensional ferroelectric semiconductor and preparation method thereof
By designing a storage vertical device based on two-dimensional ferroelectric semiconductors, the problem of large subthreshold swing at room temperature is solved, and a high-performance tunneling field effect device is realized, with high switching ratio and long-term retention characteristics.
Patent Information
- Application Number
- CN202510001928.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-04-18
AI Technical Summary
The existing TMDCs tunneling field effect devices have a large subthreshold swing at room temperature and have a lot of room for performance improvement.
The device is prepared by mechanical peeling and dry transfer methods, such as mechanical peeling and dry transfer.
The performance parameters of TMDCs tunneling field effect devices are improved, the switching ratio reaches 107, and the long-term open and close-state retention characteristics are achieved, and the multi-resistance storage capability is provided.
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Figure CN119855157A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of vertical field effect transistors, and in particular relates to a storage vertical device based on a two-dimensional ferroelectric semiconductor and a preparation method thereof. Background Art
[0002] After the external electric field is removed, the ferroelectric crystal that has been polarized by an external electric field can still have a certain polarization, which is called remnant polarization. Because ferroelectrics have this power-off retention property, they become an ideal medium for manufacturing non-destructive random access memory. The positive remnant polarization represents the "1" information in binary storage, while the reverse remnant polarization represents the "0" information in binary storage. Therefore, the ferroelectric memory cell does not need to maintain an external electric field or voltage, and can still maintain the original polarization information. This bistable operation is different from the semiconductor dynamic random access memory that needs to maintain power to maintain the original information. FeFET uses ferroelectric materials as the gate dielectric layer to adjust the resistance of the channel. By maintaining the electric polarization, the on or off state can be maintained, thereby playing the role of non-volatile memory.
[0003] The on-state current of the graphene field effect device with h-BN as the tunneling layer is relatively small. The switching ratio and on-state current of the graphene field effect device with TMDCs as the tunneling layer are improved compared with the h-BN tunneling field effect device, but its room temperature subthreshold swing still has great room for improvement. It is very meaningful to improve the performance of TMDCs tunneling field effect devices. Summary of the invention
[0004] In response to the above technical problems, the present invention provides a storage vertical device based on two-dimensional ferroelectric semiconductors and a preparation method thereof, which can effectively improve the performance of TMDCs tunneling field effect devices.
[0005] The present invention solves the above-mentioned problem as follows:
[0006] A vertical storage device based on a two-dimensional ferroelectric semiconductor and a preparation method thereof. The device comprises, from bottom to top, a supporting substrate, a graphene back gate, a ferroelectric dielectric layer, a graphene floating gate, an insulating dielectric layer, a source electrode, a semiconductor channel, and a drain electrode, wherein the source and drain electrodes are respectively located on the upper and lower sides of the semiconductor channel.
[0007] Furthermore, the support substrate is silicon dioxide, hafnium dioxide or quartz glass with different thicknesses.
[0008] Furthermore, the back gate electrode is graphene of any thickness.
[0009] Furthermore, the ferroelectric dielectric layer is CuInP2S6, and the thickness of the ferroelectric dielectric layer is 10-50nm.
[0010] Furthermore, the floating gate electrode is graphene of arbitrary thickness.
[0011] Furthermore, the insulating dielectric layer is h-BN.
[0012] Furthermore, the source electrode is a single layer of graphene.
[0013] Furthermore, the semiconductor channel is a transition metal dichalcogenide, the transition metal dichalcogenide is WS2, WSe2 or MoS2, and the thickness of the conductive channel is 1-10 layers.
[0014] Furthermore, the drain electrode is a single-layer graphene.
[0015] The above-mentioned vertical storage device based on two-dimensional ferroelectric semiconductor and its preparation method include the following steps in sequence:
[0016] (1) stripping the source and drain graphene electrodes, the insulating dielectric layer, the ferroelectric dielectric layer, the graphene gate and the semiconductor channel material by a mechanical stripping method and setting them aside for later use;
[0017] (2) transferring the ferroelectric dielectric layer to the back-gate graphene support substrate by dry transfer, and sequentially transferring the graphene floating gate electrode, insulating dielectric layer, source electrode, semiconductor channel, and drain electrode in step (1) to the ferroelectric dielectric layer;
[0018] (3) Setting mask regions on the source and drain electrodes, graphene floating gate electrode, and graphene back gate electrode of the device in step (2) by photolithography, and then electron beam depositing a double-layer metal electrode, performing debonding, and preparing a vertical storage device based on a two-dimensional ferroelectric semiconductor.
[0019] Furthermore, in step (2), the dry transfer uses a PC and PDMS composite membrane.
[0020] Furthermore, for a vertical storage device based on a two-dimensional ferroelectric semiconductor, the transfer temperature in step (2) is 75-90°C and the placement temperature is 170-190°C.
[0021] The present invention has the following beneficial effects:
[0022] 1. In the present invention, a few layers of WS2 are selected as the tunneling layer to improve the performance parameters of the tunneling field effect device. At a temperature of 300K, the switching ratio is as high as 10 7 ;
[0023] 2. The present invention uses two-dimensional ferroelectric material CuInP2S6 as the dielectric layer and a graphene floating gate structure to enhance the stability of channel control by the ion migration effect and achieve long-retention memory storage characteristics; and utilizes the controllable amount of ion movement to achieve multi-resistance state storage under low-voltage operation. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to clearly illustrate the technical solution of the embodiment of the present invention, the following is a description of the accompanying drawings:
[0025] Figure 1 It is a schematic structural diagram of a vertical storage device based on a two-dimensional ferroelectric semiconductor according to the present invention;
[0026] Figure 2 The transfer characteristic curve of the vertical device based on two-dimensional ferroelectric semiconductor memory;
[0027] Figure 3 The device is maintained in the on and off states within 200 seconds.
[0028] Figure 4 This is the on-state and off-state retention characteristic diagram of the device within 5000s;
[0029] Figure 5 The resistance state diagram of the device with continuous pulse control and continuous change;
[0030] Markings in the figure: 1-support substrate, 2-graphene back gate, 3-ferroelectric dielectric layer, 4-graphene floating gate, 5-insulating dielectric layer, 6-source electrode, 7-conductive channel, 8-drain electrode. DETAILED DESCRIPTION
[0031] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the embodiments described are only part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.
[0032] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.
[0033] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0034] The features and performance of the present invention are further described in detail below in conjunction with the embodiments.
[0035] Example 1
[0036] A vertical storage device based on a two-dimensional ferroelectric semiconductor, the device comprises, from bottom to top, a supporting substrate 1, a graphene back gate 2, a ferroelectric dielectric layer 3, a graphene floating gate 4, an insulating dielectric layer 5, a source electrode 6, a conductive channel 7, and a drain electrode 8, wherein the source and drain electrodes are respectively located on the upper and lower sides of the semiconductor channel; the silicon dioxide layer of the supporting substrate SiO2 / Si is 285nm thick; the thickness of the graphene back gate and the graphene floating gate are both two layers; the ferroelectric dielectric layer is CuInP2S6 with a thickness of 10nm; the insulating dielectric layer is h-BN; the thickness of the source and drain graphene electrodes is both single layer; the conductive channel is WS2; a double-layer metal electrode is deposited on the graphene electrode, the upper layer of gold is 40nm thick, and the lower layer of chromium is 5nm thick.
[0037] The method for preparing the vertical storage device based on two-dimensional ferroelectric semiconductor comprises the following steps:
[0038] (1) Place the graphene block on a white transparent tape, tear it several times, and then stick it on a supporting substrate;
[0039] (2) preparing CuInP2S6, WS2, and h-BN samples by mechanical exfoliation according to the method of step (1);
[0040] (3) Preparation of dry transfer film: 3 ml of PVC solution was dropped onto a clean glass substrate, and a flat PC film was obtained by scraping. A 1 cm × 2 cm PC film was placed with the flat surface facing upward on the PDMS substrate adhered to one end of a transparent glass substrate;
[0041] (4) With the assistance of a microscope, a three-axis translation stage, and a temperature control platform, the dry transfer film prepared in step (3) is used to stack CuInP2S6, floating gate graphene, h-BN, source graphene, WS2, and drain graphene on the back gate graphene in this order to construct a van der Waals heterojunction; finally, the film is placed in a chloroform solution to wash away the PC film attached to the surface;
[0042] (5) Mask regions are set on the source and drain electrodes, graphene floating gate electrode, and graphene back gate electrode of the device by photolithography, and then a double-layer metal electrode is deposited by electron beam and debonded to prepare a vertical storage device based on a two-dimensional ferroelectric semiconductor.
[0043] Example 2
[0044] A vertical storage device based on a two-dimensional ferroelectric semiconductor, the device comprises, from bottom to top, a supporting substrate 1, a graphene back gate 2, a ferroelectric dielectric layer 3, a graphene floating gate 4, an insulating dielectric layer 5, a source electrode 6, a conductive channel 7, and a drain electrode 8, wherein the source and drain electrodes are respectively located on the upper and lower sides of the semiconductor channel; the silicon dioxide layer of the supporting substrate SiO2 / Si is 285nm thick; the thickness of the graphene back gate and the graphene floating gate are both two layers; the ferroelectric dielectric layer is CuInP2S6 with a thickness of 20nm; the insulating dielectric layer is h-BN; the thickness of the source and drain graphene electrodes is both single layer; the conductive channel is WSe2; a double-layer metal electrode is deposited on the graphene electrode, the upper layer of gold is 40nm thick, and the lower layer of chromium is 8nm thick.
[0045] The method for preparing the vertical storage device based on two-dimensional ferroelectric semiconductor comprises the following steps:
[0046] (1) Place the graphene block on a white transparent tape, tear it several times, and then stick it on a supporting substrate;
[0047] (2) Mechanically exfoliate and prepare CuInP2S6, WSe2, and h-BN samples according to the method of step (1) for later use;
[0048] (3) Preparation of dry transfer film: 3 ml of PVC solution was dropped onto a clean glass substrate, and a flat PC film was obtained by scraping. A 1 cm × 2 cm PC film was placed with the flat surface facing upward on the PDMS substrate adhered to one end of a transparent glass substrate;
[0049] (4) With the assistance of a microscope, a three-axis translation stage, and a temperature control platform, the dry transfer film prepared in step (3) is used to stack CuInP2S6, floating gate graphene, h-BN, source graphene, WSe2, and drain graphene on the back gate graphene in this order to construct a van der Waals heterojunction; finally, the film is placed in a chloroform solution to wash away the PC film attached to the surface;
[0050] (5) Mask regions are set on the source and drain electrodes, graphene floating gate electrode, and graphene back gate electrode of the device by photolithography, and then a double-layer metal electrode is deposited by electron beam and debonded to prepare a vertical storage device based on a two-dimensional ferroelectric semiconductor.
[0051] Example 3
[0052] A vertical storage device based on a two-dimensional ferroelectric semiconductor, the device comprises, from bottom to top, a supporting substrate 1, a graphene back gate 2, a ferroelectric dielectric layer 3, a graphene floating gate 4, an insulating dielectric layer 5, a source electrode 6, a conductive channel 7, and a drain electrode 8, wherein the source and drain electrodes are respectively located on the upper and lower sides of the semiconductor channel; the silicon dioxide layer of the supporting substrate SiO2 / Si is 285nm thick; the thickness of the graphene back gate and the graphene floating gate are both two layers; the ferroelectric dielectric layer is CuInP2S6 with a thickness of 30nm; the insulating dielectric layer is h-BN; the thickness of the source and drain graphene electrodes is both single layer; the conductive channel is MoS2; a double-layer metal electrode is deposited on the graphene electrode, the upper layer of gold is 35nm thick, and the lower layer of chromium is 5nm thick.
[0053] The method for preparing the vertical storage device based on two-dimensional ferroelectric semiconductor comprises the following steps:
[0054] (1) Place the graphene block on a white transparent tape, tear it several times, and then stick it on a supporting substrate;
[0055] (2) preparing CuInP2S6, MoS2, and h-BN samples by mechanical exfoliation according to the method of step (1) for later use;
[0056] (3) Preparation of dry transfer film: 3 ml of PVC solution was dropped onto a clean glass substrate, and a flat PC film was obtained by scraping. A 1 cm × 2 cm PC film was placed with the flat surface facing upward on the PDMS substrate adhered to one end of a transparent glass substrate;
[0057] (4) With the assistance of a microscope, a three-axis translation stage, and a temperature control platform, the dry transfer film prepared in step (3) is used to stack CuInP2S6, floating gate graphene, h-BN, source graphene, MoS2, and drain graphene on the back gate graphene in this order to construct a van der Waals heterojunction; finally, the film is placed in a chloroform solution to wash away the PC film attached to the surface;
[0058] (5) Mask regions are set on the source and drain electrodes, graphene floating gate electrode, and graphene back gate electrode of the device by photolithography, and then a double-layer metal electrode is deposited by electron beam and debonded to prepare a vertical storage device based on a two-dimensional ferroelectric semiconductor.
[0059] Test example
[0060] Taking the vertical memory device prepared in Example 1 as an example, the structure of the prepared device is as follows: Figure 1 The transfer characteristic curve of the vertical storage device based on two-dimensional ferroelectric semiconductor is shown in Figure 2 As shown in Figure 2, by adjusting the Fermi level of the graphene electrode to be close to or even higher than the conduction band of WS2, both the conduction band transport and the thermal transition transport will greatly increase the on-state current, thereby increasing the on-off ratio, which can reach 10 7 ; Test the device's retention characteristics after inputting the gate voltage signal, such as Figure 3 As shown in FIG. 1 , after inputting 4V and -1.5V gate voltage signals for 0.2s, the change in the resistance state of the channel caused by the gate voltage lasts for 200s; Figure 4 As shown in the figure, after inputting 4V and -1.5V respectively and applying a gate voltage signal for 1s, the change in the resistance state of the channel caused by the gate voltage lasts for up to 5000s. This shows that the use of WS2 two-dimensional semiconductor material as a conductive channel and CuInP2S6 as a ferroelectric dielectric layer achieves long-term retention characteristics.
[0061] Taking the vertical memory device prepared in Example 1 as an example, the response under a shorter pulse width is tested, such as Figure 5 As shown, a continuously changing resistance is obtained by using -1.5V 0.2s continuous pulse regulation. The device with memristor characteristics can be used as a basic element for multi-bit storage.
[0062] The experimental results in Example 2 and Example 3 are similar to those in Example 1, and no further details are given here. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A vertical storage device based on a two-dimensional ferroelectric semiconductor, characterized in that: From bottom to top, it includes a supporting substrate, a graphene back gate electrode, a ferroelectric dielectric layer, a graphene floating gate electrode, an insulating dielectric layer, a source-drain electrode, and a semiconductor channel. A semiconductor channel is arranged between the source electrode and the drain electrode, and the semiconductor channel is a transition metal dichalcogenide material; the source electrode and the drain electrode respectively form ohmic contacts with the semiconductor channel at a clean van der Waals interface.
2. The vertical storage device based on two-dimensional ferroelectric semiconductor according to claim 1, characterized in that: The supporting substrate is silicon dioxide, hafnium dioxide or quartz glass with different thicknesses.
3. The vertical storage device based on two-dimensional ferroelectric semiconductor according to claim 1, characterized in that: The graphene back gate electrode has any thickness.
4. The vertical storage device based on two-dimensional ferroelectric semiconductor according to claim 1, characterized in that: The ferroelectric dielectric layer is CuInP2S6, and the thickness of the ferroelectric dielectric layer is 10-50nm.
5. The vertical storage device based on two-dimensional ferroelectric semiconductor according to claim 1, characterized in that: The graphene floating gate electrode has any thickness.
6. The vertical storage device based on two-dimensional ferroelectric semiconductor according to claim 1, characterized in that: The insulating dielectric layer is h-BN.
7. The vertical storage device based on two-dimensional ferroelectric semiconductor according to claim 1, characterized in that: The source electrode and the drain electrode are both single-layer graphene.
8. The vertical storage device based on two-dimensional ferroelectric semiconductor according to claim 1, characterized in that: The semiconductor channel is a transition metal dichalcogenide compound, the transition metal dichalcogenide compound is WS2, WSe2 or MoS2, and the thickness of the conductive channel is 1-10 layers.
9. The method for preparing a vertical storage device based on a two-dimensional ferroelectric semiconductor according to any one of claims 1 to 8, characterized in that: The following steps are included in sequence: (1) stripping the source and drain graphene electrodes, the insulating dielectric layer, the ferroelectric dielectric layer, the graphene gate and the semiconductor channel material by a mechanical stripping method and setting them aside for later use; (2) transferring the ferroelectric dielectric layer to the back-gate graphene support substrate by dry transfer, and sequentially transferring the graphene floating gate electrode, insulating dielectric layer, source electrode, semiconductor channel, and drain electrode in step (1) to the ferroelectric dielectric layer; (3) Setting mask regions on the source and drain electrodes, graphene floating gate electrode, and graphene back gate electrode of the device in step (2) by photolithography, and then electron beam depositing a double-layer metal electrode, performing debonding, and preparing a vertical storage device based on a two-dimensional ferroelectric semiconductor.
10. The vertical storage device based on two-dimensional ferroelectric semiconductor according to claim 9, characterized in that: In step (2), the dry transfer uses a PC and PDMS composite membrane.
11. The vertical storage device based on two-dimensional ferroelectric semiconductor according to claim 9, characterized in that: In step (2), the transfer temperature is 75-90°C and the placement temperature is 170-190°C.