Three-dimensional structure Ga2O3 heterogeneous super junction diode and preparation method thereof

Abstract

The invention discloses a three-dimensional Ga2O3 heterogeneous super junction diode and a preparation method thereof, and the method comprises the steps: providing a substrate, and sequentially growing a p + type NiO epitaxial layer and an alkaline earth doped silicon oxide layer on the surface of the substrate; windowing the alkaline earth doped silicon oxide layer to form a plurality of windows arranged at intervals, and then reflowing the residual alkaline earth doped silicon oxide layer by using a rapid thermal annealing process to form a hemispherical mask; etching the p + type NiO epitaxial layer based on a hemispherical mask to form a plurality of hemispherical structures; growing an n + type Ga2O3 epitaxial layer on the upper surface of the device, and performing ion implantation on a plurality of sub-regions in the n + type Ga2O3 epitaxial layer to form an n + type electron transport layer; performing source region electrode region windowing on the n + type Ga2O3 epitaxial layer on the surface of the hemispherical structure in the source region, and growing a field oxygen passivation layer on the upper surface of the device; and removing the field oxygen passivation layer in the source region to perform source region electrode region windowing, forming a front electrode on the upper surface of the source region, and forming a back electrode on the lower surface of the substrate. The diode has excellent voltage resistance balance capability.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices and particularly relates to a three-dimensional structure Ga 2 O 3 Heterojunction superjunction diode and method for preparing the same. Background Art

[0002] Super junction (SJ) device is a new type of power semiconductor device that combines the excellent properties of silicon carbide materials and the advantages of super junction structure. It has good application prospects in electric vehicles, renewable energy, industrial power supplies and consumer electronics.

[0003] Gallium oxide is a third-generation wide bandgap semiconductor material with an ultra-wide bandgap (4.8-5.3eV) and ultra-high breakdown electric field (8MV / cm). Its power factor (BFOM) far exceeds that of silicon and silicon carbide, and is suitable for high-voltage and high-efficiency power electronic devices. Gallium oxide single crystals can be prepared by a low-cost melt growth method, with low reverse leakage current, high-temperature stability and excellent breakdown performance, and are suitable for use in superjunction devices.

[0004] However, there is no reliable P-type material for gallium oxide, and it can only form a superjunction structure through a heterojunction. The conventional lateral heterojunction structure used in the existing technology is not conducive to improving the blocking pressure-bearing capacity of the device. In addition, the thermal conductivity of gallium oxide is low and cannot meet the requirements of high power density applications. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a three-dimensional structure Ga 2 O 3 Heterogeneous superjunction diode and its preparation method. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, the present invention provides a three-dimensional structure Ga 2 O 3 A method for preparing a heterogeneous super junction diode, comprising:

[0007] Providing an n+ type SiC substrate, and sequentially growing a p+ type NiO epitaxial layer and an alkaline earth doped silicon oxide layer on the surface of the n+ type SiC substrate;

[0008] Opening windows in the alkaline earth doped silicon oxide layer to form a plurality of windows arranged at intervals, and then reflowing the remaining alkaline earth doped silicon oxide layer by a rapid thermal annealing process to form a hemispherical mask;

[0009] The p+ type NiO epitaxial layer is etched using a dry etching process and the hemispherical mask to form a plurality of hemispherical structures arranged at intervals; wherein the hemispherical structure with the largest diameter is located in a transition region of the device, and the two sides of the transition region are the source region and the terminal region of the device respectively;

[0010] n+ type Ga is epitaxially grown on the device surface 2 O 3 epitaxial layer, and the n+ type Ga 2 O 3 Ion implantation is performed on multiple sub-regions of the epitaxial layer to form an n+ type electron transport layer; in a direction perpendicular to the plane where the n+ type SiC substrate is located, the orthographic projection of the sub-region is located between the orthographic projections of two adjacent hemispherical structures in the source region, or between the orthographic projection of the hemispherical structure in the source region and the orthographic projection of the hemispherical structure in the transition region;

[0011] The n+ type Ga 2 O 3 The epitaxial layer is windowed in the source region and the electrode region, and a field oxygen passivation layer is grown on the upper surface of the device to form an ohmic contact on the lower surface of the n+ type SiC substrate;

[0012] The field oxygen passivation layer in the source region is removed to open a window in the source region electrode region, a Schottky contact and a front electrode are formed on the upper surface of the device source region, and a back electrode is formed on the lower surface of the n+ type SiC substrate.

[0013] In one embodiment of the present invention, after opening windows in the alkaline earth doped silicon oxide layer to form a plurality of spaced windows, the step of reflowing the remaining alkaline earth doped silicon oxide layer by a rapid thermal annealing process to form a hemispherical mask includes:

[0014] The alkaline earth doped silicon oxide layer is opened by photolithography and etching process to form a plurality of windows arranged at intervals; wherein, in a direction perpendicular to the plane where the n+ type SiC substrate is located, the orthographic projection of the window is a square, and the side length of the square is 6 to 20 μm;

[0015] Under the conditions of an annealing temperature of 900-1000° C. and a time of 120-180 seconds, a rapid thermal annealing process is used to reflow the remaining alkaline earth doped silicon oxide layer to form a hemispherical mask.

[0016] In one embodiment of the present invention, the n+ type Ga 2 O 3 The epitaxial layer and the p+ type NiO epitaxial layer maintain a charge balance state.

[0017] In one embodiment of the present invention, the thickness of the n+ type SiC substrate is 350 μm and the doping concentration is 5×10 18 cm -3 The thickness of the p+ type NiO epitaxial layer is 6 to 20 μm, and the doping concentration is 2×10 16 ~6×10 16 cm -3 The thickness of the alkaline earth doped silicon oxide layer is 6 to 20 μm, and the n+ type Ga 2 O 3 The thickness of the epitaxial layer is 4 to 28 μm, and the doping concentration is 2×10 16 ~6×10 16 cm -3 .

[0018] In one embodiment of the present invention, when the p+ type NiO epitaxial layer is etched using a dry etching process and the hemispherical mask, the etching selectivity is 1.

[0019] In one embodiment of the present invention, the step of forming an ohmic contact on the lower surface of the n+ type SiC substrate comprises:

[0020] Depositing Ni metal with a thickness of 75 to 100 nm on the lower surface of the n+ type SiC substrate using an electron beam evaporation process;

[0021] Under the conditions of an annealing temperature of 950 to 1050° C. and an annealing time of 120 to 300 seconds, an ohmic contact is formed on the lower surface of the n+ type SiC substrate by using a rapid thermal annealing process.

[0022] In one embodiment of the present invention, the step of removing the field oxide passivation layer in the source region to open a window in the source region electrode region, forming a Schottky contact on the upper surface of the device source region and forming a front electrode includes:

[0023] Using photolithography and wet etching processes, the field oxide passivation layer in the source region is removed to open a window in the source electrode region;

[0024] Depositing Schottky metal Ti or Ni on the upper surface of the device by electron beam evaporation or magnetron sputtering;

[0025] A Schottky pattern is formed by a photolithography process, and a Schottky contact is formed by a rapid thermal annealing process at an annealing temperature of 400 to 600° C. and an annealing time of 5 to 10 minutes;

[0026] Al is deposited on the upper surface of the device by electron beam evaporation or magnetron sputtering, and a front electrode is formed on the upper surface of the source region of the device by photolithography and wet etching.

[0027] In one embodiment of the present invention, before the step of forming a back electrode on the lower surface of the n+ type SiC substrate, the method further comprises:

[0028] A polyimide PI passivation layer with a thickness of 6 mm is formed on the upper surface of the field oxygen passivation layer in the transition zone and the terminal zone.

[0029] In one embodiment of the present invention, the step of forming a back electrode on the lower surface of the n+ type SiC substrate comprises:

[0030] By using an electron beam evaporation process, Ti / Ni / Ag with a thickness of 200nm / 200nm / 1000nm is deposited on the lower surface of the n+ type SiC substrate to form a back electrode.

[0031] In a second aspect, the present invention also provides a three-dimensional structure Ga 2 O 3 The heterogeneous super junction diode is manufactured by the method described in the first aspect.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The present invention provides a three-dimensional Ga2O3 heterogeneous superjunction diode and a preparation method thereof. The prepared superjunction diode is a three-dimensional structure, which has a slower electric field extension capability than the existing two-dimensional structure, and thus can have a better voltage-resistance balance capability, and can achieve lower resistance under the same voltage level conditions. In addition, the present invention uses an n+ type SiC substrate in the preparation process. SiC, a material with high thermal conductivity, helps to dissipate heat, further improving the three-dimensional structure Ga 2 O 3 Performance of heterojunction superjunction diodes.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The three-dimensional structure Ga provided by the embodiment of the present invention 2 O 3 Flow chart of the method for preparing a heterojunction superjunction diode;

[0036] Figures 2 to 12 The three-dimensional structure Ga provided by the embodiment of the present invention 2 O 3 Schematic diagram of the preparation process of heterojunction superjunction diode. DETAILED DESCRIPTION

[0037] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0038] Figure 1 The three-dimensional structure Ga provided by the embodiment of the present invention 2 O 3 Flow chart of the method for preparing a heterojunction superjunction diode, Figures 2 to 12 The three-dimensional structure Ga provided by the embodiment of the present invention 2 O 3 Schematic diagram of the preparation process of heterojunction superjunction diode. Figures 1 to 12 As shown, the embodiment of the present invention provides a three-dimensional structure Ga 2 O 3 A method for preparing a heterogeneous super junction diode, comprising:

[0039] S1, providing an n+ type SiC substrate 1, and sequentially growing a p+ type NiO epitaxial layer 2 and an alkaline earth doped silicon oxide layer 3 on the surface of the n+ type SiC substrate 1;

[0040] S2, after opening windows in the alkaline earth doped silicon oxide layer 3 to form a plurality of windows 4 arranged at intervals, the remaining alkaline earth doped silicon oxide layer 3 is reflowed by a rapid thermal annealing process to form a hemispherical mask 5;

[0041] S3, using a dry etching process and a hemispherical mask 5 to etch the p+ type NiO epitaxial layer 2 to form a plurality of hemispherical structures 6 arranged at intervals; wherein the hemispherical structure 6 with the largest diameter is located in the transition region of the device, and the two sides of the transition region are the source region and the terminal region of the device respectively;

[0042] S4, epitaxially grow n+ type Ga on the upper surface of the device 2 O 3 Epitaxial layer 7, and for n+ type Ga 2 O 3 Ion implantation is performed on multiple sub-regions of the epitaxial layer 7 to form an n+ type electron transport layer 8; in a direction perpendicular to the plane where the n+ type SiC substrate 1 is located, the orthographic projection of the sub-region is located between the orthographic projections of two adjacent hemispherical structures 6 in the source region, or between the orthographic projection of the hemispherical structure 6 in the source region and the orthographic projection of the hemispherical structure 6 in the transition region;

[0043] S5, the n+ type Ga 2 O 3 The epitaxial layer 7 is windowed in the source region electrode region, and a field oxygen passivation layer 9 is grown on the upper surface of the device to form an ohmic contact on the lower surface of the n+ type SiC substrate 1;

[0044] S6, removing the field oxygen passivation layer 9 in the source region to open a window in the source region electrode region, forming a Schottky contact and a front electrode 10 on the upper surface of the device source region, and forming a back electrode 11 on the lower surface of the n+ type SiC substrate 1.

[0045] It should be understood that the existing two-dimensional superjunction structure can be decomposed into the superposition of electric field vectors in the horizontal and vertical directions, in which the electric field in any direction extending too fast will cause the device to avalanche breakdown. The superjunction diode prepared by the above method in the present invention is a three-dimensional structure, which can obtain better PN junction depletion and high controllability of the electric field in the vertical direction. Compared with the two-dimensional structure, it has a slower electric field extension ability, so it can have a better voltage-resistance balance ability and can achieve lower resistance under the same voltage level. At the same time, since the heat dissipation performance of the power device will also affect the reliability of the device, the present invention uses an n+ type SiC substrate in the preparation process. SiC, a material with high thermal conductivity, helps to dissipate heat, further improving the three-dimensional structure Ga 2 O 3 Performance of heterojunction superjunction diodes.

[0046] Optionally, in this embodiment, the thickness of the n+ type SiC substrate 1 is 350 μm and the doping concentration is 5×10 18 cm -3 The thickness of the p+ type NiO epitaxial layer 2 is 6 to 20 μm, and the doping concentration is 2×10 16 ~6×10 16 cm -3 The thickness of the alkaline earth doped silicon oxide layer 3 is 6 to 20 μm.

[0047] like Figures 3 to 5 As shown, in step S2, after opening windows in the alkaline earth doped silicon oxide layer 3 to form a plurality of spaced windows 4, the remaining alkaline earth doped silicon oxide layer 3 is reflowed by a rapid thermal annealing process to form a hemispherical mask 5, comprising:

[0048] S201, opening windows in the alkaline earth doped silicon oxide layer 3 by photolithography and etching processes to form a plurality of windows 4 arranged at intervals; wherein, in a direction perpendicular to the plane where the n+ type SiC substrate 1 is located, the orthographic projection of the window 4 is a square, and the side length of the square is 6 to 20 μm;

[0049] S202 , under the condition of annealing temperature of 900-1000° C. and time of 120-180 s, the remaining alkaline earth doped silicon oxide layer 3 is reflowed by a rapid thermal annealing process to form a hemispherical mask 5 .

[0050] Specifically, firstly, the alkaline earth doped silicon oxide layer 3 is opened by photolithography and etching process, and the formed multiple windows 4 are arranged at intervals. Figure 4 At the viewing angle shown, the vertical projection of each window 4 is a square. Figure 4Only six windows 4 are used as an example for illustration. In fact, the present application does not limit the number and shape of the windows 4. Next, a rapid thermal annealing treatment is performed under the conditions of an annealing temperature of 900 to 1000°C and a time of 120 to 180 seconds. During this process, the alkaline earth-doped silicon oxide layer 3 remaining after etching in step S201, i.e., the alkaline earth-doped silicon oxide layer 3 between two adjacent windows 4, will reflow to form a hemispherical mask 5.

[0051] Furthermore, in step S3, when the p+ type NiO epitaxial layer 2 is etched using the dry etching process and the hemispherical mask 5, the etching selectivity ratio is 1.

[0052] Still Figure 4 For example, it is worth noting that Figure 4 The six windows 4 in the middle divide the remaining alkaline earth doped silicon oxide layer 3 into five parts, and the alkaline earth doped silicon oxide layer 3 in each part is reflowed to form a hemispherical mask 5, wherein the hemispherical mask 5 formed by the reflow of the alkaline earth doped silicon oxide layer 3 in the middle part has the largest width in the horizontal direction. Therefore, when the etching selectivity is 1, five hemispherical structures 6 (such as Figure 6 As shown), similarly, the hemispherical structure 6 in the middle has the largest size and is located in the transition region of the device, while its left and right sides are the source region and terminal region of the device.

[0053] In addition, it should be noted that if more windows 4 are formed by etching in step S2, more hemispherical structures 6 will be formed accordingly. At this time, the hemispherical structure 6 located in the middle position is still the largest in size. It is located in the transition zone, and the left and right sides are the source region and the terminal region of the device respectively.

[0054] See also Figure 7 In step S4, n+ type Ga is epitaxially grown on the upper surface of the device. 2 O 3 Epitaxial layer 7, n+ type Ga 2 O 3 The epitaxial layer 7 covers the surface of the plurality of hemispherical structures 6 and is wavy in shape. The thickness of the epitaxial layer is 4 to 28 μm and the doping concentration is 2×10 16 ~6×10 16 cm -3 , by the p+ type NiO epitaxial layer 2 and the n+ type Ga 2 O 3 The design of the thickness and doping concentration of the epitaxial layer 7 can keep the two in a charge balance state to avoid premature breakdown of the device.

[0055] n+ type Ga 2 O 3The epitaxial layer 7 includes a plurality of sub-regions. Specifically, the sub-region is located between two adjacent hemispherical structures 6 in the source region. 2 O 3 n+ type Ga in the epitaxial layer 7 and between the two hemispherical structures 6 at the junction of the source region and the transition region 2 O 3 The epitaxial layer 7 is implanted into each sub-region by ion implantation to form an n+ type electron transport layer 8 with a concentration of 1×10 18 ~5×10 18 cm -3 , and finally high temperature ion implantation activation is performed.

[0056] Furthermore, in step S5, a dry etching process is used to etch the n+ type Ga 2 O 3 The epitaxial layer 7 is windowed in the source and electrode regions, and then subjected to sacrificial oxidation, and a field oxygen passivation layer 9 is grown on the upper surface of the device using a PECVD process.

[0057] The step of forming an ohmic contact on the lower surface of the n+ type SiC substrate 1 comprises:

[0058] S501, using electron beam evaporation process to deposit Ni metal with a thickness of 75-100 nm on the lower surface of the n+ type SiC substrate 1;

[0059] S502 , forming an ohmic contact on the lower surface of the n + -type SiC substrate 1 by using a rapid thermal annealing process under the conditions of an annealing temperature of 950 to 1050° C. and an annealing time of 120 to 300 seconds.

[0060] like Figures 10-11 As shown, in step S6, the field oxide passivation layer 9 in the source region is removed to open a window in the source region electrode region, and a Schottky contact is formed on the upper surface of the device source region and a front electrode 10 is formed, including:

[0061] S601, using photolithography and wet etching processes to remove the field oxide passivation layer 9 in the source region to open a window in the source electrode region;

[0062] S602, depositing Schottky metal Ti or Ni on the upper surface of the device by electron beam evaporation or magnetron sputtering process;

[0063] S603, forming a Schottky pattern by using a photolithography process, and forming a Schottky contact by a rapid thermal annealing process at an annealing temperature of 400 to 600° C. and an annealing time of 5 to 10 minutes;

[0064] S604, using electron beam evaporation or magnetron sputtering technology to deposit Al on the upper surface of the device, using photolithography and wet etching technology to form a front electrode 10 on the upper surface of the source region of the device.

[0065] Alternatively, if Fig.12 As shown, before the step of forming the back electrode 11 on the lower surface of the n+ type SiC substrate 1, the method further includes:

[0066] A polyimide PI passivation layer 12 with a thickness of 6 mm is formed on the upper surface of the field oxygen passivation layer 9 in the transition region and the terminal region.

[0067] The step of forming a back electrode 11 on the lower surface of the n+ type SiC substrate 1 comprises:

[0068] By using an electron beam evaporation process, Ti / Ni / Ag with a thickness of 200nm / 200nm / 1000nm is deposited on the lower surface of the n+ type SiC substrate 1 to form a back electrode 11.

[0069] On the other hand, Fig.12 As shown, the present invention also provides a three-dimensional structure Ga 2 O 3 Heterojunction superjunction diodes, using the above three-dimensional structure Ga 2 O 3 The invention discloses a method for preparing a heterojunction superjunction diode.

[0070] It can be seen from the above embodiments that the beneficial effects of the present invention are:

[0071] The present invention provides a three-dimensional Ga2O3 heterogeneous superjunction diode and a preparation method thereof. The prepared superjunction diode is a three-dimensional structure, which has a slower electric field extension capability than the existing two-dimensional structure, and thus can have a better voltage-resistance balance capability, and can achieve lower resistance under the same voltage level conditions. In addition, the present invention uses an n+ type SiC substrate in the preparation process. SiC, a material with high thermal conductivity, helps to dissipate heat, further improving the three-dimensional structure Ga 2 O 3 Performance of heterojunction superjunction diodes.

[0072] In the description of the present invention, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0073] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a three-dimensional Ga2O3 heterojunction diode, characterized in that: include: Providing an n+ type SiC substrate, and sequentially growing a p+ type NiO epitaxial layer and an alkaline earth doped silicon oxide layer on the surface of the n+ type SiC substrate; Opening windows in the alkaline earth doped silicon oxide layer to form a plurality of windows arranged at intervals, and then reflowing the remaining alkaline earth doped silicon oxide layer by a rapid thermal annealing process to form a hemispherical mask; The p+ type NiO epitaxial layer is etched using a dry etching process and the hemispherical mask to form a plurality of hemispherical structures arranged at intervals; wherein the hemispherical structure with the largest diameter is located in a transition region of the device, and the two sides of the transition region are the source region and the terminal region of the device respectively; An n+ type Ga2O3 epitaxial layer is epitaxially grown on the upper surface of the device, and ion implantation is performed on a plurality of sub-regions of the n+ type Ga2O3 epitaxial layer to form an n+ type electron transport layer; in a direction perpendicular to the plane where the n+ type SiC substrate is located, the orthographic projection of the sub-region is located between the orthographic projections of two adjacent hemispherical structures in the source region, or between the orthographic projection of the hemispherical structure in the source region and the orthographic projection of the hemispherical structure in the transition region; Opening a window in the source electrode region of the n+ type Ga2O3 epitaxial layer located on the surface of the hemispherical structure in the source region of the device, growing a field oxygen passivation layer on the upper surface of the device, and forming an ohmic contact on the lower surface of the n+ type SiC substrate; The field oxygen passivation layer in the source region is removed to open a window in the source region electrode region, a Schottky contact and a front electrode are formed on the upper surface of the device source region, and a back electrode is formed on the lower surface of the n+ type SiC substrate.

2. The method for preparing a three-dimensional Ga2O3 heterojunction diode according to claim 1, characterized in that: After opening windows in the alkaline earth doped silicon oxide layer to form a plurality of windows arranged at intervals, the step of reflowing the remaining alkaline earth doped silicon oxide layer by a rapid thermal annealing process to form a hemispherical mask comprises: The alkaline earth doped silicon oxide layer is opened by photolithography and etching process to form a plurality of windows arranged at intervals; wherein, in a direction perpendicular to the plane where the n+ type SiC substrate is located, the orthographic projection of the window is a square, and the side length of the square is 6 to 20 μm; Under the conditions of an annealing temperature of 900-1000° C. and a time of 120-180 seconds, a rapid thermal annealing process is used to reflow the remaining alkaline earth doped silicon oxide layer to form a hemispherical mask.

3. The method for preparing a three-dimensional Ga2O3 heterojunction diode according to claim 1, characterized in that: The n+ type Ga2O3 epitaxial layer and the p+ type NiO epitaxial layer maintain a charge balance state.

4. The method for preparing a three-dimensional Ga2O3 heterojunction diode according to claim 3, characterized in that: The thickness of the n+ type SiC substrate is 350 μm and the doping concentration is 5×10 18 cm -3 The thickness of the p+ type NiO epitaxial layer is 6 to 20 μm, and the doping concentration is 2×10 16 ~6×10 16 cm -3 The thickness of the alkaline earth doped silicon oxide layer is 6 to 20 μm, the thickness of the n+ type Ga2O3 epitaxial layer is 4 to 28 μm, and the doping concentration is 2×10 16 ~6×10 16 cm -3 .

5. The method for preparing a three-dimensional Ga2O3 heterojunction diode according to claim 1, characterized in that: When the p+ type NiO epitaxial layer is etched using a dry etching process and the hemispherical mask, the etching selectivity ratio is 1.

6. The method for preparing a three-dimensional Ga2O3 heterojunction diode according to claim 1, characterized in that: The step of forming an ohmic contact on the lower surface of the n+ type SiC substrate comprises: Depositing Ni metal with a thickness of 75 to 100 nm on the lower surface of the n+ type SiC substrate using an electron beam evaporation process; Under the conditions of an annealing temperature of 950 to 1050° C. and an annealing time of 120 to 300 seconds, an ohmic contact is formed on the lower surface of the n+ type SiC substrate by using a rapid thermal annealing process.

7. The method for preparing a three-dimensional Ga2O3 heterojunction diode according to claim 1, characterized in that: The steps of removing the field oxygen passivation layer in the source region to open a window in the source region electrode region, forming a Schottky contact on the upper surface of the device source region and forming a front electrode include: Using photolithography and wet etching processes, the field oxide passivation layer in the source region is removed to open a window in the source electrode region; Depositing Schottky metal Ti or Ni on the upper surface of the device by electron beam evaporation or magnetron sputtering; A Schottky pattern is formed by a photolithography process, and a Schottky contact is formed by a rapid thermal annealing process at an annealing temperature of 400 to 600° C. and an annealing time of 5 to 10 minutes; Al is deposited on the upper surface of the device by electron beam evaporation or magnetron sputtering, and a front electrode is formed on the upper surface of the source region of the device by photolithography and wet etching.

8. The method for preparing a three-dimensional Ga2O3 heterojunction diode according to claim 7, characterized in that: Before the step of forming a back electrode on the lower surface of the n+ type SiC substrate, the method further comprises: A polyimide PI passivation layer with a thickness of 6 mm is formed on the upper surface of the field oxygen passivation layer in the transition zone and the terminal zone.

9. The method for preparing a three-dimensional Ga2O3 heterojunction diode according to claim 8, characterized in that: The step of forming a back electrode on the lower surface of the n+ type SiC substrate comprises: By using an electron beam evaporation process, Ti / Ni / Ag with a thickness of 200nm / 200nm / 1000nm is deposited on the lower surface of the n+ type SiC substrate to form a back electrode.

10. A three-dimensional Ga2O3 heterojunction diode, characterized in that: The method is prepared by the method according to any one of claims 1 to 9.

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