Terminal structure and preparation method thereof, semiconductor device, power module and vehicle

Abstract

The invention discloses a terminal structure of a semiconductor device, a preparation method of the terminal structure, the semiconductor device, a power module and a vehicle, and the terminal structure of the semiconductor device comprises a substrate of a first conduction type, a main junction region of a second conduction type, and a plurality of transverse variable doping regions of the second conduction type. The main junction region is formed in the substrate and is close to the upper surface of the substrate; the plurality of lateral variable doping regions are all formed in the substrate, the plurality of lateral variable doping regions are located at one side, close to the edge of the terminal structure, of the main junction region, the plurality of lateral variable doping regions and the main junction region are arranged along a first direction, the lateral variable doping region closest to the main junction region in the plurality of lateral variable doping regions is connected with the main junction region, and the lateral variable doping region closest to the main junction region is connected with the substrate. Every two adjacent transverse variable doping regions are connected with each other, and the impurity concentration of the connecting position of the transverse variable doping regions in the first direction is smaller than the impurity concentration of the interiors of the transverse variable doping regions. According to the terminal structure, the adverse effect of charge dose change on voltage resistance of the terminal structure is reduced, and the voltage resistance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a terminal structure of a semiconductor device, a method for preparing the terminal structure of a semiconductor device, a semiconductor device, a power module and a vehicle. Background Art

[0002] In the field of semiconductor device manufacturing, the design and optimization of the terminal structure are crucial to improving the stability and reliability of the device. At present, planar junction terminal technologies include equipotential ring (ER), field plate (FP), field limiting ring (FLR), junction terminal extension (JTE) and variable lateral doping (VLD) technology. Among them, VLD technology uses certain design rules to change the opening size of the ion implantation mask. After ion implantation and junction pushing, the lateral doping concentration gradually decreases from the main junction to the edge of the chip, thereby reducing the curvature at the edge of the depletion region and improving the withstand voltage.

[0003] However, VLD technology still faces the problem of charge sensitivity, that is, changes in charge dose may have a negative impact on the withstand voltage performance of the terminal structure, and can only maintain a high withstand voltage level within a narrow range of implantation doses. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a terminal structure of a semiconductor device, which can reduce the adverse effect of charge dose variation on the withstand voltage of the terminal structure, so that the entire terminal structure can maintain a high withstand voltage level within a wider range of injection doses, thereby increasing the overall withstand voltage capability of the device, thereby improving the stability and reliability of the device.

[0005] A second object of the present invention is to provide a semiconductor device.

[0006] The third objective of the present invention is to provide a power module.

[0007] A fourth objective of the present invention is to provide a vehicle.

[0008] A fifth object of the present invention is to provide a method for preparing a terminal structure of a semiconductor device.

[0009] In order to achieve the above-mentioned purpose, the terminal structure of the semiconductor device of the first aspect embodiment of the present invention includes: a substrate of a first conductive type; a main junction region of a second conductive type, the main junction region is formed in the substrate and close to the upper surface of the substrate; a plurality of lateral variable doping regions of the second conductive type, the plurality of lateral variable doping regions are all formed in the substrate, the plurality of lateral variable doping regions are located on one side of the edge of the main junction region close to the terminal structure, the plurality of lateral variable doping regions and the main junction region are arranged along a first direction, the lateral variable doping region closest to the main junction region among the plurality of lateral variable doping regions is connected to the main junction region, two adjacent lateral variable doping regions are connected to each other, and the impurity concentration at the connection of the lateral variable doping regions in the first direction is less than the impurity concentration inside the lateral variable doping regions.

[0010] According to the terminal structure of the semiconductor device of the embodiment of the present invention, a group-designed lateral variable doping region is adopted, and the impurity concentration at the connection in the first direction is less than the impurity concentration inside the lateral variable doping region. This means that the impurity concentration at the connection of the lateral variable doping region is low, so that the electric field distribution is more uniform. That is, when the charge dose changes, the electric field distribution in the low-concentration area is more gentle, which effectively reduces the concentration of the electric field between the lateral variable doping regions. This arrangement and connection method ensures that the impurity concentration between adjacent lateral variable doping regions gradually transitions, reducing the electric field gradient at the connection in the first direction. Therefore, the entire terminal structure can maintain a high withstand voltage level within a wider range of injection doses. This design not only increases the overall withstand voltage capability of the device, but also reduces the sensitivity to changes in doping concentration. That is, the adverse effect of charge dose changes on the withstand voltage of the terminal structure is reduced, thereby improving the stability and reliability of the device.

[0011] In some embodiments, the impurity concentration distribution inside at least one of the lateral variable doping regions along the first direction is the same or different.

[0012] In some embodiments, the impurity concentration distribution inside at least one of the lateral variable doping regions along the first direction includes a plurality of concentration peaks or at least one concentration valley.

[0013] In some embodiments, the terminal structure further includes: a dielectric layer, wherein the dielectric layer is located on the substrate in a second direction perpendicular to the first direction.

[0014] In some embodiments, the terminal structure further includes: a first floating field plate, which is located on the dielectric layer in the second direction and is arranged corresponding to a connection between two adjacent lateral variable doping regions.

[0015] In some embodiments, the terminal structure also includes: a second floating field plate, which is located on the dielectric layer in the second direction and corresponds to an edge lateral variable doping region of the plurality of lateral variable doping regions that is closest to the edge of the terminal structure, and the second floating field plate is located above the end of the edge lateral variable doping region that is close to the edge of the terminal structure.

[0016] In some embodiments, the terminal structure further includes: a metal anode, which is located above the main junction region in the second direction and connected to the main junction region, and the metal anode extends along the first direction to above one end of the dielectric layer close to the main junction region.

[0017] In some embodiments, the terminal structure further includes: a metal cathode located on the lower surface of the substrate in the second direction.

[0018] In order to achieve the above object, a semiconductor device according to an embodiment of the second aspect of the present invention comprises an active region and a terminal structure of the semiconductor device described in the above embodiment, wherein the terminal structure surrounds the active region.

[0019] According to the semiconductor device of the embodiment of the present invention, by adopting the terminal structure of the semiconductor device described in the above embodiment, the terminal structure surrounds the active area and effectively integrates the active area with the terminal structure. By adopting the lateral variable doping area designed in groups, the impurity concentration at the connection in the first direction is less than the impurity concentration inside the lateral variable doping area. This means that the impurity concentration at the connection of the lateral variable doping area is low, so that the electric field distribution is more uniform. That is, when the charge dose changes, the electric field distribution in the low concentration area is more gentle, which effectively reduces the concentration of the electric field between the lateral variable doping areas. This arrangement and connection method ensures that the impurity concentration between adjacent lateral variable doping areas gradually transitions, reducing the electric field gradient at the connection in the first direction. Therefore, the entire terminal structure can maintain a high withstand voltage level within a wider range of injection doses. This design not only increases the overall withstand voltage capability of the device, but also reduces the sensitivity to changes in doping concentration. That is, the adverse effect of charge dose changes on the withstand voltage of the terminal structure is reduced, thereby improving the stability and reliability of the device.

[0020] In order to achieve the above object, a power module according to an embodiment of the third aspect of the present invention includes at least one semiconductor device as described in the above embodiment.

[0021] According to the power module of the embodiment of the present invention, by adopting at least one semiconductor device as described in the above embodiment, the adverse effect of charge dose variation on the withstand voltage of the terminal structure can be reduced, so that the entire terminal structure can maintain a high withstand voltage level within a wider injection dose range, thereby increasing the overall withstand voltage capability of the device, thereby improving the stability and reliability of the device.

[0022] In order to achieve the above-mentioned object, a vehicle according to an embodiment of the fourth aspect of the present invention comprises the power module described in the above embodiment.

[0023] According to the vehicle of the embodiment of the present invention, by adopting the power module described in the above embodiment, the adverse effect of the charge dose change on the voltage resistance of the terminal structure can be reduced, so that the entire terminal structure can maintain a high voltage resistance level within a wider injection dose range, thereby increasing the overall voltage resistance capability of the device, thereby improving the stability and reliability of the device.

[0024] In order to achieve the above-mentioned purpose, a method for preparing a terminal structure of a semiconductor device in an embodiment of the fifth aspect of the present invention includes: providing a substrate of a first conductive type; forming an injection barrier layer on the upper surface of the substrate; forming multiple groups of injection windows on the injection barrier layer along a first direction, wherein the interval between two adjacent groups of injection windows is greater than the interval between the injection windows in the group; injecting impurities of a second conductive type into the injection windows to form injection regions with intervals arranged along the first direction in the substrate; removing the barrier layer and diffusing and pushing the impurities of the second conductive type to form a main junction region and multiple lateral variable doping regions arranged along the first direction in the substrate, wherein the lateral variable doping region closest to the main junction region among the multiple lateral variable doping regions is connected to the main junction region, and two adjacent lateral variable doping regions are connected to each other, and the impurity concentration at the connection between the lateral variable doping regions in the first direction is less than the impurity concentration inside the lateral variable doping region.

[0025] According to the method for preparing the terminal structure of the semiconductor device of the embodiment of the present invention, by forming an injection barrier layer on the upper surface of the substrate, and forming multiple groups of injection windows along the first direction on the injection barrier layer, the interval between two adjacent groups of injection windows is greater than the interval between the injection windows in the group, the injection position and concentration distribution of the impurities can be accurately controlled. After the second conductivity type impurities are injected into the injection window, the injection barrier layer is removed and the second conductivity type impurities are diffused and pushed to form a main junction area and multiple lateral variable doping areas. Through this design, the impurity concentration of the lateral variable doping area is relatively low in the transition area between groups, and the concentration is high in the group. This concentration distribution design ensures that the electric field is more evenly distributed between the lateral variable doping areas, reducing the electric field inhomogeneity caused by the drastic change of local doping concentration. When the charge dose changes, the electric field distribution in the low concentration area is more gentle, effectively reducing the electric field concentration phenomenon between the lateral variable doping areas. Therefore, this preparation method ensures that the impurity concentration between adjacent lateral variable doping areas is gradually transitioned, reduces the electric field gradient at the connection in the first direction, and enables the entire terminal structure to maintain a higher withstand voltage level within a wider range of injection doses. This design not only increases the overall withstand voltage capability of the device, but also reduces the sensitivity to changes in doping concentration and the adverse effects of charge dose changes on the withstand voltage of the terminal structure, thereby improving the stability and reliability of the device.

[0026] In some embodiments, the impurity concentration N1 at the connection of the lateral variable doping region satisfies: 1E 13 cm -3 ≤N1≤1E 16 cm -3 .

[0027] In some embodiments, the impurity concentration N2 inside the lateral variable doping region satisfies: 1E 14 cm -3 ≤N1≤1E 17 cm -3 .

[0028] In some embodiments, the interval S between two adjacent groups of injection windows is 间隔1 The value of satisfies: 2μm≤S 间隔1 ≤15μm.

[0029] In some embodiments, the interval S between the injection windows in a group 间隔2 The value of satisfies: 0.5μm≤S 间隔2 ≤5μm.

[0030] In some embodiments, a width T of the injection window along the first direction satisfies: 0.5 μm≤T≤5 μm.

[0031] In some embodiments, the preparation method also includes: forming a dielectric layer on the upper surface of the substrate; preparing a metal anode on the substrate corresponding to the main junction region, and the metal anode extends along the first direction to above one end of the dielectric layer close to the main junction region.

[0032] In some embodiments, the preparation method further includes: preparing a first floating field plate at a connection position on the dielectric layer corresponding to the lateral variable doping region.

[0033] In some embodiments, the preparation method also includes: preparing a second floating field plate on the dielectric layer corresponding to an edge lateral doping region of the plurality of lateral doping regions closest to the edge of the terminal structure, wherein the second floating field plate is located above the end of the edge lateral doping region close to the edge of the terminal structure.

[0034] In some embodiments, the preparation method further includes: preparing a metal cathode on the lower surface of the substrate.

[0035] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0037] Figure 1 is a schematic diagram of a terminal structure of a semiconductor device according to an embodiment of the present invention;

[0038] Figure 2 According to one embodiment of the present invention Figure 1 A schematic diagram of the impurity concentration distribution of the second conductivity type at the middle dotted line position;

[0039] Figure 3 is a curve diagram showing the relationship between charge injection dose and withstand voltage value in the prior art and the present invention according to one embodiment of the present invention;

[0040] Figure 4 is a schematic diagram of a terminal structure of a semiconductor device according to yet another embodiment of the present invention;

[0041] Figure 5 is a block diagram of a semiconductor device according to an embodiment of the present invention;

[0042] Figure 6 is a block diagram of a power module according to an embodiment of the present invention;

[0043] Figure 7 is a block diagram of a vehicle according to one embodiment of the present invention;

[0044] Figure 8 is a flow chart of a method for preparing a terminal structure of a semiconductor device according to an embodiment of the present invention;

[0045] Fig. 9 is a schematic diagram of a substrate of a first conductivity type according to an embodiment of the present invention;

[0046] Fig.10 is a schematic diagram of multiple groups of injection windows according to an embodiment of the present invention;

[0047] Fig.11 is a schematic diagram of implanting impurities of a second conductivity type into an implantation window according to an embodiment of the present invention;

[0048] Fig.12 is a schematic diagram of forming a main junction region and a plurality of lateral variable doping regions arranged along a first direction according to an embodiment of the present invention;

[0049] Fig.13 is a schematic diagram of forming a dielectric layer and a metal anode according to an embodiment of the present invention;

[0050] Reference numerals:

[0051] Vehicle 100;

[0052] Power module 110;

[0053] Semiconductor device 111;

[0054] Terminal structure 1; Active region 2;

[0055] Substrate 10 ; main junction region 20 ; lateral variable doping region 30 ; dielectric layer 40 ; first floating field plate 50 ; second floating field plate 60 ; metal anode 70 ; metal cathode 80 . DETAILED DESCRIPTION

[0056] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0057] Reference below Figure 1 A terminal structure of a semiconductor device according to an embodiment of the present invention is described.

[0058] Figure 1 Schematic diagram of a terminal structure of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the terminal structure 1 of the semiconductor device includes: a substrate 10 of a first conductivity type, a main junction region 20 of a second conductivity type, and a plurality of lateral variable doping regions 30 of the second conductivity type.

[0059] The substrate 10 is the base layer of the semiconductor device and can be made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN) or other semiconductor materials. The first conductivity type can be a specific doping type, which can be N-type (electrons are the main carriers) or P-type (holes are the main carriers). The main function of the first conductivity type substrate 10 is to provide mechanical support and electrical foundation for the entire semiconductor device.

[0060] In some embodiments, the main junction region 20 of the second conductivity type is a doped region of the opposite conductivity type to the substrate 10 of the first conductivity type. For example, if the substrate 10 is of P type, the main junction region 20 is of N type. The main function of the main junction region 20 is to form a PN junction with the substrate 10, and the PN junction can control the direction and magnitude of the current, thereby realizing functions such as rectification and switching. Therefore, the main junction region 20 is the core functional region of the semiconductor device, which affects the distribution of current and electric field.

[0061] In some embodiments, the main junction region 20 is formed in the substrate 10 and close to the upper surface of the substrate 10, so that it can easily form an ohmic contact with the metal in the subsequent process. The ohmic contact between the metal and the semiconductor can ensure good current conduction, reduce contact resistance, and improve the overall performance of the device. Since the main junction region 20 is close to the upper surface of the substrate 10, it is more convenient to make electrical connections in the integrated circuit, reduce manufacturing complexity, and improve process consistency.

[0062] In addition, the presence of the main junction region 20 enables the current to be effectively controlled at the PN junction, thereby improving the switching speed of the device. The main junction region 20 is close to the upper surface of the substrate 10, which means that the transmission path of the carrier (electron or hole) from the main junction region 20 to the contact point is shorter, thereby reducing the transmission delay and further improving the response speed of the device.

[0063] In some embodiments, the plurality of lateral variable doping regions 30 of the second conductivity type may be doping regions of the opposite conductivity type to the substrate 10. The plurality of lateral variable doping regions 30 are all formed in the substrate 10 to ensure good electrical contact with the main junction region 20 and the substrate 10. The plurality of lateral variable doping regions 30 are located on one side of the edge of the main junction region 20 close to the terminal structure 1, and the plurality of lateral variable doping regions 30 and the main junction region 20 are arranged along the first direction. The lateral variable doping region 30 closest to the main junction region 20 among the plurality of lateral variable doping regions 30 is connected to the main junction region 20 to form a continuous electrical connection to ensure a smooth transition of the electric field and the current. Two adjacent lateral variable doping regions 30 are connected to each other to form a series of continuous transition regions. This connection method ensures a smooth transition of the electric field distribution and reduces the electric field concentration phenomenon.

[0064] In some embodiments, the impurity concentration distribution of the lateral variable doping region 30 is different from the existing linear distribution or square root distribution, such as Figure 2 As shown, from left to right, the impurity concentration changes of the main junction region 20 and the impurity concentration changes of the three groups of lateral variable doping regions 30 are respectively shown. Among them, the impurity concentration changes inside the three groups of lateral variable doping regions 30 fluctuate slightly, the impurity concentration changes between the lateral variable doping regions 30 fluctuate greatly, and the impurity concentration at the connection of the lateral variable doping regions 30 in the first direction is less than the impurity concentration inside the lateral variable doping regions 30. This design ensures the gradual transition of the impurity concentration between the lateral variable doping regions 30, thereby reducing the gradient of the electric field, further smoothing the electric field distribution, and reducing the impact of the charge dose change on the withstand voltage performance.

[0065] Figure 3 FIG. 4 is a graph showing the relationship between the charge injection dose and the withstand voltage value according to the prior art and the present invention according to an embodiment of the present invention. Figure 3 As shown, the dotted line represents the relationship curve between the charge injection dose and the withstand voltage of the terminal structure in the prior art, and the solid line represents the relationship curve between the charge injection dose and the withstand voltage of the terminal structure 1 of the present invention.

[0066] Among them, the withstand voltage value of the terminal structure of the prior art is significantly affected by the change of charge injection dose, and only in the dose range of 1E12~4E12cm -2 When the withstand voltage is above 1200V, the dose range is narrower when the withstand voltage is greater than 1400V, only between 2.2E12 and 3.4E12cm -2 The withstand voltage of the terminal structure 1 of the present invention is relatively less affected by the change of charge injection dose, and in the dose range of 2E12~1E13cm -2 The dose range for withstand voltage values ​​above 1200V and greater than 1400V is 3.6E12~9.2E12cm -2 By comparison, it can be seen that the terminal structure 1 of the present invention can maintain a high withstand voltage level within a wider range of implantation doses, thereby reducing the adverse effects of charge dose changes on the withstand voltage of the terminal structure 1 .

[0067] According to the terminal structure 1 of the semiconductor device of the embodiment of the present invention, a group-designed lateral variable doping region 30 is adopted, and the impurity concentration at the connection in the first direction is less than the impurity concentration inside the lateral variable doping region 30. This means that the impurity concentration at the connection of the lateral variable doping region 30 is low, so that the electric field distribution is more uniform. That is, when the charge dose changes, the electric field distribution in the low-concentration area is more gentle, which effectively reduces the concentration of the electric field between the lateral variable doping regions 30. This arrangement and connection method ensures that the impurity concentration between adjacent lateral variable doping regions 30 gradually transitions, reducing the electric field gradient at the connection in the first direction. Therefore, the entire terminal structure 1 can maintain a high withstand voltage level within a wider range of injection doses. This design not only increases the overall withstand voltage capability of the device, but also reduces the sensitivity to changes in doping concentration. That is, the adverse effect of charge dose changes on the withstand voltage of the terminal structure 1 is reduced, thereby improving the stability and reliability of the device.

[0068] In some embodiments, the impurity concentration distribution along the first direction inside at least one lateral variable doping region 30 is the same or different. Among them, at least one lateral variable doping region 30 may include one, two, more or even all, without specific limitation here. Even if the impurity concentration distribution is different, the amplitude of the change is relatively small to avoid the electric field concentration phenomenon, ensure that the electric field distribution is relatively uniform, and reduce the device performance fluctuation caused by the change of impurity gradient. In order to ensure that the impurity concentration fluctuation between the lateral variable doping regions 30 is small, the impurity concentration change inside the lateral variable doping region 30 can be made more gentle and controllable by accurately controlling the ion implantation process or optimizing the diffusion process.

[0069] In some embodiments, the impurity concentration distribution along the first direction inside at least one lateral variable doping region has multiple concentration peaks or at least one concentration valley. Among them, the concentration peak can be a point or region where the impurity concentration reaches a relative maximum value at a certain position. By setting multiple concentration peaks inside the lateral variable doping region, a local electric field enhancement region can be formed, thereby affecting the overall distribution of the electric field and the withstand voltage characteristics of the device. The concentration peak can be a point or region with a relatively low impurity concentration at a certain position. The existence of a concentration valley can reduce the concentration of the local electric field and avoid unstable device performance or local breakdown caused by excessive concentration of the electric field.

[0070] Therefore, by setting multiple concentration peaks or at least one concentration valley inside the lateral variable doping region, the distribution of the electric field can be controlled more accurately. Especially in the terminal area of ​​the semiconductor device, this design can effectively reduce the concentration of the electric field, thereby improving the voltage resistance of the device. By optimizing the distribution of impurity concentration and avoiding the formation of excessively high electric fields in certain areas, the risk of device breakdown under high voltage conditions can be reduced, and the long-term stability and reliability of the device can be enhanced.

[0071] like Figure 1 As shown, the terminal structure 1 further includes a dielectric layer 40, which may be an insulating layer for isolating and protecting devices and may be made of a variety of materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4), and the like.

[0072] In some embodiments, the dielectric layer 40 is located on the substrate 10 in a second direction perpendicular to the first direction, which can effectively isolate different conductive regions, prevent unnecessary electrical interference, and improve the electrical performance and reliability of the device. In addition, the dielectric layer 40 can also protect the substrate 10 and the doped region from the influence of the external environment, such as humidity, oxidation and mechanical damage, thereby extending the life of the semiconductor device.

[0073] Figure 4 Schematic diagram of a terminal structure of a semiconductor device according to another embodiment of the present invention. Figure 4 As shown, the terminal structure 1 also includes a first floating field plate 50 and a second floating field plate 60. The floating field plate is a conductive layer that is not connected to a fixed potential. It is suspended above the potential, which can change and optimize the electric field distribution in the device, reduce the electric field concentration phenomenon, and further reduce the impact of the charge dose change on the withstand voltage of the terminal structure 1, thereby improving the withstand voltage stability.

[0074] In some embodiments, the first floating field plate 50 is located on the dielectric layer 40 in the second direction and is disposed corresponding to the connection between two adjacent lateral variable doping regions 30. The first floating field plate 50 at such a specific position is designed to optimize the electric field distribution at the connection to the maximum extent, prevent excessive electric field concentration in this area, and enhance the withstand voltage performance.

[0075] In some embodiments, the second floating field plate 60 is located on the dielectric layer 40 in the second direction and corresponds to the edge lateral variable doping region 30 closest to the edge of the terminal structure 1 among the multiple lateral variable doping regions 30, and the second floating field plate 60 is located above the end of the edge lateral variable doping region 30 close to the edge of the terminal structure 1. The second floating field plate 60 can further optimize the electric field distribution in the region, reduce the edge electric field concentration, reduce the risk of edge breakdown, and thus improve the edge withstand voltage capability. In addition, the second floating field plate 60 also alleviates the stress caused by the electric field concentration in the edge region, and improves the mechanical stability of the edge of the terminal structure 1.

[0076] In some embodiments, the first floating field plate 50 and the second floating field plate 60 may be made of metal materials, such as aluminum, copper, etc., or polysilicon, etc. These materials have good conductivity and stability and can effectively adjust the electric field.

[0077] like Figure 1 and Figure 4As shown, the terminal structure 1 further includes a metal anode 70. The metal anode 70 is a conductive material that can be used as an electrode in an electronic device for electric field control and current guidance. The metal anode 70 provides an interface for connecting to an external circuit to ensure that current can be effectively transmitted.

[0078] In some embodiments, the metal anode 70 can be made of a highly conductive metal material such as aluminum, copper, gold, etc., or a metal alloy whose main component is aluminum, or multiple layers of metals of different materials, such as a titanium aluminum gold composite metal layer.

[0079] In some embodiments, the metal anode 70 is located above the main junction region 20 in the second direction and connected to the main junction region 20. The connection between the metal anode 70 and the main junction region 20 can adopt standard semiconductor manufacturing processes, such as photolithography, sputtering and deposition. By accurately controlling the position and shape of the metal anode 70, a good electrical connection with the main junction region 20 can be ensured, and the electrical performance of the device can be improved. The metal anode 70 extends along the first direction to the upper side of the dielectric layer 40 near the main junction region 20, provides a flow path for the current, and participates in the regulation and control of the electric field distribution.

[0080] like Figure 1 and Figure 4 As shown, the terminal structure 1 also includes a metal cathode 80, which is also a conductive material and can be used as an electrode in an electronic device for grounding or providing a current conduction path. The metal cathode 80 also provides an interface for connecting to an external circuit to ensure efficient current transmission and improve the conductivity of the device.

[0081] In some embodiments, the metal cathode 80 can be designed with multiple layers of different materials, such as a titanium-nickel-silver composite metal layer. Among them, the titanium layer can be used as the bottom layer, directly in contact with the substrate 10. Titanium has good adhesion and can form a strong bond with the substrate 10, thereby improving the adhesion between the metal layer and the substrate 10. The nickel layer can be located on the titanium layer. Nickel has good electrical conductivity and corrosion resistance, can protect the titanium layer, and provide a good diffusion barrier for the upper silver layer. The silver layer can be used as the top layer. Silver has excellent electrical conductivity and low resistivity, can effectively conduct current and reduce power loss.

[0082] Therefore, the design of the metal cathode 80 with multiple layers of different materials, through the combination of titanium, nickel and silver, not only enhances the adhesion between the metal cathode 80 and the substrate 10 and prevents metal diffusion, but also greatly improves the current conduction efficiency and the overall performance of the device.

[0083] In some embodiments, the metal cathode 80 is located on the lower surface of the substrate 10 in the second direction, and the connection between the metal cathode 80 and the substrate 10 can be made using standard semiconductor manufacturing processes, such as sputtering, evaporation, and electroplating. By precisely controlling the position and shape of the metal cathode 80, a good electrical connection with the substrate 10 can be ensured, thereby improving the electrical performance of the device.

[0084] Reference below Figure 5 A semiconductor device according to an embodiment of the present invention is described.

[0085] Figure 5 is a block diagram of a semiconductor device according to an embodiment of the present invention, Figure 5 As shown, the semiconductor device 111 includes an active region 2 and a terminal structure 1 of the semiconductor device 111 described in the above embodiment.

[0086] Among them, the active area 2 is the area in the semiconductor device 111 where the main electronic activities are carried out and the device functions are realized. The active area 2 may include a PN junction, a channel of a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), a base region of an IGBT (Insulated Gate Bipolar Transistor), etc. This area determines the basic electrical properties of the semiconductor device 111, such as on-current, threshold voltage, and switching speed.

[0087] In some embodiments, the terminal structure 1 is a structure located outside the active area 2, that is, the terminal structure 1 surrounds the active area 2, and is used to control the electric field distribution, protect the active area 2, improve the voltage resistance and stability of the device, prevent the device from breaking down under high voltage, and ensure the reliable operation of the device under high voltage and high power conditions.

[0088] According to the semiconductor device 111 of the embodiment of the present invention, by adopting the terminal structure 1 of the semiconductor device 111 described in the above embodiment, the terminal structure 1 surrounds the active area 2 and effectively integrates the active area 2 with the terminal structure 1. By adopting the lateral variable doping region 30 designed in groups, the impurity concentration at the connection in the first direction is less than the impurity concentration inside the lateral variable doping region 30. This means that the impurity concentration at the connection of the lateral variable doping region 30 is low, so that the electric field distribution is more uniform. That is, when the charge dose changes, the electric field distribution in the low concentration area is more gentle, which effectively reduces the concentration of the electric field between the lateral variable doping regions 30. This arrangement and connection method ensures that the impurity concentration between adjacent lateral variable doping regions 30 gradually transitions, reducing the electric field gradient at the connection in the first direction. Therefore, the entire terminal structure 1 can maintain a high withstand voltage level within a wider range of injection doses. This design not only increases the overall withstand voltage capability of the device, but also reduces the sensitivity to changes in doping concentration. That is, the adverse effect of charge dose changes on the withstand voltage of the terminal structure 1 is reduced, thereby improving the stability and reliability of the device.

[0089] Reference below Figure 6 A power module according to an embodiment of the present invention is described.

[0090] Figure 6 is a block diagram of a power module according to an embodiment of the present invention, such as Figure 6 As shown, the power module 110 includes at least one semiconductor device 111 as described in the above embodiments.

[0091] The at least one semiconductor device 111 may be one semiconductor device 111, two semiconductor devices 111, three semiconductor devices 111, five semiconductor devices 111, ten semiconductor devices 111 or more semiconductor devices 111. The number of semiconductor devices 111 in the power module 110 may be set according to power requirements, voltage and current requirements, redundancy design, circuit topology, size and cost, and is not specifically limited herein.

[0092] In some embodiments, the power module 110 can be used to efficiently convert and control electrical energy, for example, direct current to alternating current (DC-AC), alternating current to direct current (AC-DC), direct current to direct current (DC-DC), or alternating current to alternating current (AC-AC). The power module 110 also has a voltage stabilization or voltage regulation function to ensure that the output voltage is stable and adaptable to different load requirements. The power module 110 can also provide over-current, over-voltage, over-heating and other protections to ensure safe operation of the system.

[0093] In some embodiments, the power module 110 can play a key role in various power electronic applications, such as electric vehicles, power conversion systems, industrial motor drives, etc. It can provide efficient and reliable power control and conversion.

[0094] According to the power module 110 of the embodiment of the present invention, by adopting at least one semiconductor device 111 as described in the above embodiment, the adverse effect of the charge dose variation on the withstand voltage of the terminal structure 1 can be reduced, so that the entire terminal structure 1 can maintain a high withstand voltage level within a wider injection dose range, thereby increasing the overall withstand voltage capability of the device, thereby improving the stability and reliability of the device.

[0095] Reference below Figure 7 A vehicle according to an embodiment of the present invention is described.

[0096] Figure 7 is a block diagram of a vehicle according to an embodiment of the present invention, such as Figure 7 As shown, the vehicle 100 includes the power module 110 described in the above embodiment.

[0097] In some embodiments, the power module 110 in the vehicle 100 can be used to manage and control the conversion, regulation and distribution of electrical energy. Specific functions include, but are not limited to: motor drive, battery management, auxiliary power supply, converter and inverter. Through the optimized design of the power module 110, the vehicle 100 can achieve higher energy conversion efficiency, reduce energy loss, and extend battery life. The power module 110 has a built-in protection function to ensure that the circuit can respond and cut off the power supply in time under abnormal circumstances to protect the safety of the vehicle 100 and passengers. The power module 110 can adopt multiple semiconductor devices 111 and redundant design to enhance the reliability of the system, and can still ensure the basic functions of the vehicle 100 even in the event of failure of certain devices. The design of the power module 110 can also take into account the diversity of the operating environment of the vehicle 100, such as factors such as temperature, humidity and vibration, and has good environmental adaptability.

[0098] In some embodiments, the vehicle 100 may be any type of automobile, including but not limited to passenger cars or commercial vehicles such as cars, buses, trucks, and vans.

[0099] According to the vehicle 100 of the embodiment of the present invention, by adopting the power module 110 described in the above embodiment, the adverse effect of the charge dose change on the withstand voltage of the terminal structure 1 can be reduced, so that the entire terminal structure 1 can maintain a high withstand voltage level within a wider injection dose range, thereby increasing the overall withstand voltage capability of the device, thereby improving the stability and reliability of the device.

[0100] Reference below Figure 8 A method for preparing a terminal structure of a semiconductor device according to an embodiment of the present invention is described.

[0101] Figure 8 1 is a flow chart of a method for preparing a terminal structure of a semiconductor device according to an embodiment of the present invention. The method for preparing a terminal structure of a semiconductor device at least includes steps S1-S3, which are specifically as follows:

[0102] S1, providing a substrate of a first conductivity type.

[0103] Among them, when preparing the terminal structure of the semiconductor device, a substrate with a first conductivity type can be provided first. The substrate can be the base layer of the semiconductor device, and its type can be N-type or P-type, depending on the needs of the device design. The substrate plays the role of support and basic conductive function in the semiconductor device. It not only provides physical support, but also plays an important role as a conductive path during current transmission and device operation.

[0104] S2, forming an implantation blocking layer on the upper surface of the substrate.

[0105] In some embodiments, the injection barrier layer can be made of materials such as silicon dioxide (SiO2) or silicon nitride (Si3N4). The main function of the injection barrier layer is to limit the diffusion range of impurities and ensure that impurities are only injected into predetermined areas, thereby precisely controlling the electrical properties and structure of the device.

[0106] S3, forming a plurality of groups of injection windows along a first direction on the injection blocking layer, wherein a distance between two adjacent groups of injection windows is greater than a distance between injection windows within a group.

[0107] In some embodiments, the plurality of groups of injection windows are openings or holes formed by etching the injection barrier layer, and are used to introduce impurities of the second conductivity type into the substrate. The spacing between the two groups of injection windows is greater than the spacing between the injection windows within the group. This arrangement design helps to control the diffusion area of ​​the impurities and form a specific lateral variable doping area.

[0108] S4, implanting impurities of the second conductivity type into the implantation windows to form implantation regions spaced apart and arranged along the first direction in the substrate.

[0109] The purpose of forming the implanted region is to change the electrical properties of a portion of the substrate region, for example, from N-type to P-type or vice versa, to meet the functional and performance requirements of the device.

[0110] S5, removing the barrier layer and performing diffusion and push-up of impurities of the second conductivity type to form a main junction region and a plurality of lateral variable doping regions arranged along the first direction in the substrate.

[0111] Among the multiple lateral variable doping regions, the lateral variable doping region closest to the main junction region is connected to the main junction region, and two adjacent lateral variable doping regions are connected to each other, and the impurity concentration at the connection of the lateral variable doping regions in the first direction is less than the impurity concentration inside the lateral variable doping regions. This design ensures a gradual transition of the impurity concentration between the lateral variable doping regions, thereby reducing the gradient of the electric field, further smoothing the electric field distribution, and reducing the impact of the charge dose change on the withstand voltage performance.

[0112] In some embodiments, the barrier layer can be removed by chemical etching, physical etching, mechanical grinding or polishing, laser lift-off, etc. The second conductivity type impurities can be diffused by high temperature treatment so that the impurities can diffuse to the required depth and concentration in the substrate.

[0113] According to the method for preparing the terminal structure of the semiconductor device of the embodiment of the present invention, by forming an injection barrier layer on the upper surface of the substrate, and forming multiple groups of injection windows along the first direction on the injection barrier layer, the interval between the two groups of injection windows is greater than the interval between the injection windows in the group, the injection position and concentration distribution of the impurities can be accurately controlled. After the second conductivity type impurities are injected into the injection window, the injection barrier layer is removed and the second conductivity type impurities are diffused and pushed to form a main junction area and multiple lateral variable doping areas. Through this design, the impurity concentration of the lateral variable doping area is relatively low in the transition area between groups, and the concentration is high in the group. This concentration distribution design ensures that the electric field is more evenly distributed between the lateral variable doping areas, reducing the electric field inhomogeneity caused by the drastic change of local doping concentration. When the charge dose changes, the electric field distribution in the low concentration area is more gentle, effectively reducing the electric field concentration phenomenon between the lateral variable doping areas. Therefore, this preparation method ensures that the impurity concentration between adjacent lateral variable doping areas is gradually transitioned, reduces the electric field gradient at the connection in the first direction, and enables the entire terminal structure to maintain a higher withstand voltage level within a wider range of injection doses. This design not only increases the overall withstand voltage capability of the device, but also reduces the sensitivity to changes in doping concentration and the adverse effects of charge dose changes on the withstand voltage of the terminal structure, thereby improving the stability and reliability of the device.

[0114] In some embodiments, the impurity concentration N1 at the connection of the lateral variable doping region satisfies: 1E 13 cm -3 ≤N1≤1E 16 cm -3 The impurity concentration N2 inside the lateral variable doping region satisfies: 1E 14 cm -3 ≤N1≤1E 17 cm -3The impurity concentration at the connection of the lateral variable doping region is lower than the impurity concentration inside the lateral variable doping region. For example, the impurity concentration N1 at the connection is 1E 13 cm -3 , the impurity concentration inside the lateral variable doping region is N2 = 1E 14 cm -3 ; Or, the impurity concentration at the connection is N1 = 1E 14 cm -3 , the impurity concentration inside the lateral variable doping region is N2 = 1E 15 cm -3 ; Or, the impurity concentration at the connection is N1 = 1E 15 cm -3 , the impurity concentration inside the lateral variable doping region is N2 = 1E 16 cm -3 ; Or, the impurity concentration at the connection is N1 = 1E 16 cm -3 , the impurity concentration inside the lateral variable doping region is N2 = 1E 17 cm -3 ; Or, the impurity concentration at the connection is N1 = 5E 14 cm -3 , the impurity concentration inside the lateral variable doping region is N2 = 1E 16 cm -3 ; Or, the impurity concentration at the connection is N1 = 8E 13 cm -3 , the impurity concentration inside the lateral variable doping region is N2 = 1E 15 cm -3 .

[0115] Different from the prior art in which the impurity concentration of the lateral variable doping region along the first direction is linearly distributed or square root distributed, in the embodiment of the present application, the impurity concentration at the connection of the lateral variable doping region is less than the impurity concentration inside the lateral variable doping region, and the voltage resistance level of the device can be guaranteed within a wider range of impurity concentration changes, thereby reducing the sensitivity of the device's voltage resistance performance to charge changes.

[0116] In some embodiments, the interval S between two adjacent groups of injection windows is 间隔1 The value of satisfies: 2μm≤S 间隔1 ≤15μm, for example, S 间隔1 =2μm or 5μm or 8μm or 12μm or 15μm.

[0117] In some embodiments, the interval S between injection windows in a group 间隔2 The value of satisfies: 0.5μm≤S 间隔2 ≤5μm, for example, S 间隔2=0.5μm or 1μm or 3μm or 5μm.

[0118] In some embodiments, the width T of the injection window along the first direction satisfies: 0.5 μm≤T≤5 μm, for example, T=0.5 μm or 1 μm or 3 μm or 5 μm.

[0119] In general, by precisely defining the spacing and width of the injection window, the operability of the method for preparing the terminal structure of the semiconductor device in the actual process is ensured, and it helps to improve the voltage resistance and reliability of the device. The design of these parameters is the key to achieving a high-performance terminal structure. By reasonably selecting the parameters, the feasibility of the manufacturing process can be taken into account while ensuring the electrical performance of the device.

[0120] In some embodiments, the method for preparing the terminal structure of the semiconductor device further includes: forming a dielectric layer on the upper surface of the substrate. The dielectric layer is an electrical insulating material used to isolate and protect the device structure below to prevent electrical short circuit or leakage. The dielectric layer can also provide mechanical support and structural stability to protect the main junction region and the lateral doping region from being affected or damaged by the external environment.

[0121] In some embodiments, the dielectric layer can be formed on the substrate by chemical vapor deposition (CVD), physical vapor deposition (PVD) or sputtering to ensure its uniformity and thickness control to ensure good insulation performance and device reliability.

[0122] In some embodiments, the method for preparing the terminal structure of the semiconductor device further includes: preparing a metal anode on the substrate corresponding to the main junction region, and the metal anode extends along the first direction to the upper side of one end of the dielectric layer close to the main junction region.

[0123] Among them, the metal anode is used to connect the device to the external circuit to transmit current and signals. The metal anode has good electrical conductivity, ensuring fast transmission of electrical signals and low resistance. The metal anode should have good stability under high temperature and high electric field conditions to ensure long-term reliable operation of the device.

[0124] In some embodiments, the metal anode can be prepared on the dielectric layer by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, etc., to ensure uniformity and precise position control of the metal electrode.

[0125] In some embodiments, the method for preparing the terminal structure of the semiconductor device further includes: preparing a first floating field plate at the connection of the corresponding lateral variable doping region on the dielectric layer. The first floating field plate can help adjust and control the electric field distribution at the connection of the lateral variable doping region. This is very helpful for reducing the electric field gradient, reducing the breakdown risk, and improving the voltage resistance of the device.

[0126] In some embodiments, the first floating field plate can be prepared on the dielectric layer by physical vapor deposition (PVD), chemical vapor deposition (CVD) or sputtering. During the preparation process, the thickness and uniformity of the first floating field plate need to be controlled to ensure good electrical and mechanical properties.

[0127] In some embodiments, the method for preparing the terminal structure of the semiconductor device further includes: preparing a second floating field plate in an edge lateral variable doping region corresponding to the edge of the terminal structure in the plurality of lateral variable doping regions on the dielectric layer, the second floating field plate being located above the end of the edge lateral variable doping region close to the edge of the terminal structure. The second floating field plate can help optimize the electric field distribution in these regions, reduce the electric field concentration phenomenon, and further reduce the impact of the charge dose change on the withstand voltage of the terminal structure, thereby improving the withstand voltage capability and stability of the device.

[0128] In some embodiments, the second floating field plate can also be prepared by physical vapor deposition (PVD), chemical vapor deposition (CVD) or sputtering, etc. During the preparation process, the thickness and uniformity of the second floating field plate need to be controlled to ensure good electrical and mechanical properties.

[0129] In some embodiments, the method for preparing the terminal structure of the semiconductor device further includes: preparing a metal cathode on the lower surface of the substrate. The metal cathode serves as an electrical connection point of the device and can be connected to a power supply or a ground line in other electronic circuits to ensure the correct function and operation of the circuit.

[0130] In some embodiments, during the preparation process, a metal cathode can be formed on the lower surface of the substrate by a metallization process. These processes can not only ensure good contact between the metal cathode and the substrate, but also improve its corrosion resistance and conductivity. According to the specific semiconductor device design requirements and application scenarios, the size, thickness and shape of the metal cathode can be optimized to maximize its grounding effect and electrical performance.

[0131] As Figure 1 Taking the terminal structure of the semiconductor device shown in FIG. 1 as an example, the following reference Figure 9-13 The process flow of the terminal structure of the semiconductor device according to the embodiment of the present invention is described. The process flow of the terminal structure of the semiconductor device may include the following steps:

[0132] First, Fig. 9As shown, a substrate of a first conductivity type is provided, and the doping concentration of the substrate is 1E13-1E16cm -3 The higher the required withstand voltage, the lower the doping concentration of the substrate, the fewer carriers, and the higher the blocking property.

[0133] Second, if Fig.10 As shown, an injection barrier layer is formed on the upper surface of the substrate, and part of the injection barrier layer is removed by photolithography to form multiple groups of injection windows. The size T of the injection window, such as w11, w12, w13, w21, w22, w23, w31, w32, and w33 in the figure, can be between 0.5 μm and 5 μm. The spacing between the injection windows in the group, i.e., S 间隔2 For example, s11, s12, s21, s22, s31, and s32 in the figure can be between 0.5 μm and 5 μm. 间隔1 For example, s1, s2, and s3 in the figure can be between 2μm and 15μm. The intervals s11, s12, s21, s22, s31, and s32 between the injection windows in a group are smaller than the intervals s2 and s3 between the injection windows between groups. Therefore, by setting a smaller injection window interval within a group and a larger injection window interval between groups, and through subsequent injection and push-in processes, the following can be obtained: Figure 2 The lateral impurity distribution shown has small fluctuations in impurity concentration within a group and large changes in impurity concentration in the transition region between groups.

[0134] Third, if Fig.11 As shown, the second conductivity type impurities are injected into the injection window to form injection regions arranged along the first direction in the substrate. The injection dose is 1E12-5E13cm -2 between.

[0135] Fourth, if Fig.12 As shown, the injection barrier layer is removed, and the second conductive type impurities are diffused and pushed in a high temperature environment to form an uninterrupted area in the terminal area, that is, a main junction area and multiple lateral variable doping areas arranged along the first direction are formed in the substrate. The diffusion temperature can be set between 1000°C and 1200°C, and the main diffusion time is between 30 and 360 minutes. At this point, a lateral impurity distribution is formed in which the impurity concentration change fluctuation inside the lateral variable doping area is small, the impurity concentration change fluctuation between the lateral variable doping area and the lateral variable doping area is large, and the impurity concentration at the connection of the lateral variable doping area in the first direction is less than the impurity concentration inside the lateral variable doping area.

[0136] Fifth, if Fig.13As shown, a dielectric layer is formed on the upper surface of the substrate, a portion of the dielectric layer is removed above the main junction region by photolithography technology, and then a metal anode is formed thereon, and a portion of the anode metal is removed by photolithography technology. The remaining anode metal only covers a portion of the main junction region and the lateral variable doping region.

[0137] Sixth, a metal cathode is prepared on the lower surface of the substrate, and the resulting structure is as follows Figure 1 shown.

[0138] In some embodiments, Figure 4 The process flow of the terminal structure of the semiconductor device is similar to the above Figure 1 The process flow of the terminal structure of the semiconductor device is similar to that of the present invention, except that the preparation of the first floating field plate and the second floating field plate is added. The specific process will not be described in detail here.

[0139] In general, by preparing Figure 1 and Figure 4 The terminal structure of the semiconductor device can reduce the adverse effect of charge dose variation on the withstand voltage of the terminal structure, so that the entire terminal structure can maintain a high withstand voltage level within a wider range of injection doses, thereby increasing the overall withstand voltage capability of the device and thus improving the stability and reliability of the device.

[0140] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0141] In the description of the present invention, "plurality" means two or more.

[0142] In the description of the present invention, a first feature being “on” or “under” a second feature may include that the first and second features are directly in contact with each other, or may include that the first and second features are not in direct contact with each other but are in contact with each other via another feature therebetween.

[0143] In the description of the present invention, "above", "over" and "on" a first feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature.

[0144] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0145] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A terminal structure of a semiconductor device, characterized in that: include: a substrate of a first conductivity type; A main junction region of a second conductivity type, the main junction region being formed in the substrate and close to an upper surface of the substrate; A plurality of lateral variable doping regions of the second conductivity type, wherein the plurality of lateral variable doping regions are all formed in the substrate, the plurality of lateral variable doping regions are located on a side of the edge of the main junction region close to the terminal structure, the plurality of lateral variable doping regions and the main junction region are arranged along a first direction, the lateral variable doping region closest to the main junction region among the plurality of lateral variable doping regions is connected to the main junction region, two adjacent lateral variable doping regions are connected to each other, and the impurity concentration at the connection of the lateral variable doping regions in the first direction is less than the impurity concentration inside the lateral variable doping regions.

2. The terminal structure according to claim 1, characterized in that: The impurity concentration distribution inside at least one of the lateral variable doping regions along the first direction is the same or different.

3. The terminal structure according to claim 2, characterized in that: The impurity concentration distribution inside at least one of the lateral variable doping regions along the first direction includes a plurality of concentration peaks or at least one concentration valley.

4. The terminal structure according to claim 1, characterized in that: The terminal structure also includes: A dielectric layer is located on the substrate in a second direction perpendicular to the first direction.

5. The terminal structure according to claim 4, characterized in that: The terminal structure also includes: A first floating field plate is located on the dielectric layer in the second direction and is arranged corresponding to a connection between two adjacent lateral variable doping regions.

6. The terminal structure according to claim 5, characterized in that: The terminal structure also includes: A second floating field plate, the second floating field plate is located on the dielectric layer in the second direction and is arranged corresponding to an edge lateral variable doping region of the plurality of lateral variable doping regions closest to the edge of the terminal structure, the second floating field plate is located above an end portion of the edge lateral variable doping region close to the edge of the terminal structure.

7. The terminal structure (1) according to claim 4, characterized in that: The terminal structure also includes: A metal anode is located above the main junction region in the second direction and connected to the main junction region, and the metal anode extends along the first direction to an upper side of an end of the dielectric layer close to the main junction region.

8. The terminal structure according to claim 1, characterized in that: The terminal structure also includes: A metal cathode is located on the lower surface of the substrate in the second direction.

9. A semiconductor device, characterized in that: A semiconductor device comprising an active region and a terminal structure as claimed in any one of claims 1 to 8, wherein the terminal structure surrounds the active region.

10. A power module, characterized in that: Comprising at least one semiconductor device as claimed in claim 9.

11. A vehicle, characterized in that: Comprising the power module as claimed in claim 10.

12. A method for preparing a terminal structure of a semiconductor device, characterized in that: include: providing a substrate of a first conductivity type; forming an implantation blocking layer on the upper surface of the substrate; forming a plurality of groups of injection windows along a first direction on the injection blocking layer, wherein the interval between two adjacent groups of the injection windows is greater than the interval between the injection windows in the same group; Implanting impurities of a second conductivity type into the implantation window to form implantation regions spaced apart and arranged along the first direction in the substrate; The barrier layer is removed and the impurities of the second conductivity type are diffused and pushed to form a main junction region and a plurality of lateral variable doping regions arranged along the first direction in the substrate, wherein the lateral variable doping region closest to the main junction region among the plurality of lateral variable doping regions is connected to the main junction region, and two adjacent lateral variable doping regions are connected to each other, and the impurity concentration at the connection of the lateral variable doping regions in the first direction is less than the impurity concentration inside the lateral variable doping region.

13. The preparation method according to claim 12, characterized in that: The impurity concentration N1 at the connection of the lateral variable doping region satisfies: 1E 13 cm -3 ≤N1≤1E 16 cm -3 .

14. The preparation method according to claim 13, characterized in that: The impurity concentration N2 inside the lateral variable doping region satisfies: 1E 14 cm -3 ≤N1≤1E 17 cm -3 .

15. The preparation method according to claim 12, characterized in that: The interval S between two adjacent groups of injection windows 间隔1 Satisfy: 2μm≤S 间隔1 ≤15μm.

16. The preparation method according to claim 15, characterized in that: The interval S between the injection windows in a group 间隔2 Satisfy: 0.5μm≤S 间隔2 ≤5μm.

17. The preparation method according to any one of claims 12 to 16, characterized in that: A value of a width T of the injection window along the first direction satisfies: 0.5 μm≤T≤5 μm.

18. The preparation method according to claim 12, characterized in that: The preparation method further comprises: forming a dielectric layer on the upper surface of the substrate; A metal anode is prepared on the substrate corresponding to the main junction region, and the metal anode extends along the first direction to the upper side of one end of the dielectric layer close to the main junction region.

19. The preparation method according to claim 18, characterized in that: The preparation method further comprises: A first floating field plate is prepared at a connection position on the dielectric layer corresponding to the lateral variable doping region.

20. The preparation method according to claim 19, characterized in that: The preparation method further comprises: A second floating field plate is prepared on the dielectric layer corresponding to an edge lateral doping region closest to the edge of the terminal structure among the multiple lateral doping regions, and the second floating field plate is located above the end of the edge lateral doping region close to the edge of the terminal structure.

21. The preparation method according to claim 12, characterized in that: The preparation method further comprises: A metal cathode is prepared on the lower surface of the substrate.

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