Gallium nitride and germanium monolithic heterogeneous integrated complementary inverter and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, and discloses a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter and a preparation method thereof. A silicon substrate layer is arranged on the lowermost portion of the phase inverter, and two-dimensional electron gas is formed between an N-channel transistor channel layer and an N-channel transistor barrier layer and serves as a conducting channel of an N-channel transistor. And the P-channel transistor gate electrode controls the formation of an inverted conducting channel on the upper surface of the N-type germanium well of the P-channel transistor. The gate electrode of the N-channel transistor and the gate electrode of the P-channel transistor are connected to form an input end of the complementary inverter; and the drain electrode of the N channel transistor is connected with the source electrode of the P channel transistor to form the output end of the complementary inverter. According to the inverter, silicon-based gallium nitride and germanium semiconductor monolithic heterogeneous integration is adopted, the two materials have high electron mobility and high hole mobility respectively, the working speed of an existing complementary inverter is increased, the process compatibility is high, and the inverter can be applied to high-speed large-scale digital circuits and gallium nitride radio frequency and power electronic device platforms.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter and a preparation method thereof. Background Art

[0002] The third generation semiconductor materials represented by gallium nitride (GaN) have significant advantages such as bandwidth gap (3.4eV), high electron mobility, and high electron saturation rate. Therefore, they have a wider range of application scenarios in the fields of next-generation radio frequency devices and power electronic devices. The III-nitride semiconductor heterojunction has strong spontaneous polarization and piezoelectric polarization effects, which can form a large concentration (1×10 13 cm -2 ), large mobility (2000cm 2 / V·s) of high-density two-dimensional electron gas (2DEG), which makes GaN-based transistor devices have the advantages of high breakdown voltage, low on-resistance, high switching frequency and small size, making them the preferred solution for the development of high-performance, low-power, low-cost microwave and millimeter-wave devices and their front-end circuits. In particular, it has important applications in the fields of wireless charging, laser radar, electric vehicles and intelligent transportation.

[0003] More and more practical applications require electronic systems with higher integration, smaller size, lighter weight and more functions. They need to integrate chips with various functions such as wireless transceiver, power management, drive, digital processing, etc. in the smallest possible area.

[0004] However, as a high-speed device, gallium nitride only conducts electricity through electrons, and it is difficult to form a complementary logic inverter with two types of carriers conducting electricity, which limits the application of this material in large-scale digital and analog integrated circuits. Therefore, in public reports, it is proposed to use gallium nitride and silicon to make N-channel transistors and P-channel transistors respectively to form a complementary inverter. However, both silicon and gallium nitride devices require high-temperature processes during the manufacturing process, which poses a challenge to the design of a compatible manufacturing process for a complementary inverter that is heterogeneously integrated with gallium nitride and silicon on a single chip.

[0005] On the other hand, germanium PMOS has superior performance compared to silicon PMOS. Germanium (Ge) has a higher hole mobility than silicon (Si), which means that in germanium-based PMOS, holes can move faster, thereby increasing the switching speed of the transistor. Due to the high mobility of germanium, germanium-based PMOS transistors perform better in high-frequency applications, which is very important for RF applications and high-speed digital circuits. Germanium is compatible with existing silicon-based semiconductor manufacturing processes, which makes it easier to integrate germanium into existing semiconductor production lines, reducing production costs and promoting the adoption of technology. Germanium PMOS has obvious advantages over silicon PMOS in terms of mobility, speed, compatibility, performance improvement, etc., and is especially suitable for high-frequency and high-speed applications. Summary of the invention

[0006] The present application provides a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter and a preparation method thereof to solve one or more technical problems existing in the prior art and at least provide a beneficial choice or create conditions.

[0007] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0008] According to one aspect of an embodiment of the present application, a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter is proposed, and the method comprises the following steps:

[0009] The bottom layer is a silicon substrate layer (1), and the N-channel transistor side includes an N-channel transistor nucleation layer (2), an N-channel transistor buffer layer (3), an N-channel transistor channel layer (4), an N-channel transistor barrier layer (5), an N-channel transistor gate electrode (6), an N-channel transistor source electrode (7), and an N-channel transistor drain electrode (8); the N-channel transistor nucleation layer (2), the N-channel transistor buffer layer (3), the N-channel transistor channel layer (4), and the N-channel transistor barrier layer (5) are group III nitrides. A two-dimensional electron gas is formed between an N-channel transistor channel layer (4) and an N-channel transistor barrier layer (5), serving as a conductive channel of the N-channel transistor and being controlled by an N-channel transistor gate electrode (6); a P-channel transistor side includes a P-channel transistor N-type germanium well (9), a P-channel transistor P-type germanium well (10), a P-channel transistor drain electrode (11), a P-channel transistor source electrode (12), a P-channel transistor oxide dielectric layer (13), and a P-channel transistor gate electrode (14);

[0010] The N-channel transistor source electrode (7) and the N-channel transistor drain electrode (8) both form ohmic contact with the N-channel transistor barrier layer (5);

[0011] The P-channel transistor source electrode (12) and the P-channel transistor drain electrode (11) both form ohmic contact with the P-channel transistor P-type germanium well (10); the P-channel transistor gate electrode (14) controls the formation of an inversion conductive channel on the upper surface of the P-channel transistor N-type germanium well (9);

[0012] The gate electrode (6) of the N-channel transistor is connected to the gate electrode (14) of the P-channel transistor to form the input end of the complementary inverter; the drain electrode (8) of the N-channel transistor is connected to the source electrode (12) of the P-channel transistor to form the output end of the complementary inverter; the drain electrode (11) of the P-channel transistor is connected to a bias voltage VDD; and the source electrode (7) of the N-channel transistor is grounded.

[0013] In one embodiment of the present application, based on the above-mentioned solution, the N-channel transistor is an enhancement-type device, a gate groove (61) is provided on the upper surface portion of the N-channel transistor barrier layer (5) and below the N-channel transistor gate electrode (6), and the metal of the N-channel transistor gate electrode (6) fills the groove; the enhancement-type operation of the N-channel transistor is achieved through the gate groove (61).

[0014] In one embodiment of the present application, based on the above scheme, the N-channel transistor is an enhancement-mode device, and a P-type group III nitride cap layer (62) is provided on the upper surface of the N-channel transistor barrier layer (5) and below the N-channel transistor gate electrode (6), and the enhancement-mode operation of the N-channel transistor is achieved through the action of the P-type group III nitride cap layer.

[0015] In one embodiment of the present application, based on the above scheme, the N-channel transistor is an enhancement-type device, and an F ion implantation region (63) is provided on the upper surface of the N-channel transistor barrier layer (5) and below the N-channel transistor gate electrode (6), and the enhancement-type operation of the N-channel transistor is achieved through the action of negative ions in the F ion implantation region (63).

[0016] In one embodiment of the present application, based on the above scheme, the material of the N-channel transistor nucleation layer (2) is AlN or gallium nitride, with a thickness of 50-300nm; the material of the N-channel transistor buffer layer (3) is gallium nitride or AlGaN, with a thickness of 200-1000nm; the material of the N-channel transistor barrier layer (5) includes AlGaN, InAlN, and the thickness of AlN is 3-40nm; the materials of the N-channel transistor nucleation layer (2), the N-channel transistor buffer layer (3), and the N-channel transistor barrier layer (5) are unintentionally doped.

[0017] In one embodiment of the present application, based on the above scheme, the structures of the N-channel transistor source electrode (7) and the N-channel transistor drain electrode (8) are Ti / Al and other metals, or Ta / Al and other metals, or TiN / Al and other metals from bottom to top; the N-channel transistor gate electrode (6) includes Ni and other metals, or Ti and other metals, or TiN and other metals, including P-type gallium nitride and other metals from bottom to top.

[0018] In one embodiment of the present application, based on the above scheme, the material of the N-type germanium well (9) of the P-channel transistor is germanium, which can be doped with group V elements when growing germanium, or ion implanted with group V elements after growth to achieve N-type doping.

[0019] In one embodiment of the present application, based on the above solution, the P-channel transistor source electrode (12) and the P-channel transistor source and drain (12) are P-type germanium, Al and other metals from bottom to top.

[0020] In one embodiment of the present application, based on the above solution, the P-channel transistor oxide dielectric layer (13) can be germanium oxide, silicon oxide, hafnium oxide or other oxides.

[0021] According to one aspect of an embodiment of the present application, a method for preparing a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter is provided, and the method comprises the following steps:

[0022] Step 1: cleaning pollutants on the surface of the silicon substrate layer (1);

[0023] Step 2: sequentially growing an N-channel transistor nucleation layer (2), an N-channel transistor buffer layer (3), an N-channel transistor channel layer (4), and an N-channel transistor barrier layer (5);

[0024] Step 3: preparing an N-channel transistor source electrode (7) and an N-channel transistor drain electrode (8), and performing annealing, wherein the N-channel transistor source electrode (7) and the N-channel transistor drain electrode (8) simultaneously form an ohmic contact with a two-dimensional electron gas generated near a heterojunction interface formed by the N-channel transistor channel layer (4) and the N-channel transistor barrier layer (5);

[0025] Step 4: Making an N-channel transistor gate electrode (6);

[0026] Step 5: digging a groove in the structural part obtained in step 2, growing germanium epitaxial material, and performing N-type doping on germanium during growth to obtain an N-type germanium well (9) of a P-channel transistor;

[0027] Step 6: epitaxially grow germanium oxide (13) on the structure obtained in step 3, then etch the exposed part of the oxide layer to expose the N-type germanium underneath. Use the oxide layer as a masking layer to perform ion implantation. Then perform annealing to activate the doping elements and finally obtain a P-channel transistor P-type germanium well (10);

[0028] Step 7: A P-channel transistor gate electrode (14), a P-channel transistor drain electrode (11) and a P-channel transistor source electrode (12) are fabricated on the P-channel transistor oxide dielectric layer (13).

[0029] Step 8: Metal interconnection lines are made on the structure obtained in step 7. The gate electrode (6) of the N-channel transistor is connected to the gate electrode (14) of the P-channel transistor to form the input end of the complementary inverter; the drain electrode (8) of the N-channel transistor is connected to the source electrode (12) of the P-channel transistor to form the output end of the complementary inverter; the drain electrode (11) of the P-channel transistor is connected to the bias voltage VDD; the source electrode (7) of the N-channel transistor is grounded; and the complementary inverter is realized.

[0030] Beneficial effects of this application:

[0031] (1) Realize monolithic integrated GaN and Ge complementary inverters, which constitute the smallest unit of digital integrated circuits and lay the foundation for the production of large-scale GaN and Ge heterogeneous integrated digital integrated circuits and analog integrated circuits.

[0032] (2) In the complementary inverter, the N-type transistor uses a gallium nitride-based structure, which has a high two-dimensional electron gas concentration, high mobility, and low square resistance. The gallium nitride-based channel material has a wide modern width, low inter-band tunneling probability, high on-state current and low off-state leakage at a small size; the P-type transistor uses a germanium-based semiconductor structure, which has a high mobility and a high on-state circuit of the device. The combined complementary transistor has the characteristics of fast switching speed and low power consumption;

[0033] (3) The material structure is compatible with GaN RF devices and GaN power electronic devices, and can realize multifunctional GaN RF chips and multifunctional GaN power electronic chips that integrate analog drive, power management and digital processing on a single chip;

[0034] (4) The manufacturing process temperature of germanium semiconductor devices is relatively low, and the process flow of preparing complementary inverters will not cause damage or degradation to gallium nitride materials and devices, ensuring the long-term reliability of the monolithic integrated chip.

[0035] (5) Monolithic integrated chips use silicon substrates and existing mature manufacturing processes, which is expected to significantly reduce the cost of monolithic integrated chips.

[0036] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0038] Figure 1 A schematic diagram of a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter proposed by the present invention;

[0039] Figure 2 A schematic diagram of the structure of a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter proposed in the first embodiment of the present invention;

[0040] Figure 3 A schematic diagram of the structure of a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter proposed in the second embodiment of the present invention;

[0041] Figure 4 A schematic diagram of the structure of a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter proposed in the third embodiment of the present invention;

[0042] Figure 5 A schematic diagram of a method for manufacturing a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter proposed by the present invention;

[0043] Figure 6 This is the principle diagram of the gallium nitride and germanium monolithic heterogeneous integrated complementary inverter proposed by the present invention.

[0044] Reference numerals:

[0045] Silicon substrate layer (1), N-channel transistor nucleation layer (2), N-channel transistor buffer layer (3), N-channel transistor channel layer (4), N-channel transistor barrier layer (5), N-channel transistor gate electrode (6), N-channel transistor source electrode (7), N-channel transistor drain electrode (8), P-channel transistor N-type germanium well (9), P-channel transistor P-type germanium well (10), P-channel transistor drain electrode (11), P-channel transistor source electrode (12), P-channel transistor oxide dielectric layer (13), P-channel transistor gate electrode (14), gate groove (61), P-type III-nitride cap layer (62), and F ion implantation region (63). DETAILED DESCRIPTION

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0047] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the present application.

[0048] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or micro-control node devices.

[0049] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0050] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0051] The implementation details of the technical solution of the embodiment of the present application are described in detail below:

[0052] The present invention discloses a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter and a preparation method thereof, and relates to the technical field of semiconductor devices. The bottom of the inverter is a silicon substrate layer, and a two-dimensional electron gas is formed between the channel layer of the N-channel transistor and the barrier layer of the N-channel transistor, which serves as a conductive channel of the N-channel transistor; the gate electrode of the P-channel transistor controls the formation of an inversion conductive channel on the upper surface of the N-type germanium well of the P-channel transistor. The gate electrode of the N-channel transistor and the gate electrode of the P-channel transistor are connected to form the input end of the complementary inverter; the drain electrode of the N-channel transistor and the source electrode of the P-channel transistor are connected to form the output end of the complementary inverter; the drain electrode of the P-channel transistor is connected to the bias voltage VDD; and the source electrode of the N-channel transistor is grounded. The preparation method mainly includes epitaxially growing various structures of an N-channel gallium nitride-based transistor on a silicon substrate to prepare an N-channel gallium nitride-based transistor; then trenching the N-channel transistor area, epitaxially growing germanium material, preparing a germanium MOS device, and finally completing metal interconnection to obtain a complementary inverter, such as Figure 1 The inverter uses silicon-based gallium nitride and germanium semiconductor monolithic heterogeneous integration. The two materials have high electron and hole mobility respectively, which improves the working speed of the existing complementary inverter. It has high process compatibility and can be applied to high-speed large-scale digital circuits and gallium nitride radio frequency and power electronic device platforms.

[0053] Embodiment 1

[0054] See also Figure 2 , Figure 2 The schematic diagram of a GaN and Ge monolithic heterogeneous integrated complementary inverter is shown. The bottom of the structure is a silicon substrate layer 1, and the N-channel transistor side includes an N-channel transistor nucleation layer 2, an N-channel transistor buffer layer 3, an N-channel transistor channel layer 4, an N-channel transistor barrier layer 5, an N-channel transistor gate electrode 6, an N-channel transistor source electrode 7, and an N-channel transistor drain electrode 8. The P-channel transistor side includes a P-channel transistor N-type germanium well 9, a P-channel transistor P-type germanium well 10, a P-channel transistor drain electrode 11, a P-channel transistor source electrode 12, a P-channel transistor oxide dielectric layer 13, and a P-channel transistor gate electrode 14. Figure 6 In the present invention, Mp refers to germanium PMOS, and Mn refers to gallium nitride HEMT.

[0055] The N-channel transistor source electrode 7 and the N-channel transistor drain electrode 8 each form an ohmic contact with the N-channel transistor barrier layer 5 .

[0056] The P-channel transistor source electrode 12 and the P-channel transistor drain electrode 11 both form ohmic contacts with the P-channel transistor P-type germanium well 10 ; the P-channel transistor gate electrode 14 controls the formation of an inversion conductive channel on the upper surface of the P-channel transistor N-type germanium well 9 .

[0057] The gate electrode 6 of the N-channel transistor is connected to the gate electrode 14 of the P-channel transistor, forming the input end of the complementary inverter; the drain electrode 8 of the N-channel transistor is connected to the source electrode 12 of the P-channel transistor, forming the output end of the complementary inverter; the drain electrode 11 of the P-channel transistor is connected to the bias voltage VDD; the source electrode 7 of the N-channel transistor is grounded; thereby realizing a complementary inverter with heterogeneous integration of gallium nitride and germanium on a single chip.

[0058] Specifically, the material of the N-channel transistor nucleation layer 2 is aluminum nitride or gallium nitride, and the thickness is 50-300 nm.

[0059] Preferably, the material of the N-channel transistor nucleation layer 2 is aluminum nitride, and the thickness is 200 nm.

[0060] Specifically, the material of the N-channel transistor buffer layer 3 is gallium nitride or AlGaN, and the thickness is 200-1000 nm.

[0061] Preferably, the material of the N-channel transistor buffer layer 3 is AlGaN with a gradient composition and a thickness of 750 nm.

[0062] Specifically, the material of the N-channel transistor barrier layer 4 includes AlGaN, or InAlN, or AlN, and the thickness is 3-40 nm.

[0063] Preferably, the material of the N-channel transistor barrier layer 4 is AlGaN, with an Al component of 25% and a thickness of 20 nm.

[0064] Specifically, the N-channel transistor is an enhancement-mode device. A gate groove 61 is provided on the upper surface of the N-channel transistor barrier layer 5 and below the N-channel transistor gate electrode 6. The metal of the N-channel transistor gate electrode 6 fills the groove. The enhancement-mode operation of the N-channel transistor is achieved through the gate groove 61.

[0065] Specifically, the structures of the source electrode of the N-channel transistor and the drain electrode of the N-channel transistor are Ti / Al and other metals, or Ta / Al and other metals, or TiN / Al and other metals from bottom to top;

[0066] Preferably, the structures of the source electrode of the N-channel transistor and the drain electrode of the N-channel transistor are Ti / Al / TiN from bottom to top.

[0067] Specifically, the N-channel transistor gate electrode 6 includes Ni and other metals, or Ti and other metals, or TiN and other metals, including P-type gallium nitride and other metals from bottom to top.

[0068] Preferably, the channel transistor gate electrode 6 comprises Ni / Al from bottom to top.

[0069] Specifically, the material of the N-type germanium well 9 of the P-channel transistor is germanium, which can be doped with group V elements while growing germanium, or group V elements can be ion-implanted after growth to achieve N-type doping;

[0070] Preferably, the N-type germanium well 9 of the P-channel transistor is doped with group V elements while growing germanium.

[0071] Specifically, the source electrode 10 of the P-channel transistor and the source and drain electrode 11 of the P-channel transistor are P-type germanium, Al and other metals from bottom to top.

[0072] Preferably, the P-channel transistor source electrode 10 and the P-channel transistor source and drain electrode 11 are respectively made of P-type germanium, Al and TiN from bottom to top.

[0073] Specifically, the oxide dielectric layer 13 of the P-channel transistor may be germanium oxide, silicon oxide, hafnium oxide or other oxides.

[0074] Preferably, the oxide dielectric layer 13 of the P-channel transistor is germanium oxide.

[0075] Embodiment 2

[0076] See also Figure 3 , Figure 3 The schematic diagram of a GaN and Ge monolithic heterogeneous integrated complementary inverter is shown in FIG. The bottom of the structure is a silicon substrate layer 1, and the N-channel transistor side includes an N-channel transistor nucleation layer 2, an N-channel transistor buffer layer 3, an N-channel transistor channel layer 4, an N-channel transistor barrier layer 5, an N-channel transistor gate electrode 6, an N-channel transistor source electrode 7, and an N-channel transistor drain electrode 8. The P-channel transistor side includes a P-channel transistor N-type germanium well 9, a P-channel transistor P-type germanium well 10, a P-channel transistor drain electrode 11, a P-channel transistor source electrode 12, a P-channel transistor oxide dielectric layer 13, and a P-channel transistor gate electrode 14.

[0077] Specifically, the N-channel transistor is an enhancement-mode device, and a P-type group III nitride cap layer 62 is disposed on the upper surface of the N-channel transistor barrier layer 5 and below the N-channel transistor gate electrode 6, and the enhancement-mode operation of the N-channel transistor is achieved through the effect of the P-type group III nitride cap layer;

[0078] Specifically, the material of the P-type III-nitride cap layer 62 is gallium nitride, the doping impurity is Mg, the doping concentration is 1x1018 cm-3 to 1x1021 cm-3, and the thickness is 20-150nm;

[0079] Preferably, the material doping concentration of the P-type group III nitride cap layer 62 is 5×10 19 cm −3 and the thickness is 80 nm.

[0080] Specifically, the material of the gate electrode 6 of the N-channel transistor is one or more metals selected from Ni, Ti, TiN, Ta, TaN, Mo, Al, Au, Ti, and Cu;

[0081] Preferably, the material of the N-channel transistor gate electrode 6 is TiN and Al.

[0082] Other structural details are the same as those of the first embodiment.

[0083] Embodiment 3

[0084] See also Figure 4 , Figure 4 The schematic diagram of a GaN and Ge monolithic heterogeneous integrated complementary inverter is shown in FIG. The bottom of the structure is a silicon substrate layer 1, and the N-channel transistor side includes an N-channel transistor nucleation layer 2, an N-channel transistor buffer layer 3, an N-channel transistor channel layer 4, an N-channel transistor barrier layer 5, an N-channel transistor gate electrode 6, an N-channel transistor source electrode 7, and an N-channel transistor drain electrode 8. The P-channel transistor side includes a P-channel transistor N-type germanium well 9, a P-channel transistor P-type germanium well 10, a P-channel transistor drain electrode 11, a P-channel transistor source electrode 12, a P-channel transistor oxide dielectric layer 13, and a P-channel transistor gate electrode 14.

[0085] The N-channel transistor is an enhancement-mode device. An F-ion implantation region 63 is provided on the upper surface of the N-channel transistor barrier layer 5 and below the N-channel transistor gate electrode 6. The enhancement-mode operation of the N-channel transistor is achieved through the action of negative ions in the F-ion implantation region 63.

[0086] Specifically, the depth of the F ion implantation region 63 is 5-30 nm, and the concentration is 1x1018-1x1021 cm-3;

[0087] Preferably, the depth of the F ion implantation region 63 is 15 nm and the concentration is 1x1019 cm-3;

[0088] Other structural details are the same as those of the first embodiment.

[0089] Embodiment 4

[0090] See also Figure 5 , Figure 5 The present invention is a schematic diagram of a method for manufacturing a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter.

[0091] S1: At a high temperature of 900-1100° C., hydrogen is introduced into the reaction chamber to clean pollutants on the surface of the silicon substrate layer 1;

[0092] S2: On the substrate layer 1 cleaned in step 1, a metal organic chemical vapor deposition (MOCVD) method is used to sequentially grow an AlN nucleation layer of 20 nm, a GaN buffer layer of 1 μm, a GaN channel layer of 100 nm, an Al GaN barrier layer of 23 nm, and a P-type GaN material of 50 nm.

[0093] S3: performing coating, pre-baking, and exposure operations on the structure obtained in step 2, and preparing a P-gallium nitride gate photoresist pattern by using a pattern flipping and developing process;

[0094] S4: using the photoresist pattern prepared in step 3 as a mask, etching away the P-type gallium nitride layer material without a mask in step 2 by using an ICP device to obtain a P-type gallium nitride gate;

[0095] S5: The structure obtained in step 1 to step 4 is ultrasonically cleaned in acetone (MOS grade) for no less than 10 minutes, then placed in a heated cleaning and stripping solution, and finally cleaned with deionized water and blown dry with nitrogen;

[0096] S6: performing glue coating, pre-baking, and exposure operations on the structure obtained in step 5, and using pattern flipping and development processes to prepare source and drain photoresist patterns;

[0097] S7: using the photoresist pattern prepared in step 6 as a mask, vacuum evaporation is used to evaporate Ti / Al / Ni / Au, the thickness of which is 20 / 120 / 50 / 45 nm respectively, to prepare the source electrode 7 and the drain electrode 8 respectively, and high temperature annealing is performed at 850 degrees Celsius for 30 seconds, so that the source electrode 7 and the drain electrode 8 simultaneously form an ohmic contact with the two-dimensional electron gas generated near the heterojunction interface formed by the gallium nitride channel layer 4 and the barrier layer 5;

[0098] S8: On the P-GaN gate structure obtained in step 7, a metal gate of the device is manufactured by vacuum evaporating Ni / Au: 40 / 200nm to obtain a gate 6 which is P-GaN and metal from bottom to top;

[0099] S9: digging a groove on the right side of the structure obtained in step 8, using MOCVD equipment to grow germanium epitaxial material, and performing N-type doping on germanium during growth, using P element as the dopant, and finally obtaining an N-type germanium well 9;

[0100] S10: epitaxially grow germanium oxide 13 on the structure obtained in step 9, with a thickness of 1000nm, and perform photolithography and development to expose the oxide layer of the source and drain regions, and then perform ICP etching on the exposed oxide layer to expose the N-type germanium underneath. Using the oxide layer as a masking layer, perform ion implantation, and the implanted ions are group III elements, such as Al. Then perform annealing at 550 degrees Celsius for 30 seconds to activate the doped elements and finally obtain the P-type germanium well 10;

[0101] S11: Electron beam evaporation of Al Ag as metal electrodes is used on the source and drain of the structure obtained in step 10 to obtain source electrode 11 and drain electrode 12. Then, an Al metal gate 14 is made on the oxide layer;

[0102] S12: Metal interconnects are made on the structure obtained in step 11. The HEMT drain 8 is connected to the germanium PMOS source 10 as a signal output terminal. The HEMT gate is connected to the PMOS gate as a signal input terminal. The HEMT source is grounded and the PMOS drain is connected to the high level VDD.

[0103] In summary, the present invention finally realizes an on-chip heterogeneously integrated complementary inverter structure, which heterogeneously integrates the enhanced gallium nitride HEMT and the germanium-based PMOS on the same silicon substrate, effectively utilizing the advantages of the high working speed of the gallium nitride HEMT and the germanium-based PMOS, greatly improving the working speed of the inverter. At the same time, the inverter is compatible with the silicon process and can be manufactured using the existing process, which greatly reduces the manufacturing cost and can be applied to large-scale high-speed integrated circuits.

[0104] In the description of the present application, it should be noted that the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application; unless otherwise clearly specified and limited, the terms "install", "connect", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediary medium, and it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0105] The device includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device; in the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device that includes the elements.

[0106] The above description is only a specific implementation mode of the present application, which is convenient for those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined in this article can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in this article, but will conform to the widest scope consistent with the principles and novel features of the application in this article.

Claims

1. A gallium nitride and germanium monolithic heterogeneous integrated complementary inverter, characterized in that: The bottom layer is a silicon substrate layer (1), and the N-channel transistor side includes an N-channel transistor nucleation layer (2), an N-channel transistor buffer layer (3), an N-channel transistor channel layer (4), an N-channel transistor barrier layer (5), an N-channel transistor gate electrode (6), an N-channel transistor source electrode (7), and an N-channel transistor drain electrode (8); the N-channel transistor nucleation layer (2), the N-channel transistor buffer layer (3), the N-channel transistor channel layer (4), and the N-channel transistor barrier layer (5) are group III nitrides. A two-dimensional electron gas is formed between an N-channel transistor channel layer (4) and an N-channel transistor barrier layer (5), serving as a conductive channel of the N-channel transistor and being controlled by an N-channel transistor gate electrode (6); a P-channel transistor side includes a P-channel transistor N-type germanium well (9), a P-channel transistor P-type germanium well (10), a P-channel transistor drain electrode (11), a P-channel transistor source electrode (12), a P-channel transistor oxide dielectric layer (13), and a P-channel transistor gate electrode (14); The N-channel transistor source electrode (7) and the N-channel transistor drain electrode (8) both form ohmic contact with the N-channel transistor barrier layer (5); The P-channel transistor source electrode (12) and the P-channel transistor drain electrode (11) both form ohmic contact with the P-channel transistor P-type germanium well (10); the P-channel transistor gate electrode (14) controls the formation of an inversion conductive channel on the upper surface of the P-channel transistor N-type germanium well (9); The gate electrode (6) of the N-channel transistor is connected to the gate electrode (14) of the P-channel transistor to form the input end of the complementary inverter; the drain electrode (8) of the N-channel transistor is connected to the source electrode (12) of the P-channel transistor to form the output end of the complementary inverter; the drain electrode (11) of the P-channel transistor is connected to a bias voltage VDD; and the source electrode (7) of the N-channel transistor is grounded.

2. The gallium nitride and germanium monolithic heterogeneous integrated complementary inverter according to claim 1, characterized in that: The N-channel transistor is an enhancement-type device. A gate groove (61) is provided on the upper surface of the N-channel transistor barrier layer (5) and below the N-channel transistor gate electrode (6). The metal of the N-channel transistor gate electrode (6) fills the groove. The enhancement-type operation of the N-channel transistor is achieved through the gate groove (61).

3. The gallium nitride and germanium monolithic heterogeneous integrated complementary inverter according to claim 1, characterized in that: The N-channel transistor is an enhancement-type device. A P-type group III nitride cap layer (62) is arranged on the upper surface of the N-channel transistor barrier layer (5) and below the N-channel transistor gate electrode (6). The enhancement-type operation of the N-channel transistor is achieved through the action of the P-type group III nitride cap layer.

4. The gallium nitride and germanium monolithic heterogeneous integrated complementary inverter according to claim 1, characterized in that: The N-channel transistor is an enhancement-type device. An F ion implantation region (63) is provided on the upper surface of the N-channel transistor barrier layer (5) and below the N-channel transistor gate electrode (6). The enhancement-type operation of the N-channel transistor is achieved through the action of negative ions in the F ion implantation region (63).

5. The gallium nitride and germanium monolithic heterogeneous integrated complementary inverter according to claim 1, characterized in that: The material of the N-channel transistor nucleation layer (2) is AlN or gallium nitride, with a thickness of 50-300 nm; the material of the N-channel transistor buffer layer (3) is gallium nitride or AlGaN, with a thickness of 200-1000 nm; the material of the N-channel transistor barrier layer (5) includes AlGaN, InAlN, and the AlN thickness is 3-40 nm; the materials of the N-channel transistor nucleation layer (2), the N-channel transistor buffer layer (3), and the N-channel transistor barrier layer (5) are unintentionally doped.

6. The gallium nitride and germanium monolithic heterogeneous integrated complementary inverter according to claim 1, characterized in that: The structures of the N-channel transistor source electrode (7) and the N-channel transistor drain electrode (8) are Ti / Al and other metals, or Ta / Al and other metals, or TiN / Al and other metals from bottom to top; the N-channel transistor gate electrode (6) includes Ni and other metals, or Ti and other metals, or TiN and other metals, including P-type gallium nitride and other metals from bottom to top.

7. The gallium nitride and germanium monolithic heterogeneous integrated complementary inverter according to claim 1, characterized in that: The material of the N-type germanium well (9) of the P-channel transistor is germanium, which can be doped with group V elements when growing germanium, or group V elements can be ion-implanted after growth to achieve N-type doping.

8. The gallium nitride and germanium monolithic heterogeneous integrated complementary inverter according to claim 1, characterized in that: The P-channel transistor source electrode (12) and the P-channel transistor source and drain (12) are P-type germanium, Al and other metals from bottom to top.

9. The gallium nitride and germanium monolithic heterogeneous integrated complementary inverter according to claim 1, characterized in that: The P-channel transistor oxide dielectric layer (13) may be germanium oxide, silicon oxide, hafnium oxide or other oxides.

10. A method for preparing a gallium nitride and germanium monolithic heterogeneous integrated complementary inverter, characterized in that: The following steps are involved: Step 1: cleaning pollutants on the surface of the silicon substrate layer (1); Step 2: sequentially growing an N-channel transistor nucleation layer (2), an N-channel transistor buffer layer (3), an N-channel transistor channel layer (4), and an N-channel transistor barrier layer (5); Step 3: preparing an N-channel transistor source electrode (7) and an N-channel transistor drain electrode (8), and performing annealing, wherein the N-channel transistor source electrode (7) and the N-channel transistor drain electrode (8) simultaneously form an ohmic contact with a two-dimensional electron gas generated near a heterojunction interface formed by the N-channel transistor channel layer (4) and the N-channel transistor barrier layer (5); Step 4: Making an N-channel transistor gate electrode (6); Step 5: digging a groove in the structural part obtained in step 2, growing germanium epitaxial material, and performing N-type doping on germanium during growth to obtain an N-type germanium well (9) of a P-channel transistor; Step 6: epitaxially oxidize germanium on the structure obtained in step 3, and then etch the exposed portion of the oxide layer to expose the N-type germanium underneath; Ion implantation is performed using the oxide layer as a masking layer; Then annealing is performed to activate the doping elements and finally obtain a P-channel transistor P-type germanium well (10); Step 7: manufacturing a P-channel transistor gate electrode (14), a P-channel transistor drain electrode (11) and a P-channel transistor source electrode (12) on the P-channel transistor oxide dielectric layer (13); Step 8: Metal interconnection lines are made on the structure obtained in step 7. The gate electrode (6) of the N-channel transistor is connected to the gate electrode (14) of the P-channel transistor to form the input end of the complementary inverter; the drain electrode (8) of the N-channel transistor is connected to the source electrode (12) of the P-channel transistor to form the output end of the complementary inverter; the drain electrode (11) of the P-channel transistor is connected to the bias voltage VDD; the source electrode (7) of the N-channel transistor is grounded; and the complementary inverter is realized.

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