A superconducting quantum chip processor folding bit processing method and process

Abstract

The application discloses a superconducting quantum chip processor folding bit processing method and process, relates to the field of superconducting quantum computation and micro-nano processing technology, and specifically comprises the following steps: S100, substrate pretreatment and SiO2 pattern initial engraving: selecting a 12-inch and below silicon, SiC and GaN wafer as a base, using an atomic force microscope and a stress tester to detect the substrate surface topography and stress initial value, the application realizes folding processing of superconducting quantum bits by introducing focused ion beam technology, greatly breaks through the limitations of traditional plane processing technology, and the traditional superconducting quantum bit processing method is mainly based on plane processing technology, and many challenges are faced when complex three-dimensional structures are processed, and the application accurately controls the stress distribution of the thin film by using the focused ion beam technology, realizes height-controllable deformation in a set direction, and thus easily realizes folding of the superconducting quantum bit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of superconducting quantum computing and micro-nano processing technology, in particular to a superconducting quantum chip processor folded bit processing method and process. BACKGROUND

[0002] With the rapid development of quantum computing technology, superconducting quantum bits as a kind of extremely potential quantum computing elements, the optimization of its performance and the improvement of processing technology have become the focus of research, superconducting quantum computing micro-nano processing field has been exploring more efficient and accurate processing method, to meet the growing demand for high precision and miniaturization quantum bits, in this background, the present application proposes a superconducting quantum bit folding processing method and process based on focused ion beam technology, aiming to provide a new processing means for the field of superconducting quantum computing.

[0003] However, the traditional superconducting quantum bit processing method is mainly based on planar processing technology, this method in the realization of complex three-dimensional structure processing faces great challenges, in addition, the traditional planar processing technology in the measurement of parallel chip magnetic field of superconducting chip, often low precision, can not accurately obtain the key information, which hinders the in-depth study of the characteristics of superconducting materials and optimizes the chip design, more importantly, in the space utilization of wafer, the existing technology can not fully play its potential, resulting in the integration of superconducting bits is limited, restricts the large-scale development and application of superconducting quantum bits, the traditional technology also lacks effective means in the research of material electromagnetic defects, TLS and crosstalk distribution between bits.

[0004] Therefore, to develop a superconducting quantum chip processor folded bit processing method and process, has the advantages of high processing precision, good repeatability, good process compatibility, is expected to bring revolutionary changes to the field of superconducting quantum computing. SUMMARY

[0005] The purpose of the present application is to make up for the shortcomings of the prior art, provide a superconducting quantum chip processor folded bit processing method and process, which realizes the folding of superconducting quantum bits by using focused ion beam technology to accurately process superconducting thin film materials and planar structures, thereby improving the performance and stability of quantum bits, not only providing a new processing means for the field of superconducting quantum computing, but also effectively solving the problems of traditional planar processing technology that is difficult to realize complex three-dimensional structure processing and miniaturization, through the folding of the thin film, the three-dimensional scale space of the wafer can be fully utilized, the integration of superconducting bits is improved, and a solid foundation is laid for the large-scale application of superconducting quantum bits.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: On one hand, a method for fabricating folded qubits in a superconducting quantum chip processor, the specific steps of which are as follows:

[0007] S100, Substrate pretreatment and initial SiO2 patterning: Select silicon, SiC, or GaN wafers of 12 inches or smaller as the base, use atomic force microscope and stress tester to detect the surface morphology and initial stress value of the substrate, and use KrF excimer lithography to etch SiO2 patterns. The design rules are determined according to the superconducting qubit functional layout and electrical interconnection requirements.

[0008] S200, Dielectric Layer Deposition and Performance Enhancement: In the PECVD equipment, at a low temperature range of 80-100℃, SiH4 is used as the main gas source with a flow rate of 50-150 sccm, and a small amount of N2O is added with a flow rate of 5-15 sccm. The plasma is excited by 100-300W radio frequency power to deposit SiO2 film. The film thickness is monitored in real time using an optical interferometer based on the principle of multi-beam interference to ensure that the film thickness uniformity deviation is within ±5% and the deposition rate is stable at 0.5-2nm / s. The temperature is increased to 400-600℃ at a heating rate of 5-10℃ / min and held for 30-90min for annealing treatment, thereby reducing the stress to ≤50MPa, eliminating micro-defects, increasing the high temperature thermal budget to above 800℃, and achieving a Knoop hardness of 8-12GPa.

[0009] S300, fabrication of superconducting Josephson junctions: Al / AlOx / Al Josephson junctions were fabricated in an electron beam evaporation chamber. Before depositing the BE-Al film, impurities were removed by degassing at 150-200℃ for 30-60 min. The deposition temperature was selected from room temperature to 150℃, and the deposition rate was 0.1-0.3 nm / s. The electron beam current was set to 10-30 mA and the accelerating voltage to 5-10 kV. The film thickness was monitored in real time using a quartz crystal microbalance. A 10 nm AlOx insulating layer was fabricated by oxidation. The O2 flow rate was adjusted to 5-15 sccm using a mass flow controller, and the chamber pressure was stabilized at 5 × 10⁻⁶ using a capacitive thin-film vacuum gauge. -3 -1×10 -2 Torr, oxidation time 20-40s, continue deposition of TE-Al film, followed by photoresist spin coating at 200-400μC / cm 2 Electron beam exposure transfer design pattern is performed, and after development, the BE and TE layers are etched by ion beam at an etching energy of 300-500eV, a beam current of 10-30mA, and an angle of 5-15° to form Josephson junctions.

[0010] S400, film layer suspended structure processing: using wet etching process to etch SiO2 film to achieve suspended state, etching temperature 20-25℃, etching time is determined according to SiO2 film thickness and pattern profile, with the help of reaction kinetics model, combining in-situ optical microscope to monitor etching front gray scale change and morphological characteristics, dynamically optimize the etching process within 30-90s, control the etching rate at 10-30nm / s, manufacture fan-shaped etching area, fan-shaped radius 50-150μm, central angle 30-60°, precision ±2°, suspended precision within ±10μm;

[0011] S500, FIB irradiation film layer folding: the processed sample is fixed on the 6-inch vacuum clamp on the FIB stage with a clamping force of 50-100N, vacuum extraction to <10 -6 After 50Pa, start the electron beam and ion beam, calibrate the beam spot size, energy, scanning accuracy according to the standard calibration program of the equipment, tilt the stage by 55°±1°, adjust the WD to 6mm±0.1mm to lock the processing area, draw the processing frame according to the design blueprint and set the size, irradiate with a current of 50Pa±5Pa and an energy of 30Kev, use SEM to collect images in real time to analyze the evolution of thin film stress-strain field, fine-tune the parameters according to the strain rate of Ta film deformation 0.005-0.02% / s, adjust the scanning rate in steps of 0.5-2μm / s, dynamically optimize the beam spot size 5-15nm, control the deformation rate 0.05-0.2μm / s, direction accuracy ±1°, until the Ta film stands up or reaches the bending shape, stop irradiation;

[0012] S600, FIB deposition function: move the platinum probe to the processing position, heat to 300-400℃ at a rate of 10-20℃ / min, draw the deposition area, length 3-8μm, width 2-6μm, depth 1μm, precision ±0.3μm, start deposition with a current of 100-250PA and an energy of 30Kev according to the pattern area, introduce argon gas into the chamber before deposition to drive off oxygen impurities, optimize and accurately control the deposition rate at 0.05-0.2μm / min according to the Pt deposition kinetics equation and electric field distribution finite element simulation, monitor the surface morphology with atomic force microscope for feedback control, monitor the platinum atom deposition distribution uniformity and thickness precision in real time with SEM and energy dispersive spectrometer, verify the microstructure observation with high-resolution transmission electron microscope according to the Pt crystal growth model and thin film nucleation theory, customize the irradiation strategy according to the thin film material characteristics and thickness range, combine with TSV process to pre-plan the via layout, avoid interference at each stage of film folding, realize vertical electrical interconnection with TSV, improve integration and performance.

[0013] Further, the S100, the parameter setting of the line width, the pitch, the depth and the pattern profile accuracy of the etching in the substrate pretreatment and the SiO2 pattern initial etching is: the line width is 100-500 nm according to the accurate calculation of the bit transmission line width and the coupling strength theory, the pitch is 200-800 nm according to the accurate calculation of the electromagnetic shielding and the crosstalk suppression model, the depth is 100-300 nm according to the strict determination of the subsequent deposition film thickness and the etching process compatibility, and the pattern profile accuracy is <±10 nm.

[0014] Further, the S200, the SiO2 film thickness deposited in the medium layer deposition and performance enhancement is 200-300 nm.

[0015] Further, the S300, the BE-Al film thickness is 95-105 nm and the TE-Al film thickness is 98-102 nm in the preparation of the superconducting Josephson junction.

[0016] Further, the S300, the rotation speed of the photoresist spin coating is 3000-5000 rpm and the thickness is 1-2 μm in the preparation of the superconducting Josephson junction.

[0017] Further, the S400, the solution used for etching the lower SiO2 film by using the wet etching process in the processing of the film layer suspended structure is hydrofluoric acid HF solution.

[0018] Further, the S500, the beam current of the electron beam is 1-5 nA and the beam current of the ion beam is 50-100 pA in the FIB irradiation film layer folding.

[0019] Further, the S600, the film material characteristics involved in the FIB deposition function advancement are: single layer includes Nb, Al, Ta, TiN; and multi-layer includes Nb / AlOx / Nb, Al / AlOx / Al.

[0020] Further, the S600, when the thickness is <100 nm, the energy is reduced to 15-25 Kev and the speed is increased to 1-3 μm / s for fine adjustment of the shape; when the thickness is ≥300 nm, the irradiation time is increased by 10-30 min, and multi-section irradiation is adopted in 3-5 sections, and the energy is fine adjusted by ±5 Kev in each section.

[0021] On the other hand, a superconducting quantum chip processor folding bit processing process, the specific steps of the processing process are:

[0022] S100, substrate selection and SiO2 pattern initial carving: using 12 inches and below silicon, SiC, GaN wafer as substrate, measuring surface topography and stress initial value by atomic force microscope and stress tester, etching SiO2 pattern by KrF excimer laser technology, line width is set to 100-500 nm according to bit transmission line width and coupling strength theory, spacing is set to 200-800 nm according to electromagnetic shielding and crosstalk suppression model, depth is determined to be 100-300 nm according to subsequent process, and pattern profile accuracy is <±10 nm;

[0023] S200, medium layer deposition and quality leap: in the low temperature range of 80-100℃ of PECVD equipment, SiH4 of 50-150sccm is used as main gas source, N2O of 5-15sccm is used as doping gas, and SiO2 film is deposited by plasma excited by 100-300W radio frequency power, optical interferometer is monitored to make film thickness uniformity deviation within ±5%, deposition rate is 0.5-2nm / s, after depositing 200-300nm thick film, annealing at 5-10℃ / min to 400-600℃ for 30-90min, reducing stress to ≤50MPa, eliminating micro defects, improving thermal budget and mechanical strength;

[0024] S300, fine shaping of Josephson junction: Al / AlOx / Al Josephson junction is prepared in an electron beam evaporation chamber, impurities are removed by Degas treatment for 30-60min at 150-200℃ before depositing BE-Al film, the deposition temperature is room temperature to 150℃, the deposition rate is 0.1-0.3nm / s, the thickness of BE-Al film is 95-105nm, the electron beam current is 10-30mA, the acceleration voltage is 5-10kV, and the quartz crystal microbalance is monitored, after 10nm AlOx insulating layer is prepared by controlling O2 flow of 5-15sccm, 98-102nm thick TE-Al film is deposited, photoresist is spin-coated to 1-2μm thick film at 3000-5000rpm, then electron beam exposure and development are carried out, and BE and TE layers are etched to form junction by ion beam etching;

[0025] S400, craftsmanship of film layer overhanging structure: SiO2 film is overhanging by wet etching with hydrofluoric acid HF solution at 20-25℃, the etching time is determined according to film thickness and pattern, 30-90s is optimized for etching by reaction kinetics model combined with in-situ optical microscope monitoring, the rate is 10-30nm / s to prepare fan-shaped area, the radius is 50-150μm, the central angle is 30-60°±2°, and the overhanging accuracy is within ±10μm;

[0026] S500, three-dimensional folding of FIB irradiated film layer: the sample is clamped to the 6-inch vacuum clamp FIB stage with a clamping force of 50-100N, the vacuum is extracted to <10 -6After Pa, start 1-5nA beam current electron beam and 50-100pA beam current ion beam, tilt the platform 55°±1°, adjust the WD to 6mm±0.1mm, lock the processing area, irradiate according to the drawing to set the parameters, analyze the stress-strain field evolution of the film by SEM image, adjust the strain rate of Ta film to 0.005-0.02% / s, control the deformation rate to 0.05-0.2μm / s and the direction accuracy to ±1° to achieve the target shape of the Ta film;

[0027] S600, FIB deposition performance advanced: platinum probe moves to the processing site to draw the deposition area, the deposition area is 3-8μm long, 2-6μm wide and 1μm deep, 100-250PA current and 30Kev energy are deposited according to the area of the graph, argon gas is introduced to drive out oxygen impurities, the deposition rate is controlled to 0.05-0.2μm / min, atomic force microscopy is monitored for feedback control, and irradiation strategies are customized according to the characteristics of different thickness films, the thickness is less than 100nm, the energy is reduced and the speed is adjusted, the thickness is greater than or equal to 300nm, the irradiation time is increased and the segments are adjusted, the interconnection is planned by TSV process, and the integration and electrical performance are improved.

[0028] Compared with the prior art, the superconducting quantum chip processor folding bit processing method and process have the following beneficial effects:

[0029] Firstly, the present application realizes the folding processing of superconducting quantum bits by introducing focused ion beam technology, greatly breaking through the limitations of traditional planar processing technology, and the traditional superconducting quantum bit processing method is mainly based on planar processing technology, which faces many challenges in realizing the processing of complex three-dimensional structures, while the present application uses focused ion beam technology to accurately control the stress distribution of the film and realizes the deformation of the set direction with high controllability, so that the folding of the superconducting quantum bit is easily realized, not only providing a new idea for the processing of superconducting quantum bits, but also effectively solving the problem that the traditional technology cannot realize the processing of complex three-dimensional structures, improving the processing precision and repeatability.

[0030] Secondly, the present application can fully utilize the three-dimensional space of the wafer by folding the film, improve the integration of superconducting bits, and has important significance for the development of the field of superconducting quantum computing, the traditional planar processing technology has limitations in the space utilization of the wafer, which limits the integration of superconducting bits and seriously restricts the large-scale development and application of superconducting quantum bits, while the present application realizes the folding processing, so that the superconducting quantum bits can be arranged more closely on the wafer, thereby greatly improving the integration, and combining with the mature semiconductor TSV process to realize the electrical connection in the vertical direction, further improving the performance and integration of the superconducting quantum chip, and providing a new idea for the large-scale application of superconducting quantum technology.

[0031] Additional advantages, objects, and features of the application will be apparent to those skilled in the art upon examination of the following detailed description, it being understood that each of the foregoing general statements are not limiting upon the scope of the application and that all patentable combinations of the recited features are contemplated as being within the scope of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0033] Figure 1 A flow framework diagram of a superconducting quantum chip processor folding bit processing method;

[0034] Figure 2 A flowchart of a superconducting quantum chip processor folding bit processing technology. DETAILED DESCRIPTION

[0035] In order to further illustrate the technical means and effects adopted by the present application to achieve the predetermined application purpose, the following will combine the drawings and the preferred embodiments to specifically describe the specific embodiments, structures, features and effects according to the present application.

[0036] Embodiment one

[0037] First, etch SiO2 pattern, then deposit Al film:

[0038] In a quantum physics laboratory of a certain university, a scientific research team started to develop a new type of superconducting quantum chip processor, aiming to provide stable and efficient hardware support for quantum computing teaching and basic scientific research projects, and decided to adopt the process of first etching SiO2 pattern, then depositing Al film, the specific operation is as follows:

[0039] Substrate pretreatment and SiO2 pattern initial etching (S100): 10-inch silicon wafer is selected as the substrate, atomic force microscope is used to scan the substrate surface in detail, the surface flatness is accurately detected to be good, only a small fluctuation, the initial stress value is in the normal range, KrF excimer lithography technology is used to etch SiO2 pattern, according to the bit transmission line width and coupling strength theory, the line width is set to 300nm, according to the electromagnetic shielding and crosstalk suppression model, the spacing is accurately determined to be 500nm, the depth is combined with the compatibility of subsequent deposition film thickness and etching process, and is set to 200nm, the pattern outline accuracy is strictly controlled to be less than ±10nm, so as to ensure that the pattern meets the requirements of superconducting bit function layout and electrical interconnection.

[0040] Medium layer deposition and performance enhancement (S200): The wafer is transferred to a PECVD device, and at a low temperature of 90°C, a SiH4 gas source of 100 sccm is used as the main gas source, 10 sccm of N2O is added, and a 200W radio frequency power is used to excite the plasma to start depositing a SiO2 film. Real-time monitoring is performed by using an optical interferometer to ensure that the film thickness uniformity deviation is stably maintained within ±5%, and the deposition rate is stably maintained at 1 nm / s. Finally, a 250nm-thick SiO2 film is obtained. Subsequently, the temperature is increased to 500°C at a rate of 8°C / min, and annealing is performed for 60 min. The stress is successfully reduced to 30MPa, the micro defects are eliminated, the high-temperature thermal budget is increased to 850°C, and the mechanical strength reaches a Knoop hardness of 10GPa.

[0041] Preparation of superconducting Josephson junction (S300): Enter the electron beam evaporation chamber, and before depositing the BE-Al film, perform Degas treatment at 180°C for 45 min to effectively remove impurities. The deposition temperature is selected to be 100°C, the deposition rate is set to be 0.2 nm / s, the electron beam current is set to be 20mA, and the acceleration voltage is set to be 8kV. The film thickness is monitored in real time by using a quartz crystal microbalance. A 100nm-thick BE-Al film is deposited. Then, the O2 flow rate is adjusted to be 10sccm by using a mass flow controller, and the cavity pressure is stably controlled to be 8×10 - 3 Torr by using a capacitive thin film vacuum gauge. The oxidation time is set to be 30s, and a 10nm-thick AlOx insulating layer is manufactured. Then, a 100nm-thick TE-Al film is deposited. The photoresist is spin-coated into a 1.5μm-thick film at a speed of 4000rpm. Then, electron beam exposure is performed to transfer the designed pattern, and after development, the BE and TE layers are etched by using an ion beam. The etching energy is 400eV, the beam current is 20mA, and the angle is 10°. A Josephson junction is successfully formed. 2

[0042] Processing of the film layer overhang structure (S400): HF solution is used to etch the SiO2 film in a wet etching manner to achieve an overhang state. The etching time is determined according to the thickness of the SiO2 film and the pattern profile. The etching front gray scale change and morphological characteristics are monitored in real time by using a reaction kinetics model combined with an in-situ optical microscope. The etching process is dynamically optimized within 60s, and the etching rate is stably maintained at 20nm / s. A fan-shaped etching area is manufactured. The fan-shaped radius is 100μm, the circle center angle is 45°, the precision is ±2°, and the overhang precision is controlled within ±10μm.

[0043] FIB irradiation film layer folding (S500): The processed sample is fixed on a 6-inch vacuum clamp on the FIB stage with a clamping force of 80N. The vacuum is extracted to be <10 -6 ​After Pa, the electron beam (beam current 3 nA) and the ion beam (beam current 80 pA) are started, the size, energy, scanning accuracy of the beam spot are calibrated according to the standard calibration procedure of the equipment, the stage is tilted by 55°±1°, the WD is adjusted to 6 mm±0.1 mm to lock the processing area, the processing frame is drawn according to the design blueprint, and the size is set, the irradiation is carried out at a current of 50 PA±5 PA and an energy of 30 Kev, the image is collected in real time by SEM to analyze the evolution of the stress-strain field of the film, the parameters are fine-tuned according to the strain rate of 0.01% / s of the Ta film deformation, the scanning rate is adjusted in steps of 1 μm / s, the beam spot size is dynamically optimized to 10 nm, the deformation rate is controlled to 0.1 μm / s, the direction accuracy is ±1°, until the Ta film stands up, and the irradiation is stopped.

[0044] FIB deposition function (S600): move the platinum probe to the processing position, heat to 350℃ at 15℃ / min, draw a deposition area with a length of 5 μm, a width of 4 μm, and a depth of 1 μm, with an accuracy of ±0.3 μm, start deposition according to the area of the pattern with a current of 180 PA and an energy of 30 Kev, introduce argon gas into the chamber before deposition to drive off oxygen impurities, the deposition rate is optimized and accurately controlled at 0.1 μm / min according to the Pt deposition kinetics equation and finite element simulation of electric field distribution, the surface morphology is monitored by atomic force microscope for feedback control, the Pt atom deposition distribution uniformity and thickness accuracy are monitored in real time by SEM with energy spectrometer, the microstructure is observed by high-resolution transmission electron microscope according to the Pt crystal growth model and thin film nucleation theory, the layout of the through hole is pre-planned combined with the TSV process to avoid interference at each stage of film folding, vertical electrical interconnection is realized by TSV to improve integration and performance.

[0045] In summary, the present embodiment focuses on the research and development needs of the quantum physics laboratory in colleges and universities, and details the superconducting quantum chip processor folding bit processing flow of first etching SiO2 pattern and then depositing Al film, highlighting the significant advantages of the process in basic scientific research and teaching scenarios. From the beginning of substrate pretreatment, with the help of advanced detection equipment and photolithography technology, the key parameters of the SiO2 pattern are accurately controlled, laying a solid foundation for subsequent processes; in the deposition stage of the dielectric layer, the PECVD equipment is matched with strict monitoring means to optimize the film thickness, stress and mechanical properties, meeting the demands of long-term and stable operation of the chip in the laboratory.

[0046] In the preparation link of superconducting Josephson junction, multi-parameter fine adjustment ensures the high-quality formation of the junction; the wet etching of the overhanging structure and the FIB irradiation and deposition process are closely linked, real-time monitoring feedback and dynamic adjustment are throughout the whole process, ensuring the processing accuracy at the microscopic level and the performance at the macroscopic level, and the final product performs outstandingly in bit transmission stability and coupling strength, which effectively proves that the process route not only can produce chip samples that meet the needs of teaching direct demonstration, but also can provide reliable hardware support for basic quantum research projects, helping colleges and universities to steadily move forward in the academic exploration and talent cultivation in the field of quantum.

[0047] Example Two:

[0048] Directly engraving Al film:

[0049] A certain quantum technology enterprise received an order from a customer to customize a high-performance superconducting quantum chip processor. The customer requires high integration and fast operation speed. The enterprise's R&D team decided to try the process route of directly engraving Al film, hoping to optimize the processing flow and shorten the construction period. The specific implementation steps are as follows:

[0050] Substrate selection and SiO2 pattern initial engraving (S100): Select an 8-inch SiC wafer as the substrate, use an atomic force microscope and a stress tester to quickly determine the surface topography and initial stress value, use KrF excimer lithography technology to etch SiO2 patterns, the line width is accurately set to 200 nm according to the bit transmission line width and coupling strength theory, the spacing is accurately set to 400 nm according to the electromagnetic shielding and crosstalk suppression model, and the depth is determined according to the subsequent process to be 150 nm, with a pattern profile accuracy of <±10 nm, providing a matching basic pattern architecture for subsequent direct Al film engraving.

[0051] Medium layer deposition and quality leap (S200): In the 85°C low temperature range of the PECVD equipment, introduce SiH4 as the main gas source with a flow rate of 80sccm, and 8sccm of N2O as the doping gas, and deposit SiO2 film by exciting plasma with a radio frequency power of 150W. Rely on the optical interferometer to strictly monitor, maintain the thickness uniformity deviation of the film within ±5%, the deposition rate is stable at 0.8nm / s, successfully deposit 220nm thick SiO2 film, then anneal at 450℃ for 45min with a heating rate of 6℃ / min, the stress is successfully reduced to 40MPa, the micro defects are eliminated, the high temperature thermal budget is improved, and the mechanical strength meets the subsequent processing requirements.

[0052] Fine shaping of Josephson junction (S300): Quickly place the wafer in the electron beam evaporation chamber and start preparing the Al / AlOx / Al Josephson junction. Before depositing the BE-Al film, perform Degas treatment at 160℃ for 50min to completely remove impurities; select a deposition temperature of room temperature and a deposition rate of 0.15nm / s to deposit a 98nm thick BE-Al film. Set the electron beam current to 15mA and the acceleration voltage to 6kV, and use a quartz crystal microbalance to monitor the whole process to accurately control the O2 flow rate to 8sccm to oxidize and manufacture a 10nm AlOx insulating layer. Then deposit a 99nm thick TE-Al film, spin coat photoresist to a thickness of 1.2μm at a speed of 3500rpm, immediately perform electron beam exposure, development, and then use ion beam to etch the BE and TE layers with an etching energy of 350eV, a beam current of 15mA, and an angle of 8°. High-efficiency Josephson junction is created.

[0053] Crafting of the overhanging film layer architecture (S400): Under the constant temperature condition of 23°C, the overhanging of the SiO2 film is etched by using hydrofluoric acid (HF) solution wet etching, combined with the reaction kinetics model and in-situ optical microscope, monitoring and etching at the same time, adjusting the etching time according to the thickness and pattern profile of the film, realizing the optimized etching within 45s, keeping the etching rate at 15nm / s, and manufacturing a fan-shaped etching area with a fan radius of 80μm and a central angle of 35°, the accuracy is ±2°, and the overhanging accuracy is controlled within ±10μm.

[0054] Three-dimensional folding of the FIB irradiated film layer (S500): The sample is firmly fixed on the 6-inch vacuum clamp FIB stage with a clamping force of 60N, and the vacuum is extracted to <10 -6 After 30min, the electron beam (beam current is 2nA) and the ion beam (beam current is 60pA) are started, the stage is tilted by 55°±1°, the WD is adjusted to 6mm±0.1mm to lock the processing area, the processing frame is drawn according to the design blueprint, and the parameters are accurately set for irradiation, the images are collected in real time by SEM, the stress-strain field evolution of the thin film is deeply analyzed, the parameters are fine-tuned according to the strain rate of the Ta film 0.008% / s, the deformation rate 0.08μm / s and the direction accuracy ±1° are strictly controlled, and the Ta film reaches the ideal bending shape.

[0055] Excellent progress of FIB deposition performance (S600): Move the platinum probe to the processing position, heat to 320°C at a rate of 12°C / min, draw a deposition area with a length of 4μm, a width of 3μm, and a depth of 1μm, with an accuracy of ±0.3μm, start deposition with a current of 120PA and an energy of 30Kev according to the area of the pattern, pre-argon gas is introduced to drive off oxygen impurities, the deposition rate is accurately controlled at 0.08μm / min, real-time monitoring and feedback control are realized by atomic force microscope, special irradiation strategies are customized according to the characteristics of thin films of different thicknesses, when the thickness is <100nm, the energy is reduced to 20Kev and the speed is increased to 2μm / s for fine control, when the thickness is ≥300nm, the irradiation time is increased by 20min, 4-stage irradiation is adopted, each stage is fine-tuned with an energy of ±5Kev, combined with TSV process to plan efficient interconnection, greatly improving the integration and electrical performance.

[0056] In summary, in the scenario of quantum technology enterprises pursuing efficient production and high-performance delivery, the superconducting quantum chip processor processing technology of directly etching Al film shows great value. Using SiC wafer as the substrate, the etching of SiO2 pattern in the early stage closely meets the high-performance requirements of the chip, and the key size accuracy is locked, laying a good foundation for subsequent direct etching of Al; the deposition and annealing of the dielectric layer are completed efficiently, and the ideal film quality and stress state are quickly achieved, which meets the production rhythm of enterprises to shorten the construction period and strictly control the cost.

[0057] In the preparation of Josephson junction, each link is completed at one time, and precise parameter setting guarantees the electrical performance of the junction; the suspended structure processing and FIB related operation, with real-time monitoring and targeted fine-tuning, make the microstructure under control, meet the high integration demand of chip, especially in the advanced link of FIB deposition, according to the irradiation strategy customized according to the thickness of the film, combined with TSV process, all-round improve the electrical performance and integration effect, the finished product successfully passed the strict quality inspection of the enterprise, far beyond the customer's expectation, inject strong impetus for the enterprise to open up the market and establish the brand image, also accumulate valuable experience for the commercialization of quantum chip production, help the industry to move towards a new stage of efficient and high-quality development.

[0058] The above is only the preferred embodiment of the present application, not any form of limitation on the present application, although the present application has been disclosed as above with the preferred embodiment, however, it is not intended to limit the present application, any person skilled in the art, without departing from the scope of the present application, can make some changes or modifications to the above disclosed technical content to make equivalent embodiments, but as long as it does not deviate from the technical solution of the present application, any modification, equivalent change and modification of the above embodiments according to the technical essence of the present application are still within the scope of the present application.

Claims

1. A method for fabricating folded qubits in a superconducting quantum chip processor, characterized in that, The specific steps of this processing method are as follows: S100, Substrate pretreatment and initial SiO2 patterning: Select silicon, SiC, or GaN wafers of 12 inches or smaller as the base, use atomic force microscope and stress tester to detect the surface morphology and initial stress value of the substrate, and use KrF excimer lithography to etch SiO2 patterns. The design rules are determined according to the superconducting qubit functional layout and electrical interconnection requirements. S200, Dielectric Layer Deposition and Performance Enhancement: In the PECVD equipment, at a low temperature range of 80-100℃, SiH4 is used as the main gas source with a flow rate of 50-150 sccm, and a small amount of N2O is added with a flow rate of 5-15 sccm. The plasma is excited by 100-300W radio frequency power to deposit SiO2 film. The film thickness is monitored in real time using an optical interferometer based on the principle of multi-beam interference to ensure that the film thickness uniformity deviation is within ±5% and the deposition rate is stable at 0.5-2nm / s. The temperature is increased to 400-600℃ at a heating rate of 5-10℃ / min and held for 30-90min for annealing treatment, thereby reducing the stress to ≤50MPa, eliminating micro-defects, increasing the high temperature thermal budget to above 800℃, and achieving a Knoop hardness of 8-12GPa. S300, fabrication of superconducting Josephson junctions: Al / AlOx / Al Josephson junctions were fabricated in an electron beam evaporation chamber. Before depositing the BE-Al film, impurities were removed by degassing at 150-200℃ for 30-60 min. The deposition temperature was selected from room temperature to 150℃, and the deposition rate was 0.1-0.3 nm / s. The electron beam current was set to 10-30 mA and the accelerating voltage to 5-10 kV. The film thickness was monitored in real time using a quartz crystal microbalance. A 10 nm AlOx insulating layer was fabricated by oxidation. The O2 flow rate was adjusted to 5-15 sccm using a mass flow controller, and the chamber pressure was stabilized at 5 × 10⁻⁶ using a capacitive thin-film vacuum gauge. -3 -1×10 -2 Torr, oxidation time 20-40s, continue deposition of TE-Al film, followed by photoresist spin coating at 200-400μC / cm 2 Electron beam exposure transfer design pattern is performed, and after development, the BE and TE layers are etched by ion beam at an etching energy of 300-500eV, a beam current of 10-30mA, and an angle of 5-15° to form Josephson junctions. S400, Suspended Structure Fabrication: A wet etching process is used to etch the SiO2 film to achieve a suspended state. The etching temperature is 20-25℃, and the etching time is determined based on the SiO2 film thickness and pattern outline. The grayscale change and morphological characteristics of the etching front are monitored in real time using a reaction kinetic model combined with an in-situ optical microscope. The etching process is dynamically optimized within 30-90s, and the etching rate is controlled at 10-30nm / s to create a fan-shaped etching area with a fan radius of 50-150μm, a central angle of 30-60°, an accuracy of ±2°, and a suspension accuracy within ±10μm. S500, FIB irradiation film folding: Fix the treated sample in a 6-inch vacuum fixture on the FIB stage with a clamping force of 50-100N, and evacuate to <10°C. -6 After Pa, the electron beam and ion beam are started. The beam spot size, energy, and scanning accuracy are calibrated according to the equipment standard calibration procedure. The stage is tilted at 55°±1° and the WD adjustment is 6mm±0.1mm to lock the processing area. The processing frame is drawn according to the design blueprint and the size is set. Irradiation is carried out with a current of 50Pa±5Pa and an energy of 30Kev. The stress-strain field evolution of the thin film is analyzed by real-time image acquisition using SEM. The parameters are fine-tuned according to the strain rate of Ta film deformation of 0.005-0.02% / s. The scanning rate is adjusted in steps of 0.5-2μm / s, and the beam spot size is dynamically optimized from 5-15nm. The deformation rate is controlled at 0.05-0.2μm / s and the directional accuracy is ±1° until the Ta film stands up or reaches a bent shape. Then the irradiation is stopped. S600, advanced FIB deposition function: Move the platinum probe to the processing position, heat to 300-400℃ at 10-20℃ / min, draw the deposition area with a length of 3-8μm, width of 2-6μm, and depth of 1μm, with an accuracy of ±0.3μm. Set a current of 100-250PA and an energy of 30Kev to start deposition according to the area of ​​the pattern. Before deposition, argon gas is introduced into the chamber to remove oxygen impurities. The deposition rate is optimized and precisely controlled at 0.05-0.2μm / min based on the Pt deposition kinetic equation and finite element simulation of the electric field distribution. The surface morphology is monitored by atomic force microscopy for feedback control. The uniformity of platinum atom deposition distribution and thickness accuracy are monitored in real time by SEM energy distribution spectroscopy. Based on the Pt crystal growth model and thin film nucleation theory, the microstructure is verified by high-resolution transmission electron microscopy. The irradiation strategy is customized according to the thin film material characteristics and thickness range. Combined with the TSV process, the via layout is pre-planned to avoid interference at each stage of thin film folding. Vertical electrical interconnection is achieved through TSV to improve integration and performance.

2. The method for fabricating folded qubits in a superconducting quantum chip processor according to claim 1, characterized in that, In S100, the parameters for etching linewidth, spacing, depth, and pattern contour accuracy during substrate pretreatment and initial SiO2 patterning are set as follows: linewidth is 100-500nm based on the theoretical calculation of bit transmission linewidth and coupling strength; spacing is 200-800nm ​​based on the electromagnetic shielding and crosstalk suppression model; depth is strictly determined to be 100-300nm based on the subsequent deposition film thickness and etching process compatibility; and pattern contour accuracy is <±10nm.

3. The method for fabricating folded qubits in a superconducting quantum chip processor according to claim 1, characterized in that, In the S200 process, the thickness of the SiO2 film deposited during dielectric layer deposition and performance enhancement is 200-300 nm.

4. The method for fabricating folded qubits in a superconducting quantum chip processor according to claim 1, characterized in that, In the preparation of the S300 superconducting Josephson junction, the BE-Al film thickness is 95-105 nm and the TE-Al film thickness is 98-102 nm.

5. The method for fabricating folded qubits in a superconducting quantum chip processor according to claim 1, characterized in that, In the preparation of the S300 superconducting Josephson junction, the photoresist spin coating speed is 3000-5000 rpm and the thickness is 1-2 μm.

6. The method for fabricating folded qubits in a superconducting quantum chip processor according to claim 1, characterized in that, In the S400 process, the solution used for etching the lower SiO2 film using a wet etching process is a hydrofluoric acid HF solution.

7. The method for fabricating folded qubits in a superconducting quantum chip processor according to claim 1, characterized in that, In the S500, the electron beam current during the FIB irradiation film folding is 1-5 nA, and the ion beam current is 50-100 pA.

8. The method for fabricating folded qubits in a superconducting quantum chip processor according to claim 1, characterized in that, The thin film material characteristics involved in the advanced FIB deposition function in S600 are as follows: single layer includes Nb, Al, Ta, TiN; multilayer includes Nb / AlOx / Nb, Al / AlOx / Al.

9. The method for fabricating folded qubits in a superconducting quantum chip processor according to claim 1, characterized in that, In the advanced FIB deposition function of the S600, when the thickness is <100nm, the energy is reduced to 15-25Kev and the speed is increased to 1-3μm / s for fine-tuning. When the thickness is ≥300nm, the irradiation time is increased by 10-30min, and multi-segment irradiation is used in 3-5 segments, with the energy of each segment fine-tuned by ±5Kev.

10. A folded qubit fabrication process for a superconducting quantum chip processor, characterized in that, The specific steps of this processing technology are as follows: S100, Substrate Selection and Initial SiO2 Patterning: Using 12-inch and smaller silicon, SiC, or GaN wafers as substrates, the surface morphology and initial stress values ​​are measured using an atomic force microscope and stress tester. SiO2 patterns are etched using KrF excimer lithography. The linewidth is set to 100-500nm based on the theory of bit transmission linewidth and coupling strength. The spacing is set to 200-800nm ​​based on the electromagnetic shielding and crosstalk suppression model. The depth is determined to be 100-300nm according to subsequent processes. The pattern outline accuracy is <±10nm. S200, Dielectric Layer Deposition and Quality Leap: In the low temperature range of 80-100℃ of PECVD equipment, SiH4 with 50-150sccm as the main gas source and N2O with 5-15sccm as the dopant gas are used to excite plasma to deposit SiO2 film with 100-300W radio frequency power. The film thickness uniformity deviation is monitored by an optical interferometer to ensure that it is within ±5%. The deposition rate is 0.5-2nm / s. After depositing a 200-300nm thick film, the temperature is increased to 400-600℃ at 5-10℃ / min for annealing for 30-90min to reduce stress to ≤50MPa, eliminate micro-defects, and improve thermal budget and mechanical strength. S300, the fine shaping of Josephson junctions: Al / AlOx / Al Josephson junctions are fabricated in an electron beam evaporation chamber. Before depositing the BE-Al film, a Degas treatment at 150-200℃ for 30-60 min is performed to remove impurities. The deposition temperature is from room temperature to 150℃, and the deposition rate is 0.1-0.3 nm / s to deposit a 95-105 nm thick BE-Al film. The electron beam current is set at 10-30 mA, the accelerating voltage at 5-10 kV and monitored by a quartz crystal microbalance. The O2 flow rate is controlled at 5-15 sccm to oxidize and create a 10 nm AlOx insulating layer. Then, a 98-102 nm thick TE-Al film is deposited. The photoresist is spin-coated at 3000-5000 rpm to form a 1-2 μm thick film. After electron beam exposure and development, the BE and TE layers are etched by ion beam to form the junction. S400, a masterpiece of suspended film architecture: SiO2 film is suspended by wet etching with hydrofluoric acid HF solution at 20-25℃. The etching time depends on the film thickness and pattern. Through reaction kinetic model combined with in-situ optical microscopy monitoring, the etching is optimized in 30-90s. Fan-shaped regions are formed at a rate of 10-30nm / s with a radius of 50-150μm and a central angle of 30-60°±2°. The suspension accuracy is within ±10μm. S500, stereotactic folding of FIB irradiated film: The sample is clamped to a 6-inch vacuum fixture FIB stage with a clamping force of 50-100N, and the vacuum level is <10. -6 After Pa, the 1-5nA electron beam and 50-100pA ion beam are started. The stage is tilted at 55°±1° and the WD is adjusted to lock the processing area by 6mm±0.1mm. The processing frame is drawn according to the blueprint and the parameters are set for irradiation. SEM images are collected to analyze the stress-strain field evolution of the thin film. The strain rate of the Ta film is finely adjusted according to 0.005-0.02% / s, and the deformation rate is controlled at 0.05-0.2μm / s and the directional accuracy is ±1° until the Ta film reaches the target morphology. S600 represents a significant advancement in FIB deposition performance: A platinum probe is moved to the processing position to map the deposition area, which is 3-8 μm long, 2-6 μm wide, and 1 μm deep. Deposition is performed at a current of 100-250 PA and an energy of 30 KeV, depending on the area of ​​the pattern. Argon gas is introduced to remove oxygen impurities, and the deposition rate is controlled at 0.05-0.2 μm / min. Atomic force microscopy is used for monitoring and feedback control. Irradiation strategies are customized for films of different thicknesses based on their characteristics. For films with a thickness of <100 nm, energy reduction and speed increase are finely adjusted to shape the film. For films with a thickness of ≥300 nm, the irradiation time is increased in multiple stages for fine-tuning. Interconnects are planned using TSV technology to improve integration and electrical performance.

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