Dual path charge pump

Abstract

Examples of an improved charge pump are disclosed. In one example, a system includes a first charging path including a first stage to boost an input voltage and a second stage to boost a voltage received from the first stage of the first charging path; and a second charging path comprising a first stage for boosting an input voltage and a second stage for boosting a voltage received from the first stage of the second charging path; wherein an output of the second stage of the first charging path is coupled to the first stage of the second charging path, and an output of the second stage of the second charging path is coupled to the first stage of the first charging path.

Description

[0001] Priority declaration

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 427,398, filed on November 22, 2022, and entitled “Dual-Path Charge Pump With Cross-Feedback,” and U.S. Patent Application No. 18 / 109,397, filed on February 14, 2023, and entitled “Dual-Path Charge Pump.” Technical Field

[0003] An improved charge pump is disclosed that utilizes dual paths and cross-feedback between stages and paths. Background Art

[0004] Non-volatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(“the '130 patent”), which is incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which is a type of flash memory cell. Such a memory cell 110 is shown in FIG. 1 . Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12 with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16.

[0005] Memory cell 110 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on word line terminal 22, which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim (FN) tunneling from floating gate 20 to word line terminal 22.

[0006] The memory cell 110 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22 and a positive voltage on the source region 14. The electron flow will flow from the drain region 16 to the source region 14. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, the electrons will accelerate and become hot. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons will be injected through the gate oxide onto the floating gate 20.

[0007] The memory cell 110 is read by placing a positive read voltage on the drain region 16 and the word line terminal 22 (which turns on the portion of the channel region 18 below the word line terminal). If the floating gate 20 is positively charged (i.e., the electrons are erased), the portion of the channel region 18 below the floating gate 20 is also turned on, and current will flow through the channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below the floating gate 20 is mostly or completely turned off, and no current (or very little current) will flow through the channel region 18, which is sensed as a programmed state or a "0" state.

[0008] Table 1 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 110 for performing read operations, erase operations, and program operations:

[0009] Table 1: Operation of the flash memory cell 110 of FIG. 1

[0010] WL BL SL Read 2V-3V 0.6V-2V 0V Erase About 11V-13V 0V 0V programming 1V-2V 10.5μA-3μA 9V-10V

[0011] Other split gate memory cell configurations are known as other types of flash memory cells. For example, FIG. 2 depicts a quad-gate memory cell 210 that includes a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating gates, meaning that they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0012] Table 2 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 210 for performing read operations, erase operations, and program operations:

[0013] Table 2: Operation of the flash memory unit 210 of FIG. 2

[0014] WL / SG BL CG EG SL Read 1.0V-2V 0.6V-2V 0V-2.6V 0V-2.6V 0V Erase -0.5V / 0V 0V 0V / -8V 8V-12V 0V programming 1V 0.1μA-1μA 8V-11V 4.5V-9V 4.5V-5V

[0015] FIG3 depicts a tri-gate memory cell 310, which is another type of flash memory cell. Memory cell 310 is the same as memory cell 210 of FIG2, except that memory cell 310 does not have a separate control gate. Erase operations (thus erasing by using an erase gate) and read operations are similar to the operations of FIG2, except that no control gate bias is applied. Program operations are also completed without a control gate bias, and therefore, a higher voltage is applied on the source line during a programming operation to compensate for the lack of a control gate bias.

[0016] Table 3 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 310 for performing read operations, erase operations, and program operations:

[0017] Table 3: Operation of the flash memory unit 310 of FIG. 3

[0018] WL / SG BL EG SL Read 0.7V-2.2V 0.6V-2V 0V-2.6V 0V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 0.2μA-3μA 4.5V 7V-9V

[0019] FIG4 depicts a stacked gate memory cell 410, which is another type of flash memory cell. Memory cell 410 is similar to memory cell 110 of FIG1, except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be coupled to the word line) extends over floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection at the region between channel 18 and drain region 16, by electron flow from source region 14 toward drain region 16, and a read operation similar to memory cell 210 with a higher control gate voltage.

[0020] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 410 and the substrate 12 for performing read operations, erase operations, and program operations:

[0021] Table 4: Operation of the flash memory unit 410 of FIG. 4

[0022] CG BL SL Substrate Read 2V-5V 0.6V-2V 0V 0V Erase –8V to –10V / 0V FLT FLT 8V-10V / 15V-20V programming 8V-12V 3V-5V 0V 0V

[0023] The methods and devices described herein can be applied to other non-volatile memory technologies, such as but not limited to FINFET split-gate flash memory or stacked-gate flash memory, NAND flash memory, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapped in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge trapping) memory, CN (carbon tube) memory, OTP (two-level or multi-level one-time programmable) and CeRAM (correlated electron RAM), etc.

[0024] 5 depicts a block diagram of a prior art memory system 500. The memory 500 includes an array 501, a row decoder 502, a high voltage decoder 503, a column decoder 504, a bit line driver 505, an input circuit 506, an output circuit 507, a control logic component 508, and a bias generator 509. The memory system 500 also includes a high voltage generation block 510, which includes a charge pump 511, a charge pump regulator 512, and a high voltage level generator 513. The memory system 500 also includes a (program / erase or weight adjustment) algorithm controller 514, an analog circuit 515, a control engine 516 (which may include special functions such as arithmetic functions, activation functions, embedded microcontroller logic, but not limited thereto), a test control logic component 517, and an SRAM block 518 to store data such as intermediate data for input circuits (e.g., activation data) or output circuits (neuron output data) or data for programming (such as data for an entire row or multiple rows).

[0025] Array 501 includes rows and columns of non-volatile memory cells, such as memory cells 110, 210, 310, or 410 from Figures 1-4, respectively.

[0026] The input circuit 506 may include various circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time modulated pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter, a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 506 may implement one or more of normalization, linear or nonlinear up / down scaling functions, or arithmetic functions. The input circuit 506 may implement a temperature compensation function for the input level. The input circuit 506 may implement an activation function such as a ReLU or a sigmoid. The input circuit 506 may store digital activation data to be applied as an input signal or combined with an input signal during a programming or read operation. The digital activation data may be stored in a register. The input circuit 506 may include circuits for driving array terminals, such as CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers. The DAC may be used to convert the digital activation data into an analog input voltage to be applied to the array.

[0027] The output circuit 507 may include circuits such as ITV (current voltage circuit), ADC (analog-to-digital converter for converting neuron analog output into digital bits), AAC (analog-to-analog converter, such as current-voltage converter, logarithmic converter), APC (analog-to-pulse converter, analog-to-time modulated pulse converter), or any other type of converter. The output circuit 507 may convert the array output into activation data. The output circuit 507 may implement an activation function, such as a rectified linear activation function (ReLU) or sigmoid. The output circuit 507 may implement one or more of statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) for the neuron output. The output circuit 507 may implement a temperature compensation function for the neuron output or the array output (such as the bit line output) to keep the power consumption of the array approximately constant over a temperature range or to improve the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same over a temperature range. The output circuit 507 may include registers for storing output data.

[0028] Charge pump 511 must generate the high voltages required for erase and program operations, such as those shown in Tables 1-4 above, from a supply voltage typically between 1.5V and 3.0V.

[0029] FIG6 depicts a prior art charge pump 600. Prior art charge pump 600 includes i+1 stages, which are stage 601-0 (stage 0), 601-1 (stage 1), ..., 601-(i-1) (pre-output stage) and 601-i (output stage). Prior art charge pump 600 also includes dual paths, specifically, path 601 and path 651. Each stage boosts the input voltage it receives and outputs the boosted voltage to the next stage as the input voltage of the next stage, or in the case of stage 601-i, as the output Vout of charge pump 600. Paths 601 and 651 operate out of phase with each other so that the output Vout is always at the maximum boost voltage.

[0030] FIG. 7 depicts an example of a clock timing diagram of clock signals CK1, CK2, CK3, and CK4 used in charge pump 600. Clock signals CK1, CK2, CK3, and CK4 are generated by a common clock signal represented as CLK. Clock signals CK2 and CK3 are complements of each other, and clock signals CK1 and CK4 are complements of each other. Therefore, CK2 and CK3 are complementary clock signals, and CK1 and CK4 are complementary clock signals. The corresponding edges of clock signals CK2 and CK3 are delayed by an amount Tdelay1 from the corresponding first edge of the common clock signal CLK. The corresponding edges of clock signals CK1 and CK4 are delayed by an amount Tdelay2 from the corresponding second edge of the common clock signal CLK.

[0031] FIG8 depicts two example stages for one of the paths in the charge pump 600, shown here as stage N and stage N+1. Each stage in each path in the charge pump 600 performs a boost operation in the same manner, which will be explained with reference to stage N+1. Node C is the input voltage received by stage N+1. CK3 and CK4 are clock signals as shown in FIG7 and are coupled to capacitors 804 and 805, respectively. When CK3 goes high, the voltage on the top plate of capacitor 804 (i.e., node C) increases by the amount of voltage that CK3 increases. As shown in FIG7, there is a delay period Tdelay2 between the rising edge of CK3 and the rising edge of CK4, and this delay will precharge node B through MB_T2 with the higher potential on node C to VOUT minus V of MB_T2. TH When CK4 goes high, the voltage on the top plate of capacitor 805 (i.e., node B) is raised by the amount of voltage that CK4 has increased. Therefore, due to the precharge cycle and the boost of CK4, the potential on node B is now extremely high. The higher potential on node B helps transfer charge from node C to VOUT through transistor 804. Transistor 806 can be enabled to place VOUT at an initial voltage of VDD, or it can remain enabled throughout the operation of charge pump 600 to provide a lower limit on the value of VOUT (VOUT will always be equal to or exceed VDD).

[0032] One disadvantage of the prior art charge pump 600 is that the body effect will increase the threshold voltage V of transistors 801 (MB_T1), 802 (MS_T1), 803 (MB_T2), and 804 (MS_T2). TH Given the configuration of charge pump 600, the voltage supplied to the gates of those transistors may not be large enough to exceed the increased V TH and fully turn on those transistors. This problem becomes more pronounced with each subsequent stage.

[0033] There is a need for an improved charge pump. Summary of the invention

[0034] An improved charge pump is disclosed. The charge pump uses a dual-path topology. Cross-feedback is provided between the paths so that a high voltage generated by a stage (N+1) in one path is applied to the gate of a transistor of a previous stage (N) in another path. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG. 1 depicts a prior art split-gate flash memory cell.

[0036] FIG. 2 depicts another prior art split gate flash memory cell.

[0037] FIG. 3 depicts another prior art split gate flash memory cell.

[0038] FIG. 4 depicts another prior art split gate flash memory cell.

[0039] FIG. 5 depicts a prior art memory system.

[0040] FIG. 6 depicts a prior art charge pump.

[0041] FIG. 7 depicts a clocking scheme for the prior art charge pump of FIG. 6 .

[0042] FIG. 8 depicts a simplified diagram of the prior art charge pump of FIG. 6 .

[0043] Fig. 9 A charge pump is depicted.

[0044] Fig.10 Describes the use Fig. 9 The timing scheme of the charge pump.

[0045] Fig.11 A simplified diagram of the charge pump of FIG. 6 is depicted. DETAILED DESCRIPTION

[0046] Fig. 9A charge pump 900 is depicted. The charge pump 900 includes i+1 stages, which are stages 901-0 (stage 0), 901-1 (stage 1), ..., 901-(i-1) (pre-output stage) and 901-i (output stage). The charge pump 900 also includes dual paths, specifically, paths 901 and 951. Each stage in the path can be referred to as a boost stage. Each boost stage boosts the input voltage it receives and outputs the boosted voltage to the next stage as the input voltage of the next stage, or in the case of stage 901-i, as the output Vout of the charge pump 900. Paths 901 and 951 operate out of phase with each other so that the output Vout is always at the maximum boost voltage. Fig.10 An example of a clock timing diagram for CK1, CK2, CK3, and CK4 used in the charge pump 900 is depicted. The clock signals CK1, CK2, CK3, and CK4 are generated by a common clock signal represented as CLK. The clock signals CK1 and CK2 are complements of each other, and the clock signals CK3 and CK4 are complements of each other. The respective first edges of the clock signals CK1 and CK2 are delayed from the respective first edges of the common clock signal CLK by an amount Tdelay1, and the respective second edges of the clock signals CK1 and CK2 are aligned with the respective second edges of the common clock signal CLK. The respective first edges of the clock signals CK3 and CK4 are aligned with the respective first edges of the common clock signal CLK, and the respective second edges of the clock signals CK3 and CK4 are delayed from the respective second edges of the common clock signal CLK by an amount Tdelay2. Compared to the prior art charge pump 600, the charge pump 900 improves the body effect, as described below with reference to Fig.11 discussed in more detail.

[0047] Fig.11 Depicted are three example stages for paths 901 and 951 in charge pump 900: stages N, N+1, and N+2 (where N ranges from 0 to (i-1), corresponding to Fig. 9 901-0, ..., 901-i in the charge pump 900). The corresponding boost stages in the corresponding paths in the charge pump 900 perform boost operations in the same manner, which will be explained with reference to the boost stage corresponding to stage N in path 901. Node D is the input voltage received by stage N+1 in path 901. CK2 and CK3 are as follows: Fig.10 , and are coupled to capacitors 1105 and 1106, respectively. When CK2 goes high, the voltage on the top plate of capacitor 1105 (i.e., node D) increases by the amount of voltage that CK2 increases. Fig.10 As shown in FIG, there is a delay period Tdelay2 between the rising edge of CK2 and the rising edge of CK3, and this delay will use the higher potential on node D to precharge node A through MB_T2 to OUT2 minus the V of MB_T2. THThereafter, CK3 goes high, and the voltage on the top plate of capacitor 1106 (i.e., node A) is boosted by the amount of voltage that CK3 increased. Therefore, the potential at node A is now equal to the amount of voltage boosted from CK3 plus the amount of voltage from the precharge time, and charge can now be transferred more efficiently from node D to node E due to the boosted voltage on node A.

[0048] Referring back to FIG. 8 , transistor 806 may be enabled to place VOUT at an initial voltage of VDD, or it may remain enabled throughout operation of charge pump 600 to provide a lower limit on the value of VOUT (VOUT will always equal or exceed VDD).

[0049] Stage N+2 in path 901 or charge pump 900 includes native NMOS transistor 1103 (first native NMOS transistor) and native NMOS transistor 1104 (second native NMOS transistor) having a lower threshold voltage than NMOS transistor 806 used in prior art charge pump 600. Using native NMOS transistors 1103 and 1104 instead of NMOS transistors allows a high initial voltage to be placed on OUT1 and similar nodes in other stages, which allows charge pump 900 to reach its target faster. In addition, signal VGI provides a gating signal to native NMOS transistor 1103 and can turn off native NMOS transistor 1103 immediately after charge pump 900 is activated to reduce the chance of significant leakage due to the low threshold voltage of native NMOS transistor 1103. Native NMOS transistor 1104 is provided to reduce stress on native NMOS transistor 1103 because when charge pump 900 is activated, the voltage difference between the source and gate of native NMOS transistor 1103 will be relatively large (HV-0V), where HV is the high voltage generated by the charge pump.

[0050] Native NMOS transistors 1153 (third native NMOS transistor) and 1154 (fourth native NMOS transistor) play the same role in stage N+1 of path 951 as native NMOS transistors 1103 and 1104 in stage N+1 of path 901. Fig. 9 and Fig.11 As shown, the other pumping stages of charge pump 900 include native NMOS transistors that perform the same function.

[0051] To overcome the body effect on boost transistors 1101 (MB_T2) (first boost transistor) and 1151 (MB_B2) (second boost transistor), the charge pump 900 applies a higher voltage to the gates of these transistors than in the prior art charge pump 600. Specifically, the charge pump 900 uses the output voltage of path 951 (node ​​OUT2) from stage N+21 as the gate voltage of transistor 1101 (MB_T2) in stage N+1 of path 901, and uses the output voltage of path 901 (node ​​OUT1) from stage N+2 as the gate voltage of transistor 1151 (MB_B2) in stage N+1 of path 951. Due to the boost provided by the subsequent stage, the gate voltages of transistors 1101 (MB_T2) and 1151 (MB_B2) are greater than in the prior art charge pump 600, and node A and node B can be precharged to higher levels than in the prior art charge pump 600, respectively, which means that the gate voltages of transistors 1102 (MS_T2) and 1152 (MS_B2) will be higher than in the prior art charge pump 600 after being boosted by CK3 and CK1, respectively, so that they can handle the increased V after the body effect. TH Therefore, the voltage boost in charge pump 900 is more efficient than the voltage boost in prior art charge pump 600. Charge pump 900 is capable of providing a higher output voltage than charge pump 600, with higher efficiency and lower process temperature variation.

[0052] The boost stage of the charge pump 900 is operable to perform a method, the method comprising: boosting a first voltage (voltage at node D) by a first stage (stage N+1) in a first charging path (path 901) to generate a second voltage (voltage at node E); boosting the second voltage by a second stage (stage N+2) in the first charging path (path 901) to generate a third voltage (voltage OUT1); boosting a fourth voltage (voltage at node C) by a first stage (stage N+1) in a second charging path (path 951) to generate a fifth voltage (voltage at node F); boosting a fourth voltage (voltage at node C) by a first stage (stage N+1) in a second charging path (path 951) to generate a fifth voltage (voltage at node F); boosting a fourth voltage (voltage at node C) by a first stage (stage N+2) in the second charging path (path 951) to generate a fifth voltage (voltage at node F); The second stage (stage N+2) boosts the fifth voltage to generate a sixth voltage (voltage OUT2); applies the third voltage to the first stage of the second charging path; and applies the sixth voltage to the first stage of the first charging path; wherein applying the sixth voltage to the first stage of the first charging path includes: applying the sixth voltage to the gate of the first boost transistor (1101) in the first stage of the first charging path, and applying the third voltage to the first stage of the second charging path includes: applying the third voltage to the gate of the second boost transistor (1151) in the first stage of the second charging path. The method may also include: applying a first clock signal (CK3) to the first stage of the first charging path and the second stage of the second charging path; applying a second clock signal (CK4) to the first stage of the first charging path and the second stage of the second charging path; applying a third clock signal (CK1) to the first stage of the second charging path and the second stage of the first charging path; and applying a fourth clock signal (CK2) to the first stage of the second charging path and the second stage of the first charging path.

[0053] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intermediate material, element or space is provided between) and "indirectly on" (intermediate material, element or space is provided between). Similarly, the term "adjacent" includes "directly adjacent" (no intermediate material, element or space is provided between) and "indirectly adjacent" (intermediate material, element or space is provided between), "mounted to" includes "directly mounted to" (no intermediate material, element or space is provided between) and "indirectly mounted to" (intermediate material, element or space is provided between), and "electrically coupled to" includes "directly electrically coupled to" (no intermediate material or element electrically connecting the elements together between) and "indirectly electrically coupled to" (intermediate material or element electrically connecting the elements together between). For example, forming an element "above a substrate" may include directly forming the element on the substrate without intermediate materials / elements between the two, and indirectly forming the element on the substrate with one or more intermediate materials / elements between the two.

Claims

1. A system, comprising: a first charging path including a first stage for boosting an input voltage and a second stage for boosting a voltage received from the first stage of the first charging path; and a second charging path including a first stage for boosting an input voltage and a second stage for boosting a voltage received from the first stage of the second charging path; The output of the second stage of the first charging path is coupled to the first stage of the second charging path, and the output of the second stage of the second charging path is coupled to the first stage of the first charging path.

2. The system of claim 1, wherein the output of the second stage of the second charging path is applied to a gate of a first boost transistor in the first stage of the first charging path.

3. The system of claim 2, wherein the output of the second stage of the first charging path is applied to a gate of a second boost transistor in the first stage of the second charging path. The system of claim 3 , wherein the second boost transistor is an NMOS transistor. The system of claim 4 , wherein the first boost transistor is an NMOS transistor. 6 . The system of claim 3 , wherein the first stage of the first charging path and the second stage of the second charging path receive a first clock signal and a second clock signal. 7 . The system of claim 6 , wherein the first stage of the second charging path and the second stage of the first charging path receive a third clock signal and a fourth clock signal.

8. The system of claim 7, wherein the first clock signal and the second clock signal are complementary clock signals.

9. The system of claim 8, wherein the third clock signal and the fourth clock signal are complementary clock signals.

10. The system of claim 1, wherein the second stage in the first charging path comprises: a first native NMOS transistor comprising a first terminal coupled to a power supply voltage, a second terminal, and a gate for receiving a control signal; and A second native NMOS transistor includes a first terminal coupled to the second terminal of the first native NMOS transistor, a second terminal coupled to the output of the second stage of the first charging path, and a gate coupled to the supply voltage.

11. The system of claim 10, wherein the second stage in the second charging path comprises: a third native NMOS transistor, the third native NMOS transistor comprising a first terminal coupled to a power supply voltage, a second terminal, and a gate for receiving a control signal; and A fourth native NMOS transistor includes a first terminal coupled to the second terminal of the first native NMOS transistor, a second terminal coupled to the output of the second stage of the second charging path, and a gate coupled to the supply voltage.

12. A method comprising: boosting a first voltage by a first stage in a first charging path to generate a second voltage; boosting the second voltage by a second stage in the first charging path to generate a third voltage; boosting the fourth voltage by the first stage in the second charging path to generate a fifth voltage; boosting the fifth voltage by a second stage in the second charging path to generate a sixth voltage; applying the third voltage to the first stage of the second charging path; and applying the sixth voltage to the first stage of the first charging path.

13. The method of claim 12, wherein applying the sixth voltage to the first stage of the first charging path comprises: The sixth voltage is applied to a gate of a first boosting transistor in the first stage of the first charging path.

14. The method of claim 13, wherein applying the third voltage to the first stage of the second charging path comprises: The third voltage is applied to a gate of a second boosting transistor in the first stage of the second charging path. The method of claim 14 , wherein the second boost transistor is an NMOS transistor. The method of claim 15 , wherein the first boost transistor is an NMOS transistor.

17. The method according to claim 16, comprising: applying a first clock signal to the first stage of the first charging path and the second stage of the second charging path; as well as A second clock signal is applied to the first stage of the first charging path and the second stage of the second charging path.

18. The method according to claim 17, comprising: applying a third clock signal to the first stage of the second charging path and the second stage of the first charging path; as well as A fourth clock signal is applied to the first stage of the second charging path and the second stage of the first charging path. The method of claim 18 , wherein the first clock signal and the second clock signal are complementary clock signals.

20. The method of claim 19, wherein the third clock signal and the fourth clock signal are complementary clock signals.

21. A system, comprising: A first charging path, the first charging path comprising (i+1) boost stages, where i>1; and a second charging path, the second charging path comprising (i+1) boost stages; wherein the first charging path and the second charging path receive an input voltage and generate an output voltage greater than the input voltage; and The output of the boost stage (N+1) of the first charging path is coupled to the boost stage N of the second charging path, and the output of the boost stage (N+1) of the second charging path is coupled to the boost stage N of the first charging path, wherein 1≤N≤i.

22. The system according to claim 21, comprising: a first clock signal and a second clock signal, the first clock signal and the second clock signal being provided to the first charging path, wherein the first clock signal and the second clock signal are complementary clock signals; and A third clock signal and a fourth clock signal are provided to the second charging path, wherein the third clock signal and the fourth clock signal are complementary clock signals.

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