Imaging element and electronic apparatus

Abstract

The present technology relates to an imaging element and an electronic device capable of suppressing the generation of a white point or a dark current. The imaging element includes a photoelectric conversion section that converts light into electric charges, an accumulation section that temporarily accumulates the electric charges, and a transfer section that transfers the electric charges to the accumulation section. The imaging element further includes an inter-pixel isolation portion establishing isolation between the pixels, an element isolation portion of the isolation element, and a plurality of transistors arranged around the transfer portion in a plan view. In plan view, in each of the plurality of transistors, there is a region in which at least one side of the transistor overlaps the inter-pixel isolation portion, and a side opposite to the one side includes a region overlapping the element isolation portion. The present technology can be applied, for example, to an imaging element having a plurality of accumulation sections.

Description

Technical Field

[0001] The present technology relates to an imaging element and an electronic device, and, for example, to an imaging element and an electronic device configured to allow realization of higher quality images. Background Art

[0002] Generally, imaging elements such as CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCD (Charge Coupled Devices) are widely used in digital still cameras, digital video cameras, etc. It is desirable to improve the characteristics of imaging elements, and, for example, it is desirable to expand the dynamic range. Patent document 1 proposes a method for expanding the dynamic range by including a plurality of accumulation capacitance elements that can accumulate charges overflowing from a photodiode.

[0003] An imaging element (image sensor) is also proposed, which includes a mechanism for switching the conversion efficiency of a floating diffusion (FD) arranged in each pixel (refer to patent document 2). In the technology according to patent document 2, based on a general CMOS (complementary metal oxide semiconductor) image sensor, a gate for switching a first FD and a second FD having a higher capacitance than the first FD is arranged. In addition, patent document 2 also includes a description of the following. In the case of switching to high conversion efficiency, the gate is turned off to minimize the parasitic capacitance of the first FD. On the contrary, in the case of switching to low conversion efficiency, the gate is turned on, and the first FD and the second FD are connected to maximize the parasitic capacitance. Citation List Patent Literature

[0004] Patent Document 1: JP 2006-245522A Patent Document 2: JP 2014-112580A Summary of the invention Technical issues

[0005] In recent years, pixel miniaturization has been advanced. As a result, the arrangement area of ​​transistors constituting one pixel has also become smaller, and it has become difficult to arrange transistors in a size that can sufficiently obtain transistor characteristics.

[0006] The present technology has been made in view of such circumstances, and can achieve miniaturization of pixels without degrading transistor characteristics. Problem Solution

[0007] An imaging element of one aspect of the present technology is an imaging element including a photoelectric conversion unit that converts light into electric charge, an accumulation unit that temporarily accumulates electric charge, and a transmission unit that transfers the electric charge to the accumulation unit. The imaging element also includes an inter-pixel isolation unit that establishes isolation between pixels, an element isolation unit that isolates the element, and a plurality of transistors arranged around the transmission unit in a plan view. In the plan view, in each of the plurality of transistors, there is a region where at least one side of the transistor overlaps with the inter-pixel isolation unit, and the side opposite to the one side includes a region that overlaps with the element isolation unit.

[0008] An electronic device of one aspect of the present technology is an electronic device including an imaging element. The imaging element includes a photoelectric conversion unit that converts light into electric charge, an accumulation unit that temporarily accumulates electric charge, and a transmission unit that transfers the electric charge to the accumulation unit. The imaging element also includes an inter-pixel isolation unit that establishes isolation between pixels, an element isolation unit of the isolation element, and a plurality of transistors arranged around the transmission unit in a plan view. In the plan view, in each of the plurality of transistors, there is a region in which at least one side of the transistor overlaps with the inter-pixel isolation unit, and the side opposite to the one side includes a region overlapping with the element isolation unit. The electronic device also includes a processing unit that processes a signal from the imaging element.

[0009] The imaging element of the present technical aspect includes a photoelectric conversion unit that converts light into electric charge, an accumulation unit that temporarily accumulates electric charge, and a transfer unit that transfers the electric charge to the accumulation unit. The imaging element also includes an inter-pixel isolation unit that establishes isolation between pixels, an element isolation unit that isolates the element, and a plurality of transistors arranged around the transfer unit in a plan view. In the imaging element, in a plan view, in each of the plurality of transistors, there is a region where at least one side of the transistor overlaps with the inter-pixel isolation unit, and the side opposite to the one side includes a region overlapping with the element isolation unit.

[0010] An electronic device according to the present technical aspect includes an imaging element.

[0011] It should be noted that the electronic device may be an independent device or an internal module included in a device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing a configuration example of an embodiment of an imaging device to which the present technology is applied. Figure 2 is a diagram showing an example of a circuit configuration of a pixel. Figure 3 It is a diagram for explaining the operation of a pixel. Figure 4 It is a diagram for explaining the operation of a pixel. Figure 5 A diagram showing an example of a planar structure of a pixel in the first embodiment. Figure 6 A diagram showing an example of a planar structure of a pixel in the first embodiment. Figure 7 A diagram showing an example of a cross-sectional structure of a pixel in the first embodiment. Figure 8 A diagram showing an example of a cross-sectional structure of a pixel in the first embodiment. Fig. 9 A diagram showing an example of a planar structure of a pixel in the second embodiment. Fig.10 A diagram showing an example of a planar structure of a pixel in the third embodiment. Fig.11 A diagram showing an example of a cross-sectional structure of a pixel in the third embodiment. Fig.12 It is a diagram for explaining the position of the contact portion. Fig.13 It is a diagram showing an example of a circuit configuration of a pixel in the fourth embodiment. Fig.14 A diagram showing an example of a planar structure of a pixel in the fourth embodiment. Fig.15 It is a diagram showing an example of the circuit configuration of a pixel in the fifth embodiment. Fig.16 A diagram showing an example of a planar structure of a pixel in the fifth embodiment. Fig.17 A diagram showing an example of a planar structure of a pixel in the fifth embodiment. Fig.18 is a diagram showing an example of a planar configuration of a pixel. Fig.19 This is a diagram for explaining the position where a strong electric field appears. Fig. 20 It is a diagram for explaining the position where a strong electric field appears. Fig.21 It is a diagram for explaining the position where a strong electric field appears. Fig. 22 A diagram showing an example of a cross-sectional structure of a pixel in the sixth embodiment. Fig.23 A diagram showing an example of a cross-sectional structure of a pixel in the sixth embodiment. Fig.24 A diagram showing an example of a cross-sectional structure of a pixel in the sixth embodiment. Fig.25 It is a diagram for explaining the depth of the element isolation portion. Fig.26 A diagram showing an example of a cross-sectional structure of a pixel in the seventh embodiment. Fig. 27A diagram showing an example of a cross-sectional structure of a pixel in the seventh embodiment. Fig.28 A diagram showing an example of a cross-sectional structure of a pixel in the seventh embodiment. Fig.29 A diagram showing an example of a cross-sectional structure of a pixel in the eighth embodiment. Fig.30 A diagram showing an example of a cross-sectional structure of a pixel in the eighth embodiment. Fig.31 A diagram showing an example of a cross-sectional structure of a pixel in the ninth embodiment. Fig.32 A diagram showing an example of a cross-sectional structure of a pixel in the ninth embodiment. Fig.33 A diagram for explaining the structure of an element isolation unit is shown. Fig.34 A diagram for explaining the structure of an inter-pixel partition is shown. Fig.35 A diagram for explaining the influence of dark current is shown. Fig.36 A diagram for explaining a method of suppressing dark current is shown. Fig.37 It is a diagram showing an example of a circuit configuration of a pixel in the tenth embodiment. Fig.38 A diagram for explaining the operation of a pixel is shown. Fig.39 FIG. 1 is a diagram showing another circuit structure example of a pixel in the tenth embodiment. Fig.40 A diagram showing an example of a cross-sectional structure of a pixel in the tenth embodiment. Fig.41 A diagram showing an example of a circuit configuration of a pixel in the 11th embodiment. Fig.42 A diagram showing an example of a cross-sectional structure of a pixel in the 11th embodiment. Fig.43 is a diagram showing another circuit structure example of a pixel in the 11th embodiment. Fig.44 FIG. 1 is a diagram showing another cross-sectional structure example of a pixel in the 11th embodiment. Fig.45 is a diagram showing another circuit structure example of a pixel in the 11th embodiment. Fig.46 FIG. 1 is a diagram showing another cross-sectional structure example of a pixel in the 11th embodiment. Fig.47 A diagram is shown for explaining where dark current may occur. Fig.48FIG. 1 is a diagram showing another planar structure example of a pixel in the twelfth embodiment. Fig.49 FIG. 1 is a diagram showing another cross-sectional structure example of a pixel in the twelfth embodiment. Fig.50 FIG. 1 is a diagram showing another planar structure example of a pixel in the twelfth embodiment. Fig.51 FIG. 1 is a diagram showing another cross-sectional structure example of a pixel in the twelfth embodiment. Fig.52 FIG. 1 is a diagram showing another planar structure example of a pixel in the 13th embodiment. Fig.53 FIG. 1 is a diagram showing another planar structure example of a pixel in the fourteenth embodiment. Fig.54 This is a diagram showing an example of a planar structure of a pixel in the case where the fifth embodiment and the twelfth embodiment are combined. Fig.55 is a diagram showing another circuit configuration example of a pixel in the 15th embodiment. Fig.56 is a diagram showing another cross-sectional structure example of a pixel in the sixteenth embodiment. Fig.57 is a diagram showing another cross-sectional structure example of a pixel in the sixteenth embodiment. Fig.58 A diagram showing an example of a circuit configuration of a pixel in the seventeenth embodiment. Fig.59 A diagram showing an example of a planar structure of a pixel in the seventeenth embodiment. Fig.60 A diagram showing an example of a cross-sectional structure of a pixel in the seventeenth embodiment. Fig.61 A diagram showing an example of a cross-sectional structure of a pixel in the seventeenth embodiment. Fig.62 A diagram showing an example of a cross-sectional structure of a pixel in the seventeenth embodiment. Fig.63 A diagram showing an example of a cross-sectional structure of a pixel in the seventeenth embodiment. Fig.64 is a diagram showing another circuit structure example of a pixel in the 17th embodiment. Fig.65 is a diagram showing another planar structure example of a pixel in the 17th embodiment. Fig.66 FIG. 1 is a diagram showing another example of the cross-sectional structure of a pixel in the seventeenth embodiment. Fig.67 FIG. 1 is a diagram showing another example of the cross-sectional structure of a pixel in the seventeenth embodiment. Fig.68 FIG. 1 is a diagram showing another example of the cross-sectional structure of a pixel in the seventeenth embodiment. Fig.69 FIG. 1 is a diagram showing another example of the cross-sectional structure of a pixel in the seventeenth embodiment. Fig.70 A diagram showing an example of a planar structure of a pixel in the eighteenth embodiment. Fig.71 is a diagram showing another planar structure example of a pixel in the 18th embodiment. Fig.72 is a diagram showing another planar structure example of a pixel in the 18th embodiment. Fig.73 1 is a diagram showing an example of a cross-sectional structure of a portion related to pixel connection. Fig.74 A diagram showing an example of a planar structure of a pixel in the 19th embodiment. Fig.75 A diagram showing an example of a cross-sectional structure of a pixel in the 19th embodiment. Fig.76 is a diagram showing another cross-sectional structure example of a pixel in the 19th embodiment. Fig.77 is a diagram showing another cross-sectional structure example of a pixel in the 19th embodiment. Fig.78 is a diagram showing another cross-sectional structure example of a pixel in the 19th embodiment. Fig.79 is a diagram showing another cross-sectional structure example of a pixel in the 19th embodiment. Fig.80 is a diagram showing another cross-sectional structure example of a pixel in the 19th embodiment. Fig.81 A diagram showing an example of a planar structure of a pixel in the 20th embodiment. Fig.82 FIG. 2 is a diagram showing another planar structure example of a pixel in the 20th embodiment. Fig.83 FIG. 2 is a diagram showing another planar structure example of a pixel in the 20th embodiment. Fig.84 FIG. 1 is a diagram showing another cross-sectional structure example of a pixel in the 20th embodiment. Fig.85 FIG. 2 is a diagram showing another planar structure example of a pixel in the 20th embodiment. Fig.86 FIG. 1 is a diagram showing another cross-sectional structure example of a pixel in the 20th embodiment. Fig.87FIG. 2 is a diagram showing another planar structure example of a pixel in the 20th embodiment. Fig.88 FIG. 1 is a diagram showing another cross-sectional structure example of a pixel in the 20th embodiment. Fig.89 is a diagram showing a configuration example of an electronic device. Fig.90 is a diagram showing a schematic configuration example of an endoscopic surgery system. Fig.91 is a block diagram showing an example of the functional configuration of a camera head and a camera control unit (CCU). Fig.92 is a block diagram showing a schematic configuration example of a vehicle control system. Fig.93 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0013] Modes for carrying out the present technology (hereinafter referred to as embodiments) will be described below.

[0014] <Configuration Example of Imaging Device> Figure 1 A configuration example in an embodiment of an imaging device to which the present technology is applied is shown.

[0015] Figure 1 The imaging device 1 has a pixel array unit 3 in which pixels 2 are arranged in a two-dimensional array and a peripheral circuit unit around it. The peripheral circuit unit includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0016] The pixel 2 has a photodiode as a photoelectric conversion element and a plurality of pixel transistors, such as a transfer transistor, a selection transistor, a reset transistor, and an amplifier transistor, and includes a MOS transistor.

[0017] The control circuit 8 receives input clocks and data to issue commands such as operation modes, and outputs data such as internal information of the imaging device 1. That is, the control circuit 8 generates clock signals and control signals based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock as the basis for the operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc. The control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0018] The vertical drive circuit 4 includes, for example, a shift register, selects a predetermined pixel drive line 10, and supplies a pulse for driving the pixel 2 to the selected pixel drive line 10, so as to drive the pixel 2 in a row unit. That is, the vertical drive circuit 4 selectively scans each pixel 2 of the pixel array unit 3 sequentially in the vertical direction in a row unit, and supplies a pixel signal based on a signal charge generated according to the amount of light received in the photoelectric conversion portion of each pixel 2 to the column signal processing circuit 5 through the vertical signal line 9.

[0019] The column signal processing circuit 5 is arranged for each column of pixels 2, and performs signal processing such as noise removal on the signal output from a row of pixels 2 for each pixel column. For example, the column signal processing circuit 5 performs CDS (correlated double sampling) or DDS (double data sampling) signal processing for removing fixed pattern noise unique to pixels, AD conversion, and the like.

[0020] The horizontal drive circuit 6 includes, for example, a shift register, and sequentially selects the respective column signal processing circuits 5 by sequentially outputting horizontal scanning pulses, so that pixel signals are output from the respective column signal processing circuits 5 to the horizontal signal lines 11 .

[0021] The output circuit 7 performs signal processing on the signals sequentially supplied from the column signal processing circuits 5 through the horizontal signal line 11, and outputs the resultant signals. The output circuit 7 performs only buffering in some cases, and performs black level adjustment, column difference correction, various digital signal processing, etc. in other cases. The input / output terminal 13 exchanges signals with the outside.

[0022] The imaging device 1 configured as above is referred to as a column AD type CMOS image sensor in which a column signal processing circuit 5 that performs CDS processing or DDS processing and AD conversion processing is arranged on each pixel column.

[0023] <Circuit Configuration Example of Pixel> The configuration of the unit pixel arranged in the pixel array unit 3 will be described. The configuration of the unit pixel arranged in the pixel array unit 3 is, for example, as follows: Figure 2 It should be noted that Figure 1 The corresponding part of the situation is in Figure 2 The same figure marks are given in the figure, and their descriptions are appropriately omitted.

[0024] The pixel 2 as a unit pixel has a photoelectric conversion portion 51, a first transfer transistor 52, a first FD (floating diffusion) portion 53, a second transfer transistor 54, a second FD portion 55, a third transfer transistor 56, a third FD portion 57, a reset transistor 58, an amplification transistor 59 and a selection transistor 60.

[0025] For the pixel 2, for example, a plurality of drive lines are wired for each pixel row as the pixel drive line 10. In addition, a drive signal TRG, a drive signal FDG, a drive signal FCG, a drive signal RST, and a drive signal SEL are respectively supplied from the vertical drive circuit 4 to the first transfer transistor 52, the second transfer transistor 54, the third transfer transistor 56, the reset transistor 58, and the selection transistor 60 through the plurality of drive lines.

[0026] These drive signals are pulse signals, which are in a valid state when they have a high level (e.g., power supply voltage VDD), and in an invalid state when they have a low level (e.g., negative potential). That is, when each of the drive signals TRG to the drive signal SEL is set to a high level, the transistor as its supply destination becomes a conductive state, i.e., an on state. When each drive signal is set to a low level, the transistor as its supply destination becomes a non-conductive state, i.e., an off state.

[0027] The photoelectric conversion unit 51 includes, for example, a PN junction photodiode. The photoelectric conversion unit 51 receives incident light and performs photoelectric conversion, thereby accumulating charges obtained thereby.

[0028] The first transfer transistor 52 is arranged between the photoelectric conversion portion 51 and the first FD portion 53. A drive signal TRG is supplied to a gate electrode of the first transfer transistor 52. When the drive signal TRG becomes a high level, the first transfer transistor 52 is turned on, and the charge accumulated in the photoelectric conversion portion 51 is transferred to the first FD portion 53 through the first transfer transistor 52.

[0029] The first FD portion 53 , the second FD portion 55 , and the third FD portion 57 are each a floating diffusion region called a floating diffusion portion, and function as an accumulation portion that temporarily accumulates transferred charges and charges overflowing from the photoelectric conversion portion 51 .

[0030] The second transfer transistor 54 is arranged between the first FD portion 53 and the second FD portion 55. A drive signal FDG is supplied to a gate electrode of the second transfer transistor 54. When the drive signal FDG becomes a high level, the second transfer transistor 54 is turned on, and the charge from the first FD portion 53 is transferred to the second FD portion 55 through the second transfer transistor 54.

[0031] Since the second transfer transistor 54 is turned on, the region for accumulating charges becomes the region obtained by combining the first FD portion 53 and the second FD portion 55, and the conversion efficiency when converting the charges generated by the photoelectric conversion portion into voltage can be switched. The second transfer transistor 54 serves as a conversion efficiency switching transistor that switches the conversion efficiency.

[0032] The third transfer transistor 56 is arranged between the second FD portion 55 and the third FD portion 57. A drive signal FCG is supplied to a gate electrode of the third transfer transistor 56. When the drive signal FCG becomes a high level, the third transfer transistor 56 is turned on, and the charge from the second FD portion 55 is transferred to the third FD portion 57 through the third transfer transistor 56.

[0033] Due to the turning on of the third transfer transistor 56, the region for accumulating charges becomes a region obtained by combining the first FD portion 53, the second FD portion 55, and the third FD portion 57, and the conversion efficiency when converting the charges generated by the photoelectric conversion portion into a voltage can be switched. The third transfer transistor 56 acts as a conversion efficiency switching transistor that switches the conversion efficiency.

[0034] It is also possible to adopt a structure in which a metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitor element is connected to either or both of the second FD portion 55 and the third FD portion 57. The MIM capacitor element is a trench capacitor and has, for example, a U-shaped three-dimensional structure, and is therefore configured to be able to obtain a relatively high capacitance with a smaller mounting area. Different capacitor elements other than the MIM capacitor element can also be used. For example, the capacitor element can be a metal oxide metal (MetalOxide Metal, MOM) capacitor element, a Poly-Poly capacitor element (the relative electrodes of the capacitor element all include polysilicon) or an additional capacitor including a parasitic capacitor formed by an interconnection portion.

[0035] The reset transistor 58 is connected between the power supply VDD and the third FD portion 57. The drive signal RST is supplied to the gate electrode of the reset transistor 58. When the drive signal RST is set to a high level, the reset transistor 58 is turned on, and the potential of the third FD portion 57 is reset to the level of the power supply voltage VDD.

[0036] The gate electrode of the amplifier transistor 59 is connected to the first FD portion 53 and the drain is connected to the power supply VDD, and the amplifier transistor 59 is used as an input portion of a readout circuit that reads out a signal corresponding to the charge held by the first FD portion 53, which is what is generally called a source follower circuit. That is, the source of the amplifier transistor 59 is connected to the vertical signal line 9 through the selection transistor 60. This allows the amplifier transistor 59 and a constant current source (not shown) connected to one end of the vertical signal line 9 to form a source follower circuit.

[0037] The selection transistor 60 is connected between the source of the amplifying transistor 59 and the vertical signal line 9. The drive signal SEL is supplied to the gate electrode of the selection transistor 60. When the drive signal SEL is set to a high level, the selection transistor 60 is turned on, and the pixel 2 becomes a selected state. Therefore, the pixel signal output from the amplifying transistor 59 is output to the vertical signal line 9 through the selection transistor 31.

[0038] It should be noted that, in the following, each drive signal that becomes a valid state (i.e., a high level) is also represented as being turned on, and each drive signal that becomes an invalid state (i.e., a low level) is also represented as being turned off.

[0039] Figure 2 The pixel 2 shown includes a first FD portion 53, a second FD portion 55, and a third FD portion 57, and these FD portions are connected in series to form a configuration that can switch the conversion efficiency when converting the charge generated in the photoelectric conversion portion into a voltage in three stages.

[0040] High conversion efficiency (HCG) is constructed by the first FD portion 53, medium conversion efficiency (MCG) is constructed by (first FD portion 53+second FD portion 55), and low conversion efficiency (LCG) is constructed by (first FD portion 53+second FD portion 55+third FD portion 57).

[0041] Due to the turning on of the first transfer transistor 52 , the charge accumulated in the photoelectric conversion portion 51 is received and output by the first FD portion 53 (high conversion efficiency) or the first FD portion 53 + the second FD portion 55 (medium conversion efficiency).

[0042] A configuration is formed in which, at high illuminance, the charge accumulated in the photoelectric conversion portion 51 overflows to the first FD portion 53 side through the first transfer transistor 52 and is accumulated in the first FD portion 53 , the second FD portion 55 , and the third FD portion 57 .

[0043] When the amount of received light is small and the signal is small, the conversion efficiency is switched to high conversion efficiency, and the charge is accumulated in the first FD portion 53. When the amount of received light is large and the signal is large, the conversion efficiency is switched to low conversion efficiency, and the charge is accumulated in the first FD portion 53+the second FD portion 55+the third FD portion 57. In addition, an intermediate conversion efficiency between the high conversion efficiency and the low conversion efficiency is set here, so that the conversion efficiency that allows the charge to be accumulated in the first FD portion 53+the second FD portion 55 is set.

[0044] The charges overflowing from the photoelectric conversion portion 51 and accumulated in the first FD portion 53 , the second FD portion 55 , and the third FD portion 57 are received by the first FD portion 53 + the second FD portion 55 + the third FD portion 57 and output together with the charges accumulated in the photoelectric conversion portion 51 .

[0045] The readout of each of the high conversion efficiency, the medium conversion efficiency, and the low conversion efficiency is respectively subjected to AD conversion, and which readout signal to use is determined according to the amount of the readout signal of each efficiency. The two readout signals can be mixed and used in the bridge portion between the high conversion efficiency signal and the medium conversion efficiency signal and in the bridge portion between the medium conversion efficiency signal and the low conversion efficiency signal. By using the mixed signal, image quality degradation can be suppressed in the bridge portion.

[0046] As described above, by arranging the FD section at three locations, a configuration can be formed in which, for example, high conversion efficiency, medium conversion efficiency, and low conversion efficiency are achieved at 160uV / e, 80uV / e, and 10uV / e, respectively, and these three conversion efficiencies are used. This can suppress the S / N step of the bridge portion.

[0047] <About Pixel 2 Operation> Will refer to Figure 3 and 4 The operation of pixel 2 is described. Here, Figure 2 The operation of the pixel 2 of the shown circuit configuration is explained as an example. Figure 3 is a timing chart for explaining the operation of pixel 2. Figure 4 is a potential diagram for explaining the operation of the pixel 2.

[0048] exist Figure 3 In the figure, HGC, MCG and LCG represent high conversion efficiency, medium conversion efficiency and low conversion efficiency, respectively. Figure 4 , PD denotes PD 51. TRG denotes a first transfer transistor 52. FD1 denotes a first FD portion 53. FDG denotes a second transfer transistor 54. FD2 denotes a second FD portion 55. FCG denotes a third transfer transistor 56. FD3 denotes a third FD portion 57. RST denotes a reset transistor 58.

[0049] The time T1 is the time immediately after the shutter operation is performed. Figure 3 After the shutter operation is performed, the drive signal SEL provided to the selection transistor 60, the drive signal RST provided to the reset transistor 58, the drive signal FCG provided to the third transfer transistor 56, the drive signal FDG provided to the second transfer transistor 54, and the drive signal TRG provided to the first transfer transistor 52 are immediately in the off state.

[0050] Reference Figure 4 , immediately after the shutter operation is performed, the PD 51 , the first FD portion 53 , the second FD portion 55 , and the third FD portion 57 are in an off state, and are in a state where signals are not accumulated.

[0051] The exposure period starts from the time T1, photoelectric conversion is performed in the PD 51 and the signal is accumulated in the PD 51. Here, in the case where the signal amount becomes larger relative to the saturated electron number, the signal overflows under the first transfer transistor 52, and the signal is accumulated in the first FD portion 53, the second FD portion 55, and the third FD portion 57 according to the overflowed signal amount.

[0052] Time T2 is the reset period in MCG (medium conversion efficiency) mode. Figure 3 , in the reset period in the MCG mode, the drive signal SEL supplied to the selection transistor 60 and the drive signal FDG supplied to the second transfer transistor 54 are turned on.

[0053] exist Figure 4 In the illustrated example, a state is shown in which a signal overflowing from the PD 51 is accumulated in the first FD portion 53 and the second FD portion 55 .

[0054] When the reset period in the MCG mode ends, it switches to the reset period in the HCG (high conversion efficiency) mode at time T3. Figure 3 , in the reset period in the HCG mode, the drive signal SEL supplied to the selection transistor 60 is maintained in the on state, and the drive signal FDG supplied to the second transfer transistor 54 is turned off from the on state.

[0055] Reference Figure 4 Since it is shifted to the reset period in the HCG mode and the driving signal FDG supplied to the second transfer transistor 54 is turned off, the signals accumulated in the first FD portion 53 and the second FD portion 55 are divided by capacitance.

[0056] When the reset period in the HCG mode ends, the period switches to the readout period in the HCG mode at time T4. Figure 3 During the transition from time T3 to time T4, the driving signal TRG supplied to the first transfer transistor 52 is set to an on state for a predetermined time. Due to the turning on of the driving signal TRG, the signal accumulated in the PD 51 is read out by the first transfer transistor 52. The reading from the PD 51 is performed by correlated double sampling (CDS) driving.

[0057] Image data during the HCG mode is generated and output by CDS driving using a reset signal obtained in the reset period in the HCG mode at time T3 and a signal read out in the readout period in the HCG mode at time T4.

[0058] Reference Figure 4Since the HDG mode-based readout is performed at time T4, the signal accumulated in PD 51 is read out and PD 51 becomes an empty state, and a signal depending on the signal accumulated in PD 51 is accumulated in each of the first FD portion 53, the second FD portion 55 and the third FD portion 57.

[0059] When the readout period in the HCG mode ends, the readout period in the MCG mode is switched at time T5. Figure 3 During the transition from the time T4 to the time T5, the driving signal FDG supplied to the second transfer transistor 54 is set to the on state. Due to the turning on of the driving signal FDG, the charges accumulated in the first FD portion 53 and the second FD portion 55 are read out.

[0060] At time T5 , image data during the MCG mode is generated and output by CDS driving using a reset signal obtained in the reset period in the MCG mode at time T2 and a signal read out in the readout period in the MCG mode at time T5 .

[0061] When the readout period in the MCG mode ends, the readout period in the LCG mode is switched at time T6. Figure 3 During the transition from the time T5 to the time T6, the driving signal FCG supplied to the third transfer transistor 56 is turned on. At the time T6, the second transfer transistor 54 and the third transfer transistor 56 are set to the on state.

[0062] Since the second transfer transistor 54 and the third transfer transistor 56 are set to the on state, the signals accumulated in the first FD portion 53 , the second FD portion 55 , and the third FD portion 57 are read out.

[0063] When the readout period in the LCG mode ends, it switches to the reset period at time T7. In the reset period at time T7, a reset operation is performed in the same state as when the shutter is executed, so that the black level signal in the reset period in the LCG mode at time T8 is the same as the black level signal when the shutter is executed.

[0064] Reference Figure 3 , in the reset period at time T7, the drive signal SEL supplied to the selection transistor 60 is set to the off state from time T6 to time T8. The drive signal RST supplied to the reset transistor 58 is set to the on state within a predetermined time within the period from time T6 to time T8. The drive signal FCG supplied to the third transfer transistor 56 is set to the on state within a predetermined time within the period from time T6 to time T8. The drive signal FDG supplied to the second transfer transistor 54 is set to the on state within a predetermined time within the period from time T6 to time T8.

[0065] Since the reset operation is performed in the reset period at time T7, Figure 4 As shown, the signals accumulated in the first FD portion 53 , the second FD portion 55 , and the third FD portion 57 are reset.

[0066] When the reset period at time T7 ends, it is switched to the reset period in the LCG mode at time T8. In the reset period in the LCG mode at time T8, the drive signal SEL supplied to the selection transistor 60 is set to the on state. The drive signal FCG supplied to the third transfer transistor 56 and the drive signal FDG supplied to the second transfer transistor 54 are also set to the on state.

[0067] Reading in the LCG mode is performed by double data sampling (DDS) driving, which is a driving that reads out signal charges held or accumulated in the FD as a signal level and then resets the FD to a predetermined potential to read out the predetermined potential as a reset level.

[0068] Since readout in the LCG mode is performed by DDS driving, a signal read out in the readout period in the LCG mode at time T6 and a reset signal read out in the reset period in the LCG mode at time T8 are utilized, and image data in the LCG mode is generated and output.

[0069] At the end of the readout period in the LCG mode, the drive signal SEL, the drive signal FCG, and the drive signal FDG are all turned off.

[0070] By performing such a series of operations, the signal at HCG (high conversion efficiency), the signal at MCG (medium conversion efficiency), and the signal at LCG (low conversion efficiency) are read out respectively. By adopting this structure, the signal is read out three times using three conversion efficiencies, and the deterioration of the S / N step difference of the bridge portion can be suppressed.

[0071] <Example of Planar Structure of Pixels> Figure 5 1 is a diagram showing an example of a planar configuration of a silicon substrate surface on which transistors of the pixel 2 are arranged.

[0072] The gate electrode TRG of the first transfer transistor 52 is formed around the center of the pixel 2. The gates of the transistors other than the first transfer transistor 52 included in the pixel 2 are constructed with the gate electrode TRG of the first transfer transistor 52 as the center. In the figure, the gate electrode FDG of the second transfer transistor 54 is formed on the left side of the gate electrode TRG of the first transfer transistor 52. The first FD portion 53 including an N+ diffusion layer is arranged between the gate electrode TRG and the gate electrode FDG and is located in the silicon substrate.

[0073] In the figure, the gate electrode FCG of the third transfer transistor 56 is formed on the upper side of the gate electrode TRG of the first transfer transistor 52. The second FD portion 55 is arranged between the second transfer transistor 54 and the third transfer transistor 56.

[0074] The gate electrode RST of the reset transistor 58 is formed on the upper right side of the gate electrode TRG of the first transfer transistor 52. The third FD portion 57 is formed between the third transfer transistor 56 and the reset transistor 58.

[0075] In the figure, the gate electrode AMP of the amplifier transistor 59 is formed on the right side of the gate electrode TRG of the first transfer transistor 52. A VDD region 71 including a P+ diffusion layer and connected to a power supply voltage VDD is formed between the reset transistor 58 and the amplifier transistor 59.

[0076] In the drawing, the gate electrode SEL of the selection transistor 60 is formed on the lower side of the gate electrode TRG of the first transfer transistor 52. In the drawing, a VSL region connected to the vertical signal line 9 is formed on the left side of the selection transistor 60.

[0077] In the drawing, a VSS region 73 including a P+ diffusion layer is formed on the lower left side of the first transfer transistor 52 .

[0078] The inter-pixel isolation part 81 is formed to surround the pixel 2. For example, the inter-pixel isolation part 81 is formed by a front full trench isolation part (Front Full Trench Isolation, FFTI). The inter-pixel isolation part 81 can be formed by a groove that does not penetrate or penetrates the semiconductor substrate. The pixel 2 is isolated by an insulator caused by the inter-pixel isolation part 81, and each pixel 2 is constructed to be electrically isolated.

[0079] The element isolation portion 82 is formed between transistors constituting the pixel 2. The element isolation portion 82 employs, for example, a structure formed by forming a trench having a predetermined depth in an element isolation region and burying an insulating film in the trench, or a region formed by ion implantation.

[0080] For pixel 2, the inter-pixel isolation section 81 is arranged in the pixel boundary region, and element isolation is established in the active region by the element isolation section 82. The active region is a region shown as an open region in the figure, and is formed to have a shape continuous from the lower side of the gate electrode TRG of the first transfer transistor 52 to the VSL region 72.

[0081] The element isolation portion 82 is partially formed so as to be in contact with the inter-pixel isolation portion 81. Figure 5In the illustrated example, the element isolation portion 82 existing between the second transfer transistor 54 and the VSS region 73 and the element isolation portion 82 existing between the VSS region 73 and the VSL region 72 are formed in contact with the inter-pixel isolation portion 81 .

[0082] Pixel transistors other than the first transfer transistor 52 (the second transfer transistor 54 , the third transfer transistor 56 , the reset transistor 58 , the amplification transistor 59 , and the selection transistor 60 ) are arranged not only on the element isolation portion 82 as an element isolation structure but also on the inter-pixel isolation portion 81 .

[0083] like Figure 5 As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 are configured to overlap with the inter-pixel isolation portion 81. In other words, partial regions of the gate electrodes of these pixel transistors are configured to be in a state where the partial regions include a region overlapping with the inter-pixel isolation portion 81 in a plan view. By forming a configuration overlapping with the inter-pixel isolation portion 81, the region of the electrode gate can be ensured.

[0084] like Figure 5 As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 are configured to overlap the element isolation section 82. In other words, partial regions of the gate electrodes of these pixel transistors are configured to be in a state including a region overlapping the element isolation section 82 in a plan view.

[0085] The left side in the figure of the gate electrode FDG of the second transfer transistor 54 overlaps with the pixel isolation portion 81 in plan view, and the right side and the lower side in the figure overlap with the element isolation portion 82 in plan view. The upper side in the figure of the gate electrode FCG of the third transfer transistor 56 overlaps with the pixel isolation portion 81 in plan view, and the lower side in the figure overlaps with the element isolation portion 82 in plan view.

[0086] The upper and right sides of the gate electrode RST of the reset transistor 58 in the figure overlap with the inter-pixel isolation portion 81 in the plan view, and the left side portion and the lower side portion (lower left) in the figure overlap with the element isolation portion 82 in the plan view. The right side of the gate electrode AMP of the amplifier transistor 59 in the figure overlaps with the inter-pixel isolation portion 81 in the plan view, and the left side in the figure overlaps with the element isolation portion 82 in the plan view.

[0087] The gate electrode SEL of the selection transistor 60 has its lower side in the figure overlapped with the inter-pixel isolation portion 81 in plan view, and its upper side in the figure overlapped with the element isolation portion 82 in plan view.

[0088] In this way, the transistors other than the first transfer transistor 52 included in the pixel 2 are arranged to surround the first transfer transistor. In addition, each transistor other than the first transfer transistor 52 included in the pixel 2 is constructed so that at least one side overlaps with the inter-pixel isolation portion 81 in a plan view, and the opposite side of the side overlapping with the inter-pixel isolation portion 81 overlaps with the element isolation portion 82.

[0089] By arranging the transistors in this way, the WL size of the pixel transistor that can be arranged in each pixel can be expanded, so that the cutoff difference and amplification noise of the pixel transistor can be designed to be small. In addition, the first transfer transistor 52 for transferring the charge obtained by the conversion of the photoelectric conversion unit 51 to the FD unit is arranged at the center of the pixel 2, that is, at the center of the photoelectric conversion unit 51. This can form a structure that easily transmits the signal from the photoelectric conversion unit 51 to the first FD unit 53.

[0090] <Example of cross-sectional structure of pixel> Figure 6 Shown in Figure 5 The figure is obtained by adding the line segment AA' to the pixel 2 shown. Figure 7 Shows about Figure 6 The cross-sectional structure example of the pixel 2 along the line segment AA' is shown.

[0091] Reference Figure 7 The pixel 2 shown in FIG. 1 is an example of a cross-sectional structure of the pixel 2, wherein the pixel 2 includes a semiconductor substrate 80 and a multilayer interconnection layer (not shown) formed on the front side (upper side in the figure) of the semiconductor substrate. Figure 7 In the figure, the lower side is the light incident side and is the side where the on-chip lens and color filter (not shown) are arranged. Figure 7 In the embodiment, the upper side is an interconnect layer side, and a plurality of transistors are formed on this side.

[0092] The semiconductor substrate 80 includes, for example, silicon (hereinafter referred to as Si), and its thickness is, for example, 1 to 10 μm. In the semiconductor substrate 80, for example, an N-type (second conductivity type) semiconductor region 101 is formed in a P-type (first conductivity type) semiconductor region 102 in units of pixels. Therefore, a photodiode PD is formed in units of pixels.

[0093] Between the pixels 2 of the semiconductor substrate 80, an inter-pixel isolation portion 81 is formed at a predetermined depth in the depth direction of the substrate from the back side (light incident side) of the semiconductor substrate 80 to isolate adjacent pixels from each other in the depth direction of the semiconductor substrate 80. The formation depth of the inter-pixel isolation portion 81 in the substrate thickness direction can be set to an arbitrary depth. Figure 7In the example shown, the inter-pixel isolation portion 81 is shown to penetrate from the back side to the front side of the semiconductor substrate 80 and establish complete isolation in units of pixels. It is also possible to configure as follows: the outer peripheral portion including the side wall of the inter-pixel isolation portion 81 is covered with an anti-reflection film including a layer containing a hafnium oxide film, etc. It is also possible that the inter-pixel isolation portion 81 is configured to have the function of preventing incident light from penetrating to the adjacent pixel 2 to confine the incident light within the pixel and preventing incident light from the adjacent pixel 2 from leaking and entering.

[0094] At the same time, on the front side of the semiconductor substrate 80 where the multi-layer interconnection layer is formed, a first transfer transistor 52 is formed for one photodiode PD formed in each pixel 2. The gate electrode TRG of the first transfer transistor 52 is connected to the N-type region of the photodiode PD. In the figure, an N+ region 105 as a first FD portion 53 is formed on the left side of the first transfer transistor 52.

[0095] In the figure, an element isolation portion 82 is formed on the left side of the first FD portion 53. The element isolation portion 82 includes, for example, an oxide film, and is arranged to isolate the transistor of the pixel 2. A pinning film 107 is formed on the lower side of the element isolation portion 82. The pinning film 107 is formed at a boundary portion between the element isolation portion 82 and the P-type semiconductor region 102, and is, for example, a fixed charge film having a negative fixed charge. The pinning film 107 is formed using, for example, hafnium oxide (HfO2), zirconium dioxide (ZrO2), or tantalum oxide (Ta2O5).

[0096] Since the pinning film 107 is arranged, a positive charge (hole) accumulation region is formed at the boundary portion of the silicon semiconductor substrate 80, so that the occurrence of dark current can be suppressed.

[0097] In the figure, the selection transistor 60 is formed on the left side of the element isolation portion 82. The channel 104 is formed by the N-type region on the lower side of the gate electrode SEL of the selection transistor 60.

[0098] like Figure 7 As shown in FIG. 1 , the gate electrode SEL of the selection transistor 60 is formed in position and size so that one side thereof includes a region overlapping with the element isolation portion 82 and the other side thereof includes a region overlapping with the inter-pixel isolation portion 81. It should be noted that although the gate electrode SEL is Figure 7 Although described as a rectangle, a configuration is adopted in which the side wall is also included in the rectangle or not. When the side wall is also included in the gate electrode SEL, the gate electrode SEL can be configured so that part of the side wall overlaps with the element isolation portion 82 and overlaps with the inter-pixel isolation portion 81. Similar configurations can also be used for other transistors.

[0099] In the figure, an element isolation portion 82 is formed on the right side of the first transfer transistor 52. A fixed film 108 is formed on the lower side of the element isolation portion 82. In the figure, an amplifier transistor 59 is formed on the right side of the element isolation portion 82. A channel 106 is formed by an N-type region on the lower side of the gate electrode AMP of the amplifier transistor 59.

[0100] like Figure 7 As shown, the gate electrode AMP of the amplifier transistor 59 is formed in position and size such that one side thereof includes a region overlapping with the element isolation portion 82 and the other side includes a region overlapping with the inter-pixel isolation portion 81 .

[0101] As described above, transistors (eg, Figure 7 The selection transistor 60 and the amplification transistor 59 in the transistor 80 are structured so that one side thereof exists on the inter-pixel isolation portion 132 and the other side exists on the element isolation portion 82.

[0102] The gate electrode TRG of the first transfer transistor 52 may have a Figure 8 The structure shown also has the gate arranged in the vertical direction. Figure 8 , the photodiode PD is configured as a buried photodiode PD, and a configuration is formed in which a portion of the gate electrode TRG of the first transfer transistor 52 is arranged to reach a portion of the photodiode PD.

[0103] The gate electrode TRG of the first transfer transistor 52 is formed to have the following structure, which has a gate arranged on the front side of the semiconductor substrate 80 (a gate arranged in the horizontal direction) and a gate arranged inside the N-type semiconductor region 101 of the photodiode PD in the semiconductor substrate 80 (a gate arranged in the vertical direction).

[0104] It is also possible to use a vertical transistor that also has a gate in the vertical direction. Here, the case where the first transfer transistor 52 is a vertical transistor is described as an example. However, the present technology can also be applied to the case where transistors other than the first transfer transistor 52 are vertical transistors.

[0105] <Second Embodiment> Fig. 9 FIG. 2 is a diagram showing an example of a planar structure of a pixel 2 in the second embodiment. Fig. 9 In the structure of the pixel 2 shown in FIG. Figure 5 Similar parts to those of the pixel 2 in the first embodiment are denoted by similar reference numerals, and description thereof will be appropriately omitted.

[0106] and Figure 5 Compared to the pixel 2 shown, Fig. 9The pixel 2 shown is different in that part of the element isolation portion 82 is formed by ion implantation, but is similar in other respects.

[0107] exist Fig. 9 In the pixel 2 shown in FIG. 1 , the element isolation section 131 - 1 formed by ion implantation is used as the element isolation section 82 arranged between the VSL region 72 and the VSS region 73. Fig. 9 In the illustrated pixel 2 , an element isolation portion 131 - 2 formed by ion implantation is employed as the element isolation portion 82 arranged between the VSS region 73 and the second transfer transistor 54 .

[0108] The element isolation portion 131 is, for example, an element isolation portion formed by doping the semiconductor substrate 80 with P-type impurities.

[0109] exist Fig. 9 In the example shown, in the element isolation portion 82, the element isolation portion 131 formed by ion implantation is adopted as the element isolation portion 82 in the region in contact with the pixel isolation portion 81. By forming the element isolation portion 82 in the region in contact with the pixel isolation portion 81 by ion implantation as described above, manufacturing becomes easy.

[0110] <Third Embodiment> Fig.10 2 is a diagram showing an example of a planar structure of a pixel 2 in the third embodiment. Fig.10 In the structure of the pixel 2 shown in FIG. Figure 5 Similar parts to those of the pixel 2 in the first embodiment are given similar reference numerals, and description thereof will be appropriately omitted.

[0111] and Figure 5 Compared to the pixel 2 shown, Fig.10 The pixel 2 shown is different in that a region formed by ion implantation is adopted as the entirety of the element isolation portion 82 , but is similar in other respects.

[0112] exist Fig.10 In the pixel 2 shown, an element isolation portion 131 formed by ion implantation is used as the element isolation portion 82. The element isolation portion 131 is an element isolation portion formed by doping the semiconductor substrate 80 with a P-type impurity, for example.

[0113] It is also possible to form a configuration in which the element isolation portion 131 formed by ion implantation is used as the above-described element isolation portion.

[0114] Fig.11 is a graph showing the pixel 2 along Fig.10 The figure shows an example of the cross-sectional structure of the line segment AA' shown. Fig.11 The cross-sectional structure example of the pixel 2 shown is similar to Figure 7The illustrated cross-sectional configuration example of the pixel 2 is similar but differs in that the element isolating portion 82 is replaced by the element isolating portion 131 .

[0115] The element isolation portion 131 disposed between the first FD portion 53 and the selection transistor 60 is an element isolation portion formed by ion implantation. The element isolation portion 131 disposed between the first transfer transistor 52 and the amplification transistor 59 is an element isolation portion formed by ion implantation.

[0116] It is also possible to configure as follows: the element isolation portion is formed as a region formed by ion implantation and doped with, for example, the above-mentioned P-type impurity.

[0117] <Position of contact part> Fig.12 1 is a diagram for explaining the arrangement position of a contact portion for fixing the substrate potential of each pixel. Fig.12 The cross-sectional configuration example of the pixel 2 is shown. This cross-sectional configuration example basically has the same Figure 7 The cross-sectional configuration of the pixel 2 shown illustrates a similar configuration.

[0118] The contact portion for providing the substrate potential may be configured to be shared from the back side. Fig.12 In the figure, the contact portion 151 is arranged on the lower side (back side) of the left and right sides respectively. The contact portion 151 is connected to the P+ layer having a high P-type impurity concentration formed on the side of the inter-pixel isolation portion 81. For example, the contact portion 151 is connected to the power supply voltage VSS and is connected to the position in the pixel 2 to which the voltage VSS is provided.

[0119] <Fourth Embodiment> Fig.13 1 is a diagram showing a circuit configuration example of the pixel 2 in the fourth embodiment. The pixel 2 in the first to third embodiments has been described by giving a configuration example having three FD portions. However, the present technology can also be applied to a pixel 2 having a circuit configuration example having three FD portions. Fig.13 The structure shown has two FD parts. Fig.13 In the circuit diagram of pixel 2 shown in FIG. Figure 2 Parts similar to those in the circuit diagram of the pixel 2 shown are given the same reference numerals, and description thereof will be appropriately omitted.

[0120] Fig.13 The pixel 2 shown is formed by Figure 2 The pixel 2 shown in the figure is a structure obtained by deleting the third transfer transistor 56 and the third FD portion 57. That is, Fig.13 The pixel 2 shown has a photoelectric conversion portion 51 , a first transfer transistor 52 , a first FD portion 53 , a second transfer transistor 54 , a second FD portion 55 , a reset transistor 58 , an amplification transistor 59 , and a selection transistor 60 .

[0121] The photoelectric conversion unit 51 includes, for example, a PN junction photodiode, receives incident light, and performs photoelectric conversion to accumulate the charge obtained thereby. The first transfer transistor 52 is arranged between the photoelectric conversion unit 51 and the first FD unit 53. The drive signal TRG is supplied to the gate electrode of the first transfer transistor 52. When the drive signal TRG becomes a high level, the first transfer transistor 52 is turned on, and the charge accumulated in the photoelectric conversion unit 51 is transferred to the first FD unit 53 through the first transfer transistor 52.

[0122] The second transfer transistor 54 is arranged between the first FD portion 53 and the second FD portion 55. A drive signal FDG is supplied to a gate electrode of the second transfer transistor 54. When the drive signal FDG becomes a high level, the second transfer transistor 54 is turned on, and the charge from the first FD portion 53 is transferred to the second FD portion 55 through the second transfer transistor 54.

[0123] Due to the turning on of the second transfer transistor 54, the region for accumulating charges becomes a region obtained by combining the first FD portion 53 and the second FD portion 55, and the conversion efficiency when converting the charges generated in the photoelectric conversion portion into a voltage can be switched. The second transfer transistor 54 serves as a conversion efficiency switching transistor for switching the conversion efficiency, and serves as a switch for turning the conversion efficiency on and off.

[0124] The reset transistor 58 is connected between the power supply VDD and the second FD portion 55. The drive signal RST is supplied to the gate electrode of the reset transistor 58. When the drive signal RST is set to a high level, the reset transistor 58 is turned on, and the potential of the second FD portion 55 is reset to the level of the power supply voltage VDD.

[0125] The gate electrode of the amplifier transistor 59 is connected to the first FD portion 53 and the drain is connected to the power supply VDD, and the amplifier transistor 59 is used as an input portion of a readout circuit that reads out a signal corresponding to the charge held by the first FD portion 53, which is what is generally called a source follower circuit. That is, the source of the amplifier transistor 59 is connected to the vertical signal line 9 through the selection transistor 60. This allows the amplifier transistor 59 and a constant current source (not shown) connected to one end of the vertical signal line 9 to form a source follower circuit.

[0126] The selection transistor 60 is connected between the source of the amplifying transistor 59 and the vertical signal line 9. The drive signal SEL is supplied to the gate electrode of the selection transistor 60. When the drive signal SEL is set to a high level, the selection transistor 60 is turned on, and the pixel 2 becomes a selected state. Thus, the pixel signal output from the amplifying transistor 59 is output to the vertical signal line 9 through the selection transistor 60.

[0127] <Example of Planar Structure of Pixels> Fig.14 is shown arranged with Fig.13 FIG. 2 is a diagram showing an example of a planar structure of a transistor on a silicon substrate surface of a pixel 2 having a circuit structure shown.

[0128] The gate electrode TRG of the first transfer transistor 52 is formed around the center of the pixel 2. The gates of the transistors other than the first transfer transistor 52 included in the pixel 2 are arranged around the gate electrode TRG of the first transfer transistor 52. In other words, the transistors other than the first transfer transistor 52 constituting the pixel 2 are arranged around the first transfer transistor 52, with the first transfer transistor 52 as the center.

[0129] In the figure, the gate electrode FDG of the second transfer transistor 54 is formed on the left side of the gate electrode TRG of the first transfer transistor 52. The first FD portion 53 including an N+ diffusion layer is arranged between the gate electrode TRG and the gate electrode FDG and is located in the silicon substrate.

[0130] In the figure, the gate RST of the reset transistor 58 is formed on the upper side of the gate TRG of the first transfer transistor 52. The second FD portion 55 is formed between the second transfer transistor 54 and the reset transistor 58.

[0131] In the figure, the gate AMP of the amplifier transistor 59 is formed on the right side of the gate TRG of the first transfer transistor 52. A VDD region 71 connected to the power supply voltage VDD is formed between the reset transistor 58 and the amplifier transistor 59.

[0132] In the drawing, the gate electrode SEL of the selection transistor 60 is formed on the lower side of the gate electrode TRG of the first transfer transistor 52. In the drawing, a VSL region connected to the vertical signal line 9 is formed on the left side of the selection transistor 60.

[0133] In the drawing, a VSS region 73 including a P+ diffusion layer is formed on the lower left side of the first transfer transistor 52 .

[0134] The pixel isolation section 81 is formed between the pixels 2. The element isolation section 82 is formed between the transistors. The element isolation section 82 adopts a structure obtained by forming a groove having a predetermined depth in the element isolation region and burying an insulating film in the groove. Fig.10 The element isolation portion 131 is formed by ion implantation.

[0135] The inter-pixel isolation section 81 is arranged in the pixel boundary region of the pixel 2, and element isolation is established in the active region through the element isolation section 82. The active region is formed as a continuous region (continuous region). Fig.14In the example shown, the active region is formed as a region continuous from the lower side of the gate electrode TRG of the first transfer transistor 52 to the VSL region 72. The element isolation portion 82 is formed as a structure part of which is in contact with the inter-pixel isolation portion 81.

[0136] like Fig.14 As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 are configured to overlap with the inter-pixel isolation portion 81. In other words, partial regions of the gate electrodes of these pixel transistors are configured to be in a state where the partial regions include a region overlapping with the inter-pixel isolation portion 81 in a plan view. By forming a configuration overlapping with the inter-pixel isolation portion 81, the region of the electrode gate can be ensured.

[0137] like Fig.14 As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 are configured to overlap the element isolation section 82. In other words, partial regions of the gate electrodes of these pixel transistors are configured to be in a state including a region overlapping the element isolation section 82 in a plan view.

[0138] The left side in the figure of the gate electrode FDG of the second transfer transistor 54 overlaps with the pixel isolation portion 81 in plan view, and the right side in the figure overlaps with the element isolation portion 82 in plan view. The upper side in the figure of the gate electrode RST of the reset transistor 58 overlaps with the pixel isolation portion 81 in plan view, and the lower side in the figure overlaps with the element isolation portion 82 in plan view.

[0139] The right side in the figure of the gate electrode AMP of the amplifying transistor 59 overlaps with the inter-pixel isolation portion 81 in plan view, and the left side in the figure overlaps with the element isolation portion 82 in plan view. The lower side in the figure of the gate electrode SEL of the selecting transistor 60 overlaps with the inter-pixel isolation portion 81 in plan view, and the upper side in the figure overlaps with the element isolation portion 82 in plan view.

[0140] In this way, the transistors other than the first transfer transistor 52 included in the pixel 2 are arranged to surround the first transfer transistor 52. In addition, each transistor other than the first transfer transistor 52 included in the pixel 2 is configured so that at least one side thereof overlaps with the inter-pixel isolation portion 81 in a plan view, and the opposite side to the side overlapping with the inter-pixel isolation portion 81 overlaps with the element isolation portion 82.

[0141] By arranging the transistors in this way, the WL size of the pixel transistor that can be arranged in each pixel can be expanded, so that the cutoff difference and amplification noise of the pixel transistor can be designed to be small. In addition, the first transfer transistor 52 for transferring the charge obtained by the conversion of the photoelectric conversion unit 51 to the FD unit is arranged at the center of the pixel 2, that is, at the center of the photoelectric conversion unit 51. This can form a structure that easily transmits the signal from the photoelectric conversion unit 51 to the first FD unit 53.

[0142] exist Fig.14 In the pixel 2 shown, the number of transistors arranged is Figure 5 The number of pixels 2 shown is small, so one transistor can be formed into a large size. In particular, the amplifier transistor 59 can be formed into a large size, so that noise can be reduced.

[0143] <Fifth Embodiment> Fig.15 1 is a diagram showing a circuit configuration example of a pixel 2 in Embodiment 5. Like the pixel 2 in Embodiments 1 to 3, the pixel 2 in Embodiment 5 is configured to have three FD portions, and is formed into a configuration in which an overflow transistor 201 is further added.

[0144] The pixel 2 has a photoelectric conversion portion 51 , a first transfer transistor 52 , a first FD portion 53 , a second transfer transistor 54 , a second FD portion 55 , a third transfer transistor 56 , a third FD portion 57 , a reset transistor 58 , an amplification transistor 59 , a selection transistor 60 , and an overflow transistor 201 .

[0145] The overflow transistor 201 is arranged between the photoelectric conversion portion 51 and the third FD portion 57 , and is configured so that charges overflowing from the photoelectric conversion portion 51 are accumulated in the third FD portion 57 .

[0146] The first transfer transistor 52 is arranged between the photoelectric conversion portion 51 and the first FD portion 53. A drive signal TRG is supplied to a gate electrode of the first transfer transistor 52. When the drive signal TRG becomes a high level, the first transfer transistor 52 is turned on, and the charge accumulated in the photoelectric conversion portion 51 is transferred to the first FD portion 53 through the first transfer transistor 52.

[0147] The second transfer transistor 54 is arranged between the first FD portion 53 and the second FD portion 55. A drive signal FDG is supplied to a gate electrode of the second transfer transistor 54. When the drive signal FDG becomes a high level, the second transfer transistor 54 is turned on, and the charge from the first FD portion 53 is transferred to the second FD portion 55 through the second transfer transistor 54.

[0148] Due to the turning on of the second transfer transistor 54 , the region for accumulating charges becomes a region obtained by combining the first FD portion 53 and the second FD portion 55 , and the conversion efficiency when converting charges generated in the photoelectric conversion portion into a voltage can be switched.

[0149] The third transfer transistor 56 is arranged between the second FD portion 55 and the third FD portion 57. A drive signal FCG is supplied to a gate electrode of the third transfer transistor 56. When the drive signal FCG becomes a high level, the third transfer transistor 56 is turned on, and the charge from the second FD portion 55 is transferred to the third FD portion 57 through the third transfer transistor 56.

[0150] Due to the turning on of the third transfer transistor 56, the region for accumulating charges becomes a region obtained by combining the first FD portion 53, the second FD portion 55, and the third FD portion 57, and the conversion efficiency when converting the charges generated in the photoelectric conversion portion into a voltage can be switched. As described above, the charges overflowing from the photoelectric conversion portion 51 and transferred through the overflow transistor 201 are also accumulated in the third FD portion 57.

[0151] The reset transistor 58 is connected between the power supply VDD and the intersection of the second FD portion 55 and the third FD portion 57. The drive signal RST is supplied to the gate electrode of the reset transistor 58. When the drive signal RST is set to a high level, the reset transistor 58 is turned on, and the potentials of the second FD portion 55 and the third FD portion 57 are reset to the level of the power supply voltage VDD.

[0152] The gate electrode of the amplifier transistor 59 is connected to the first FD portion 53 and the drain is connected to the power supply VDD, and the amplifier transistor 59 is used as an input portion of a readout circuit that reads out a signal corresponding to the charge held by the first FD portion 53, which is what is generally called a source follower circuit. That is, the source of the amplifier transistor 59 is connected to the vertical signal line 9 through the selection transistor 60. This allows the amplifier transistor 59 and a constant current source (not shown) connected to one end of the vertical signal line 9 to form a source follower circuit.

[0153] The selection transistor 60 is connected between the source of the amplifying transistor 59 and the vertical signal line 9. The drive signal SEL is supplied to the gate electrode of the selection transistor 60. When the drive signal SEL is set to a high level, the selection transistor 60 is turned on, and the pixel 2 becomes a selected state. Thus, the pixel signal output from the amplifying transistor 59 is output to the vertical signal line 9 through the selection transistor 31.

[0154] <Example of Planar Structure of Pixels> Fig.16 is shown arranged with Fig.15FIG. 2 is a diagram showing an example of a planar structure of a transistor on a silicon substrate surface of a pixel 2 having a circuit structure shown.

[0155] The gate electrode TRG of the first transfer transistor 52 is formed around the center of the pixel 2. The gates of the transistors other than the first transfer transistor 52 included in the pixel 2 are arranged with the gate electrode TRG of the first transfer transistor 52 as the center. In the figure, the gate electrode FDG of the second transfer transistor 54 is formed on the left side of the gate electrode TRG of the first transfer transistor 52. The first FD portion 53 including an N+ diffusion layer is arranged between the gate electrode TRG and the gate electrode FDG, and is located in the silicon substrate.

[0156] The gate RST of the reset transistor 58 is formed on the upper side in the figure of the gate TRG of the first transfer transistor 52. The second FD portion 55 is formed between the second transfer transistor 54 and the reset transistor 58.

[0157] The gate electrode AMP of the amplifier transistor 59 is formed on the upper right side of the gate electrode TRG of the first transfer transistor 52. The VDD region 71 is formed between the reset transistor 58 and the amplifier transistor 59.

[0158] The gate electrode SEL of the selection transistor 60 is formed on the right side in the figure of the gate electrode TRG of the first transfer transistor 52 , and the VSL region 72 is formed on the lower side in the figure of the selection transistor 60 .

[0159] The gate electrode OFG of the overflow transistor 201 is formed on the lower right side in the figure of the gate electrode TRG of the first transfer transistor 52. The VSS region 73 is formed on the right side in the figure of the overflow transistor 201. The gate electrode FCG of the third transfer transistor 56 is formed on the lower left side in the figure of the gate electrode TRG of the first transfer transistor 52. The third FD portion 57 is formed between the overflow transistor 201 and the third transfer transistor 56.

[0160] Part of the second FD portion 55 is formed on the left side in the figure of the third transfer transistor 56. The second FD portion 55 is arranged on each of the upper side and the lower side of the second transfer transistor 54.

[0161] like Fig.17 As shown, a configuration may also be adopted in which the second FD portion 55 is disposed on each of the upper side and the lower side of the second transfer transistor 54 and is continuous. Fig.17 In the example shown, the first transfer transistor 52 and the other transistors are formed from one active region.

[0162] The pixel isolation section 81 is formed to surround the pixel 2. The element isolation section 82 is formed between the respective transistors. The element isolation section 82 adopts, for example, a structure obtained by forming a groove having a predetermined depth in the element isolation region and burying an insulating film in the groove. Fig.10 The element isolation portion 131 is formed by ion implantation.

[0163] The pixel transistors (the second transfer transistor 54, the third transfer transistor 56, the reset transistor 58, the amplification transistor 59, the selection transistor 60 and the overflow transistor 201) other than the first transfer transistor 52 are arranged so that a part of them is located on the element isolation portion 82 which is an element isolation structure, and a part of them is located on the inter-pixel isolation portion 81.

[0164] like Fig.16 As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 are configured to overlap with the inter-pixel isolation portion 81. In other words, partial regions of the gate electrodes of these pixel transistors are configured to be in a state where the partial regions include a region overlapping with the inter-pixel isolation portion 81 in a plan view. By forming a configuration overlapping with the inter-pixel isolation portion 81, the region of the electrode gate can be ensured.

[0165] like Fig.16 As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 are configured to overlap the element isolation section 82. In other words, partial regions of the gate electrodes of these pixel transistors are configured to be in a state including a region overlapping the element isolation section 82 in a plan view.

[0166] The left side in the figure of the gate electrode FDG of the second transfer transistor 54 overlaps with the pixel isolation portion 81 in the plan view, and the right side in the figure overlaps with the element isolation portion 82 in the plan view. The upper side in the figure of the gate electrode RST of the reset transistor 58 overlaps with the pixel isolation portion 81 in the plan view, and the lower side in the figure overlaps with the element isolation portion 82 in the plan view.

[0167] The upper and right sides in the figure of the gate electrode AMP of the amplifying transistor 59 overlap with the inter-pixel isolation portion 81 in plan view, and the lower side portion in the figure overlaps with the element isolation portion 82 in plan view. The right side in the figure of the gate electrode SEL of the selecting transistor 60 overlaps with the inter-pixel isolation portion 81 in plan view, and the left side in the figure overlaps with the element isolation portion 82 in plan view.

[0168] The lower side in the figure of the gate electrode OFG of the overflow transistor 201 overlaps with the pixel isolation portion 81 in the plan view, and the upper side in the figure overlaps with the element isolation portion 82 in the plan view. The lower side in the figure of the gate electrode FCG of the third transfer transistor 56 overlaps with the pixel isolation portion 81 in the plan view, and the upper side in the figure overlaps with the element isolation portion 82 in the plan view.

[0169] In this way, the transistors other than the first transfer transistor 52 included in the pixel 2 are arranged to surround the first transfer transistor 52. In addition, each transistor other than the first transfer transistor 52 included in the pixel 2 is configured so that at least one side thereof overlaps with the inter-pixel isolation portion 81 in a plan view, and the opposite side to the side overlapping with the inter-pixel isolation portion 81 overlaps with the element isolation portion 82.

[0170] By arranging the transistors in this way, the WL size of the pixel transistor that can be arranged in each pixel can be expanded, so that the cutoff difference and amplification noise of the pixel transistor can be designed to be small. In addition, the first transfer transistor 52 for transferring the charge obtained by the conversion of the photoelectric conversion unit 51 to the FD unit is arranged at the center of the pixel 2, that is, at the center of the photoelectric conversion unit 51. This can form a structure that easily transmits the signal from the photoelectric conversion unit 51 to the first FD unit 53.

[0171] <About the occurrence of white spots and dark current> The above-mentioned pixel 2 has a plurality of transistors. When the size of the pixel 2 is miniaturized, defects occurring due to weakening of pinning during application of voltage to the transistor or due to a strong electric field caused by a PN junction between an N-type source or drain and a P-type well are likely to enter the FD portion or the photoelectric conversion portion, and white spots or dark currents are degraded.

[0172] Will refer to Figures 18 to 21 This point will be explained. Fig.18 is obtained by adding line segments A-A', B-B' and C-C' to the Figure 5 A diagram obtained by looking at an example of a planar structure of a pixel 2 shown in FIG. Fig.19 is shown along Fig.18 A diagram showing an example of a cross-sectional structure of the line segment AA' in FIG. Fig. 20 is shown along Fig.18 A diagram showing an example of a cross-sectional structure of a line segment BB' in FIG. Fig.21 is shown along Fig.18 A diagram showing an example of a cross-sectional structure of the line segment CC'.

[0173] Fig.19 The cross-sectional structure example of the pixel 2 shown is similar to Figure 7 The cross-sectional configuration examples shown are similar, so their description is omitted. Fig.19As shown, a strong electric field may appear at the junction between the N+ region 105 forming the first FD portion 53 and the pinning film 107 which is a P-type region formed on the lower side of the element isolation portion 82 (hereinafter, the element isolation portion 82 existing between the first transfer transistor 52 and the first FD portion 53 will be referred to as the element isolation portion 82SF).

[0174] In the case where the element isolation portion 82SF has a rectangular shape, the electric field tends to concentrate at the corner portions, and a strong electric field tends to occur at these portions. Fig.19 As shown, since a strong electric field occurs between the N+ region 105 and the element isolation portion 82SF, charges flow to the first FD portion 53 or the photodiode PD, which may cause white spots or dark current.

[0175] Reference Fig. 20 In the cross-sectional configuration example along the line segment BB' shown, the gate electrode TRG of the first transfer transistor 52 is formed around the center of the semiconductor substrate 80. The element isolation portion 82 (which is defined as the element isolation portion 82TA) is formed on the left side in the figure of the first transfer transistor 52. The pinning film 108 is formed on the lower side of the element isolation portion 82TA.

[0176] The amplifier transistor 59 is formed on the left side of the element isolation portion 82TA in the figure. The channel 106 is formed by an N-type region located below the gate electrode AMP of the amplifier transistor 59.

[0177] like Fig. 20 As shown, the gate electrode AMP of the amplifier transistor 59 is formed in position and size such that one side thereof includes a region overlapping with the element isolation portion 82TA and the other side includes a region overlapping with the inter-pixel isolation portion 81 .

[0178] The element isolation portion 82 (which is defined as the element isolation portion 82TF) is formed on the right side of the first transfer transistor 52. The pinning film 109 is formed on the lower side of the element isolation portion 82TF. The N+ region 111 forming the second FD portion 55 is formed on the left side of the element isolation portion 82TF.

[0179] like Fig. 20 As shown, a strong electric field may occur at the junction portion between the N+ region 111 forming the second FD portion 55 and the P-type pinning film 109 formed on the lower side of the element isolation portion 82TF. Fig. 20 As shown, since a strong electric field occurs between the N+ region 111 and the element isolation portion 82TF, charges flow to the second FD portion 55 or the photodiode PD, which may cause white spots or dark current.

[0180] Reference Fig.21In the cross-sectional configuration along line segment CC' shown, the gate electrode TRG of the first transfer transistor 52 is formed around the center of the semiconductor substrate 80. The element isolation portion 82TS is formed on the left side of the first transfer transistor 52. The pinning film 108 is formed on the lower side of the element isolation portion 82TS.

[0181] The selection transistor 60 is formed on the left side of the element isolation portion 82TS in the figure. The channel 104 is formed by an N-type region located below the gate electrode SEL of the selection transistor 60.

[0182] like Fig.21 As shown, the gate electrode SEL of the selection transistor 60 is formed in a position and size so that one side thereof includes a region overlapping with the element isolation portion 82TS and the other side includes a region overlapping with the inter-pixel isolation portion 81 .

[0183] The element isolation portion 82TF is formed on the right side in the figure of the first transfer transistor 52. The pinning film 110 is formed on the lower side of the element isolation portion 82TF. The N+ region 112 forming the third FD portion 57 is formed on the left side in the figure of this element isolation portion 82TF.

[0184] like Fig.21 As shown, a strong electric field may occur at the junction portion between the N+ region 112 forming the third FD portion 57 and the P-type pinning film 110 formed on the lower side of the element isolation portion 82TF. Fig.21 As shown, since a strong electric field occurs between the N+ region 112 and the element isolation portion 82TF, charges flow to the third FD portion 57 or the photodiode PD, which may cause white spots or dark current.

[0185] As described above, a strong electric field may occur at the element isolation portion 82 adjacent to the FD portion, and white spots or dark current may occur. Next, a configuration of the pixel 2 that suppresses the occurrence of a strong electric field at the element isolation portion 82 adjacent to the FD portion and suppresses the occurrence of white spots or dark current will be described.

[0186] <Sixth Embodiment> Figures 22 to 24 A diagram showing an example of a cross-sectional structure of a pixel 2 in the sixth embodiment. Fig. 22 To show the Fig.18 A diagram showing an example of a cross-sectional structure of the line segment AA' in FIG. Fig.23 is shown along Fig.18 A diagram showing an example of a cross-sectional structure of a line segment BB' in FIG. Fig.24 is shown along Fig.18 A diagram showing an example of a cross-sectional structure of the line segment CC'.

[0187] Reference Fig. 22In the cross-sectional configuration example of the pixel 2 along the line segment AA' shown in the figure, the depth of the element isolation portion 82SF adjacent to the first FD portion 53 is set to be deeper than the depth of the element isolation portion 82 not adjacent to the FD portion. Fig. 22 In the example shown, the element isolation portion 82TA adjacent to the amplifying transistor 59 exists as the element isolation portion 82 not adjacent to the FD portion. The depth of this element isolation portion 82TA is defined as depth “a.” The depth is the length in the vertical direction (up and down direction) in the figure.

[0188] When the depth of the element isolation portion 82SF adjacent to the first FD portion 53 is defined as depth "b", the relationship of depth "b" > depth "a" holds. By setting the depth "b" of the element isolation portion 82SF to be deeper, the distance between the corner portion of the element isolation portion 82SF (P-type pinning film 107) and the N+ region 105 of the first FD portion 53 can be made longer. By separating the pinning film 107 and the N+ region 105, junction leakage can be suppressed. Therefore, the above-mentioned Fig.19 The occurrence of white spots or dark currents.

[0189] It should be noted that since the depth "b" of the element isolation portion 82SF is set to be deeper, the element isolation portion 82SF is likely to become close to the N-type semiconductor region 101 of the photoelectric conversion portion 61. Therefore, there is a possibility that a structure is formed in which the charges generated at the Si-SiO2 interface below the element isolation portion 82SF easily flow into the photoelectric conversion portion 61 and dark current occurs. Therefore, the depth "b" of the element isolation portion 82SF is set to a depth that does not cause dark current to occur.

[0190] The element isolation portion 82TA adjacent to the amplifier transistor 59 may also be formed deeper. However, as with the element isolation portion 82SF, increasing the depth may cause a possibility that charge flows into the photoelectric conversion portion 61. For this reason, a configuration may also be adopted in which the depth of the element isolation portion 82 adjacent to the FD portion is set deeper, but the depths of the other element isolation portions 82 are not set deeper.

[0191] Reference Fig.23 In the cross-sectional configuration example of the pixel 2 along the line segment BB' shown in the figure, the depth "c" of the element isolation portion 82TF adjacent to the second FD portion 55 is set to be deeper than the depth of the element isolation portion 82 not adjacent to the FD portion. Fig.23 In the example shown, an element isolation portion 82TA adjacent to the amplification transistor 59 exists as an element isolation portion 82 not adjacent to the FD portion. The depth of this element isolation portion 82TA is depth "a".

[0192] The depth "c" of the element isolation part 82TF adjacent to the second FD part 55 is a depth that satisfies the relationship of depth "c" > depth "a". By setting the depth "c" of the element isolation part 82TF to be deeper, the distance between the corner portion of the element isolation part 82TF (P-type pinning film 109) and the N+ region 111 of the second FD part 55 can be made longer. Therefore, a structure capable of suppressing junction leakage can be formed. Therefore, the reference Fig. 20 Explain the occurrence of white spots or dark current.

[0193] Reference Fig.24 In the cross-sectional configuration example of the pixel 2 along the line segment CC' shown in the figure, the depth "c" of the element isolation portion 82TF adjacent to the third FD portion 57 is set to be deeper than the depth of the element isolation portion 82 not adjacent to the FD portion. Fig.24 In the example shown, the element isolation portion 82TS adjacent to the selection transistor 60 exists as the element isolation portion 82 not adjacent to the FD portion. The depth of this element isolation portion 82TS is the depth "a".

[0194] The depth "c" of the element isolation part 82TF adjacent to the third FD part 57 is a depth that satisfies the relationship of depth "c" > depth "a". By setting the depth "c" of the element isolation part 82TF to be deeper, the distance between the corner portion of the element isolation part 82TF (P-type pinning film 110) and the N+ region 112 of the third FD part 57 can be made longer. Therefore, a structure capable of suppressing junction leakage can be formed. Therefore, the reference Fig.21 Explain the occurrence of white spots or dark current.

[0195] Reference Figures 22 to 24 The depth "b" of the element isolation portion 82 adjacent to the first FD portion 53, the depth "c" of the element isolation portion 82 adjacent to the second FD portion 55, and the depth "d" of the element isolation portion 82 adjacent to the third FD portion 57 satisfy the relationship of depth "b" = depth "c" = depth "d". As described above, the depths of the element isolation portions 82 adjacent to the FD portions can be set to be the same.

[0196] Depths b, c, and d are set as an example to about 1.2 to 2.0, with depth "a" defined as 1. The depth of the element isolation portion 82 adjacent to the FD portion is set to a depth of about 1.2 to 2.0 times the depth "a" as a reference.

[0197] like Fig.25As shown, the depth "b" of the element isolation portion 82 adjacent to the first FD portion 53, the depth "c" of the element isolation portion 82 adjacent to the second FD portion 55, and the depth "d" of the element isolation portion 82 adjacent to the third FD portion 57 can be set to satisfy the relationship of depth "b" < depth "c" < depth "d".

[0198] Here, the case where three positions (i.e., the element isolation portion 82 adjacent to the first FD portion 53, the element isolation portion 82 adjacent to the second FD portion 55, and the element isolation portion 82 adjacent to the third FD portion 57) are formed to be deeper than the depth "a" of the element isolation portion 82 not adjacent to the FD portion is explained as an example. However, two positions or one position of the three positions may be formed to be deeper than the depth "a".

[0199] For example, the following setting may be made: the depth "a" of the element isolation portion 82 not adjacent to the FD portion = the depth "b" of the element isolation portion 82 adjacent to the first FD portion 53 = the depth "c" of the element isolation portion 82 adjacent to the second FD portion 55 < the depth "d" of the element isolation portion 82 adjacent to the third FD portion 57. In this case, the relationship of depth "a" = depth "b" = depth "c" < depth "d" is satisfied, and a structure is formed in which one position of the element isolation portion 82 adjacent to the FD portion is formed deeper.

[0200] For example, the following setting may be made: the depth "a" of the element isolation portion 82 not adjacent to the FD portion = the depth "b" of the element isolation portion 82 adjacent to the first FD portion 53 < the depth "c" of the element isolation portion 82 adjacent to the second FD portion 55 = the depth "d" of the element isolation portion 82 adjacent to the third FD portion 57. In this case, the relationship of depth "a" = depth "b" < depth "c" = depth "d" is satisfied, and the following structure is formed: two positions of the element isolation portion 82 adjacent to the FD portion are formed deeper.

[0201] In the case of a structure including a plurality of element isolation portions 82 adjacent to the FD portion, which element isolation portion 82 is formed deeper can be set according to a voltage applied to the FD portion or according to the capacitance of the FD portion.

[0202] In terms of driving, the depth of the element isolation portion 82 adjacent to the FD portion to which a high voltage is applied can be set deeper than other element isolation portions 82. The depth of the element isolation portion 82 can also be set according to the voltage applied to the FD portion.

[0203] The depth of the element isolation portion 82 adjacent to the FD portion having a high capacitance may be set deeper than other element isolation portions 82. Since dark current is easily accumulated in the FD portion having a high capacitance, the depth of the element isolation portion 82 may be set deeper to suppress the occurrence of dark current. The depth of the element isolation portion 82 may be set according to the capacitance of the FD portion.

[0204] <Seventh Embodiment> Fig.26 A diagram showing an example of a cross-sectional structure of a pixel 2 in the seventh embodiment. Fig.26 The illustrated element isolation portion 82 includes two regions. The element isolation portion 82TF adjacent to the third FD portion 57 includes an element isolation portion 82TF-1 and an element isolation portion 82TF-2.

[0205] The element isolation portion 82TF-1 is an element isolation portion 82 located on the side separated from the third FD portion 57, and is formed to a depth equal to the depth of the element isolation portion 82 not adjacent to the FD portion (e.g., the element isolation portion 82TS). At the same time, the element isolation portion 82TF-2 adjacent to the third FD portion 57 is formed to be deeper than the depth of the element isolation portion 82 not adjacent to the FD portion.

[0206] It is also possible to form the element isolation portion 82 more deeply on the side close to the FD portion, thereby forming a structure in which the N+ region of the FD portion and the pinning film are separated. In other words, it is also possible to form a structure in which the element isolation portion 82 located on the side close to the FD portion is formed more deeply, and the element isolation portion 82 located on the side away from the FD portion is formed to have the same depth as the other element isolation portions 82.

[0207] like Fig. 27 As shown, the element isolation portion 82 can be formed to have a plurality of steps. It can also be said that Fig.26 The element isolation portion 82TF shown is formed to have a depth of two levels. On the other hand, Fig. 27 The element isolation portion 82TF shown is formed to have three levels of depth. As described above, the element isolation portion 82 may be formed so that the depth becomes deeper in a stepwise manner as the position moves from the side away from the FD portion toward the side close to the FD portion.

[0208] like Fig.28 As shown, the element isolation portion 82 may also be formed to have a triangular shape. Fig.28 The element isolation portion 82TF shown is formed so that the depth gradually deepens from the side of the first transfer transistor 52 to the third FD portion 57, and is formed into a triangular shape with one side of the element isolation portion 82TF as the hypotenuse. As described above, the element isolation portion 82 can be formed so that the depth gradually deepens as the position moves from the side away from the FD portion toward the side close to the FD portion.

[0209] Although the description is given here by taking the element isolation portion 82 adjacent to the third FD portion 57 as an example, it is also applicable to the element isolation portion 82 adjacent to the first FD portion 53 or the second FD portion 55 .

[0210] <Eighth Embodiment> Fig.29 It is a diagram showing an example of a cross-sectional structure of a pixel 2 in the eighth embodiment. Fig.29 The illustrated element isolating portion 82 is formed to have a shape other than a rectangular shape.

[0211] Fig.29 The element isolation portion 82TF shown is formed to have a trapezoidal shape. The short side of the trapezoid exists in the semiconductor substrate 80, and the pinning film 110 is formed on the short side. By forming the element isolation portion 82TF into a trapezoid and forming the pinning film 110 on the short side thereof, the pinning film 110 and the third FD portion 57 can be separated, and junction leakage can be suppressed.

[0212] In the case where the element isolation portion 82 is formed in a rectangular shape, the electric field tends to concentrate at the corner portion. Fig.30 The shape with rounded corners shown in FIG. 1 can reduce the electric field in the portion where the electric field concentration is likely to occur, and can suppress the occurrence of a strong electric field. In addition, by rounding the corners, the side where the pinning film 110 is formed can be shortened, and a structure can be formed that separates the pinning film 110 and the N+ region 112 accordingly.

[0213] As described above, the shape of the element isolating portion 82 is not limited to a rectangular shape, and may be a trapezoidal shape or a shape with rounded corners. Figures 22 to 24 In the above case, the depth of the element isolation portion 82 can be set deeper than the element isolation portion 82 that is not adjacent to the FD portion.

[0214] Although the description is given here by taking the element isolation portion 82 adjacent to the third FD portion 57 as an example, it is also applicable to the element isolation portion 82 adjacent to the first FD portion 53 or the second FD portion 55 .

[0215] <Ninth Embodiment> Fig.31 This is a diagram showing an example of a cross-sectional structure of a pixel 2 in the ninth embodiment. Fig.31 The element isolation portion 82 shown comprises two different materials.

[0216] The element isolation portion 82 adjacent to the first FD portion 53 includes an element isolation portion 82SF-1 and an element isolation portion 82SF-2. The element isolation portion 82SF-1 is an element isolation portion 82 formed on a side away from the first FD portion 53, and includes an oxide film, etc. The element isolation portion 82SF-2 is an element isolation portion 82 formed on a side close to the first FD portion 53, and is an element isolation portion 82 formed as a P-type region by ion implantation.

[0217] It is also possible to configure as follows: a P-type region formed by ion implantation is formed between the element isolation portion 82SF-1 including an oxide film or the like and the diffusion layer (N+ region 105) of the above-mentioned FD portion.

[0218] Although the description is given here by taking the element isolation portion 82 adjacent to the first FD portion 53 as an example, it is also applicable to the element isolation portion 82 adjacent to the second FD portion 55 or the third FD portion 57 .

[0219] like Fig.32 As shown, the entire element isolation portion 82 can be formed as a P-type region formed by ion implantation. Fig.32 In the example shown, the element isolation portion 82TF adjacent to the third FD portion 57 is formed as a P-type impurity region and is, for example, a region formed by ion implantation. In this case, the depth of the element isolation portion 82TF can be set deeper than or the same depth as other element isolation portions 82.

[0220] Although the description is given here by taking the element isolation portion 82 adjacent to the third FD portion 57 as an example, it is also applicable to the element isolation portion 82 adjacent to the first FD portion 53 or the second FD portion 55 .

[0221] <Structure of Element Isolation Section> In the case where the element isolation portion 82 includes an oxide film, as in Fig.33 As shown, a single layer or stacked layers can be used. Fig.33 A, the element isolation portion 82 can adopt a single-layer oxide film including SiO2 or SiN.

[0222] Reference Fig.33 B, the element isolation portion 82 may be formed of an oxide film including a stacked layer of SiO2 and SiN. Fig.33 In the example shown in B, a structure in which a SiO 2 layer, a SiO layer, and a SiO 2 layer are stacked is shown.

[0223] <Structure of Inter-Pixel Isolation Section> Fig.34 A configuration example of the inter-pixel isolation section 81 is shown. Fig.34The example shown in A shows an example in which the pixel isolation portion 81 is formed by a front side deep trench isolation portion (FDTI). The FDTI is a trench dug from the front side (upper side in the figure) of the semiconductor substrate 80. Fig.34 The example shown in B shows an example in which the pixel isolation portion 81 is formed by a reverse side deep trench isolation (RDTI). The RDTI is a trench dug from the back side (lower side in the figure) of the semiconductor substrate 80.

[0224] The inter-pixel isolation portion 81 may be a structure called a full trench (Front Full Trench Isolation, FFTI) formed to penetrate the semiconductor substrate 80 .

[0225] According to this technology, a structure can be realized in which the corner portion of the element isolation portion is separated from the diffusion layer of the FD portion and the P / N boundary portion of the well region. Therefore, the electric field can be reduced and junction leakage can be suppressed, thereby improving image quality.

[0226] <About Reduction of Dark Current Influence> As reference Figure 3 As described above, in pixel 2, the charge overflowing from PD 51 is accumulated in the first FD portion 53, the second FD portion 55, and the third FD portion 57. These first FD portion 53, the second FD portion 55, and the third FD portion 57 are used as overflow accumulation capacitors (Lateral Over Flow Integration Capacitor, LOFIC: lateral overflow integration capacitor) for accumulating the overflowed charge. For such LOFIC located on the FD accumulation side, it is difficult to reset the FD. Therefore, the FD dark current occurring in the accumulation period from the execution of the shutter operation to the completion of the signal readout may degrade the image quality of the image sensor.

[0227] Will refer to Fig.35 This point will be explained. Fig.35 Shown with Figure 3 The potential diagram corresponding to the timing diagram shown. The period from time T1 to time T2 is the exposure period. Time T1 is the time immediately after the shutter operation is performed. Figure 3 Immediately after the shutter operation is performed, the drive signal SEL provided to the selection transistor 60, the drive signal RST provided to the reset transistor 58, the drive signal FCG provided to the third transfer transistor 56, the drive signal FDG provided to the second transfer transistor 54, and the drive signal TRG provided to the first transfer transistor 52 are in the off state.

[0228] Immediately after the shutter operation is performed (time T1 ), the PD 51 , the first FD portion 53 , the second FD portion 55 , and the third FD portion 57 are in an off state, and in a state where signals are not accumulated.

[0229] The exposure period starts from the time T1, photoelectric conversion is performed in the PD 51, and the signal is accumulated in the PD 51. Here, in the case where the signal amount is greater than the saturated electron amount, the signal overflows under the first transfer transistor 52, and the signal is accumulated in the first FD portion 53, the second FD portion 55, and the third FD portion 57 according to the amount of the overflowed signal.

[0230] like Fig.35 As shown in the position from time T1 to time T2 in FIG. 5 , in the exposure period, in addition to accumulation of signals in the PD 51 , dark current may occur and accumulate in each of the first FD portion 53 , the second FD portion 55 , and the third FD portion 57 .

[0231] From time T2 to time T4, execute reference Figure 3 and 4 The operation in the reset period in the MCG (medium conversion efficiency) mode and the operation in the reset period in the HCG (high conversion efficiency) mode are described.

[0232] Fig.35 The right figure of shows a potential diagram at time T4. Time T4 is a readout period in the HCG mode. Since the readout based on the HDG mode is performed at time T4, the signal accumulated in the PD 51 is read out, and the PD 51 becomes an empty state, so that each of the first FD portion 53, the second FD portion 55, and the third FD portion 57 accumulates a signal depending on the signal accumulated in the PD 51.

[0233] Since dark current is accumulated in the first FD portion 53, the second FD portion 55, and the third FD portion 57, a signal including the dark current is accumulated. Therefore, the FD range is reduced.

[0234] <10th Embodiment> In order to suppress the reduction of the FD range and suppress the occurrence of dark current, a mechanism for reducing the voltage of the FD portion during the exposure period is set. Fig.36 A potential diagram is shown in the case where a connection line is connected to the second FD portion 55 to allow control of the decrease or increase of the voltage of the second FD portion 55 .

[0235] Fig.36 The left diagram of shows a potential diagram in the period from time T1 to time T2 (ie, exposure period). In the exposure period (signal accumulation period), control for lowering the voltage of the second FD portion 55 and suppressing dark current is performed by connection line control.

[0236] like Fig.36 As shown in the right figure of , at time T4, during signal readout in a readout period in the HCG mode or the like, control for raising the voltage of the second FD portion 55 and securing the FD range is performed by controlling through the connection line.

[0237] If there is little concern about dark current, control such as voltage reduction may not be performed during the signal accumulation period, and control such as voltage increase and FD range expansion may be performed during the signal readout period.

[0238] The connection line serves as a control line that controls the rise and fall of the voltage applied to the FD portion.

[0239] Fig.37 A circuit configuration example of the pixel 2 in the case where a connection line is connected to the second FD portion 55 to control the voltage of the second FD portion 55 is shown. Fig.37 The circuit configuration example of the pixel 2 shown is obtained by adding a connection line 301 connected to the second FD portion 55 to the Figure 2 The connection line 301 is connected to the second FD portion 55 through the capacitor 311.

[0240] Reference Fig.38 The timing diagram shown here illustrates Fig.37 The operation of pixel 2 is shown. Fig.38 The timing diagram shown is obtained by adding the signal to the connection line 301 (FD control) to Figure 3 The signal other than the signal to the connection line 301 is obtained by comparing the timing diagram shown in FIG. Figure 3 The signals in the described cases are similar. Therefore, the signals to the connection line 301 are described here.

[0241] In the exposure period from time T1 to time T2, the FD control signal changes from the on state to the off state. Then, after the off state continues for a predetermined time, the FD control signal turns on.

[0242] Due to the OFF of the FD control signal, the voltage on the capacitor 311 side connected to the connection line 301 becomes an OFF state, and the potential on the second FD portion 55 side becomes high. The charge accumulated in the second FD portion 55 flows to the capacitor 311. This lowers the potential of the second FD portion 55 (i.e., voltage decreases).

[0243] In this way, control for reducing the FD portion voltage is performed during the exposure period (during signal accumulation). This can reduce the influence of dark current. Therefore, the reduction of the FD range caused by the dark current can be prevented, and the FD range can be ensured.

[0244] like Fig.39As shown, the following configuration may be adopted: the connection line 301 is not arranged only for the second FD portion 55, but is arranged for all FD portions including the first FD portion 53, the second FD portion 55, and the third FD portion 57. Fig.39 The circuit configuration example of the pixel 2 shown is as follows Fig. 27 In the circuit configuration shown, the connection line 301 is connected to the second FD portion 55 , and the capacitive element 311 is arranged with respect to the connection line 301 .

[0245] In addition, Fig.39 In the pixel 2 shown, the connection line 302 is connected to the first FD portion 53, and the capacitance element 312 is arranged with respect to the connection line 302. Fig.39 In the illustrated pixel 2 , the connection line 303 is connected to the third FD portion 57 , and the capacitive element 313 is arranged with respect to the connection line 303 .

[0246] Fig.40 It is shown Fig.39 FIG. 2 is a diagram showing an example of a cross-sectional structure of a pixel 2. Fig.40 The first transfer transistor 52, the first FD portion 53, the second transfer transistor 54, the second FD portion 55, the third transfer transistor 56, and the third FD portion 57 are shown side by side.

[0247] The connection line 302 is connected to the diffusion layer of the first FD portion 53, and the capacitance element 312 is arranged at the portion of the connection line 302. The connection line 301 is connected to the diffusion layer of the second FD portion 55, and the capacitance element 311 is arranged at the portion of the connection line 301. The connection line 303 is connected to the diffusion layer of the third FD portion 57, and the capacitance element 313 is arranged at the portion of the connection line 303.

[0248] It is also possible to construct as follows: each FD section can be provided with a connection line and a capacitor element in this way. In the case where each FD section is provided with a connection line in this way, the FD section can be controlled individually. That is, boost and buck control can be performed for each FD section. It is also possible to construct as follows: instead of performing boost and buck control individually for each FD section, boost and buck control are performed simultaneously. In this case, it is also possible to construct as follows: the connection line connected to the FD section is shared (not arranged separately).

[0249] exist Fig.39 and 40In the example shown, an example is shown in which a connection line is arranged for each of the first FD portion 53, the second FD portion 55, and the third FD portion 57. However, it is also possible to configure as follows: a connection line is arranged for the first FD portion 53 and the second FD portion 55 but not for the third FD portion 57. In addition, it is also possible to configure as follows: a connection line is arranged for the first FD portion 53 and the third FD portion 57 but not for the second FD portion 55. It is also possible to configure as follows: a connection line is arranged for only one FD portion among the first FD portion 53, the second FD portion 55, and the third FD portion 57.

[0250] It should be noted that in the case of a configuration of a pixel 2 including three or more FD portions, a configuration in which connection lines are arranged for all FD portions or a configuration in which connection lines are arranged for one or more FD portions may be adopted. That is, a configuration in which the same number of connection lines as the number of FD portions are arranged or a configuration in which a smaller number of connection lines than the number of FD portions are arranged may be adopted.

[0251] <11th embodiment> Figures 41 to 46 It is a diagram showing a circuit configuration example and a cross-sectional configuration example of a pixel 2 in the 11th embodiment.

[0252] Fig.41 The circuit structure of the pixel 2 shown is similar to Fig.13 The circuit structure of the pixel 2 shown is different in that it is formed by Fig.13 The circuit configuration of the pixel 2 shown is obtained by adding a connection line, and other points are similar. Regarding similar parts, the description will be appropriately omitted.

[0253] Fig.41 The pixel 2 shown includes a first FD portion 53 and a second FD portion 55, and a connection line 302 is connected to the first FD portion 53. A capacitive element 312 is arranged between the connection line 302 and the first FD portion 53.

[0254] Fig.42 It is shown Fig.41 FIG. 2 is a diagram showing an example of a cross-sectional structure of a pixel 2. Fig.42 , the first transfer transistor 52, the first FD portion 53, the second transfer transistor 54, and the second FD portion 55 are shown side by side. The connection line 302 is connected to the diffusion layer of the first FD portion 53, and the capacitance element 312 is arranged at a portion of the connection line 302.

[0255] Fig.41 and 42The example shown is an example including two FD sections and the number of connecting wires is smaller than the number of FD sections. In addition, it is also an example in which the connecting wires are arranged only on the high gain side. By arranging a number of connecting wires smaller than the number of FD sections and connecting the arranged connecting wires to the FD section (in this case, the first FD section 53) on the high gain side as described above, the FD range can be expanded.

[0256] Fig.43 and 44 The circuit configuration and cross-sectional configuration examples of the pixel 2 shown show configuration examples in the case where the number of connection lines arranged is smaller than the number of FD portions and the connection lines arranged are connected to the FD portion on the low-gain side.

[0257] Fig.43 The pixel 2 shown includes a first FD portion 53 and a second FD portion 55, and a connection line 301 is connected to the second FD portion 55. A capacitive element 311 is arranged between the connection line 301 and the second FD portion 55.

[0258] Fig.44 It is shown Fig.43 FIG. 2 is a diagram showing an example of a cross-sectional structure of a pixel 2. Fig.44 , the first transfer transistor 52, the first FD portion 53, the second transfer transistor 54, and the second FD portion 55 are shown side by side. The connection line 301 is connected to the diffusion layer of the second FD portion 55, and the capacitance element 311 is arranged at a portion of the connection line 301.

[0259] Fig.43 and 44 The example shown is an example in which the pixel 2 includes two FD portions, the number of connection lines is smaller than the number of FD portions, and the connection lines are arranged only on the low gain side. By arranging a number of connection lines smaller than the number of FD portions as described above and connecting the arranged connection lines to the FD portion on the low gain side (in this case, the second FD portion 55), the FD range can be expanded and dark current can be suppressed.

[0260] Fig.45 and 46 The circuit configuration and cross-sectional configuration examples of the pixel 2 shown show configuration examples in the case where the number of connection lines arranged is the same as the number of FD portions.

[0261] Fig.45 The pixel 2 shown includes a first FD portion 53 and a second FD portion 55. A connection line 302 is connected to the first FD portion 53, and a connection line 301 is electrically connected to the second FD portion 55. A capacitance element 312 is arranged between the connection line 302 and the first FD portion 53. A capacitance element 311 is arranged between the connection line 301 and the second FD portion 55.

[0262] Fig.46 It is shown Fig.45 A diagram showing an example of a cross-sectional structure of a pixel 2. Fig.46 , a first transfer transistor 52, a first FD portion 53, a second transfer transistor 54, and a second FD portion 55 are shown side by side. A connection line 302 is connected to a diffusion layer of the first FD portion 53, and a capacitor 312 is arranged at a portion of the connection line 302. A connection line 301 is connected to a diffusion layer of the second FD portion 55, and a capacitor 311 is arranged at a portion of the connection line 301.

[0263] Fig.45 and 46 The example shown is an example in which the pixel 2 includes two FD portions, the number of connection lines is the same as the number of FD portions, and the connection lines are arranged on the high gain side and the low gain side. By arranging the same number of connection lines as the number of FD portions as described below and connecting the arranged connection lines to the FD portions on the high gain side and the low gain side (in this case, the first FD portion 53 and the second FD portion 55), the FD range can be expanded and the dark current can be suppressed.

[0264] By adding a connection line, dark current can be suppressed and the number of saturated electrons can be ensured at the same time. In a pixel having a structure that has a function of switching conversion efficiency and does not allow multiple pixels to share the FD part, a connection can be provided at a desired position, allowing effective contribution to dark current suppression and Qs expansion of the FD part.

[0265] For example, the following control can be performed: the voltage is lowered during signal accumulation to suppress dark current, and the voltage is increased during signal readout to ensure the FD range. In addition, if dark current is not a big concern, the voltage may not be particularly lowered during signal accumulation, and the voltage may be increased during signal readout to expand the FD range.

[0266] The above-mentioned first to tenth embodiments can of course be implemented individually, and a plurality of these embodiments can also be implemented in combination.

[0267] <12th embodiment> Fig.47 It is through Figure 5 The illustrated diagram is a diagram obtained by extracting the inter-pixel isolation portion 81 and the element isolation portion 82 , and illustrates a planar configuration example of the silicon substrate surface on which the transistors of the pixel 2 are arranged.

[0268] In the contact regions "a" to "d" ( Fig.47 In the region surrounded by a circle, the shapes of the pixel isolation portion 81 and the element isolation portion 82 may become sharp (for example, Fig.47The shape of the pixels intersecting at 90 degrees in the image is changed to a shape that easily causes electric field concentration. When the electric field is concentrated in the regions "a" to "d" and a high electric field is generated, dark current or white spots may be transmitted and image quality may be reduced.

[0269] Reference Fig.48 , the structure of the pixel 2 in the 12th embodiment is described, and the structure is formed to not allow the electric field to be concentrated in the contact areas "a" to "d" between the inter-pixel isolation portion 81 and the element isolation portion 82.

[0270] Fig.48 It is a diagram showing an example of a planar structure of a pixel 2 in the twelfth embodiment. Fig.49 is along Fig.48 A diagram showing an example of a cross-sectional structure of the line segment AB in FIG. Fig.47 The pixel 2 shown, Fig.48 The illustrated pixel 2 is a diagram showing an example of arrangement of the inter-pixel isolation section 81 and the element isolation section 82 .

[0271] Fig.48 Regions “a” to “d” of the illustrated pixel 2 are formed to have non-sharp shapes. Fig.48 The regions "a" to "d" of the pixel 2 shown are configured to avoid sharp shapes by enlarging the shape of the element isolation portion 82. Fig.49 As shown, in the cross-sectional configuration along line segment AB, the pixel isolation portion 81 is formed to have a predetermined thickness (width), and the element isolation portion 82 is formed between the pixel isolation portion 81 and the pixel isolation portion 81 and is located at the upper surface in the figure.

[0272] As described above, the shape of the element isolation portion 82 in contact with the inter-pixel isolation portion 81 is enlarged. This makes it possible to prevent a portion having a sharp shape in the contact area between the inter-pixel isolation portion 81 and the element isolation portion 82. By adopting the element isolation portion 82 of such a shape, it is possible to prevent electric field concentration and suppress the occurrence of dark current or white spots due to electric field concentration.

[0273] exist Fig.48 , the following example is shown: For example, the element isolation portion 82 in the region "a" is formed to have a shape including a triangle. However, the shape may be any shape as long as it is a shape without a sharp portion. For example, the shape may be a shape with an arc.

[0274] Reference Fig.48 The contact region between the pixel isolation section 81 and the element isolation section 82 exists at four locations. These four locations can be classified into the following three types.

[0275] Reference Fig.48 and 5The region corresponding to region "a" is formed with the second transfer transistor 54 (in Figure 5 The region of the gate electrode is illustrated as FDG). Figure 5 The pixel 2 shown has Figure 2 The circuit configuration shown in FIG. 1 has a first FD section 53, a second FD section 55, and a third FD section 57. In the case of adopting the above-mentioned configuration having a plurality of FD sections and accumulating overflow signals in the FD sections, when dark current occurs in the FD sections, the image quality may be degraded at the bridge point where HDR synthesis is performed.

[0276] For this reason, the dark current in the FD portion needs to be sufficiently small. By forming a shape that is not sharp in region "a", a structure that suppresses the dark current occurring in the FD portion can be achieved. The region arranged to reduce the dark current in the FD portion is defined as region 1.

[0277] Reference Fig.48 and 5 , the areas corresponding to the areas "b" and "c" exist in the VSS area 73 (in Figure 5 The VSS region 73 involves the possibility of the charge of the P+ diffusion layer moving to the FD portion or the photodiode PD, and is therefore a region where a sharp point is not desired even at a position where no electric field occurs (defined as region 2). It can be achieved that there is no sharp position in such regions "b" and "c", and the flow of charge to the FD portion or the photodiode PD can be suppressed.

[0278] Reference Fig.48 and 5 , the area corresponding to area "d" exists in VSL area 72 (in Figure 5 When dark current moves to the photodiode PD in the case where dark current occurs in the VSL region 72 or the VDD region 71, it is possible that it becomes the dark current of the photodiode PD. Therefore, it is better to reduce this possibility as well. Hereinafter, the region where such dark current occurring in the VSL region 72 or the VDD region 71 is suppressed is defined as region 3. It can be achieved that there is no sharp position in this region 3 (region d in this case), and the occurrence of dark current can be suppressed.

[0279] Fig.50 and 51 is a diagram showing another configuration example of the pixel 2 in the twelfth embodiment. Fig.50 FIG. 1 is a diagram showing another planar structure example of the pixel 2 in the twelfth embodiment. Fig.51 is shown along Fig.50 A diagram showing an example of a cross-sectional structure of the line segment AB in FIG. Fig.47 The pixel 2 shown, Fig.50The illustrated pixel 2 is a diagram showing an example of arrangement of the inter-pixel isolation section 81 and the element isolation section 82 .

[0280] For reference Fig.48 and 49 The pixel 2 described above has been described by taking an example in which the element isolation portion 82 is given an enlarged shape in the contact region between the inter-pixel isolation portion 81 and the element isolation portion 82 to form a shape without a sharp portion. Fig.50 and 51 The pixel 2 described above is an example in which the inter-pixel isolation portion 81 is given an enlarged shape in the contact region between the inter-pixel isolation portion 81 and the element isolation portion 82 to form a shape without a sharp portion.

[0281] Fig.50 Regions “a” to “d” of the illustrated pixel 2 are formed not to have a sharp shape. Fig.50 The regions “a” to “d” of the pixel 2 shown are configured to avoid a sharp shape by enlarging the shape of the inter-pixel isolation portion 81 .

[0282] like Fig.51 As shown, in the cross-sectional structure along the line segment AB, the inter-pixel isolation section 81 is formed to have a predetermined thickness (width), and the element isolation section 82 is formed between the inter-pixel isolation section 81 and the inter-pixel isolation section 81 and is located at the upper surface in the figure. Fig.49 The width of the inter-pixel separation portion 81 is set wider than the width of the inter-pixel separation portion 81 of the pixel 2 shown.

[0283] As described above, the shape of the pixel isolation portion 81 in contact with the pixel isolation portion 82 is enlarged. This makes it possible to prevent a portion having a sharp shape in the contact area between the pixel isolation portion 81 and the element isolation portion 82. By adopting the pixel isolation portion 81 having such a shape, electric field concentration can be prevented, and the occurrence of dark current or white spots due to electric field concentration can also be suppressed.

[0284] The twelfth embodiment may be applied in combination with any one or more of the first to eleventh embodiments.

[0285] <13th embodiment> Fig.52 1 is a diagram showing an example of a planar structure of a silicon substrate surface on which transistors of a pixel 2 in the thirteenth embodiment are arranged. Fig.52 Shown with Figure 2 An example of a planar structure of a pixel 2 having a circuit structure shown. Figure 5 It also shows that Figure 2 The circuit configuration of the pixel 2 is shown in FIG. 1 . However, the arrangement of the transistors is different from that of the Figure 5The planar configuration example shown is different, and the shape of the element isolation portion 82 is also different in relation to this. Figure 5 Similar parts in the pixel 2 shown are given similar reference numerals, and their description is appropriately omitted.

[0286] The gate electrode TRG of the first transfer transistor 52 is formed around the center of the pixel 2. The gates of the transistors other than the first transfer transistor 52 included in the pixel 2 are arranged with the gate electrode TRG of the first transfer transistor 52 as the center. In the figure, the gate electrode FDG of the second transfer transistor 54 is formed on the left side of the gate electrode TRG of the first transfer transistor 52. The first FD portion 53 including an N+ diffusion layer is arranged between the gate electrode TRG and the gate electrode FDG and is located in the silicon substrate.

[0287] The gate electrode FCG of the third transfer transistor 56 is formed on the upper side in the figure of the gate electrode TRG of the first transfer transistor 52. The second FD portion 55 is arranged between the second transfer transistor 54 and the third transfer transistor 56.

[0288] The gate electrode RST of the reset transistor 58 is formed on the upper right side of the gate electrode TRG of the first transfer transistor 52. The third FD portion 57 is formed between the third transfer transistor 56 and the reset transistor 58.

[0289] A VSS region 73 including a P+ diffusion layer is formed on the right side in the figure of the gate electrode TRG of the first transfer transistor 52. A VDD region 71 including a P+ diffusion layer and connected to the power supply voltage VDD is formed on the lower side in the figure of the gate electrode RST of the reset transistor 58 and is located between the reset transistor 58 and the VSS region 73. The VDD region 71 and the VSS region 73 are isolated by an element isolation portion 82.

[0290] The VSL region 72 connected to the vertical signal line 9 is formed on the lower right side in the figure of the gate electrode TRG of the first transfer transistor 52. The VSL region 72 and the VSS region 73 are isolated by an element isolation portion 82.

[0291] The gate electrode SEL of the selection transistor 60 is formed on the left side of the VSL region 72 in the figure, and is formed on the lower right side of the gate electrode TRG of the first transfer transistor 52 in the figure. The gate electrode AMP of the amplifier transistor 59 is formed on the left side of the selection transistor 60 in the figure, and is formed on the lower left side of the gate electrode TRG of the first transfer transistor 52 in the figure.

[0292] The VDD region 71 is formed on the left side of the gate electrode AMP of the amplifier transistor 59 in the figure.

[0293] For the pixel 2, the inter-pixel isolation section 81 is arranged in the pixel boundary region, and element isolation is established in the active region by the element isolation section 82. The active region is a region shown as an open region in the figure.

[0294] The element isolation portion 82 is partially formed so as to be in contact with the inter-pixel isolation portion 81. Fig.52 In the example shown, there is an element isolation portion 82 between the second transfer transistor 54 on the left side of the figure and the VDD region 71, there is an element isolation portion 82 between the VDD region 71 on the right side of the figure and the VSS region 73, and there is an element isolation portion 82 between the VSS region 73 on the right side of the figure and the VSL region 72.

[0295] In these contact regions of the pixel isolation section 81 and the element isolation section 82, there are regions corresponding to the regions 1, 2, and 3 described in the twelfth embodiment. The region 1 (ie, the region for suppressing the occurrence of dark current in the FD section) is the region "a".

[0296] The region 2 (ie, the region for suppressing the charges generated in the VSS region 73 from moving to the FD portion or the photodiode PD) is the regions “d” and “e”.

[0297] Region 3 (ie, a region for suppressing dark current generated in VDD region 71 or VSL region 72 from moving to photodiode PD) is regions “b”, “c”, and “f”.

[0298] As in the twelfth embodiment, the regions "a" to "f" are formed into a shape without a sharp portion. Fig.48 and 49 As described above, these regions can be formed by forming the element isolation portion 82 into an extended shape to avoid a sharp shape. Fig.50 and 51 As described above, these regions can be formed by forming the inter-pixel partition 81 into an extended shape to avoid a sharp shape. Fig.52 In the description, the case where the element isolation portion 82 is formed in an extended shape is taken as an example.

[0299] As described above, even when the arrangement of transistors is changed, a structure that suppresses the occurrence of dark current or white spots can be formed.

[0300] In addition, also in Fig.52 In the structure of the pixel 2 shown, as Figure 5 In the case shown, pixel transistors (second transfer transistor 54 , third transfer transistor 56 , reset transistor 58 , amplification transistor 59 , and selection transistor 60 ) other than the first transfer transistor 52 are arranged not only on the element isolation portion 82 but also on the inter-pixel isolation portion 81 .

[0301] like Fig.52 As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 are configured to overlap with the inter-pixel isolation portion 81. In other words, a partial region of the gate electrode of the pixel transistor is configured to be in a state where the partial region includes a region overlapping with the inter-pixel isolation portion 81 in a plan view. By forming a configuration overlapping with the inter-pixel isolation portion 81, the region of the electrode gate can be ensured.

[0302] like Fig.52 As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 are configured to also overlap the element isolation portion 82. In other words, a partial region of the gate electrode of the pixel transistor is configured to be in a state including a region overlapping the element isolation portion 82 in a plan view.

[0303] In this way, the transistors other than the first transfer transistor 52 included in the pixel 2 are arranged to surround the first transfer transistor. In addition, each transistor other than the first transfer transistor 52 included in the pixel 2 is configured so that at least one side thereof overlaps with the inter-pixel isolation portion 81 in a plan view, and the opposite side to the side overlapping with the inter-pixel isolation portion 81 overlaps with the element isolation portion 82.

[0304] By arranging the transistors in this way, the WL size of the pixel transistor that can be arranged in each pixel can be expanded, so that the cutoff difference and amplification noise of the pixel transistor can be designed to be small. In addition, the first transfer transistor 52 for transferring the charge obtained by the conversion of the photoelectric conversion unit 51 to the FD unit is arranged at the center of the pixel 2, that is, at the center of the photoelectric conversion unit 51. This can form a structure that easily transmits the signal from the photoelectric conversion unit 51 to the first FD unit 53.

[0305] <14th embodiment> Fig.53 1 is a diagram showing an example of a planar structure of a silicon substrate surface on which transistors of the pixel 2 in the fourteenth embodiment are arranged. Fig.53 Shown with Figure 2 An example of a planar structure of a pixel 2 having a circuit structure shown. Figure 5 It also shows that Figure 2 The circuit configuration of the pixel 2 is shown in FIG. 1 . However, the arrangement of the transistors is different from that of the Figure 5 The planar configuration example shown is different, and the shape of the element isolation portion 82 is also different in relation to this. Figure 5 Similar parts in the pixel 2 shown are given similar reference numerals, and their description is appropriately omitted.

[0306] The gate electrode TRG of the first transfer transistor 52 is formed around the center of the pixel 2. The gates of the transistors other than the first transfer transistor 52 included in the pixel 2 are configured with the gate electrode TRG of the first transfer transistor 52 as the center. In the figure, the gate electrode FDG of the second transfer transistor 54 is formed on the left side of the gate electrode TRG of the first transfer transistor 52. The first FD portion 53 is arranged between the gate electrode TRG and the gate electrode FDG.

[0307] The gate electrode FCG of the third transfer transistor 56 is formed on the upper side of the gate electrode TRG of the first transfer transistor 52. The second FD portion 55 is arranged between the second transfer transistor 54 and the third transfer transistor 56. The third FD portion 57-1 is formed on the right side of the gate electrode FCG of the third transfer transistor 56 in the figure.

[0308] The VSS region 73 is formed on the upper right side of the gate electrode TRG of the first transfer transistor 52. The element isolation portion 82 is formed between the third FD portion 57-1 and the VSS region 73.

[0309] The gate electrode RST of the reset transistor 58 is arranged on the right side of the gate electrode TRG of the first transfer transistor 52. The third FD portion 57-2 is arranged on the upper side in the figure of the gate electrode RST of the reset transistor 58, and the VDD region 71 is arranged on the lower side in the figure of the gate electrode RST. The third FD portion 57-1 and the third FD portion 57-2 are connected by an interconnection portion arranged on another layer to form a single third FD portion 57. The element isolation portion 82 is formed between the third FD portion 57-2 and the VSS region 73.

[0310] The VSL region 72 is arranged on the lower side of the VDD region 71 in the figure. The element isolation section 82 is formed between the VSL region 72 and the VDD region 71. The gate electrode SEL of the selection transistor 60 is formed on the left side of the VSL region 72 in the figure and on the lower right side of the gate electrode TRG of the first transfer transistor 52 in the figure.

[0311] The gate electrode AMP of the amplifier transistor 59 is formed on the lower left side of the selection transistor 60. The VDD region 71 is formed on the left side of the gate electrode AMP of the amplifier transistor 59, in other words, on the lower left side of the gate electrode TRG of the first transfer transistor 52.

[0312] For the pixel 2, the inter-pixel isolation section 81 is arranged in the pixel boundary region, and element isolation is established in the active region by the element isolation section 82. The active region is a region shown as an open region in the figure.

[0313] The element isolation portion 82 is partially formed so as to be in contact with the inter-pixel isolation portion 81. Fig.53In the example shown, there is an element isolation portion 82 between the second transfer transistor 54 on the left side of the figure and the VDD region 71, there is an element isolation portion 82 between the third FD portion 57-1 on the upper side of the figure and the VSS region 73, there is an element isolation portion 82 between the VSS region 73 on the right side of the figure and the third FD portion 57-2, and there is an element isolation portion 82 between the VDD region 71 on the right side of the figure and the VSL region 72.

[0314] In these contact regions between the pixel isolation section 81 and the element isolation section 82, there are regions corresponding to the regions 1, 2, and 3 described in the twelfth embodiment. Region 1 (i.e., a region for suppressing the occurrence of dark current in the FD section) is regions "a", "c", and "f".

[0315] The region 2 (ie, the region for suppressing the charges generated in the VSS region 73 from moving to the FD portion or the photodiode PD) is the regions “d” and “e”.

[0316] Region 3 (i.e., the region for suppressing the dark current generated in the VDD region 71 or the VSL region 72 from moving to the photodiode PD) is the region "b", "g", and "h".

[0317] As in the twelfth embodiment, the regions "a" to "h" are formed into a shape without a sharp portion. Fig.48 and 49 As described above, these regions can be formed by forming the element isolation portion 82 into an extended shape to avoid a sharp shape. Fig.50 and 51 As described above, these regions can be formed by forming the inter-pixel partition 81 into an extended shape to avoid a sharp shape. Fig.53 In the above description, the case where the element isolation portion 82 is formed in an extended shape is taken as an example.

[0318] As described above, even when the arrangement of transistors is changed, a structure that suppresses the occurrence of dark current or white spots can be formed.

[0319] In addition, also in Fig.53 In the structure of the pixel 2 shown, as Figure 5 In the case shown, parts of the pixel transistors (the second transfer transistor 54 , the third transfer transistor 56 , the reset transistor 58 , the amplification transistor 59 , and the selection transistor 60 ) other than the first transfer transistor 52 are also arranged on the element isolation portion 82 and the inter-pixel isolation portion 81 .

[0320] like Fig.53As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 are configured to overlap with the inter-pixel isolation portion 81. In other words, a partial region of the gate electrode of the pixel transistor is configured to be in a state where the partial region includes a region overlapping with the inter-pixel isolation portion 81 in a plan view. By forming a configuration overlapping with the inter-pixel isolation portion 81, the region of the electrode gate can be ensured.

[0321] like Fig.53 As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 are configured to also overlap the element isolation portion 82. In other words, a partial region of the gate electrode of the pixel transistor is configured to be in a state including a region overlapping the element isolation portion 82 in a plan view.

[0322] In this way, the transistors other than the first transfer transistor 52 included in the pixel 2 are arranged to surround the first transfer transistor. In addition, each transistor other than the first transfer transistor 52 included in the pixel 2 is configured so that at least one side thereof overlaps with the inter-pixel isolation portion 81 in a plan view, and the opposite side to the side overlapping with the inter-pixel isolation portion 81 overlaps with the element isolation portion 82.

[0323] By arranging the transistors in this way, the WL size of the pixel transistor that can be arranged in each pixel can be expanded, so that the cutoff difference and amplification noise of the pixel transistor can be designed to be small. In addition, the first transfer transistor 52 for transferring the charge obtained by the conversion of the photoelectric conversion unit 51 to the FD unit is arranged at the center of the pixel 2, that is, at the center of the photoelectric conversion unit 51. This can form a structure that easily transmits the signal from the photoelectric conversion unit 51 to the first FD unit 53.

[0324] <Combination with the Fifth Embodiment> Fig.54 1 is a diagram showing an example of a planar configuration of a pixel 2 for explaining a combination of the fifth embodiment and the twelfth embodiment. Fig.15 and 16 The fifth embodiment is described. As in the pixel 2 in the first to third embodiments, Fig.15 The circuit configuration example of the pixel 2 in the fifth embodiment shown is a configuration having three FD portions, and is a configuration to which an overflow transistor 201 is further added.

[0325] Fig.16 Shows that there is Fig.15 An example of a planar structure of a pixel 2 having a circuit structure shown in FIG. Fig.54 The plane structure example shown is a case where the 12th embodiment is applied to a Fig.16 The plane configuration example shown is obtained in the case of pixel 2. Fig.54The planar structure example of the pixel 2 shown is similar to Fig.16 The planar configuration example of the pixel 2 shown is similar and is formed by Fig.16 The planar configuration example of the pixel 2 shown is obtained by adding circles representing the areas "a" to "d". Fig.16 Explained Fig.54 The arrangement of transistors and the like of the pixel 2 is shown, and therefore the description thereof is omitted.

[0326] exist Fig.54 In the pixel 2 shown, there are regions corresponding to regions 1, 2, and 3 described in the twelfth embodiment in the contact region between the inter-pixel isolation portion 81 and the element isolation portion 82. Region 1 (i.e., a region for suppressing the occurrence of dark current in the FD portion) is region "a" and "b".

[0327] The region 2 (ie, the region for suppressing the movement of the charges generated in the VSS region 73 to the FD portion or the photodiode PD) is the region “d”.

[0328] The region 3 (ie, the region for suppressing the dark current generated in the VDD region 71 or the VSL region 72 from moving to the photodiode PD) is the region “c”.

[0329] As in the twelfth embodiment, the regions "a" to "d" are formed into a shape without a sharp portion. Fig.48 and 49 As described above, these regions can be formed by forming the element isolation portion 82 into an extended shape to avoid a sharp shape. Fig.50 and 51 As described above, these regions can be formed by forming the inter-pixel partition 81 into an extended shape to avoid a sharp shape. Fig.54 In the above description, the case where the element isolation portion 82 is formed in an extended shape is taken as an example.

[0330] As described above, by forming a structure without a sharp portion, it is possible to form a structure that suppresses the occurrence of dark current or white spots.

[0331] <15th embodiment> Fig.55 It is a diagram showing an example of the circuit configuration of the pixel 2 in the fifteenth embodiment. Fig.55 The circuit configuration of the pixel 2 shown is different in that it is formed by Fig.15 The circuit configuration of the pixel 2 shown in FIG. 1 is obtained by deleting the overflow transistor 201, and other aspects are similar. Fig.15In the circuit configuration of the pixel 2 shown, a configuration is shown in which the memory 501 is connected to the third FD portion 57 and the memory 501 also functions as the third FD portion 57. However, as in the above-described embodiment, a configuration without the memory 501 may also be employed.

[0332] In having Fig.55 In the case of the pixel 2 of the circuit structure shown, it is designed as follows: the low cut-off point of the third transfer transistor 56 is deeper than the low cut-off point of the reset transistor 58, and the signal accumulated in the second FD portion 55 overflows through the third transfer transistor 56 and accumulates in the third FD portion 57 (memory 501).

[0333] Fig.53 The planar structure example of the pixel 2 shown can be applied as having Fig.55 The circuit structure shown in FIG. 1 is an example of a planar structure of the pixel 2. Therefore, its description is omitted here.

[0334] For those with Fig.55 The pixel 2 with the circuit structure shown can also apply any one of the first to fourteenth embodiments or any combination of multiple embodiments.

[0335] <16th embodiment> Fig.56 16 is a diagram showing an example of a cross-sectional structure of a pixel 2 in the sixteenth embodiment. Fig.56 Pixel 2 shown with Figure 7 When compared with the pixel 2 shown in FIG. 1 , the structure of the inter-pixel isolation portion 81 is different, but other aspects are similar. Figure 7 The cross-sectional configuration example of the pixel 2 shown is similar to the description of the parts of the parts.

[0336] Fig.56 The pixel separation portion 81 of the pixel 2 shown includes an inner layer 401 filled with polysilicon or metal and an oxide film 402 surrounding the inner layer 401. The pixel separation portion 81 may be formed in a structure in which a plurality of layers are stacked in this manner.

[0337] In the case where the inter-pixel isolation portion 81 is provided with the inner layer 401, as shown in FIG. Fig.57 As shown, a power supply 421 supplying a predetermined voltage may be connected to the inner layer 401. By adopting a configuration in which a bias voltage is applied to the inner layer 401 of the inter-pixel isolation portion 81, pinning can be enhanced, and a configuration that further suppresses the occurrence of dark current can be formed.

[0338] The fifteenth embodiment may be implemented in combination with any one or more of the first to fourteenth embodiments.

[0339] <Example 17-1> Fig.58 17-1 is a diagram showing an example of a circuit configuration of the pixel 2 in the 17-1 embodiment. As in the pixel 2 in the 17-1 embodiment, the pixel 2 in the 17-1 embodiment has a configuration including three FD portions, and is formed as a configuration further adding an overflow transistor 201. Portions having the same configuration as the pixel 2 in the 1st embodiment are given the same reference numerals, and descriptions thereof are omitted as appropriate.

[0340] The pixel 2 has a photoelectric conversion portion 51 , a first transfer transistor 52 , a first FD portion 53 , a second transfer transistor 54 , a second FD portion 55 , a third transfer transistor 56 , a third FD portion 57 , a reset transistor 58 , an amplification transistor 59 , a selection transistor 60 , and an overflow transistor 201 .

[0341] The overflow transistor 201 is arranged between the photoelectric conversion portion 51 and the third FD portion 57 , and is configured so that charges overflowing from the photoelectric conversion portion 51 are accumulated in the third FD portion 57 .

[0342] The first transfer transistor 52 is arranged between the photoelectric conversion portion 51 and the first FD portion 53. A drive signal TRG is supplied to a gate electrode of the first transfer transistor 52. When the drive signal TRG becomes a high level, the first transfer transistor 52 is turned on, and the charge accumulated in the photoelectric conversion portion 51 is transferred to the first FD portion 53 through the first transfer transistor 52.

[0343] The second transfer transistor 54 is arranged between the first FD portion 53 and the second FD portion 55. A drive signal FDG is supplied to a gate electrode of the second transfer transistor 54. When the drive signal FDG becomes a high level, the second transfer transistor 54 is turned on, and the charge from the first FD portion 53 is transferred to the second FD portion 55 through the second transfer transistor 54.

[0344] Due to the turning on of the second transfer transistor 54 , the region for accumulating charges becomes a region obtained by combining the first FD portion 53 and the second FD portion 55 , and the conversion efficiency when converting charges generated in the photoelectric conversion portion into a voltage can be switched.

[0345] The third transfer transistor 56 is arranged between the second FD portion 55 and the third FD portion 57. A drive signal FCG is supplied to a gate electrode of the third transfer transistor 56. When the drive signal FCG becomes a high level, the third transfer transistor 56 is turned on, and the charge from the second FD portion 55 is transferred to the third FD portion 57 through the third transfer transistor 56.

[0346] Due to the turning on of the third transfer transistor 56, the region for accumulating charges becomes a region obtained by combining the first FD portion 53, the second FD portion 55, and the third FD portion 57, and the conversion efficiency when converting the charges generated in the photoelectric conversion portion into a voltage can be switched. As described above, the charges overflowing from the photoelectric conversion portion 51 and transferred through the overflow transistor 201 are also accumulated in the third FD portion 57.

[0347] The reset transistor 58 is connected to the power supply VDD and the third FD portion 57. A drive signal RST is supplied to the gate electrode of the reset transistor 58. When the drive signal RST is at a high level, the reset transistor 58 is turned on, and the potential of the third FD portion 57 is reset to the level of the power supply voltage VDD.

[0348] The gate electrode of the amplifier transistor 59 is connected to the first FD portion 53 and the drain is connected to the power supply VDD, and the amplifier transistor 59 is used as the input part of the readout circuit, which reads out the signal corresponding to the charge held by the first FD portion 53, that is, what is generally called a source follower circuit. That is, the source of the amplifier transistor 59 is connected to the vertical signal line 9 through the selection transistor 60. This makes the amplifier transistor 59 and the constant current source (not shown) connected to one end of the vertical signal line 9 form a source follower circuit together.

[0349] The selection transistor 60 is connected between the source of the amplifying transistor 59 and the vertical signal line 9. The drive signal SEL is supplied to the gate electrode of the selection transistor 60. When the drive signal SEL is set to a high level, the selection transistor 60 is turned on, and the pixel 2 becomes a selected state. Thus, the pixel signal output from the amplifying transistor 59 is output to the vertical signal line 9 through the selection transistor 31.

[0350] <Example of Planar Structure of Pixels> Fig.59 is shown arranged with Fig.58 A diagram showing an example of a planar structure of a transistor on a silicon substrate surface of a pixel 2 having a circuit structure shown. Fig.59 The example of the planar structure shown is similar to Figure 5 The planar structure example shown is substantially similar, but differs in that an overflow transistor 201 is added.

[0351] The gate electrode TRG of the first transfer transistor 52 is formed around the center of the pixel 2. The gates of the transistors other than the first transfer transistor 52 included in the pixel 2 are constructed with the gate electrode TRG of the first transfer transistor 52 as the center. In the figure, the gate electrode FDG of the second transfer transistor 54 is formed on the left side of the gate electrode TRG of the first transfer transistor 52. The first FD portion 53 including an N+ diffusion layer is arranged between the gate electrode TRG and the gate electrode FDG and is located in the silicon substrate.

[0352] The gate electrode FCG of the third transfer transistor 56 is formed on the upper side in the figure of the gate electrode TRG of the first transfer transistor 52. The second FD portion 55 is arranged between the second transfer transistor 54 and the third transfer transistor 56.

[0353] The gate electrode RST of the reset transistor 58 is formed on the upper right side of the gate electrode TRG of the first transfer transistor 52. The third FD portion 57 is formed between the third transfer transistor 56 and the reset transistor 58.

[0354] The gate AMP of the amplifier transistor 59 is formed on the right side in the figure of the gate TRG of the first transfer transistor 52. A VDD region 71 including a P+ diffusion layer and connected to a power supply voltage VDD is formed between the reset transistor 58 and the amplifier transistor 59.

[0355] The gate electrode SEL of the selection transistor 60 is formed on the lower side in the figure of the gate electrode TRG of the first transfer transistor 52. A VSL region connected to the vertical signal line 9 is formed on the left side of the selection transistor 60 in the figure.

[0356] A VSS region 73 including a P+ diffusion layer is formed on the lower left side of the first transfer transistor 52 in the figure.

[0357] The gate electrode OFG of the overflow transistor 201 is formed between the gate electrode TRG of the first transfer transistor 52 and the third FD portion 57 .

[0358] The pixel isolation part 81 is formed to surround the pixel 2. For example, the pixel isolation part 81 is formed by FFTI (front full trench isolation part). The pixel isolation part 81 can be formed by a groove that does not penetrate or penetrates the semiconductor substrate. The pixel 2 is isolated by the insulator caused by the pixel isolation part 81, and each pixel 2 is constructed to be electrically isolated.

[0359] The element isolation portion 82 is formed between transistors constituting the pixel 2. The element isolation portion 82 employs, for example, a structure in which a trench having a predetermined depth is formed in an element isolation region and an insulating film is buried in the trench, or a region formed by ion implantation.

[0360] For pixel 2, the inter-pixel isolation section 81 is arranged in the pixel boundary region, and element isolation is established in the active region by the element isolation section 82. The active region is a region shown as an open region in the figure, and is formed in a shape continuous from the lower side of the gate electrode TRG of the first transfer transistor 52 to the VSL region 72. In addition, the active region is also arranged in the region where the overflow transistor 201 is arranged. Therefore, a configuration having a shape that allows the active region of the first transfer transistor 52 and the active region of the third FD section 57 to also be continuous is formed.

[0361] The element isolation portion 82 is formed so as to be in contact with the pixel isolation portion 81. Fig.59 In the illustrated example, the element isolation portion 82 existing between the second transfer transistor 54 and the VSS region 73 and the element isolation portion 82 existing between the VSS region 73 and the VSL region 72 are formed in contact with the inter-pixel isolation portion 81 .

[0362] Pixel transistors other than the first transfer transistor 52 (the second transfer transistor 54 , the third transfer transistor 56 , the reset transistor 58 , the amplification transistor 59 , and the selection transistor 60 ) are arranged not only on the element isolation portion 82 as an element isolation structure but also on the inter-pixel isolation portion 81 .

[0363] like Fig.59 As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 and the overflow transistor 201 are configured to overlap with the inter-pixel isolation portion 81. In other words, a partial region of the gate electrodes of these pixel transistors is configured to be in a state where the partial region includes a region overlapping with the inter-pixel isolation portion 81 in a plan view. By forming a configuration overlapping with the inter-pixel isolation portion 81, the region of the electrode gate can be ensured.

[0364] In this way, the transistors included in the pixel 2 other than the first transfer transistor 52 are arranged to surround the first transfer transistor. In addition, each transistor included in the pixel 2 other than the first transfer transistor 52 and the overflow transistor 201 is configured so that at least one side thereof overlaps with the inter-pixel isolation portion 81 in a plan view, and the opposite side of the side overlapping with the inter-pixel isolation portion 81 overlaps with the element isolation portion 82.

[0365] By arranging the transistors in this way, the WL size of the pixel transistor that can be arranged in each pixel can be expanded, so that the cutoff difference and amplification noise of the pixel transistor can be designed to be small. In addition, the first transfer transistor 52 for transferring the charge obtained by the conversion of the photoelectric conversion unit 51 to the FD unit is arranged at the center of the pixel 2, that is, at the center of the photoelectric conversion unit 51. This can form a structure that easily transmits the signal from the photoelectric conversion unit 51 to the first FD unit 53.

[0366] <Example of cross-sectional structure of pixel> Fig.60 Shows Fig.59 The cross-sectional structure example of the pixel 2 along the line segment AA' is shown. Fig.61 Shows Fig.59 The cross-sectional structure example of the pixel 2 along the line segment BB' is shown.

[0367] Reference Fig.60 and 61The pixel 2 shown in FIG. 1 is an example of a cross-sectional structure of the pixel 2, wherein the pixel 2 includes a semiconductor substrate 80 and a multilayer interconnection layer (not shown) formed on the front side (upper side in the figure) of the semiconductor substrate. Figure 7 In the figure, the lower side is the light incident side and is the side where the on-chip lens and color filter (not shown) are arranged. Fig.60 and 61 In the embodiment, the upper side is an interconnection layer side, and a plurality of transistors are formed on this side.

[0368] The photodiode PD is formed in the semiconductor substrate 80 in units of pixels. Between the pixels 2 of the semiconductor substrate 80, an inter-pixel isolation portion 81 is formed to a predetermined depth in the depth direction of the substrate from the back side (light incident side) of the semiconductor substrate 80. At the same time, on the front side of the semiconductor substrate 80 where a multi-layer interconnection layer is formed, a first transfer transistor 52 is formed for one photodiode PD formed in each pixel 2. The gate electrode TRG of the first transfer transistor 52 is connected to the N-type region of the photodiode PD. The N+ region 105 as the first FD portion 53 is formed on the left side of the first transfer transistor 52 in the figure.

[0369] The second transfer transistor 54 is formed on the left side in the figure of the first FD portion 53. The channel 113 is formed by an N-type region located on the lower side of the gate electrode FDG of the second transfer transistor 54.

[0370] like Fig.60 As shown, the gate electrode FDG of the second transfer transistor 54 is formed in position and size so that one side thereof includes a region overlapping with the inter-pixel isolation section 81. Fig.60 Although not shown in the figure, a portion of the gate electrode FDG of the second transfer transistor 54 is formed to include a region overlapping with the element isolation portion 82 .

[0371] The element isolation portion 82 is formed on the right side of the first transfer transistor 52. The pinning film 108 is formed on the lower side of the element isolation portion 82. The amplifier transistor 59 is formed on the right side of the element isolation portion 82. The channel 106 is formed by the N-type region located on the lower side of the gate electrode AMP of the amplifier transistor 59.

[0372] like Fig.60 As shown, the gate electrode AMP of the amplifier transistor 59 is formed in position and size such that one side thereof includes a region overlapping with the element isolation portion 82 , and the other side includes a region overlapping with the inter-pixel isolation portion 81 .

[0373] As described above, transistors (eg, Fig.60The selection transistor 60 and the amplification transistor 59 in the transistor 80 are structured so that (part of) one side thereof exists on the inter-pixel isolation portion 132 and (part of) the other side exists on the element isolation portion 82.

[0374] Reference Fig.61 In the cross-sectional configuration example shown, the element isolation portion 82 is formed on the left side in the figure of the first FD portion 53. The pinning film 108 is formed on the lower side of the element isolation portion 82. The selection transistor 60 is formed on the right side in the figure of the element isolation portion 82. The channel 104 is formed by the N-type region located on the lower side of the gate electrode SEL of the selection transistor 60.

[0375] like Fig.61 As shown, the gate electrode SEL of the selection transistor 60 is formed in position and size such that one side thereof includes a region overlapping with the element isolation portion 82 , and the other side includes a region overlapping with the inter-pixel isolation portion 81 .

[0376] The gate electrode OFG of the overflow transistor 201 is formed on the right side of the gate electrode TRG of the first transfer transistor 52. The channel 114 is formed by an N-type region from the right side of the lower side of the gate electrode TRG of the first transfer transistor 52 to the lower side of the gate electrode OFG of the overflow transistor 201.

[0377] The N+ region 112 as the third FD portion 57 is formed on the right side of the overflow transistor 201 in the figure.

[0378] As described above, transistors (eg, Fig.61 The selection transistor 60 in FIG. 1 is structured so that one side thereof exists on the inter-pixel isolation portion 81 and the other side exists on the element isolation portion 82.

[0379] like Fig.62 and 63 As shown, the gate electrode TRG of the first transfer transistor 52 may have a configuration in which the gate is also arranged in the vertical direction. Fig.62 and 63 , a configuration is formed in which a portion of the gate electrode TRG of the first transfer transistor 52 is arranged to reach a portion of the photodiode PD.

[0380] The gate electrode TRG of the first transfer transistor 52 is formed as follows, which has a gate arranged on the front surface of the semiconductor substrate 80 (a gate arranged in the horizontal direction) and a gate arranged inside the N-type semiconductor region 101 of the photodiode PD in the semiconductor substrate 80 (a gate arranged in the vertical direction).

[0381] It is also possible to construct as follows: using a vertical transistor having a gate also arranged in the vertical direction. Here, the case where the first transfer transistor 52 is a vertical transistor is described as an example. However, the present technology can also be applied to the case where a transistor other than the first transfer transistor 52 is a vertical transistor.

[0382] <Example 17-2> Fig.64 is a diagram showing an example of the circuit configuration of the pixel 2 in Embodiment 17-2. Fig.64 The pixel 2 in the embodiment 17-2 shown is different in that it is formed by Fig.58 The pixel 2 in the embodiment 17-1 shown has a structure obtained by deleting the overflow transistor 201, and other aspects are similar. Regarding similar aspects, the description will be appropriately omitted.

[0383] One side of the third FD portion 57 is connected to the photoelectric conversion portion 51 , and the other side is connected to the reset transistor 58 .

[0384] Fig.65 17-2 is a diagram showing an example of a planar structure of the pixel 2 in the embodiment 17-2. Since a structure is adopted in which the overflow transistor 201 is not included between the third FD portion 57 and the photoelectric conversion portion 51, the pixel 2 is constructed so that the overflow transistor 201 is not arranged between the first transfer transistor 52 and the third FD portion 57.

[0385] Although the overflow transistor 201 is not arranged, a region having the function of the overflow transistor 201 is arranged. Fig.66 is shown along Fig.65 FIG. 1 is a diagram showing an example of a cross-sectional structure of a line segment BB′ shown in FIG. The N+ region 112 as the third FD portion 57 is formed on the right side of the gate electrode TRG of the first transfer transistor 52 in the diagram.

[0386] The N-type region 121 is formed between the right portion of the lower side in the figure of the gate electrode TRG of the first transfer transistor 52 and the third FD portion 57. The N-type region 121 is configured to have a potential gradient and allows the charge overflowing from the photoelectric conversion portion 51 to be easily transferred to the third FD portion 57. By arranging such a region having a potential gradient between the photoelectric conversion portion 51 and the third FD portion 57, a configuration in which the overflow transistor 201 is not arranged can also be adopted. Fig.66, an example is shown in which an N+ region 121 is formed in the front surface of the silicon substrate. However, a configuration may be adopted in which an N+ region 121 having a potential gradient is formed in a region at a predetermined depth from the front surface in the depth direction. By arranging the N+ region 121 at a position separated from the third FD portion 57, a configuration in which overflow control is not easily affected by drain modulation may be formed. It should be noted that the drain here is the third FD portion 57. A configuration that is not easily affected by a drop in drain voltage due to the occurrence of overflow and drain modulation may be achieved.

[0387] along Fig.65 The cross-section construction of the line segment A-A' in Fig.60 The cross-sectional configurations shown are similar, so descriptions thereof are omitted.

[0388] like Fig.67 As shown in the cross-sectional configuration example of FIG. 2 , a configuration may also be adopted in which the first transfer transistor 52 is formed as a vertical transistor also in the pixel 2 that does not include the overflow transistor 201 and includes the region 121 having the potential gradient.

[0389] <Example 17-3> The pixel 2 in the 17-3 embodiment will be described. For the circuit of the pixel 2 in the 17-3 embodiment, for example, Fig.64 The circuit configuration shown has three FD portions and does not include the overflow transistor 201. As for the planar configuration example, it is applicable Figure 5 ( Fig.18 ) is an example of a planar structure of a pixel 2 shown in FIG.

[0390] Fig.68 It is a diagram showing an example of the cross-sectional structure of the pixel 2 in Example 17-3. Fig.68 The cross-sectional configuration example shown is along Fig.18 , and shows a cross-sectional configuration example along the line segment CC', along which the selection transistor 60, the first transfer transistor 52, and the third FD portion 57 are arranged. The element isolation portion 82 is arranged between the first transfer transistor 52 and the third FD portion 57, and the N+ region 121 is arranged on the lower side of the element isolation portion 82 in the figure and is located in the silicon substrate.

[0391] The N+ region 121 includes, for example, an N-type region having a potential gradient. By forming the N+ region 121 from a region having a potential gradient, a structure in which the charge overflowing from the photoelectric conversion unit 51 is easily transferred to the third FD unit 57 can be realized. By arranging the N+ region 121 having a potential gradient between the photoelectric conversion unit 51 and the third FD unit 57 and on the lower side of the element isolation unit 82 (in the silicon substrate), a structure in which the overflow transistor 201 is not arranged can also be formed. In addition, by arranging the element isolation unit 82 between the first transfer transistor 52 and the third FD unit 57, the overflow can be controlled without being affected by the drain modulation of the third FD unit 57.

[0392] like Fig.69 As shown in the cross-sectional configuration example of , a configuration may also be adopted in which the first transfer transistor 52 is formed as a vertical transistor also in the pixel 2 which does not include the overflow transistor 201 and includes the N+ region 121 having a potential gradient.

[0393] Furthermore, in these 17th embodiments, the WL size of the pixel transistor that can be arranged per pixel can be enlarged, and the cutoff difference and amplification noise of the pixel transistor can be designed to be small. In addition, the first transfer transistor 52 for transferring the charge obtained by the conversion of the photoelectric conversion section 51 to the FD section is arranged at the center of the pixel 2, that is, at the center of the photoelectric conversion section 51. This can form a configuration that easily transfers the signal from the photoelectric conversion section 51 to the first FD section 53.

[0394] The above-mentioned first to seventeenth embodiments may of course be implemented individually, or a plurality of these embodiments may be implemented in combination.

[0395] <Example 18-1> Fig.70 The planar configuration example of the pixel 2 shown is Figure 2 The plane configuration example among the circuit configuration examples of the pixel 2 shown is a plane configuration example of the pixel 2 in Embodiment 18-1.

[0396] The gate electrode TRG of the first transfer transistor 52 is formed around the center of the pixel 2. In the figure, the gate electrode FDG of the second transfer transistor 54 is formed on the left side of the gate electrode TRG of the first transfer transistor 52. The first FD portion 53 including an N+ diffusion layer is arranged between the gate electrode TRG and the gate electrode FDG and is located in the silicon substrate.

[0397] The gate electrode FCG of the third transfer transistor 56 is formed on the upper side in the figure of the gate electrode TRG of the first transfer transistor 52. The second FD portion 55 is arranged between the second transfer transistor 54 and the third transfer transistor 56.

[0398] The gate electrode RST of the reset transistor 58 is formed on the upper right side of the gate electrode TRG of the first transfer transistor 52. The third FD portion 57 is formed between the third transfer transistor 56 and the reset transistor 58.

[0399] A VDD region 71 including a P+ diffusion layer and connected to a power supply voltage VDD and a VSS region 73 including a P+ diffusion layer are formed on the right side of the gate electrode TRG of the first transfer transistor 52 .

[0400] The VSL region 72 connected to the vertical signal line 9 is formed on the lower right side of the gate electrode TRG of the first transfer transistor 52 and on the lower side of the VSS region 73. The element isolation section 82 is arranged between the VDD region 71 and the VSS region 73 and between the VSS region 73 and the VSL region 72.

[0401] The gate electrode SEL of the selection transistor 60 and the gate electrode AMP of the amplifier transistor 59 are formed on the lower side in the figure of the gate electrode TRG of the first transfer transistor 52. The VDD region 71 is formed on the left side of the gate electrode AMP of the amplifier transistor 59 in the figure.

[0402] exist Fig.70 In the pixel 2 shown, the gate electrode AMP of the amplifier transistor 59 is formed on the lower side of the first FD portion 53. The first FD portion 53 and the gate electrode AMP are connected by an interconnection. Fig.70 In the pixel 2 in the illustrated 18-1st embodiment, the first FD portion 53 and the amplification transistor 59 are arranged at close positions compared to the pixels 2 in the 1st to 17th embodiments.

[0403] Since the first FD portion 53 and the amplifying transistor 59 are arranged in close positions, the D (data phase) range during high conversion efficiency operation can be increased. In addition, high conversion efficiency is allowed, and image quality under low illumination can be improved.

[0404] The inter-pixel isolation section 81 is formed to surround the pixel 2. The pixel 2 is isolated by the insulator caused by the inter-pixel isolation section 81, and each pixel 2 is configured to be electrically isolated. The element isolation section 82 is formed between the transistors constituting the pixel 2. The element isolation section 82 adopts, for example, a structure obtained by forming a groove having a predetermined depth in the element isolation region and burying an insulating film in the groove or a region formed by ion implantation.

[0405] For the pixel 2, the inter-pixel isolation section 81 is arranged in the pixel boundary region, and the element isolation is established in the active region by the element isolation section 82. The active region is a region shown as an open region in the figure, and is formed to have a shape continuous from the lower side of the gate electrode TRG of the first transfer transistor 52 to the VDD region 71. In addition, the active region is formed to have a shape continuous from the VSL region 72 formed along the side located on the lower side in the figure to the VDD region 71.

[0406] The element isolation portion 82 is partially formed so as to be in contact with the inter-pixel isolation portion 81. Fig.70 In the example shown, the element isolation portion 82 existing between the second transfer transistor 54 and the VDD region 71, the element isolation portion 82 existing between the VDD region 71 and the VSS region 73, and the element isolation portion 82 existing between the VSS region 73 and the VSL region 72 are formed to be in contact with the inter-pixel isolation portion 81.

[0407] Pixel transistors other than the first transfer transistor 52 (the second transfer transistor 54 , the third transfer transistor 56 , the reset transistor 58 , the amplification transistor 59 , and the selection transistor 60 ) are arranged not only on the element isolation portion 82 as an element isolation structure but also on the inter-pixel isolation portion 81 .

[0408] like Fig.70 As shown, the gate electrodes of the pixel transistors other than the first transfer transistor 52 are configured to overlap with the inter-pixel isolation portion 81. In other words, partial regions of the gate electrodes of these pixel transistors are configured to be in a state where the partial regions include a region overlapping with the inter-pixel isolation portion 81 in a plan view. By forming a configuration overlapping with the inter-pixel isolation portion 81, the region of the electrode gate can be ensured.

[0409] Similarly, in the pixel 2 of the 18-1 embodiment, the WL size of the pixel transistor that can be arranged in each pixel can be increased, and thus the cutoff difference and amplification noise of the pixel transistor can be designed to be small. In addition, the first transfer transistor 52 for transferring the charge obtained by the conversion of the photoelectric conversion unit 51 to the FD unit is arranged at the center of the pixel 2, that is, at the center of the photoelectric conversion unit 51. This can form a structure that easily transfers the signal from the photoelectric conversion unit 51 to the first FD unit 53.

[0410] <Example 18-2> Fig.71 The planar configuration example of the pixel 2 shown is Figure 2 The plane configuration example among the circuit configuration examples of the pixel 2 shown is a plane configuration example of the pixel 2 in Embodiment 18-2.

[0411] Fig.71 The adjacent pixel 2-1 and pixel 2-2 are shown. The pixel 2-1 and the pixel 2-2 each have Figure 5 The pixel 2 shown in FIG. 1 is similar in structure, and the arrangement of transistors, etc. is basically similar. Fig.71 In the pixel 2-1 and the pixel 2-2 shown in FIG. 1 , the gate electrode FDG of the second transfer transistor 54 is configured to be smaller than Figure 5 The gate electrode FDG is shown.

[0412] exist Fig.71 In the gate electrode FDG shown in FIG. 1 , the left side in the figure overlaps with the pixel isolation portion 81, and the right side overlaps with the element isolation portion 82. Figure 5 The gate electrode FDG shown is different, Fig.71 The gate electrode FDG shown is formed in a structure in which the lower side in the figure does not overlap with the element isolation portion 82 .

[0413] The pixel 2 in the 18-2nd embodiment is configured to use the amplification transistor 59 and the selection transistor 60 located in the adjacent pixel 2 as the amplification transistor 59 and the selection transistor 60 of the own pixel 2. When focusing on the pixel 2-2 as the own pixel 2, Figure 2 In the circuit structure shown in connection with the pixel 2-2, the first transfer transistor 52, the second transfer transistor 54, the third transfer transistor 56 and the reset transistor 58 are constructed by transistors arranged in the area of ​​the pixel 2-2, and the amplification transistor 59 and the selection transistor 60 are constructed by transistors arranged in the area of ​​the adjacent pixel 2-1 (another pixel 2) on the left side of the figure.

[0414] The pixel 2 in the first to 18-1 embodiments is an example in which the transistors are arranged so that Figure 2 The circuit shown in relation to the own pixel 2 can be constructed by transistors arranged in the own pixel 2. The pixel 2 in the 18-2 embodiment is an example in which the transistors are arranged so that Figure 2 The circuit shown in relation to the own pixel 2 can be constructed by a transistor arranged in the own pixel 2 and a transistor arranged in another adjacent pixel 2 .

[0415] The charge accumulated in pixel 2-2 is arranged at Fig.71The range 601 is processed by the transistors and regions in the range 601 shown. The range 601 includes the first transfer transistor 52-2, the first FD portion 53-2, the second transfer transistor 54-2, the second FD portion 55-2, the third transfer transistor 56-2, the third FD portion 57-2, the reset transistor 58-2, the VDD region 71-2, and the VSS region 73-2 arranged in the region of the pixel 2-2. In addition, the range 601 also includes the amplification transistor 59-1, the selection transistor 60-1, the VSL region 72-1, and the VSS region 73-1 arranged in the region of the pixel 2-1.

[0416] As described above, a configuration is adopted in which a transistor arranged in the region of the adjacent pixel 2 is used as the amplifier transistor 59. The first FD portion 53-2 of the own pixel 2-2 and the amplifier transistor 59-1 of another pixel 2-1 are connected by an interconnection portion arranged through an inter-pixel isolation portion, etc. This forms a configuration in which a signal can be supplied from the first FD portion 53-2 to the amplifier transistor 59-1.

[0417] By using the amplifier transistor 59 arranged in the adjacent pixel 2, the distance between the amplifier transistor 59 and the first FD portion 53 can be shortened. For example, when the distance "a" between the amplifier transistor 59-2 and the first FD portion 53-2 in the own pixel 2-2 and the distance "b" between the amplifier transistor 59-1 in the pixel 2-1 and the first FD portion 53-2 in the pixel 2-2 are compared, the relationship of distance "a">distance "b" is satisfied.

[0418] As in the 18-1st embodiment, the D range during high conversion efficiency operation can be increased by shortening the distance between the amplifying transistor 59 and the first FD portion 53. In addition, high conversion efficiency can be achieved, and image quality under low illumination can be improved.

[0419] By adopting this structure, it is not necessary to perform poly shielding on the gate electrode FDG, and Fig.71 As shown, the area of ​​the gate electrode FDG can be reduced. By reducing the area of ​​the gate electrode FDG, it is also possible to prevent a voltage drop caused by charge injection in the P phase (Preset Phase).

[0420] High conversion efficiency can be achieved while reducing coupling between the amplification transistor 59 (AMP) and the second transfer transistor 54 (FDG).

[0421] <Example 18-3> Fig.72 The planar configuration example of the pixel 2 shown is Figure 2 The plane configuration example among the circuit configuration examples of the pixel 2 shown is a plane configuration example of the pixel 2 in Embodiment 18-3.

[0422] The pixel 2 in the above-mentioned Embodiment 18-2 is described by taking the case where the amplifying transistor 59 and the selecting transistor 60 arranged in the region of the adjacent pixel 2 as an example. The pixel 2 in the Embodiment 18-3 is described by taking the case where the amplifying transistor 59 arranged in the region of the adjacent pixel 2 and the selecting transistor 60 arranged in the region of the own pixel 2 as an example. In the case of such a configuration, a similar structure as in the above-mentioned Embodiment 18-4 is formed. Fig.72 The arrangement shown is similar to the transistor arrangement.

[0423] Pixel 2-1 and pixel 2-2 have the same structure. Therefore, taking pixel 2-1 as an example, the structure of pixel 2 is described. The gate electrode TRG of the first transfer transistor 52-1 is formed around the center of the pixel 2-1. In the figure, the gate electrode FDG of the second transfer transistor 54-1 is formed on the upper left side of the gate electrode TRG of the first transfer transistor 52-1. The first FD portion 53-1 including an N+ diffusion layer is arranged between the gate electrode TRG and the gate electrode FDG and is located in the silicon substrate.

[0424] The gate electrode FCG of the third transfer transistor 56 - 1 is formed on the upper side in the figure of the gate electrode TRG of the first transfer transistor 62 - 1 The second FD portion 55 - 1 is arranged between the second transfer transistor 54 - 1 and the third transfer transistor 56 - 1 .

[0425] The gate electrode RST of the reset transistor 58 - 1 is formed on the upper right side of the gate electrode TRG of the first transfer transistor 52 - 1. The third FD portion 57 - 1 is formed between the third transfer transistor 56 - 1 and the reset transistor 58 - 1.

[0426] A VDD region 71 - 1 including a P+ diffusion layer and connected to a power supply voltage VDD and a gate electrode AMP of the amplification transistor 59 - 1 are formed on the right side of the gate electrode TRG of the first transfer transistor 52 - 1 .

[0427] A VSS region 73 - 1 , a VSL region 72 - 1 connected to the vertical signal line 9 , and a gate electrode SEL of the selection transistor 60 - 1 are formed on the lower side of the gate electrode TRG of the first transfer transistor 52 - 1 .

[0428] exist Fig.72 The figure shown shows two adjacent pixels 2 having such a configuration. Fig.72 2-1 and 2-2 are shown adjacent to each other. Fig.71 The pixel 2 shown in Fig.72 In the pixel 2 shown in FIG. 1 , the gate electrode FDG of the second transfer transistor 54 is configured to be smaller than Figure 5 The gate electrode FDG is shown.

[0429] The pixel 2 in the 18-3 embodiment is configured to use the amplification transistor 59-1 located in the adjacent pixel 2. In the case of focusing on the pixel 2-2, Figure 2 In the circuit structure shown in connection with pixel 2-2, the first transfer transistor 52, the second transfer transistor 54, the third transfer transistor 56, the reset transistor 58 and the selection transistor 60 are constructed by transistors arranged in the area of ​​pixel 2-2 (its own pixel), and the amplification transistor 59 is constructed by transistors arranged in the area of ​​the adjacent pixel 2-1 on the left side in the figure.

[0430] In the pixel 2 of the 18-3 embodiment, the transistors are arranged so that a transistor arranged in the own pixel 2 and a transistor arranged in another adjacent pixel 2 can be constructed. Figure 2 The circuit shown is related to the pixel 2 itself.

[0431] The charges accumulated in pixel 2-2 are arranged at Fig.72 The range 602 includes the first transfer transistor 52-2, the first FD portion 53-2, the second transfer transistor 54-2, the second FD portion 55-2, the third transfer transistor 56-2, the third FD portion 57-2, the reset transistor 58-2, the selection transistor 60-2, the VDD region 71, and the VSS region 73 arranged in the region of the pixel 2-2. In addition, the range 602 also includes the amplification transistor 59-1 and the VSS region 73-1 arranged in the region of the pixel 2-1.

[0432] As described above, a configuration is adopted in which a transistor arranged in a region of an adjacent pixel 2 is used as the amplifier transistor 59. The first FD portion 53-1 arranged in a region in the own pixel 2 and the amplifier transistor 59 arranged in a region in another pixel 2 are connected by an interconnection portion arranged through the inter-pixel isolation portion 81, etc. This forms a configuration in which a signal can be supplied from the first FD portion 53 to the amplifier transistor 59. In addition, the selection transistor 60-2 arranged in a region in the pixel 2-2 and the VDD region 71-1 connected to the amplifier transistor 59-1 in a region arranged in the pixel 2-1 are connected by an interconnection portion arranged through the inter-pixel isolation portion 81, etc. This forms a configuration in which a signal can be supplied from the amplifier transistor 59-1 to the selection transistor 60-2.

[0433] As in the 18-1st embodiment, the D range during high conversion efficiency operation can be increased by shortening the distance between the amplifying transistor 59 and the first FD portion 53. In addition, high conversion efficiency can be achieved, and image quality under low illumination can be improved.

[0434] By adopting such a structure, it is not necessary to perform poly shielding on the gate electrode FDG, and Fig.72 As shown, the area of ​​the gate electrode FDG can be reduced. By reducing the area of ​​the gate electrode FDG, it is also possible to prevent a voltage drop caused by charge injection in the P phase.

[0435] High conversion efficiency can be achieved while reducing coupling between the amplification transistor 59 (AMP) and the second transfer transistor 54 (FDG).

[0436] <Example 19-1> The 19th embodiment is an embodiment related to connection between transistors, connection between a transistor and a predetermined region, connection between predetermined regions, etc., and can be applied to any mode of the 1st to 18th embodiments. Here, the application of the 19th embodiment to the interconnection portion for connecting the first FD portion 53-2 to the gate AMP of the amplification transistor 59-1 is described as an example. Fig.71 The situation of pixel 2 of embodiment 18-2 is shown.

[0437] Fig.73 2 is an enlarged view of the first FD portion 53-2 and the amplifier transistor 59-1, and is a diagram showing the interconnection portion connecting them. The inter-pixel isolation portion 81 is arranged between the pixel 2-1 and the pixel 2-2. One side wall of the gate electrode AMP of the amplifier transistor 59-1 is located on the inter-pixel isolation portion 81, and the other side wall is located on the element isolation portion 82.

[0438] A metal contact 701 arranged in the vertical direction in the figure is connected to the gate electrode AMP. The metal contact 701 is connected to an interconnect 703. The interconnect 703 is an interconnect arranged in the M1 layer among the multi-layer interconnect layers stacked on the semiconductor substrate 80. The metal contact 702 is also connected to the interconnect 703, and is connected to the first FD portion 53-2.

[0439] Will refer to Fig.74 and 75 The connection without using such metal contacts 701 and 702 and interconnection 703 is illustrated. Fig.74 An example of a planar configuration of the pixel 2 in Embodiment 19-1 is shown. Fig.75 1 is an enlarged view of an example of a cross-sectional structure of a portion of the amplifier transistor 59 .

[0440] as Fig.71 The example of plane construction shown, Fig.74 The illustrated planar configuration example shows adjacent pixel 2 - 1 and pixel 2 - 2 . Fig.74The gate electrode AMP of the amplifier transistor 59-1 arranged in the region of the pixel 2-1 shown is arranged to extend to a position in contact with the first FD portion 53-2 of the adjacent pixel 2-2. The gate electrode AMP of the amplifier transistor 59-1 is also formed on the inter-pixel isolation portion 81 and further formed to the first FD portion 53-1 in front.

[0441] Reference Fig.75 In the cross-sectional configuration example shown, the inter-pixel isolation portion 81 is arranged between the pixel 2-1 and the pixel 2-2. One side wall of the gate electrode AMP of the amplifier transistor 59-1 is located on the inter-pixel isolation portion 81, and the other side wall is located on the first FD portion 53-2. The gate electrode AMP is formed from the inside of the pixel 2-1 to the position on the first FD portion 53-2 in the pixel 2-2 via the inter-pixel isolation portion 81.

[0442] In the case where the gate electrode AMP includes Poly-Si (polycrystalline silicon), the amplification transistor 59 - 1 and the first FD portion 53 - 1 are configured to be directly connected through the Poly electrode.

[0443] Since a connection without using metal contacts 701 and 702 and interconnect 703 is applied in this way, there is no need to consider the layout and contact capacitance of metal contacts 701 and 702 and interconnect 703, etc. Therefore, design restrictions are reduced and conversion efficiency can be improved.

[0444] <Example 19-2> Fig.76 It is a diagram showing an example of the cross-sectional structure of the pixel 2 in Example 19-2. Fig.76 The structure of the pixel 2 shown shows a structure in the case where a side contact portion for connection is formed between the amplification transistor 59 - 1 and the first FD portion 53 - 2 .

[0445] The gate electrode AMP of the amplifying transistor 59-1 has a groove structure at the side of the first FD portion 53 of the pixel 2-2, and the groove structure is filled with a material forming the gate electrode AMP, such as Poly-Si. The gate electrode AMP is formed into a structure that forms a contact portion in the semiconductor substrate 80 and is located at the side of the first FD portion 53-2.

[0446] Fig.76 The structure of the gate electrode AMP shown is formed as follows: one side of the gate electrode AMP is located on the element isolation portion 82-1 of the pixel 2-1, and the other side is located in a groove structure formed at the side of the first FD portion 53-1 of the semiconductor substrate 80 of the pixel 2-2, and the gate electrode AMP is in contact with the first FD portion 53-2 at a portion of the groove structure.

[0447] By adopting a structure in which a contact portion is formed from the side surface of the first FD portion 53 (forming a side contact portion), it is possible to improve the layout flexibility of the gate electrode AMP (for example, an electrode including Poly-Si) of the amplifier transistor 59. Therefore, a design with high flexibility can also be achieved for the design of conversion efficiency and anti-noise measures.

[0448] <Example 19-3> Fig.77 It is a diagram showing an example of the cross-sectional structure of the pixel 2 in Example 19-3. Fig.77 The structure of the pixel 2 shown is another structure in the case where a side contact portion for connection is formed between the amplification transistor 59 - 1 and the first FD portion 53 - 2 .

[0449] The gate electrode AMP of the amplifier transistor 59-1 has a groove structure located in the inter-pixel isolation portion 81 on the first FD portion 53-2 side of the pixel 2-2, and the groove structure is filled with a material forming the gate electrode AMP, such as Poly-Si. The gate electrode AMP is formed in the inter-pixel isolation portion 81 as a structure in contact with the side surface of the first FD portion 53-2.

[0450] Fig.77 The structure of the gate electrode AMP shown is formed as follows: one side of the gate electrode AMP is located on the element isolation portion 82-1 of the pixel 2-1, and the other side is located in a groove structure formed in the side of the inter-pixel isolation portion 81 of the pixel 2-2, and the gate electrode AMP contacts the side of the first FD portion 53-2 at a portion of the groove structure.

[0451] By adopting a structure in which a contact portion is formed from the side surface of the first FD portion 53 (forming a side surface contact portion), flexibility in layout of the gate electrode AMP of the amplifier transistor 59 can be improved. Therefore, design with high flexibility can also be achieved for designing conversion efficiency and anti-noise measures.

[0452] <Example 19-4> Fig.78 It is a diagram showing an example of the cross-sectional structure of the pixel 2 in Example 19-4. Fig.78 The configuration of the pixel 2 shown shows another configuration in the case where a side contact portion for connection is formed between the amplification transistor 59 and the first FD portion 53 .

[0453] Fig.78 The structure shown can be applied to, for example, Fig.70 Pixel 2 shown. Fig.70The pixel 2 shown has a structure in which the amplifier transistor 59 is arranged on the lower side of the first FD portion 53 in the plan view, and the first FD portion 53 and the amplifier transistor 59 are connected. The case where the connection in the 19-4 embodiment is applied to the first FD portion 53 and the amplifier transistor 59 arranged in such a pixel 2 will be described below.

[0454] The gate electrode AMP of the amplifier transistor 59 has a trench structure in a portion of the element isolation portion 82 existing between the first FD portion 53 and the amplifier transistor 59 or in a side of the element isolation portion 82, and has a structure in which a material (e.g., Poly-Si) forming the gate electrode AMP is filled in the trench structure.

[0455] One side (left side in the figure) of the gate electrode AMP is located on the inter-pixel isolation portion 81 and the other side is formed in contact with the first FD portion 53 at the portion of the trench structure.

[0456] By adopting a structure in which a contact portion is formed from the side surface of the first FD portion 53 (forming a side surface contact portion), flexibility in layout of the gate electrode AMP of the amplifier transistor 59 can be improved. Therefore, design with high flexibility can also be achieved for designing conversion efficiency and anti-noise measures.

[0457] <Example 19-5> Fig.79 It is a diagram showing an example of the cross-sectional structure of the pixel 2 in Example 19-5. Fig.79 The structure of the pixel 2 shown has a structure in which a contact portion 711 including a predetermined material is used for connection between the amplification transistor 59 - 1 and the first FD portion 53 - 2 .

[0458] The inter-pixel isolation portion 81 is arranged between the pixel 2-1 and the pixel 2-2. One side wall of the gate electrode AMP of the amplifier transistor 59-1 is located on the inter-pixel isolation portion 81, and the other side wall is located on the element isolation portion 82. The contact portion 711 is formed to cover a portion (in the figure, about half) of the upper portion of the gate electrode AMP, to cover the upper portion of the side wall arranged on the inter-pixel isolation portion 81, and to cover a range up to the upper portion of the first FD portion 53-2 arranged in the pixel 2-2.

[0459] The contact portion 711 includes, for example, Poly-Si (polycrystalline silicon). In this case, the gate electrode AMP has, for example, Fig.73 The above-described configuration is implemented, and a contact portion 711 is formed that establishes connection from such a gate electrode AMP to the first FD portion 53. A configuration in which such a contact portion 711 is arranged may also be employed.

[0460] As in the 19-1 embodiment, in the 19-5 embodiment, there is no need to consider the layout and contact capacitance of the metal contacts 701, 702 and the interconnection 703. Therefore, the design restrictions are reduced and the conversion efficiency can be improved.

[0461] <Example 19-6> Fig.80 is a diagram showing an example of a cross-sectional structure of a pixel 2 in Example 19-6. Fig.80 The structure of the pixel 2 shown is in Fig.79 The illustrated contact portion 711 is a structure in which a side contact portion is formed.

[0462] Fig.80 The illustrated contact portion 713 has a trench structure at the side of the first FD portion 53 of the pixel 2 - 2 , and the trench structure is filled with a material forming the contact portion 713 , for example, Poly-Si. Fig.80 One side of the contact portion 713 shown is located on the gate electrode AMP of the amplifier transistor 59-1 of the pixel 2-1. The other side is formed into a structure that is located in a groove structure formed on the side of the first FD portion 53-2 of the pixel 2-2 and contacts the side of the first FD portion 53-2 at a portion of the groove structure.

[0463] By adopting a structure in which a contact portion is formed from the side surface of the first FD portion 53 (forming a side surface contact portion), flexibility in layout of the gate electrode AMP of the amplifier transistor 59 can be improved. Therefore, design with high flexibility can also be achieved for designing conversion efficiency and anti-noise measures.

[0464] According to the 19th embodiment, by forming a side contact portion and a Poly contact portion in combination, it is also possible to reduce the source / drain (S / D) concentration of the FD portion, which is the cause of the increase in electric field and thus white spots in the FD portion.

[0465] The 19th embodiment can be implemented in combination with any one of the 1st to 18th embodiments. In addition, the following structure can be adopted: in one pixel 2, by applying any one or more of the 19-1 to 19-6 embodiments, the transistor and the region are connected. In addition, the following structure can be adopted: in two adjacent pixels 2, by applying any one or more of the 19-1 to 19-6 embodiments, the transistor and the region are connected.

[0466] <Example 20-1> Fig.81 It is a diagram showing an example of the planar structure of the pixel 2 in the 20-1st embodiment. Fig.81 This is a diagram showing how to apply the 20-1 embodiment to Figure 5FIG. 2 is a diagram showing an example of a planar structure of a pixel 2 in the case of the pixel 2 in the first embodiment. The 20th embodiment described below can be applied in combination with any one or more of the first to 19th embodiments. Here, the description will be continued by taking the case of combining the 20th embodiment with the first embodiment as an example.

[0467] The pixel 2 in the 20th embodiment has a contact portion. For example, in the case where the interconnection coupling between the FD portions is high, by forming the contact portions to arrange a plurality of walls based on the contact portions, the influence from the adjacent portions can be reduced and the coupling can be lowered.

[0468] exist Fig.81 The pixel 2 shown in FIG. 1 is provided with contact portions 731-1 to 731-10. Fig.73 The metal contact 701 , 731 is shown arranged to penetrate the multi-layer interconnection layer in a vertical direction from the semiconductor substrate 80 , for example, and includes a predetermined material, for example, a material such as Poly-Si or a metal.

[0469] The contact portion 731-1 is arranged at one end of the gate electrode FDG of the second transfer transistor 54, and the contact portion 731-2 is arranged at the other end. The contact portion 731-3 is arranged at one end of the gate electrode FCG of the second transfer transistor 56, and the contact portion 731-4 is arranged at the other end. The contact portion 731-5 is arranged at one end of the gate electrode RST of the reset transistor 58, and the contact portion 731-6 is arranged at the other end (lower right corner in the figure).

[0470] The contact 731-7 is arranged at one end of the gate electrode AMP of the amplification transistor 59, and the contact 731-8 is arranged at the other end. The contact 731-9 is arranged at one end of the gate electrode SEL of the selection transistor 60, and the contact 731-10 is arranged at the other end.

[0471] In this way, the contact portion 731 is arranged at both ends of each gate electrode. This provides a structure in which the contact portion 731 arranged at the end of the gate electrode can prevent the influence from the area adjacent to the gate electrode (for example, the adjacent area in the own pixel 2 or the area in the adjacent pixel 2).

[0472] The contact portions 731 - 1 to 731 - 10 may be configured to be connected to, for example, Fig.73 The interconnection 703 is shown arranged in the M1 layer. In addition, a contact 731 not connected to the interconnection 703 (hereinafter referred to as a dummy contact 732) may be included. Fig.82 is a diagram showing an example of a planar configuration of the pixel 2 in the case where the dummy contact portion 732 is included.

[0473] The contact portion 731-1 is arranged at one end of the gate electrode FDG of the second transfer transistor 54, and the dummy contact portion 732-1 is arranged at the other end. The dummy contact portion 732-2 is arranged at one end of the gate electrode FCG of the second transfer transistor 56, and the contact portion 731-4 is arranged at the other end. The dummy contact portion 732-3 is arranged at one end of the gate electrode RST of the second reset transistor 58, and the contact portion 731-6 is arranged at the other end (lower right corner in the figure).

[0474] The dummy contact 732-4 is arranged at one end of the gate electrode AMP of the amplification transistor 59, and the contact 731-8 is arranged at the other end. The dummy contact 732-5 is arranged at one end of the gate electrode SEL of the selection transistor 60, and the contact 731-10 is arranged at the other end.

[0475] The arrangement of the contact portion 731 and the dummy contact portion 732 is not limited to Fig.81 and 82 The arrangement shown in the figure can be applied to other arrangements. For example, on a predetermined gate electrode, only the dummy contact 732 can be arranged, or only the contact 731 can be arranged. In addition, a gate electrode on which neither the contact 731 nor the dummy contact 732 is arranged can exist in the pixel 2.

[0476] Similarly, in the case where a dummy contact portion 732 not connected to the interconnection portion is arranged as described above, the following structure is provided: for example, by arranging a contact portion 731 at the end of the gate electrode, influence from an adjacent area in its own pixel 2 or an area in an adjacent pixel 2 can be prevented.

[0477] <Example 20-2> Fig.83 An example of a planar configuration of the pixel 2 in Embodiment 20-2 is shown. Fig.84 shows the pixel 2 along Fig.83 Example of cross-section construction of line segment BB' in FIG. Fig.83 The planar structure example of the pixel 2 shown is obtained by applying the 20-2 embodiment to Figure 5 In the case of the pixel 2 in the first embodiment shown, an example of a planar structure of the pixel 2 is shown.

[0478] exist Fig.83 In the pixel 2 shown in FIG. 1 , the dummy contact portion 732 is arranged on the inter-pixel isolation portion 81. Fig.83 In the example shown, the dummy contact 732-11 is arranged at the upper left corner in the figure of the pixel 2. The dummy contact 732-12 is arranged at the lower left corner in the figure. The dummy contact 732-13 is arranged at the lower right corner in the figure.

[0479] exist Fig.83 In the example shown, the following example is shown: the dummy contact portion 732 is not arranged at the upper right corner of the figure because the gate electrode RST of the reset transistor 58 is formed there. For example, the 20-1st embodiment can be applied to the reset transistor 58 to allow the contacts 731-5 and 731-6 ( Fig.81 ) is arranged on the reset transistor 58. Alternatively, the 20-1st embodiment may be applied to the reset transistor 58 to allow the dummy contact portion 732-3 and the contact portion 731-6 ( Fig.81 ) is arranged on the reset transistor 58.

[0480] Embodiment 20-2 may be applied in combination with Embodiment 20-1.

[0481] Fig.84 is the edge of pixel 2 Fig.83 A diagram showing an example of a cross-sectional structure of a line segment BB' in FIG. Fig.84 The cross-sectional configuration example shown is similar to Fig. 20 The cross-sectional configuration example of is basically similar, but differs in that the dummy contact portion 732 - 13 is arranged on the inter-pixel isolation portion 81 .

[0482] The dummy contact portion 732 disposed on the inter-pixel isolation portion 81 may be configured to be fixed to GND. It should be noted that although the case where the dummy contact portion 732 is disposed on the inter-pixel isolation portion 81 is described as an example here, a configuration in which the dummy contact portion 732 is disposed on the element isolation portion 82 or a configuration in which the dummy contact portion 732 is disposed on both the inter-pixel isolation portion 81 and the element isolation portion 82 may also be adopted.

[0483] <Example 20-3> Fig.85 An example of the planar structure of the pixel 2 in the 20-3 embodiment is shown. Fig.86 shows the pixel 2 along Fig.85 Example of cross-section construction of line segment BB' in FIG.

[0484] The pixel 2 in the 20-3 embodiment is formed into a structure obtained by adding a polysilicon contact 741 to the pixel 2 in the 20-2 embodiment ( Fig.83 and 84 ).

[0485] exist Fig.85 and 86 In the pixel 2 shown, a Poly contact portion 741 including polysilicon is formed on the inter-pixel isolation portion 81 with a predetermined size and thickness, and a dummy contact portion 732 is connected to the Poly contact portion 741. For example, referring to Fig.86In the cross-sectional configuration example of FIG. 7 , the Poly contact portion 741 - 1 is formed on the inter-pixel isolation portion 81 , and the dummy contact portion 732 - 11 is connected to the Poly contact portion 741 - 1 .

[0486] Reference Fig.85 In the planar configuration example, the Poly contact 741-1 and the dummy contact 732-11 are arranged at the upper left corner of the figure of pixel 2. The Poly contact 741-2 and the dummy contact 732-12 are arranged at the lower left corner of the figure. The Poly contact 741-3 and the dummy contact 732-13 are arranged at the lower right corner of the figure.

[0487] The 20-3 embodiment can be applied in combination with either or both of the 20-1 embodiment and the 20-2 embodiment.

[0488] It is also possible to adopt a configuration in which the Poly contact 741 and the dummy contact 732 disposed on the inter-pixel isolation portion 81 are fixed to GND. It is also possible to adopt a configuration in which the Poly contact 741 and the dummy contact 732 are also disposed on the element isolation portion 82.

[0489] <Example 20-4> Fig.87 An example of a planar structure of the pixel 2 in the 20-4th embodiment is shown. Fig.88 shows the pixel 2 along Fig.87 Example of cross-section construction of line segment BB' in FIG.

[0490] The pixel 2 in the 20-4 embodiment is formed by providing the pixel 2 ( Fig.85 and 86 ) A structure obtained by adding an interconnection portion 751.

[0491] exist Fig.87 and 88 In the pixel 2 shown, a Poly contact portion 741 including polysilicon is formed on the inter-pixel isolation portion 81 with a predetermined size and thickness. A dummy contact portion 732 is connected to the Poly contact portion 741. An interconnection portion 751 is connected to the dummy contact portion 732. For example, referring to Fig.88 In the cross-sectional configuration example of FIG. 741, the Poly contact portion 741-1 is formed on the inter-pixel isolation portion 81. Furthermore, the dummy contact portion 732-11 is connected to the Poly contact portion 741-1, and the interconnection portion 751 is connected to the dummy contact portion 732-11.

[0492] Reference Fig.87In the example of the planar configuration of the pixel 2, the interconnection 751 is wired to connect the dummy contact 732-11 arranged at the upper left corner of the figure, the dummy contact 732-12 arranged at the lower left corner of the figure, and the dummy contact 732-13 arranged at the lower right corner of the figure. In addition, the interconnection 751 is also wired to the second FD portion 55.

[0493] With the interconnection 751 arranged in this manner, it is also possible to adopt a configuration in which the interconnection 751 is used as part of the second FD portion 55 or the third FD portion 57 to increase the capacitance of the second FD portion 55 or the third FD portion 57 .

[0494] The interconnection 751 may be arranged in a multi-layer interconnection layer stacked on the semiconductor substrate 80 , or formed on a surface (layer) where a transistor is formed in the semiconductor substrate 80 .

[0495] Embodiment 20-4 may be applied in combination with any one or more of Embodiments 20-1 to 20-3.

[0496] <Application examples on electronic devices> The present technology can be applied to an entire electronic device using an imaging element as an image capturing section (photoelectric conversion section), such as an imaging device including a digital still camera and a digital video camera, a portable terminal device having an imaging function, and a copier using an imaging element as an image reading section. The imaging element may have a form formed as one chip, or may have a module form having an imaging function obtained by integrally packaging an imaging section and a signal processing section or an optical system.

[0497] Fig.89 : is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied.

[0498] Fig.89 The imaging element 1000 includes an optical section 1001 including a lens group and the like, an imaging element (imaging device) 1002, and a DSP (digital signal processor) circuit 1003 as a camera signal processing circuit. In addition, the imaging element 1000 also includes a frame memory 1004, a display section 1005, a recording section 1006, an operation section 1007, and a power supply section 1008. The DSP circuit 1003, the frame memory 1004, the display section 1005, the recording section 1006, the operation section 1007, and the power supply section 1008 are connected to each other via a bus 1009.

[0499] The optical section 1001 captures incident light (image light) from a subject and forms an image on an imaging surface of the imaging element 1002. The imaging element 1002 converts the light amount of the incident light that forms an image on the imaging surface through the optical section 1001 into an electrical signal in units of pixels and outputs the electrical signal as a pixel signal.

[0500] The display section 1005 includes, for example, a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays a moving image or a still image captured by the imaging element 1002. The recording section 1006 records the moving image or the still image captured by the imaging element 1002 in a recording medium such as a hard disk or a semiconductor memory.

[0501] The operation unit 1007 issues operation commands related to various functions of the imaging element 1000 under the operation of the user. The power supply unit 1008 supplies various power sources used as operation power sources to the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006 and operation unit 1007 as needed.

[0502] The imaging device 1 in the first to ninth embodiments can be applied to Fig.89 Portions of an imaging device are shown.

[0503] <Application examples in endoscopic surgery systems> The technology according to the embodiment of the present disclosure (the present technology) can be applied to various products. For example, the technology according to the embodiment of the present disclosure can be applied to an endoscopic surgery system.

[0504] Fig.90 : is a diagram showing a schematic configuration example of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (the present technology) can be applied.

[0505] exist Fig.90 , a state is shown in which a surgical operator (doctor) 11131 is using an endoscopic surgical system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown in the figure, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 for supporting the endoscope 11100 thereon, and a cart 11200 on which various endoscopic surgical devices are mounted.

[0506] The endoscope 11100 includes a lens barrel 11101 and a camera head 11102 connected to the proximal end of the lens barrel 11101, and a region of the lens barrel 11101 having a predetermined length starting from the distal end thereof is inserted into a body cavity of a patient 11132. In the illustrated example, the endoscope 11100 is configured as a rigid endoscope having a rigid lens barrel 11101. However, the endoscope 11100 may also be configured as a flexible endoscope having a flexible lens barrel 11101.

[0507] The lens barrel 11101 has an opening at its distal end, and the objective lens is fitted into the opening. The light source device 11203 is connected to the endoscope 11100, so that the light generated by the light source device 11203 is introduced into the distal end of the lens barrel 11101 through the light guide extending inside the lens barrel 11101, and irradiated toward the observation target in the body cavity of the patient 11132 through the objective lens. It should be noted that the endoscope 11100 can be a forward-looking endoscope, or can be an oblique-looking endoscope or a side-looking endoscope.

[0508] An optical system and an image capturing element are provided inside the camera 11102, so that the reflected light (observation light) from the observation target is focused on the image capturing element through the optical system. The observation light is photoelectrically converted by the image capturing element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the CCU 11201 as raw data.

[0509] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102, and performs various image processing such as development processing (demosaic processing) on ​​the image signal to display an image based on the image signal.

[0510] Under the control of the CCU 11201 , the display device 11202 displays an image thereon based on the image signal on which the CCU 11201 has performed image processing.

[0511] The light source device 11203 includes, for example, a light source such as a light emitting diode (LED), and provides illumination light to the endoscope 11100 when imaging a surgical field.

[0512] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various types of information or instructions in the endoscopic surgery system 11000 through the input device 11204. For example, the user can input instructions for changing the image capturing conditions (type of irradiation light, magnification factor, focal length, etc.) of the endoscope 11100.

[0513] The treatment tool control device 11205 controls the drive of the energy device 11112 for cauterizing tissue, cutting tissue, sealing blood vessels, etc. The pneumoperitoneum device 11206 feeds gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity, thereby ensuring the field of view of the endoscope 11100 and ensuring the working space for the treatment operation. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing various information related to the operation in various forms such as text, images, and charts.

[0514] It should be noted that, for example, the light source device 11203 that provides irradiation light to the endoscope 11100 when imaging the surgical area may include a white light source, such as an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted by the light source device 11203. In addition, in this case, if the laser beam from the RGB laser light source is irradiated to the observation target in a time-division manner and the drive of the image capturing element of the camera 11102 is controlled in synchronization with the emission timing, images corresponding to RGB respectively can be captured in a time-division manner. According to this method, a color image can be acquired even if a color filter is not provided for the image capturing element.

[0515] In addition, the light source device 11203 can be controlled so that the intensity of the output light is changed at each predetermined time. By controlling the drive of the image capturing element of the camera 11102 in synchronization with the timing of the change in light intensity so as to acquire images in a time-division manner and synthesize the images, a high dynamic range image without underexposed shadows and overexposed highlights can be generated.

[0516] In addition, the light source device 11203 can be configured to provide light having a predetermined wavelength region domain prepared for specific light observation. In specific light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue to irradiate light having a narrower band than the irradiation light (i.e., white light) during normal observation, imaging (narrow-band imaging) for predetermined tissues such as blood vessels in the surface part of the mucosal layer with high contrast is performed. Alternatively, in specific light observation, fluorescence observation for obtaining an image based on fluorescence generated by irradiation of excitation light can be performed. In fluorescence observation, observation of fluorescence from body tissue (autofluorescence observation) can be performed by irradiating body tissue, or a fluorescent image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to provide narrow-band light and / or excitation light suitable for specific light observation as described above.

[0517] Fig.91 It is shown Fig.90 A block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0518] The camera 11102 includes a lens unit 11401, an image capturing unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 to communicate with each other.

[0519] The lens unit 11401 is an optical system provided at a position connected to the lens barrel 11101. Observation light acquired from the distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0520] The number of image capturing elements included in the image capturing unit 11402 may be one (single-board type) or multiple (multi-board type). In the case where the image capturing unit 11402 is configured as a multi-board type, for example, image signals corresponding to R, G, and B, respectively, are generated by the image capturing elements, and a color image can be obtained by synthesizing these image signals. The image capturing unit 11402 may also be configured to have a pair of image capturing elements for acquiring a right-eye image signal and a left-eye image signal for three-dimensional (3D) display. If a 3D display is performed, the surgical operator 11131 is able to more accurately perceive the depth of body tissue at the surgical site. It should be noted that in the case where the image capturing unit 11402 is configured as a multi-board type, a plurality of systems of lens units 11401 may be arranged in a manner corresponding to the respective image capturing elements.

[0521] In addition, the image capturing unit 11402 may not necessarily be disposed in the camera head 11102. For example, the image capturing unit 11402 may be disposed immediately after the objective lens inside the lens barrel 11101.

[0522] The driving unit 11403 includes an actuator, and under the control of the camera control unit 11405, the driving unit 11403 moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis. Therefore, the magnification and focus of the image captured by the image capturing unit 11402 can be appropriately adjusted.

[0523] The communication unit 11404 includes a communication device for transmitting / receiving various information to / from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the image capturing unit 11402 to the CCU 11201 through the transmission cable 11400 as raw data.

[0524] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and provides the control signal to the camera control unit 11405. For example, the control signal includes information related to imaging conditions, such as information for specifying a frame rate for capturing an image and information for specifying an exposure value when capturing an image and / or information for specifying a magnification and a focus of a captured image.

[0525] It should be noted that image capturing conditions such as frame rate, exposure value, magnification, and focus may be appropriately specified by the user or automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are combined in the endoscope 11100.

[0526] The camera control unit 11405 controls the driving of the camera 11102 based on a control signal received from the CCU 11201 through the communication unit 11404 .

[0527] The communication unit 11411 includes a communication device for transmitting / receiving various types of information to / from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 through the transmission cable 11400.

[0528] In addition, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal may be transmitted through electrical communication, optical communication, or the like.

[0529] The image processing unit 11412 performs various image processing on the image signal transmitted from the camera 11102 in the form of raw data.

[0530] The control unit 11413 performs various types of control related to image capture of the operation area, etc. performed by the endoscope 11100 and display of captured images obtained by the image capture of the operation area, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0531] In addition, the control unit 11413 controls the display device 11202 to display a captured image depicting the surgical area, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 can identify various objects in the captured image by using various image recognition technologies. For example, the control unit 11413 can identify surgical tools such as forceps, specific living parts, bleeding, fog when using the energy device 11112, etc. by detecting the shape, color, etc. of the edge of the object included in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can display various surgical auxiliary information in a manner superimposed with the image of the surgical area by using the recognition result. By displaying and presenting the surgical auxiliary information to the surgical operator 11131 in a superimposed manner, the burden on the surgical operator 11131 can be reduced, or the surgeon 11131 can be enabled to perform surgery more reliably.

[0532] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable for electric signal communication, an optical fiber for optical communication, or a composite cable for both electric communication and optical communication.

[0533] Here, in the example shown, although communication is performed by wired communication using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may be performed by wireless communication.

[0534] <Application examples on mobile objects> The technology according to the embodiments of the present disclosure (the present technology) can be applied to various products. For example, the technology according to the embodiments of the present disclosure can be implemented in the form of a device installed on any type of mobile body; the mobile body is, for example, a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, any personal mobile device, an airplane, a drone, a ship, or a robot.

[0535] Fig.92 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0536] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.92 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown as a functional configuration of the integrated control unit 12050.

[0537] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 acts as a control device for the following devices: a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a vehicle braking force, etc.

[0538] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a portable device as a key substitute or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0539] The vehicle exterior information detection unit 12030 detects external information about the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform processing for detecting objects such as people, vehicles, obstacles, signs, characters on the road surface, or processing for object distance detection.

[0540] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may also output an electrical signal as an image, or may output an electrical signal as measured distance information. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0541] The in-vehicle information detection unit 12040 detects the interior information about the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. The driver state detection unit 12041 includes, for example, a camera for capturing an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0542] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside and outside of the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and output the control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control of functions aimed at realizing an advanced driver assistance system (ADAS), including collision avoidance or shock absorption of the vehicle, following driving based on vehicle spacing, speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0543] In addition, based on the environmental information about the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc., which enables the vehicle to drive automatically without relying on the driver's operation, etc.

[0544] In addition, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the external information about the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control for preventing glare by, for example, controlling the headlights to change from high beam to low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0545] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig. 27 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are used as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0546] Fig.93 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0547] exist Fig.93 In the embodiment, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0548] The imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, arranged at the front nose, rearview mirror, rear bumper, rear door, and upper portion of the windshield of the vehicle 12100. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper portion of the windshield of the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the rearview mirror mainly acquire images on both sides of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 arranged at the upper portion of the windshield of the vehicle is mainly used to detect vehicles in front, pedestrians, obstacles, signal lights, traffic signs, lanes, etc.

[0549] Notice, Fig.93 An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0550] At least one of the imaging units 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0551] For example, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and extract the nearest three-dimensional object as the preceding vehicle, which is particularly present on the driving path of the vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in the substantially same direction as the vehicle 12100. In addition, the microcomputer 12051 is capable of presetting the following distance to be maintained in front of the preceding vehicle, and performing automatic braking control (including following stop control), automatic acceleration control (including following start control), etc. Therefore, it is possible to perform coordinated control for automatic driving so that the vehicle can travel automatically without relying on the operation of the driver, etc.

[0552] For example, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult to be visually identified by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0553] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by the following process: a process of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras; and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a square contour line for emphasis superimposed on the identified pedestrian. In addition, the sound / image output unit 12052 may control the display unit 12062 so as to display an icon or the like for indicating a pedestrian at a desired position.

[0554] In this specification, a system means an entire device including a plurality of devices.

[0555] It should be noted that the effects described in this specification are merely examples and not limiting, and there may be other effects.

[0556] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various changes can be made within the scope not departing from the gist of the present technology.

[0557] It should be noted that the present technology can also adopt the following configurations. (1) An imaging element comprising: a photoelectric conversion unit that converts light into electric charges; an accumulation section that temporarily accumulates the electric charges; a transmission section that transmits charges to the accumulation section; an inter-pixel isolation portion that establishes isolation between pixels; an element isolation portion that isolates elements; and a plurality of transistors arranged around the transfer portion in a plan view, In the plan view, in each of the plurality of transistors, there is a region where at least one side of the transistor overlaps with the inter-pixel isolation portion, and a side opposite to the one side includes a region overlapping with the element isolation portion. (2) The imaging element according to (1) above, wherein: The imaging element includes a plurality of accumulation sections and a plurality of transfer sections that transfer charges to the plurality of accumulation sections, respectively, and A second transfer section other than the first transfer section that transfers the charge from the photoelectric conversion section to the accumulation section is arranged around the first transfer section. (3) The imaging element according to (1) or (2) above, wherein: A portion of the element isolation portion is in contact with the inter-pixel isolation portion. (4) The imaging element according to any one of (1) to (3) above, wherein: The element isolation portion includes an oxide film or a region formed by ion implantation. (5) The imaging element according to any one of (1) to (4) above, wherein: The plurality of accumulating sections are connected in series, and The plurality of accumulation sections accumulate charges transferred from the photoelectric conversion section and charges overflowing from the photoelectric conversion section. (6) The imaging element according to any one of (1) to (5) above, wherein: The element isolating portion adjacent to the accumulating portion is formed to a deeper position than the element isolating portion not adjacent to the accumulating portion. (7) The imaging element according to (6) above, wherein: The imaging element includes a plurality of accumulators, and at least one of the element isolating sections adjacent to each of the plurality of accumulators is formed deeper than the other element isolating sections. (8) The imaging element according to (6) or (7) above, wherein: The depth of the element isolating portion adjacent to the accumulator portion is set to 1.2 to 2.0 times the depth of the element isolating portion not adjacent to the accumulator portion. (9) The imaging element according to any one of (6) to (8) above, wherein: The depth of the element isolating portion adjacent to the accumulating portion is a depth that depends on a voltage applied to the adjacent accumulating portion and a capacitance size of the accumulating portion. (10) The imaging device according to any one of (1) to (9) above, further comprising: A control line that controls the reduction or increase of a voltage applied to the accumulating portion. (11) The imaging element according to (10) above, wherein: The control line performs control to reduce a voltage applied to the accumulation section in an accumulation period of the photoelectric conversion section. (12) The imaging element according to (10) or (11) above, wherein: The control line performs control to increase a voltage applied to the accumulation section in a readout period in which a signal is read out from the accumulation section. (13) The imaging element according to any one of (10) to (12) above, wherein: The imaging element includes a plurality of accumulating sections, and the control line is connected to at least one of the plurality of accumulating sections. (14) The imaging element according to any one of (1) to (13) above, wherein: The inter-pixel isolation portion located in a contact region between the inter-pixel isolation portion and the element isolation portion has an expanded shape in a plan view. (15) The imaging element according to any one of (1) to (13) above, wherein: The element isolating portion located in a contact region between the inter-pixel isolating portion and the element isolating portion has an enlarged shape in a plan view. (16) The imaging element according to any one of (1) to (15) above, wherein: The inter-pixel isolation portion includes a first layer including polysilicon or metal and a second layer of an oxide film stacked on the first layer. (17) The imaging element according to (16) above, wherein: A supply voltage is connected to the first layer. (18) The imaging device according to (2) above, further comprising: An overflow gate for transferring charges overflowing from the photoelectric conversion section is located between one of the plurality of accumulation sections and the first transfer section. (19) The imaging device according to (2) above, further comprising: A region having a potential gradient is located between one of the plurality of accumulators and the first transfer portion. (20) The imaging element according to any one of (1) to (19) above, wherein: The amplifying transistor of a first pixel and the accumulating portion of a second pixel adjacent to the first pixel are connected. (21) The imaging element according to any one of (1) to (19) above, wherein: The amplification transistor of the first pixel and the accumulation section of the second pixel are connected by an interconnection section arranged on the inter-pixel isolation section between the first pixel and a second pixel adjacent to the first pixel. (22) The imaging element according to (21) above, wherein: The amplification transistor of the first pixel and the selection transistor of the second pixel are connected by an interconnection portion arranged on the inter-pixel isolation portion between the first pixel and the second pixel. (23) The imaging element according to any one of (1) to (22) above, wherein: The gate electrode of the amplification transistor of the first pixel is arranged to a position allowing connection with the accumulation section of the second pixel via the inter-pixel isolation section arranged between the first pixel and a second pixel adjacent to the first pixel. (24) The imaging element according to any one of (1) to (22) above, wherein: The gate electrode of the amplifying transistor of the first pixel is connected to the accumulating portion of the second pixel adjacent to the first pixel through a contact portion including polysilicon, and the contact portion is arranged to a position connected to the accumulating portion of the second pixel via the inter-pixel isolation portion arranged between the first pixel and the second pixel. (25) The imaging element according to (3) above, wherein: The gate electrode of the amplifying transistor of the first pixel is connected to a side surface of the accumulating portion of the second pixel adjacent to the first pixel in a region obtained by making a groove in the second pixel. (26) The imaging device according to any one of (1) to (25) above, further comprising: A contact is located on the gate electrode of each of the plurality of transistors. (27) The imaging element according to any one of (1) to (25) above, wherein: The imaging element includes a plurality of contacts located on the inter-pixel isolation portion, and The plurality of contact portions are connected to the accumulating portion. (28) An electronic device comprising an imaging element and a processing unit for processing a signal from the imaging element, wherein the imaging element comprises: a photoelectric conversion unit that converts light into electric charges; an accumulation section that temporarily accumulates the electric charge; a transmission section that transmits charges to the accumulation section; an inter-pixel isolation portion that establishes isolation between pixels; an element isolation portion that isolates elements; and a plurality of transistors arranged around the transfer portion in a plan view, In the plan view, in each of the plurality of transistors, there is a region where at least one side of the transistor overlaps with the inter-pixel isolation portion, and a side opposite to the one side includes a region overlapping with the element isolation portion. [reference numerals list]

[0558] 1: Imaging device 2: Pixels 3: Pixel array unit 4: Vertical drive circuit 5: Column signal processing circuit 6: Horizontal drive circuit 7: Output circuit 8: Control circuit 9: Vertical signal line 10: Pixel drive line 11: Horizontal signal line 13: Input / output terminals 31: Select transistor 51: Photoelectric conversion unit 52: First transfer transistor 53: First FD Division 54: Second transfer transistor 55: Second FD Division 56: Third transfer transistor 57: Third FD Division 58: Reset transistor 59: Amplifier transistor 60: Select transistor 61: Photoelectric conversion unit 71: VDD area 72: VSL area 73: VSS area 80: Semiconductor substrate 81: Inter-pixel isolation 82: Component isolation 101: Semiconductor Area 102: Semiconductor area 104: Channel 105: Region 106: Channel 107, 108, 109, 110: Pinning membrane 111: Area 112: Area 131: Component isolation unit 132: Inter-pixel isolation 151: Contact Department 201: Overflow transistor 301, 302, 303: connecting lines 311, 312, 313: capacitor elements.

Claims

1. An imaging element, comprising: a photoelectric conversion unit that converts light into electric charges; an accumulation section that temporarily accumulates the electric charges; a transmission section that transmits charges to the accumulation section; an inter-pixel isolation portion that establishes isolation between pixels; an element isolation section that isolates elements; as well as a plurality of transistors arranged around the transfer portion in a plan view, In the plan view, in each of the plurality of transistors, there is a region where at least one side of the transistor overlaps with the inter-pixel isolation portion, and a side opposite to the one side includes a region overlapping with the element isolation portion.

2. The imaging element according to claim 1, wherein The imaging element includes a plurality of accumulation sections and a plurality of transfer sections that transfer charges to the plurality of accumulation sections, respectively, and A second transfer section other than the first transfer section that transfers the charge from the photoelectric conversion section to the accumulation section is arranged around the first transfer section.

3. The imaging element according to claim 1, wherein A portion of the element isolation portion is in contact with the inter-pixel isolation portion.

4. The imaging element according to claim 1, wherein The element isolation portion includes an oxide film or a region formed by ion implantation.

5. The imaging element according to claim 1, wherein The plurality of accumulating sections are connected in series, and The plurality of accumulation sections accumulate charges transferred from the photoelectric conversion section and charges overflowing from the photoelectric conversion section.

6. The imaging element according to claim 1, wherein The element isolating portion adjacent to the accumulating portion is formed to a deeper position than the element isolating portion not adjacent to the accumulating portion.

7. The imaging element according to claim 6, wherein: The imaging element includes a plurality of accumulators, and at least one of the element isolating sections adjacent to each of the plurality of accumulators is formed deeper than the other element isolating sections.

8. The imaging element according to claim 6, wherein: The depth of the element isolating portion adjacent to the accumulator portion is set to 1.2 to 2.0 times the depth of the element isolating portion not adjacent to the accumulator portion.

9. The imaging element according to claim 6, wherein: The depth of the element isolating portion adjacent to the accumulating portion is a depth that depends on a voltage applied to the adjacent accumulating portion and a capacitance size of the accumulating portion.

10. The imaging element according to claim 1, further comprising: A control line that controls the reduction or increase of a voltage applied to the accumulating portion.

11. The imaging element according to claim 10, wherein The control line performs control to reduce a voltage applied to the accumulation section in an accumulation period of the photoelectric conversion section.

12. The imaging element according to claim 10, wherein: The control line performs control to increase a voltage applied to the accumulation section in a readout period in which a signal is read out from the accumulation section.

13. The imaging element according to claim 10, wherein: The imaging element includes a plurality of accumulating sections, and the control line is connected to at least one of the plurality of accumulating sections.

14. The imaging element according to claim 1, wherein The inter-pixel isolation portion located in a contact region between the inter-pixel isolation portion and the element isolation portion has an expanded shape in a plan view.

15. The imaging element according to claim 1, wherein The element isolating portion located in a contact region between the inter-pixel isolating portion and the element isolating portion has an enlarged shape in a plan view.

16. The imaging element according to claim 1, wherein The inter-pixel isolation portion includes a first layer including polysilicon or metal and a second layer of an oxide film stacked on the first layer.

17. The imaging element according to claim 16, wherein: A supply voltage is connected to the first layer.

18. The imaging element according to claim 2, further comprising: An overflow gate for transferring charges overflowing from the photoelectric conversion section is located between one of the plurality of accumulation sections and the first transfer section.

19. The imaging element according to claim 2, further comprising: A region having a potential gradient is located between one of the plurality of accumulators and the first transfer portion.

20. The imaging element according to claim 1, wherein The amplifying transistor of a first pixel and the accumulating portion of a second pixel adjacent to the first pixel are connected.

21. The imaging element according to claim 1, wherein The amplifying transistor of the first pixel and the accumulating portion of the second pixel are connected by an interconnection portion arranged on the inter-pixel isolation portion between the first pixel and a second pixel adjacent to the first pixel.

22. The imaging element according to claim 21, wherein The amplification transistor of the first pixel and the selection transistor of the second pixel are connected by an interconnection portion arranged on the inter-pixel isolation portion between the first pixel and the second pixel.

23. The imaging element according to claim 1, wherein The gate electrode of the amplification transistor of the first pixel is arranged to a position allowing connection with the accumulation section of the second pixel via the inter-pixel isolation section arranged between the first pixel and a second pixel adjacent to the first pixel.

24. The imaging element according to claim 1, wherein The gate electrode of the amplifying transistor of the first pixel is connected to the accumulating portion of the second pixel adjacent to the first pixel through a contact portion including polysilicon, and the contact portion is arranged to a position connected to the accumulating portion of the second pixel via the inter-pixel isolation portion arranged between the first pixel and the second pixel.

25. The imaging element according to claim 23, wherein The gate electrode of the amplifying transistor of the first pixel is connected to a side surface of the accumulating portion of the second pixel adjacent to the first pixel in a region obtained by making a groove in the second pixel.

26. The imaging element according to claim 1, further comprising: A contact is located on the gate electrode of each of the plurality of transistors.

27. The imaging element according to claim 1, wherein The imaging element includes a plurality of contacts located on the inter-pixel isolation portion, and The plurality of contact portions are connected to the accumulating portion.

28. An electronic device comprising an imaging element and a processing unit for processing a signal from the imaging element, the imaging element comprising: a photoelectric conversion unit that converts light into electric charges; an accumulation section that temporarily accumulates the electric charges; a transmission section that transmits charges to the accumulation section; an inter-pixel isolation portion that establishes isolation between pixels; an element isolation section that isolates elements; as well as a plurality of transistors arranged around the transfer portion in a plan view, In the plan view, in each of the plurality of transistors, there is a region where at least one side of the transistor overlaps with the inter-pixel isolation portion, and a side opposite to the one side includes a region overlapping with the element isolation portion.

Images