Pulse width modulation signal duty ratio sampling method and device, equipment and storage medium
By reading the number and time points of rising and falling edges of the pulse width modulated PWM signal, and combining the sampling frequency, the duty cycle of the PWM signal is determined, the problem of low duty cycle accuracy and limited sampling frequency in the prior art is solved, and high-precision and high-frequency duty cycle sampling is achieved.
Patent Information
- Application Number
- CN202311360454.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-19
- Publication Date
- 2025-04-22
AI Technical Summary
In the prior art, the pulse width modulated signal duty cycle sampling scheme has problems such as low duty cycle accuracy and limited sampling frequency.
By reading the number and time points of the rising and falling edges of the pulse width modulated PWM signal during the sampling period, and collecting levels based on the preset sampling frequency, combining the reading level and edge change time sampling, the duty cycle of the PWM signal is determined.
The high duty cycle accuracy is ensured when the level reading speed is low and the high sampling frequency needs are met, solving the problems of low duty cycle accuracy and limited sampling frequency in traditional solutions.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of industrial control technology, and in particular to a pulse width modulation signal duty cycle sampling method, device, electronic device and computer-readable storage medium. Background Art
[0002] Pulse width modulation (PWM) technology is a common technology in the field of industrial control technology. The output voltage can be adjusted by adjusting the duty cycle of the PWM signal. Generally, the value of the output voltage can be obtained according to the duty cycle of the PWM signal.
[0003] There are two main sampling schemes for PWM duty cycle: the first scheme is to sample the PWM duty cycle by reading the high and low levels of the PWM signal. This scheme has high requirements on the level reading speed, and will affect the accuracy of the PWM duty cycle when the level reading speed is low; the second scheme is to achieve it by reading the edge change moment of the PWM signal. In this scheme, the sampling frequency needs to be consistent with the frequency of the PWM signal, and cannot support the demand for higher sampling frequency. Summary of the invention
[0004] The main purpose of the present application is to provide a pulse width modulation signal duty cycle sampling method, device, electronic device and computer-readable storage medium, aiming to solve the technical problems of low duty cycle accuracy and limited sampling frequency in the pulse width modulation signal duty cycle sampling scheme in the prior art.
[0005] To achieve the above object, the present application provides a pulse width modulation signal duty cycle sampling method, the pulse width modulation signal duty cycle sampling method comprising:
[0006] In a sampling time period, read the first number and the second number of rising edges and falling edges in the pulse width modulation (PWM) signal, and read the first time corresponding to the rising edge and the second time corresponding to the falling edge, wherein the first time is the sum of the time points of all rising edges, and the second time is the sum of the time points of all falling edges;
[0007] Collecting the level of the PWM signal at each sampling moment according to a preset sampling frequency;
[0008] The duty cycle of the PWM signal is determined according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period.
[0009] Optionally, the step of determining the duty cycle of the PWM signal according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period includes:
[0010] Determine a high level duration according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period;
[0011] The ratio of the high level duration to the sampling duration is calculated to obtain the duty cycle of the PWM signal.
[0012] Optionally, the step of determining the high level duration according to the first quantity, the second quantity, the first time, the second time and the sampling duration corresponding to the sampling time period includes:
[0013] Determining whether the first quantity is equal to the second quantity;
[0014] If they are equal, determining the high level duration according to the magnitude relationship between the first time and the second time, the first time, the second time, and the sampling duration;
[0015] If they are not equal, the high level duration is determined according to the size relationship between the first number and the second number, the first time, the second time and the sampling duration.
[0016] Optionally, the step of determining the high level duration according to the relationship between the first time and the second time, the first time, the second time and the sampling duration includes:
[0017] Determine whether the first time is less than the second time;
[0018] When the first time is not greater than the second time, the difference between the second time and the first time is calculated to obtain the high level duration;
[0019] When the first time and is greater than the second time, a first difference between the first time and the second time is calculated, and a difference between the sampling duration and the first difference is calculated to obtain a high level duration.
[0020] Optionally, the step of determining the high level duration according to the size relationship between the first quantity and the second quantity, the first time, the second time and the sampling duration includes:
[0021] If the first number is smaller than the second number, the difference between the second time and the first time is calculated to obtain the high level duration.
[0022] Optionally, the step of determining the high level duration according to the size relationship between the first quantity and the second quantity, the first time, the second time and the sampling duration includes:
[0023] If the first number is greater than the second number, calculating the difference between the first time and the second time to obtain the low level duration;
[0024] The difference between the sampling duration and the low level duration is calculated to obtain the high level duration.
[0025] Optionally, the step of determining the high level duration according to the size relationship between the first quantity and the second quantity, the first time, the second time and the sampling duration includes:
[0026] If the first number is 1 and the second number is 0, determining that the first time is the first time corresponding to the rising edge;
[0027] The difference between the sampling duration and the first time is calculated to obtain the high level duration.
[0028] The present application also provides a pulse width modulation signal duty cycle sampling device, the pulse width modulation signal duty cycle sampling device comprising:
[0029] A first acquisition module is used to read the first number and the second number of rising edges and falling edges in the pulse width modulation (PWM) signal within a sampling period, and read the first time corresponding to the rising edge and the second time corresponding to the falling edge, wherein the first time is the sum of the time points of all rising edges, and the second time is the sum of the time points of all falling edges;
[0030] A second acquisition module, used for acquiring the level of the PWM signal at each sampling moment according to a preset sampling frequency;
[0031] The duty cycle determination module is used to determine the duty cycle of the PWM signal according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period.
[0032] The present application also provides an electronic device, which is a physical device, and includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the steps of the pulse width modulation signal duty cycle sampling method as described above.
[0033] The present application also provides a readable storage medium, which is a computer-readable storage medium, and stores a program for implementing a pulse width modulation signal duty cycle sampling method. The program for implementing a pulse width modulation signal duty cycle sampling method is executed by a processor to implement the steps of the pulse width modulation signal duty cycle sampling method as described above.
[0034] The present application also provides a computer program product, including a computer program, which implements the steps of the pulse width modulation signal duty cycle sampling method as described above when executed by a processor.
[0035] The present application provides a method for sampling the duty cycle of a pulse width modulation signal. The present application first reads the first number and the second number of rising edges and falling edges in a pulse width modulation PWM signal within a sampling time period, and reads the first time corresponding to the rising edge and the second time corresponding to the falling edge, wherein the first time is the sum of the time points at which all rising edges are located, and the second time is the sum of the time points at which all falling edges are located, and then collects the level of the PWM signal at each sampling moment according to a preset sampling frequency, and finally determines the duty cycle of the PWM signal according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period. The technical solution of the present application combines the method of reading the level sampling method. Compared with the scheme of sampling the PWM duty cycle only by reading the high and low levels of the PWM signal, the technical scheme of the present application ensures a higher duty cycle accuracy when the level reading speed is low; compared with the scheme of sampling the PWM duty cycle only by reading the edge change moment of the PWM signal, the technical scheme of the present application can meet a higher sampling frequency, and can determine the duty cycle value even when the number of rising and falling edges is not read. In summary, the technical scheme of the present application takes into account the duty cycle accuracy and sampling frequency in the process of PWM signal duty cycle sampling, and solves the technical problems of low duty cycle accuracy and limited sampling frequency in the traditional pulse width modulation signal duty cycle sampling scheme. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0038] Figure 1A schematic diagram of a method for sampling a duty cycle by reading a PWM signal level;
[0039] Figure 2 A schematic diagram of a method for sampling the duty cycle by reading the edge timing of a PWM signal;
[0040] Figure 3 This is a flow chart of the pulse width modulation signal duty cycle sampling method of the present application;
[0041] Figure 4 A schematic diagram of PWM signal sampling when the number of rising edges and falling edges in the pulse width modulation signal duty cycle sampling method of the present application is zero and the level of the PWM signal at any sampling moment is a high level;
[0042] Figure 5 A schematic diagram of PWM signal sampling when the number of rising edges and falling edges in the pulse width modulation signal duty cycle sampling method of the present application is zero and the level of the PWM signal at any sampling moment is a low level;
[0043] Figure 6 This is a schematic diagram of PWM signal sampling when the number of rising edges is equal to the number of falling edges and the first time is less than the second time in the pulse width modulation signal duty cycle sampling method of the present application;
[0044] Figure 7 This is a schematic diagram of PWM signal sampling in the pulse width modulation signal duty cycle sampling method of the present application, in which the number of rising edges and the number of falling edges are both 1 and the first time is less than the second time;
[0045] Figure 8 This is a schematic diagram of PWM signal sampling when the number of rising edges is equal to the number of falling edges and the first time is greater than the second time in the pulse width modulation signal duty cycle sampling method of the present application;
[0046] Fig. 9 This is a schematic diagram of PWM signal sampling in the pulse width modulation signal duty cycle sampling method of the present application, in which the number of rising edges and the number of falling edges are both 1 and the first time is greater than the second time;
[0047] Fig.10 This is a schematic diagram of PWM signal sampling when the number of rising edges is less than the number of falling edges in the pulse width modulation signal duty cycle sampling method of the present application;
[0048] Fig.11 This is a schematic diagram of PWM signal sampling when the number of rising edges is 0 and the number of falling edges is 1 in the pulse width modulation signal duty cycle sampling method of this application;
[0049] Fig.12 A schematic diagram of PWM signal sampling when the number of rising edges is greater than the number of falling edges in the pulse width modulation signal duty cycle sampling method of the present application;
[0050] Fig.13 This is a schematic diagram of PWM signal sampling when the number of rising edges is 1 and the number of falling edges is 0 in the pulse width modulation signal duty cycle sampling method of the present application;
[0051] Fig.14 This is a schematic diagram of the module structure of a pulse width modulation signal duty cycle sampling device according to an embodiment of the present application;
[0052] Fig.15 Schematic diagram of the device structure of the hardware operating environment involved in the pulse width modulation signal duty cycle sampling method in the embodiment of the present application.
[0053] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0054] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.
[0055] In the field of industrial control technology, when it is necessary to sample the duty cycle of a PWM signal, one method is to sample the PWM duty cycle by reading the high and low levels of the PWM signal. Figure 1 This solution can sample the PWM duty cycle at a higher frequency, but it has a high requirement on the speed of reading the PWM signal level. If the reading speed is slow, the calculated duty cycle accuracy will be low. Another solution is to sample the PWM duty cycle by reading the PWM signal edge change moment. Figure 2 ,The sampling frequency of this scheme is generally the same as the PWM frequency. Although the accuracy is high, if the sampling frequency is required to be high, it is difficult to meet the ,requirements for high sampling frequency.
[0056] In order to solve the technical defects of the above method and solve the technical problems of low duty cycle accuracy and limited sampling frequency in the pulse width modulation signal duty cycle sampling scheme, the present application proposes a pulse width modulation signal duty cycle sampling method of the first embodiment, please refer to Figure 3 , the pulse width modulation signal duty cycle sampling method comprises:
[0057] Step S10, within a sampling period, reading the first number and the second number of rising edges and falling edges in the pulse width modulation (PWM) signal, and reading the first time corresponding to the rising edge and the second time corresponding to the falling edge, wherein the first time is the sum of the time points of all rising edges, and the second time is the sum of the time points of all falling edges;
[0058] Step S20, collecting the level of the PWM signal at each sampling moment according to a preset sampling frequency;
[0059] In the embodiment of the present application, the pulse width modulation signal is a PWM signal that needs to be sampled for duty cycle, and can be used as a control signal to control other devices. The rising edge is the signal waveform corresponding to the moment when the PWM signal is converted from a low level to a high level, and the falling edge is the signal waveform corresponding to the moment when the PWM signal is converted from a high level to a low level. When reading the number and time corresponding to the rising edge and the falling edge respectively, the sampling frequency is consistent with the frequency of the PWM signal, that is, each rising edge and falling edge in the PWM signal is a sampling point. In addition, the time and is the sum of the times corresponding to the rising edge and the falling edge in the sampling time period. For example, the number of rising edges of the PWM signal and the time corresponding to each rising edge in the [t, t+Ts) time period are read, and the number of rising edges is recorded as Nr to obtain a first number, and the time corresponding to each rising edge is trx, x=1,2,3,..., Nr, and the sum of each rising edge is trS. Similarly, the number of falling edges of the PWM signal and the time corresponding to each falling edge in the [t, t+Ts) time period are read, and the number of falling edges is recorded as Nf to obtain a second number, and the time corresponding to each falling edge is tfx, x=1,2,3,..., Nf, and the sum of each falling edge is tfS. For example, in the [t, t+Ts) time period, the time corresponding to the point t is 0, and the time corresponding to t+Ts can be Ts.
[0060] On the other hand, when collecting the level of the pulse width modulation signal at each moment in the sampling time period corresponding to the sampling duration, the level can be read using a suitable preset sampling frequency according to actual needs, the level of the PWM signal at each sampling moment is collected, and the waveform of the PWM signal at the moment of high and low level state change is screened out to obtain the rising edge and falling edge in the PWM signal. Through the technical solution of the present application, the technical defect that the duty cycle cannot be calculated when the rising edge or falling edge is not collected in the method of sampling the duty cycle of the PWM signal by only reading the edge change moment of the PWM signal can be overcome, and the duty cycle sampling demand with high sampling frequency in industrial control scenarios can be met.
[0061] Step S30, determining the duty cycle of the PWM signal according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period.
[0062] In the embodiment of the present application, if the number of rising edges and falling edges is not zero, then in the sampling time period, the PWM signal has a transition between high and low level states, and the duty cycle is the ratio between the duration of the high level state and the total sampling time, and the sampling time is known, so to determine the duty cycle, it is necessary to first determine the duration of the high level state. When the number of rising edges and falling edges is equal, when there are one or more rising edges and falling edges in the PWM signal, the duration of each individual high level state is usually obtained by subtracting the time of the corresponding rising edge from the time of the falling edge, so when calculating the sum of the durations of each individual high level state, it can be obtained by subtracting the sum of the rising edge from the sum of the falling edge. However, this calculation method has a difficult problem to solve, that is, in the sampling time period, the last edge is a rising edge, at this time the sum of the rising edge time is greater than the sum of the falling edge time, and a negative number appears. At this time, the sum of the duration of the low level state can be obtained by subtracting the sum of the duration of the low level state from the sum of the sampling time, and then the sum of the duration of the high level state can be obtained by subtracting the sum of the duration of the low level state from the sampling time.
[0063] On the other hand, when the number of rising edges and the number of falling edges are not equal, the number of rising edges is greater than the number of falling edges and the number of falling edges is greater than the number of rising edges. When the number of rising edges is greater than the number of falling edges, the time sum of the rising edges is greater than the time sum of the falling edges. At this time, the sum of the duration of the low level state can be obtained by subtracting the sum of the duration of the low level state from the time sum of the rising edges, and then the sum of the duration of the high level state can be obtained by subtracting the sum of the duration of the low level state from the sampling duration. When the number of rising edges is less than the number of falling edges, the time sum of the rising edges is less than the time sum of the falling edges. At this time, the sum of the duration of the high level state can be obtained by subtracting the sum of the duration of the rising edges from the sum of the duration of the falling edges.
[0064] After the sum of the durations in the high level state is determined by the above method, the ratio between the sum of the durations in the high level state and the sampling duration can be calculated to obtain the duty cycle of the PWM signal.
[0065] In a feasible embodiment, it can be determined whether the first number and the second number are both zero. The purpose of determining whether the first number and the second number are both zero is to confirm whether the PWM signal is in a single high level state or a low level state during the sampling time period. It can be understood that when there is no rising edge and falling edge of the PWM signal during the sampling time period, the level state of the PWM signal during the sampling time period does not change, and always maintains a high level state or a low level state. After determining that the first number and the second number are both zero, it can be determined whether the PWM signal maintains a high level state or a low level state during the sampling time period only by the level at any sampling moment during the sampling time period. If the first number and the second number are both zero, the duty cycle of the PWM signal is determined according to the level of the PWM signal at any sampling moment;
[0066] Referring to the foregoing content, after determining that the first number and the second number are both zero, it can be determined that the level state of the PWM signal has not changed during the sampling time period, so the level state of the PWM signal at any sampling time is the same, and the duty cycle is the ratio of the duration of the high level state in the signal to the total sampling time, so if the level of the PWM signal at any sampling time is high, the duty cycle is 1; if the level of the PWM signal at any sampling time is low, the duty cycle is 0.
[0067] In a possible implementation manner, the step of determining the duty cycle of the PWM signal according to the level of the PWM signal at any sampling time may further include:
[0068] Step S31, if the level of the PWM signal at any sampling time is high, the duty cycle of the PWM signal is 1;
[0069] Step S32: if the level of the PWM signal at any sampling time is low, the duty cycle of the PWM signal is 0.
[0070] In the embodiment of the present application, when it is determined that the number of rising edges and falling edges of the PWM signal in the sampling time period is 0, it can be determined that the level state of the PWM signal in the sampling time period has not changed, so the level state in the entire sampling time period can be determined by the level state at any sampling time. Figure 4 , when the read PWM signal edge time has no rising edge or falling edge between the sampling time period t and t+Ts, and the read PWM signal level at any sampling time is high, it can be determined that the level state in the entire sampling time period is high; refer to Figure 5When there is no rising edge or falling edge between the edge time t and t+Ts of the read PWM signal, and the PWM signal level read at any sampling time is a low level, it can be determined that the level state in the entire sampling time period is a low level.
[0071] Through the above-mentioned pulse width modulation signal duty cycle sampling method, in the embodiment of the present application, when the duty cycle of the PWM signal is sampled at a high sampling rate, the current duty cycle can be determined even if the rising edge moment or the falling edge moment is not collected, thereby meeting the higher frequency sampling requirements in industrial control scenarios.
[0072] In a possible implementation, the step of determining the duty cycle of the PWM signal according to the first quantity, the second quantity, the first time, the second time, and the sampling duration corresponding to the sampling time period includes:
[0073] Step S33, determining a high level duration according to the first quantity, the second quantity, the first time, the second time, and the sampling duration corresponding to the sampling time period;
[0074] Step S34, calculating the ratio of the high level duration to the sampling duration to obtain the duty cycle of the PWM signal.
[0075] In the embodiment of the present application, it should be noted that it can be understood that the duty cycle refers to the ratio between the high level duration and the total sampling duration, so first, it is necessary to calculate the high level duration according to the first quantity, the second quantity, the first time, the second time and the sampling duration corresponding to the sampling time period collected. In general, in the process of calculating the high level duration, it is necessary to calculate the difference between the time point of each falling edge and the time point of the corresponding rising edge to obtain the high level duration of a single stage, and then combine the high level duration of each stage. Therefore, in the calculation process, it is necessary to combine the number and time points corresponding to all high level stages and low level stages respectively and the total sampling duration, and finally find the time and (i.e., high level duration) of all high level stages. After obtaining the high level duration, the ratio between the high level duration and the sampling duration can be calculated to obtain the duty cycle of the PWM signal.
[0076] Exemplarily, the calculation expression of the duty cycle of the PWM signal is: D=h / Ts, where D is the duty cycle, h is the high level duration, and Ts is the sampling duration.
[0077] In a possible implementation manner, the step of determining the high level duration according to the first quantity, the second quantity, the first time, the second time, and the sampling duration corresponding to the sampling time period may also include:
[0078] Step S331, determining whether the first quantity is equal to the second quantity;
[0079] Step S332, if they are equal, determining the high level duration according to the magnitude relationship between the first time and the second time, the first time, the second time, and the sampling duration;
[0080] Step S333: If they are not equal, determining the high level duration according to the size relationship between the first quantity and the second quantity, the first time, the second time and the sampling duration.
[0081] In an embodiment of the present application, the first time of the time corresponding to each rising edge and the second time of the time corresponding to each falling edge are first calculated, the first time and the sum of the time trx, x=1, 2, 3, ..., Nr corresponding to the rising edges are respectively recorded as trS, and the second time and the sum of tfx, x=1, 2, 3, ..., Nf are recorded as tfS, which are used to calculate the total duration corresponding to the high level state and / or the total duration corresponding to the low level state within the sampling time period.
[0082] It should be noted that in the technical solution of the embodiment of the present application, different duty cycle calculation strategies are determined by judging whether the number of the rising edges is equal to the number of the falling edges. It can be understood that, in the sampling time period, when the number of rising edges and falling edges in the PWM signal is equal, each rising edge corresponds to a single falling edge, wherein, if each falling edge is located after the corresponding rising edge, the difference between each falling edge and the corresponding rising edge time can be calculated respectively, and the duration of each single high level state can be obtained, so when calculating the total duration of the high level state, it can be obtained by calculating the difference between the sum of the time corresponding to each falling edge and the sum of the time of each rising edge, and then the duty cycle of the PWM signal can be determined. In addition, if each rising edge is after the corresponding falling edge, the duration of each single high level state cannot be calculated directly. However, the duration of each single low level state can be obtained by calculating the difference between each rising edge and the corresponding falling edge time, and the total duration of the low level state can be obtained according to the same method as above, and finally the total duration of the low level state can be subtracted from the sampling duration, and the total duration of the high level state can also be obtained, and then the duty cycle of the PWM signal can be determined.
[0083] On the other hand, when the number of rising edges and falling edges in the PWM signal is not equal, it can be understood according to the nature of the pulse signal that a certain edge (rising edge or falling edge) is located at both ends of the sampling time period and is one more than the number of another edge. For example, the PWM signal includes: rising edge-falling edge-rising edge-falling edge-rising edge. In this case, the number of rising edges is one more than the number of falling edges. For another example, the PWM signal includes: falling edge-rising edge-falling edge-rising edge-falling edge. In this case, the number of falling edges is one more than the number of rising edges. Among them, when the number of falling edges is one more than the number of rising edges, except that the first falling edge has no corresponding rising edge, the other falling edges all have corresponding rising edges. When calculating the difference respectively, the time of the first falling edge can be subtracted by 0 (that is, the corresponding time of the starting point in the sampling time period). In this case, the total duration of the high level state can also be determined according to the calculation method when the number of rising edges is equal to that of falling edges and the first time is less than the second time, thereby determining the duty cycle of the PWM signal. Similarly, when the number of rising edges is 1 more than the number of falling edges, except for the first rising edge which has no corresponding falling edge, the other rising edges all have corresponding falling edges. When calculating the differences respectively, the time of the first rising edge can be subtracted by 0. In this case, the total duration of the high level state can also be determined according to the calculation method when the number of rising edges is equal to that of falling edges and the first time is greater than the second time, thereby determining the duty cycle of the PWM signal.
[0084] In a possible implementation manner, the step of determining the high level duration according to the magnitude relationship between the first time and the second time, the first time, the second time, and the sampling duration may also include:
[0085] Step A10, determining whether the first time is less than the second time;
[0086] Step A20, when the first time and the sum are not greater than the second time, calculating the difference between the second time and the first time and the sum, and obtaining a high level duration;
[0087] Step A30, when the first time and is greater than the second time and, calculate the first difference between the first time and the second time and, and calculate the difference between the sampling duration and the first difference to obtain the high level duration.
[0088] In an embodiment of the present application, a method for obtaining a high level duration by selecting different calculation methods according to the size between the first time and the second time when the number of rising edges in a PWM signal is equal to the number of falling edges is specifically disclosed.
[0089] Specifically, refer to Figure 6When the first time and is less than the second time, within the sampling time period of the PWM signal, the distribution of the rising edge and the falling edge is: rising edge-falling edge-rising edge...falling edge. Each falling edge has a rising edge earlier than it. Therefore, the duration of the high level state between the rising edge and the falling edge can be calculated according to the difference between the time of the falling edge and the corresponding rising edge. The high level duration can also be obtained according to the difference between the second time and the first time, and then the ratio of the high level duration to the sampling duration is calculated to obtain the duty cycle of the PWM signal.
[0090] As an example, the mathematical expression for calculating the duty cycle is: if Nr=Nf≠0 and tfS≥trS, then D=(tfS-trS) / Ts, where Nr is the number of rising edges, Nf is the number of falling edges, D is the duty cycle, tfS is the second time and, trS is the first time, Ts is the sampling duration, and the high level duration h=tfS-trS.
[0091] In particular, refer to Figure 7 When the number of rising edges and the number of falling edges in the PWM signal are both 1, the high level duration h can be obtained by calculating the difference between the time of the falling edge and the time of the rising edge, and then the ratio between the high level duration h and the sampling duration Ts can be calculated to obtain the duty cycle.
[0092] Specifically, refer to Figure 8 When the first time and is greater than the second time, within the sampling time period of the PWM signal, the distribution of the rising edge and the falling edge is: falling edge-rising edge...falling edge-rising edge. Each rising edge has a falling edge earlier than it. Therefore, the duration of the low-level state between the falling edge and the rising edge can be calculated according to the difference between the time of the rising edge and the corresponding falling edge. The low-level duration can also be obtained according to the difference between the first time and the second time. The high-level duration is obtained by calculating the difference between the sampling duration and the low-level duration, and then the ratio between the high-level duration and the sampling duration is calculated to obtain the duty cycle of the PWM signal.
[0093] As an example, the mathematical expression for calculating the duty cycle is: if Nr=Nf≠0 and tfS<trS, then D=(Ts-(trS-tfS)) / Ts=(Ts+tfS-trS) / Ts, where Nr is the number of rising edges, Nf is the number of falling edges, D is the duty cycle, tfS is the second time and, trS is the first time, Ts is the sampling duration, and the high level duration h=Ts+tfS-trS.
[0094] In particular, refer to Fig. 9When the number of rising edges and the number of falling edges in the PWM signal are both 1, the low-level duration (i.e., the first difference) can be obtained by calculating the difference between the time of the rising edge and the time of the falling edge, and then the difference between the sampling duration Ts and the low-level duration is calculated to obtain the high-level duration h, and then the ratio of the high-level duration h to the sampling duration Ts is calculated to obtain the duty cycle.
[0095] In another possible implementation, the step of determining the high level duration according to the size relationship between the first quantity and the second quantity, the first time, the second time, and the sampling duration may also include:
[0096] Step A40: If the first number is smaller than the second number, the difference between the second time and the first time is calculated to obtain the high level duration.
[0097] In an embodiment of the present application, a method for calculating the duty cycle of a PWM signal when the number of rising edges in the PWM signal is less than the number of falling edges is specifically disclosed.
[0098] Specifically, refer to Fig.10 When the number of rising edges is less than the number of falling edges, within the sampling time period, the distribution of rising edges and falling edges is: falling edge-rising edge-falling edge...rising edge-falling edge. Except for the first falling edge, each falling edge has a rising edge that is earlier than it. Therefore, the duration of the high-level state between the rising edge and the falling edge can be calculated according to the difference between the time of the falling edge and the corresponding rising edge. The time of the starting point of the sampling time period (i.e. 0) can be subtracted from the time of the first falling edge to obtain the duration of the high-level state before the first falling edge. Therefore, in this case, the high-level duration can also be obtained according to the difference between the second time and the first time, and then the ratio of the high-level duration to the sampling duration is calculated to obtain the duty cycle of the PWM signal.
[0099] As an example, the mathematical expression for calculating the duty cycle is: if Nr<Nf≠0, then D=(tfS-trS) / Ts, where Nr is the number of rising edges, Nf is the number of falling edges, D is the duty cycle, tfS is the second time and, trS is the first time, Ts is the sampling time, and the high level time h=tfS-trS.
[0100] In particular, refer to Fig.11 When the number of rising edges in the PWM signal is 0 and the number of falling edges is 1, the high level duration can be obtained by calculating the difference between the time of the falling edge and the time of the starting point of the sampling time period, and then the ratio between the high level duration and the sampling time period Ts is calculated to obtain the duty cycle.
[0101] In a possible implementation manner, the step of determining the high level duration according to the size relationship between the first quantity and the second quantity, the first time, the second time, and the sampling duration includes:
[0102] Step A50, if the first number is greater than the second number, calculating the difference between the first time and the second time to obtain a low level duration;
[0103] Step A60, calculating the difference between the sampling duration and the low level duration to obtain the high level duration.
[0104] In an embodiment of the present application, a method for calculating the duty cycle of a PWM signal when the number of rising edges in the PWM signal is greater than the number of falling edges is specifically disclosed.
[0105] Specifically, refer to Fig.12 When the number of rising edges is greater than the number of falling edges, within the sampling time period of the PWM signal, the distribution of the rising edges is: rising edge-falling edge-rising edge...falling edge-rising edge. Except for the first rising edge, each rising edge has a falling edge earlier than it. Therefore, the duration of the low-level state between the falling edge and the rising edge can be calculated based on the difference between the time of the rising edge and the corresponding falling edge. The duration of the low-level state before the first rising edge can also be obtained by subtracting the initial time of the sampling time period from the time corresponding to the first rising edge. Therefore, in this case, the low-level duration can also be obtained based on the difference between the first time and the second time, and the high-level duration can be obtained by calculating the difference between the sampling time and the low-level duration, and then the ratio of the high-level duration to the sampling time is calculated to obtain the duty cycle of the PWM signal.
[0106] As an example, the mathematical expression for calculating the duty cycle is: if Nr>Nf≠0, then D=(Ts-(trS-tfS)) / Ts=(Ts+tfS-trS) / Ts, where Nr is the number of rising edges, Nf is the number of falling edges, D is the duty cycle, tfS is the second time and, trS is the first time, Ts is the sampling time, and the high level time h=Ts+tfS-trS.
[0107] In particular, in a possible embodiment, referring to Fig.13 The step of determining the high level duration according to the size relationship between the first quantity and the second quantity, the first time, the second time and the sampling duration may also include:
[0108] If the first number is 1 and the second number is 0, determining that the first time is the first time corresponding to the rising edge;
[0109] The difference between the sampling duration and the first time is calculated to obtain the high level duration.
[0110] Specifically, when the number of rising edges in the PWM signal is 1 and the number of falling edges is 0, the low-level duration can be obtained by calculating the difference between the time of the rising edge and the time of the starting point of the sampling time period, and then the difference between the sampling time period Ts and the low-level duration is calculated to obtain the high-level duration, and then the ratio of the high-level duration to the sampling time period Ts is calculated to obtain the duty cycle.
[0111] The embodiment of the present application provides a method for sampling the duty cycle of a pulse width modulation signal. The technical solution of the embodiment of the present application first reads the first number and the second number of rising edges and falling edges in a pulse width modulation PWM signal within a sampling time period, and reads the first time corresponding to the rising edge and the second time corresponding to the falling edge, wherein the first time is the sum of the time points at which all rising edges are located, and the second time is the sum of the time points at which all falling edges are located, and then collects the level of the PWM signal at each sampling moment according to a preset sampling frequency, and finally determines the duty cycle of the PWM signal according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period. The technical solution of the embodiment of the present application combines the reading of the voltage level and the sampling duration. There are two schemes: flat sampling and edge change moment sampling. Compared with the scheme of sampling the PWM duty cycle only by reading the high and low levels of the PWM signal, the technical scheme of the embodiment of the present application ensures a higher duty cycle accuracy when the level reading speed is low; compared with the scheme of sampling the PWM duty cycle only by reading the edge change moment of the PWM signal, the technical scheme of the embodiment of the present application can meet a higher sampling frequency, and can determine the duty cycle value even when the number of rising and falling edges is not read. In summary, the technical scheme of the embodiment of the present application takes into account the duty cycle accuracy and sampling frequency in the process of PWM signal duty cycle sampling, and solves the technical problems of low duty cycle accuracy and limited sampling frequency in the traditional pulse width modulation signal duty cycle sampling scheme.
[0112] The present invention also provides a pulse width modulation signal duty cycle sampling device, please refer to Fig.14 , the pulse width modulation signal duty cycle sampling device comprises:
[0113] The first acquisition module 10 is used to read the first number and the second number of rising edges and falling edges in the pulse width modulation PWM signal within a sampling period, and read the first time corresponding to the rising edge and the second time corresponding to the falling edge, wherein the first time is the sum of the time points of all rising edges, and the second time is the sum of the time points of all falling edges;
[0114] A second acquisition module 20, used for acquiring the level of the PWM signal at each sampling moment according to a preset sampling frequency;
[0115] The duty cycle determination module 30 is used to determine the duty cycle of the PWM signal according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period.
[0116] Optionally, the duty cycle determining module 30 is further configured to:
[0117] Determine a high level duration according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period;
[0118] The ratio of the high level duration to the sampling duration is calculated to obtain the duty cycle of the PWM signal.
[0119] Optionally, the duty cycle determining module 30 is further configured to:
[0120] Determining whether the first quantity is equal to the second quantity;
[0121] If they are equal, determining the high level duration according to the magnitude relationship between the first time and the second time, the first time, the second time, and the sampling duration;
[0122] If they are not equal, the high level duration is determined according to the size relationship between the first number and the second number, the first time, the second time and the sampling duration.
[0123] Optionally, the duty cycle determining module 30 is further configured to:
[0124] Determine whether the first time is less than the second time;
[0125] When the first time is not greater than the second time, the difference between the second time and the first time is calculated to obtain the high level duration;
[0126] When the first time and is greater than the second time, a first difference between the first time and the second time is calculated, and a difference between the sampling duration and the first difference is calculated to obtain a high level duration.
[0127] Optionally, the duty cycle determining module 30 is further configured to:
[0128] If the first number is smaller than the second number, the difference between the second time and the first time is calculated to obtain the high level duration.
[0129] Optionally, the duty cycle determining module 30 is further configured to:
[0130] If the first number is greater than the second number, calculating the difference between the first time and the second time to obtain the low level duration;
[0131] The difference between the sampling duration and the low level duration is calculated to obtain the high level duration.
[0132] Optionally, the duty cycle determining module 30 is further configured to:
[0133] If the first number is 1 and the second number is 0, determining that the first time is the first time corresponding to the rising edge;
[0134] The difference between the sampling duration and the first time is calculated to obtain the high level duration.
[0135] The pulse width modulation signal duty cycle sampling device provided by the present invention adopts the pulse width modulation signal duty cycle sampling method in the above-mentioned embodiment 1 or embodiment 2, which can solve the technical problems of low duty cycle accuracy and limited sampling frequency in the pulse width modulation signal duty cycle sampling scheme. Compared with the prior art, the beneficial effects of the pulse width modulation signal duty cycle sampling device provided by the embodiment of the present invention are the same as the beneficial effects of the pulse width modulation signal duty cycle sampling method provided by the above-mentioned embodiment, and other technical features in the pulse width modulation signal duty cycle sampling device are the same as the features disclosed in the above-mentioned embodiment method, which will not be repeated here.
[0136] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the pulse width modulation signal duty cycle sampling method in the above-mentioned embodiment one.
[0137] Reference below Fig.15 , which shows a schematic diagram of the structure of an electronic device suitable for implementing the embodiments of the present disclosure. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.15The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.
[0138] like Fig.15 As shown, the electronic device may include a processing device 1001 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the electronic device are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows an electronic device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.
[0139] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.
[0140] The electronic device provided by the present invention adopts the pulse width modulation signal duty cycle sampling method in the above embodiment, which can solve the technical problems of low duty cycle accuracy and limited sampling frequency in the pulse width modulation signal duty cycle sampling scheme. Compared with the prior art, the beneficial effects of the electronic device provided by the embodiment of the present invention are the same as the beneficial effects of the pulse width modulation signal duty cycle sampling method provided by the above embodiment, and other technical features in the electronic device are the same as the features disclosed in the previous embodiment method, which will not be repeated here.
[0141] It should be understood that the various parts of the present disclosure can be implemented with hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.
[0142] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
[0143] An embodiment of the present invention provides a computer-readable storage medium having computer-readable program instructions stored thereon, and the computer-readable program instructions are used to execute the pulse width modulation signal duty cycle sampling method in the above-mentioned embodiment 1.
[0144] The computer-readable storage medium provided in the embodiment of the present invention may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.
[0145] The computer-readable storage medium may be included in the electronic device, or may exist independently without being installed in the electronic device.
[0146] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by an electronic device, the electronic device: reads the first number and the second number of rising edges and falling edges in a pulse width modulation (PWM) signal within a sampling time period, and reads the first time corresponding to the rising edge and the second time corresponding to the falling edge, wherein the first time is the sum of the time points at which all rising edges are located, and the second time is the sum of the time points at which all falling edges are located; collects the level of the PWM signal at each sampling moment according to a preset sampling frequency; and determines the duty cycle of the PWM signal according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period.
[0147] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, C++, and conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0148] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.
[0149] The modules involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of the module does not limit the unit itself in some cases.
[0150] The readable storage medium provided by the present invention is a computer-readable storage medium, which stores computer-readable program instructions for executing the above-mentioned pulse width modulation signal duty cycle sampling method, and can solve the technical problems of low duty cycle accuracy and limited sampling frequency in the pulse width modulation signal duty cycle sampling scheme. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in the embodiment of the present invention are the same as the beneficial effects of the pulse width modulation signal duty cycle sampling method provided in the above-mentioned embodiment 1 or embodiment 2, and will not be repeated here.
[0151] An embodiment of the present invention further provides a computer program product, including a computer program, wherein when the computer program is executed by a processor, the steps of the pulse width modulation signal duty cycle sampling method as described above are implemented.
[0152] The computer program product provided by the present application can solve the technical problems of low duty cycle accuracy and limited sampling frequency in the pulse width modulation signal duty cycle sampling scheme. Compared with the prior art, the beneficial effects of the computer program product provided by the embodiment of the present invention are the same as the beneficial effects of the pulse width modulation signal duty cycle sampling method provided by the above-mentioned embodiment 1 or embodiment 2, and will not be repeated here.
[0153] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent processing scope of the present application.
Claims
1. A pulse width modulation signal duty cycle sampling method, characterized in that: The pulse width modulation signal duty cycle sampling method comprises: In a sampling time period, read the first number and the second number of rising edges and falling edges in the pulse width modulation (PWM) signal, and read the first time corresponding to the rising edge and the second time corresponding to the falling edge, wherein the first time is the sum of the time points of all rising edges, and the second time is the sum of the time points of all falling edges; Collecting the level of the PWM signal at each sampling moment according to a preset sampling frequency; The duty cycle of the PWM signal is determined according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period.
2. The pulse width modulation signal duty cycle sampling method according to claim 1, characterized in that: The step of determining the duty cycle of the PWM signal according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period comprises: Determine a high level duration according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period; The ratio of the high level duration to the sampling duration is calculated to obtain the duty cycle of the PWM signal.
3. The pulse width modulation signal duty cycle sampling method according to claim 1, characterized in that: The step of determining the high level duration according to the first quantity, the second quantity, the first time, the second time and the sampling duration corresponding to the sampling time period comprises: Determining whether the first quantity is equal to the second quantity; If they are equal, determining the high level duration according to the magnitude relationship between the first time and the second time, the first time, the second time, and the sampling duration; If they are not equal, the high level duration is determined according to the size relationship between the first number and the second number, the first time, the second time and the sampling duration.
4. The pulse width modulation signal duty cycle sampling method as claimed in claim 3, characterized in that: The step of determining the high level duration according to the magnitude relationship between the first time and the second time, the first time, the second time, and the sampling duration comprises: Determine whether the first time is less than the second time; When the first time is not greater than the second time, the difference between the second time and the first time is calculated to obtain the high level duration; When the first time and is greater than the second time, a first difference between the first time and the second time is calculated, and a difference between the sampling duration and the first difference is calculated to obtain a high level duration.
5. The pulse width modulation signal duty cycle sampling method as claimed in claim 3, characterized in that: The step of determining the high level duration according to the magnitude relationship between the first quantity and the second quantity, the first time, the second time and the sampling duration comprises: If the first number is smaller than the second number, the difference between the second time and the first time is calculated to obtain the high level duration.
6. The pulse width modulation signal duty cycle sampling method as claimed in claim 3, characterized in that: The step of determining the high level duration according to the magnitude relationship between the first quantity and the second quantity, the first time, the second time and the sampling duration comprises: If the first number is greater than the second number, calculating the difference between the first time and the second time to obtain the low level duration; The difference between the sampling duration and the low level duration is calculated to obtain the high level duration.
7. The pulse width modulation signal duty cycle sampling method according to claim 6, characterized in that: The step of determining the high level duration according to the magnitude relationship between the first quantity and the second quantity, the first time, the second time and the sampling duration comprises: If the first number is 1 and the second number is 0, determining that the first time is the first time corresponding to the rising edge; The difference between the sampling duration and the first time is calculated to obtain the high level duration.
8. A pulse width modulation signal duty cycle sampling device, characterized in that: The pulse width modulation signal duty cycle sampling device comprises: A first acquisition module is used to read the first number and the second number of rising edges and falling edges in the pulse width modulation (PWM) signal within a sampling period, and read the first time corresponding to the rising edge and the second time corresponding to the falling edge, wherein the first time is the sum of the time points of all rising edges, and the second time is the sum of the time points of all falling edges; A second acquisition module, used for acquiring the level of the PWM signal at each sampling moment according to a preset sampling frequency; The duty cycle determination module is used to determine the duty cycle of the PWM signal according to the first number, the second number, the first time, the second time, and the sampling duration corresponding to the sampling time period.
9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the steps of the pulse width modulation signal duty cycle sampling method according to any one of claims 1 to 7.
10. A readable storage medium, characterized in that: The readable storage medium is a computer-readable storage medium, on which is stored a program for implementing a pulse width modulation signal duty cycle sampling method. The program for implementing a pulse width modulation signal duty cycle sampling method is executed by a processor to implement the steps of the pulse width modulation signal duty cycle sampling method as described in any one of claims 1 to 7.