Online fault detection in safety critical systems using isolation and process migration

Abstract

The invention relates to online fault detection in safety critical systems using isolation and process migration. Apparatuses, systems, and techniques for testing a processing unit of a computing system are disclosed herein. A request to initiate a test procedure for each of a set of processing units is received. The first processing unit includes a first virtual processor that performs a first operation. The second processing unit includes a second virtual processor that performs a second operation. Execution of the first operation is transferred from the first virtual processor to the second virtual processor. When the second virtual processor performs the first operation and the second operation, execution of the test process is initiated at the first processing unit. In response to detecting that execution of the test process has been completed, execution of the first operation and the second operation is transferred to the first virtual processor. When the running first virtual processor performs the first operation and the second operation, execution of the test process is initiated at the second processing unit.

Description

Technical Field

[0001] At least one embodiment is directed to testing a processing unit of a computing system. For example, before executing a test process at a first processing unit including a first virtual processor, an operation to be executed can be transferred from the first virtual processor to a second virtual processor. After completing the test process, before executing the test process at a second processing unit including a second virtual processor, execution of the operation can be transferred from the second virtual processor to the first virtual processor (or another virtual processor). Background Art

[0002] A multi-core processor refers to a processor (e.g., a microprocessor) on a single integrated circuit that has two or more independent processing units (referred to as cores). Each core of a multi-core processor can read and execute program instructions (e.g., concurrently). A multi-core processor may be included in a system where its failure or malfunction could have catastrophic consequences. Testing multi-core processors in such systems is critical to ensuring the safety and effectiveness of the system. Coordinating the testing of multi-core processors in such systems while maintaining the constant availability of the processors to execute instructions related to system functionality can be difficult. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Various embodiments according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0004] Figure 1 is a block diagram of an example system architecture according to at least one embodiment;

[0005] Figure 2 is a block diagram of an example processing unit test engine according to at least one embodiment;

[0006] Figure 3 A flow chart illustrating an example method for online fault detection in a safety-critical system using isolation and process migration in accordance with at least one embodiment;

[0007] Figures 4A-4E An example of a test processing unit of a computing system according to at least one embodiment is shown;

[0008] Figure 5A-5B Additional examples of test processing units of computing systems according to at least one embodiment are shown;

[0009] Fig. 6A illustrates (one or more) example hardware structures for inference and / or training logic according to at least one embodiment;

[0010] Figure 6B illustrates (one or more) example hardware structures for inference and / or training logic according to at least one embodiment;

[0011] Figure 7 An example data center system is shown in accordance with at least one embodiment;

[0012] Figure 8 A computer system according to at least one embodiment is shown;

[0013] Fig. 9 A computer system according to at least one embodiment is shown;

[0014] Fig.10 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0015] Fig.11 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0016] Fig.12 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0017] Fig.13 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline according to at least one embodiment; and

[0018] Fig.14A as well as Fig. 14B A data flow diagram of a process for training a machine learning model, and a client-server architecture for augmenting an annotation tool with a pre-trained annotation model, according to at least one embodiment are shown. DETAILED DESCRIPTION

[0019] A safety-critical system is a system whose failure or malfunction may result in catastrophic consequences (e.g., serious injury, property loss or severe damage, etc.). Examples of safety-critical systems may include autopilot systems, aircraft and / or air traffic control systems, some medical systems, etc. Testing may be performed on the hardware (e.g., processing units, etc.) and / or software of safety-critical systems to ensure the safety and effectiveness of such systems. In some cases, testing may be performed while the system is running. In an illustrative example, a fault detection process may be performed to detect faults in a processing unit (e.g., a central processing unit (CPU), a graphics processing unit (GPU), etc.) and / or other hardware components of an autopilot system while the autopilot system is being operated (e.g., by a driver and / or passenger).

[0020] Some computing systems (including safety-critical systems) may include multiple processing units that can perform operations concurrently. In some cases, the performance of a computing system may be measured based on the availability of a processing unit to perform operations within a specific time period and / or the number of operations that a processing unit can perform within a specific time period. A computing system with a processing unit that is often available to perform operations of one or more applications and / or can safely and successfully perform a large number of operations within a time period may be considered a high-performance computing system, while a computing system with a processing unit that is often unavailable to perform operations of one or more applications and / or can only safely and successfully perform a small number (small amount) of operations within a time period may be considered a low-performance computing system. Since the corresponding processing unit cannot perform multiple operations at a time, a processing unit that is performing one or more test operations (e.g., according to a safety test) is not available to perform operations of applications running on the system, thereby affecting the overall performance of the system (e.g., efficiency, throughput, latency, etc.).

[0021] In conventional systems, when a test process is executed on a system, an entire group or cluster of processing units (e.g., processing unit cores or processor cores) is taken offline (e.g., unavailable for application operations) and is not brought back online (e.g., available for application operations) until the entire test process is completed. In an illustrative example, a computing system may include one or more processor cores that perform operations of applications running on the computing system. During the test period, the processing units of the processor cores are taken offline until the test process is completed. Thus, execution of operations of the application is temporarily suspended on the processor cores, which reduces the number of operations performed at the system in a particular time period, thereby affecting overall system performance.

[0022] Some systems may include multiple processor cores, each of which performs operations associated with one or more applications. In some cases, while the processing unit of the first processor core is being tested, the operations performed on the first processor core may be temporarily transferred to be performed on the second processor core. However, the processing unit of the second processor core may also be performing additional operations during the test period (e.g., based on the partitioning scheme of the system), so the operations transferred from the first processor core and the additional operations partitioned to the second processor core are performed during the test period. Since the processing power of the second processor core is limited, the number of operations that the second processor core can perform during the test period is limited, and the performance of performing operations and additional operations during the test period may be reduced. Therefore, the overall performance (e.g., efficiency, throughput, etc.) of the system may be reduced. This performance degradation may affect the overall security of the system and / or may affect the user's experience of the system.

[0023] Embodiments of the present disclosure address the above and other deficiencies by providing techniques for online fault detection in safety-critical systems using isolation and process migration. An operating system (or another component) of a computing system may receive a request to initiate a test process for a processing unit cluster (e.g., a processor core) of the computing system. In an illustrative example, the computing system may be included in an autonomous driving system. In some cases, a request may be received according to a test protocol to test the processing unit of the system at a specific time interval (e.g., every 100 milliseconds) based on the safety standards of the autonomous driving system. In some cases, the resources of the computing system may be divided and / or abstracted for use by one or more virtualized systems (e.g., virtual machines, containers, etc.) that execute applications of the autonomous driving system. A processing unit may be divided and / or abstracted into one or more virtual processors, each of which performs operations of a corresponding application of the autonomous driving system. In an illustrative example, a first virtual processor hosted by a first processing unit may perform a first set of operations for one or more applications, while a second virtual processor hosted by a second processing unit performs a second set of operations for one or more applications.

[0024] In response to receiving a request to initiate a test process, an operating system (or another component) of a computing system may transfer execution of a first set of operations from a first virtual processor to a second virtual processor while executing the test process on a first processing unit. The operating system may transfer execution of the first set of operations by sending an instruction to a virtual system manager (e.g., a hypervisor, etc.) to transfer execution of the first set of operations to a second virtual processor at a second processing unit. Once execution of the first set of operations is transferred to the second virtual processor, the operating system may initiate execution of the test process at the first processing unit. During execution of the test process, the first processing unit may be offline or otherwise unavailable for execution of other operations. While the test process is being executed at the first processing unit, a second virtual processor running on the second processing unit may execute the first set of operations and / or the second set of operations.

[0025] Upon detecting that execution of the test process is complete at the first processing unit, the operating system may cause execution of the first set of operations and the second set of operations to be transferred from the second virtual processor to the first virtual processor (e.g., running on the first processing unit). While the first virtual processor is executing the first set of operations and / or the second set of operations, the operating system may initiate execution of the test process at the second processing unit. As described above, during execution of the test process, the second processing unit may be offline or otherwise unavailable for execution of other operations.

[0026] In some cases, the first processing unit and the second processing unit can be included in a common processing unit group or cluster (e.g., a common processor core) with other processing units. Once the test process is completed at the second processing unit, the execution of operations of another processing unit of the processor core (e.g., a third processing unit) can be transferred to be executed on the second virtual processor while the test process is executed on the other processing unit. The execution of the operations performed by the processor core can be transferred to the virtual processors hosted by the various processing units in the above manner (e.g., a round-robin manner) until the test process is executed on each processing unit of the processor core. In some cases, the test process is a fault detection process. After detecting that the test process is completed at each processing unit of the processor core, the operating system (or another component of the computing system) can determine whether any processing unit has failed based on the results of the test process.

[0027] Aspects and embodiments of the present disclosure provide techniques that enable the isolation and testing of processing units (e.g., processing units of a processor core) of a system according to a test process while other processing units of the system continue to perform operations during the test process. By testing the processing units of a processor core according to the above-mentioned techniques, each processing unit of the processor core can be offline and tested, while the virtual processors hosted by other processing units of the processor core perform the operations originally divided into the offline processing units. Therefore, during the test period, only one unit of the processor core is offline at a time, rather than offline each processing unit of the processor core. The amount of time that each processing unit is offline during the test process is less than the total amount of time to perform the test process, which correspondingly reduces the amount of time that each processing unit is not available to perform application operations. In an illustrative example, the total amount of time used to perform the test process can be 100 milliseconds (e.g., according to the security specifications of the computing system). Instead of taking each processing unit of the processor core offline for the entire 100 milliseconds, each corresponding processor core is offline for 25 milliseconds, while the other processing units of the processor core continue to perform the operations of the application running on the computing system. As a result, the amount of time that the processing units are available in the computing system and the total number of operations performed by the processing units of the computing system are increased, thereby improving the overall performance (eg, efficiency, throughput, latency, etc.) of the computing system.

[0028] The systems and methods described herein may be used for a variety of purposes, such as, but not limited to, systems or applications for online multiplayer gaming, machine control, machine motion, machine driving, synthetic data generation, model training, perception, augmented reality, virtual reality, mixed reality, robotics, security and surveillance, autonomous or semi-autonomous machine applications, deep learning, environmental simulation, data center processing, conversational AI, light transport simulation (e.g., ray tracing, path tracing, etc.), collaborative content creation of 3D assets, digital twin systems, cloud computing, and / or any other suitable application.

[0029] The disclosed embodiments may be included in a variety of different systems, such as systems for participating in online games, automotive systems (e.g., control systems for autonomous or semi-autonomous machines, perception systems for autonomous or semi-autonomous machines), systems implemented using robots, aviation systems, medical systems, boating systems, smart area monitoring systems, systems for performing deep learning operations, systems for performing simulation operations, systems implemented using edge devices, systems including one or more virtual machines (VMs), systems for performing synthetic data generation operations, systems implemented at least in part in a data center, systems for performing conversational AI operations, systems for performing light transport simulations, systems for performing collaborative content creation of 3D assets, systems for generating or maintaining digital twin representations of physical objects, systems implemented at least in part using cloud computing resources, and / or other types of systems.

[0030] Figure 1 1 is a block diagram of an example system architecture 100 according to at least one embodiment. The system architecture 100 (also referred to herein as a "system") may include a computing device 102, one or more client devices 106A-106N (collectively and individually referred to herein as client devices 106), and / or one or more data repositories 112 (collectively and individually referred to herein as data repositories 112, each data repositories connected via a network 110). It should be noted that the system 100 may additionally or alternatively include other components (e.g., one or more server machines, etc.) connected to the computing device 102, the client device 106, the data repositories 112, etc. via the network 110. In various implementations, the network 110 may include a public network (e.g., the Internet), a private network (e.g., a local area network (LAN) or a wide area network (WAN)), a wired network (e.g., an Ethernet network), a wireless network (e.g., an 802.11 network or a Wi-Fi network), a cellular network (e.g., a long term evolution (LTE) network), a router, a hub, a switch, a server computer, and / or a combination thereof.

[0031] In some embodiments, data repository 112 is a persistent storage device that is capable of storing data and data structures for tagging, organizing, and indexing data. Data repository 112 may be hosted by one or more storage devices, such as main memory, magnetic or optical storage-based disks, tapes, or hard drives, NAS, SAN, etc. In some embodiments, data repository 112 may be a network-attached file server, while in other embodiments, data repository 112 may be some other type of persistent storage, such as an object-oriented database, a relational database, etc., which may be hosted by computing device 102 or one or more different machines coupled to computing device 102 via network 110.

[0032] The computing device 102 may be a desktop computer, a laptop computer, a smartphone, a tablet computer, a server, or any suitable computing device capable of performing the techniques described herein. In some embodiments, the computing device 102 may be a computing device of a cloud computing platform. For example, the computing device 102 may be a server machine of a cloud computing platform, or may be a component of a server machine of a cloud computing platform. In such an embodiment, the computing device 102 may be coupled to one or more edge devices (not shown) via a network 110. An edge device refers to a computing device that is capable of implementing communication between computing devices at a boundary (e.g., an interface) between two networks. For example, an edge device may be connected to the computing device 102, the client device 106, and / or the data repository 112 via a network 110, and may be connected to one or more endpoint devices (not shown) via another network. In such an example, the edge device may implement communication between the computing device 102, the client device 106, and / or the data repository 112 and one or more endpoint devices. In other or similar embodiments, the computing device 102 may be an edge device, or may be a component of an edge device. For example, computing device 102 may facilitate communications between a data repository 112 and / or a client device 106 connected to computing device 102 via network 110 and client device 106 (or one or more other user devices and / or other computing devices) connected to computing device 102 via another network.

[0033] The client device 106 may include any computing device 102 that enables a user to access features of an application. For example, the client device 106 may be a device, or may be a component of a device, such as, but not limited to, a television, a smart phone, a cellular phone, a personal digital assistant (PDA), a portable media player, a netbook, a laptop, an e-book reader, a tablet computer, a desktop computer, a set-top box, a gaming console, an autonomous vehicle, a surveillance device, and the like. In some embodiments, the computing device 102 may be an edge device that connects the client device 106 to the data repository 112 and / or other components of the system 100. In other or similar embodiments, the computing device 102 may not connect the client device 106 to the data repository 112 and / or other components, but may provide the client device 106 with data obtained by the computing device 102 (e.g., from the data repository 112). In additional or alternative embodiments, the computing device 102 and the client device 106 may be the same device and / or share the same or similar components.

[0034] In some embodiments, client device 106 may include one or more hardware components. Figure 1 As shown, client device 106A may include one or more processors 120 (collectively referred to herein as processor 120), memory 124, one or more input / output (IO) devices 126, and / or other components. Processor 120 may include one or more processing units 122. A processing unit refers to a component that performs logical and / or arithmetic operations on data. In some embodiments, processing unit 122 may include one or more central processing units (CPUs) and / or one or more graphics processing units (GPUs). A GPU may include any processing unit specifically designed to accelerate graphics rendering (e.g., for an application 132 running through client device 106). As shown in FIG. Figure 1 As shown, processor 120 may include multiple processing units. In some embodiments, processor 120 may be a multi-core processor or may otherwise correspond to a multi-core processor. A multi-core processor refers to a processor on a single integrated circuit with two or more independent processing units. As described herein, each processing unit of a multi-core processor can read and execute instructions. It should be noted that although some embodiments describe processor 120 as a multi-core processor, embodiments of the present disclosure may be applied to any type of computer architecture.

[0035] In some embodiments, each physical processing unit 122 of processor 120 may be associated with a logical processing unit. A logical processing unit may be defined as a logical partition of a physical processing unit 122 to support parallel processing of the physical processing units 122. A logical processing unit may include a virtual construct of an operating system (OS) of client device 106 for managing and scheduling tasks on the physical processing unit 122. In some cases, a logical processing unit is also referred to as a thread (e.g., an execution thread).

[0036] The memory 124 may include one or more memory devices (not shown) that may store data and / or instructions accessible to the processor 120 (e.g., via a bus, etc.). In some embodiments, the memory 124 may include a volatile memory device and / or a non-volatile memory device. For example, the memory 124 may include or otherwise correspond to a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or another memory device. The I / O device 126 may include any device capable of transmitting data between one or more components of the client device 106 (e.g., the processor 120, the memory 124, etc.) and / or between components of the client device 106 and other components of the system 100. For example, the I / O device 126 may include a network interface card (NIC), an audio / video device (e.g., a monitor, speakers, etc.), a storage device, a keyboard, a mouse, etc.

[0037] As described above, one or more physical devices (e.g., processor 120, memory 124, I / O device 126, etc.) may be used to support one or more virtualization systems 130A-130N (collectively and individually referred to herein as virtualization system 130) of system 100. Virtualization system 130 (also referred to as a virtual system) may include one or more parts of a virtual machine, a container, a process, and / or any other type of virtualization system. One or more applications 132 (or application instances) may run on virtualization system 130 under a guest operating system (OS) (not shown). A virtualization manager 134 (sometimes also referred to as a hypervisor) running under the OS of client device 106 may abstract the physical components of client device 106 and present the abstraction to virtualization system 130 as one or more virtual devices. For example, virtualization manager 134 may abstract processing unit 122A of processor 120 and present the abstraction to virtualization system 130A as an abstract (or virtual) processing unit. The guest OS may cause instructions associated with application 132A to execute using the virtual processing unit. In some embodiments, virtualization manager 134 may abstract processing unit 122A for virtualization system 130A by scheduling time slots on processing unit 122A, rather than dedicating processing unit 122A to virtualization system 130A. In one or more embodiments, virtualization manager 134 may abstract one or more logical processing units (e.g., threads), as described above, and present the abstracted logical processing units to virtualization system 130 as virtual processing units, as described above.

[0038] In other or similar embodiments, the virtualization manager 134 may abstract a portion of the memory 124 and present the abstraction to the virtualization system 130 as an abstract memory. The virtualization manager 134 may abstract the memory 124 by using a page table for translating memory accesses to the abstracted memory using a physical memory address of the memory 124. During execution of an application 132 using the virtualization system 130, the virtualization manager 134 may intercept virtual memory access operations (e.g., read operations, write operations, etc.) and may use the page table to translate the virtual memory address associated with the intercepted operation into a physical memory address at the memory 124. In additional or alternative embodiments, the virtualization manager 134 may abstract one or more I / O devices 126 at the client device 106 and present the abstraction to the virtualization system 130 as one or more corresponding abstract I / O devices. The virtualization manager 134 may abstract the I / O device 126 by assigning a specific port range of the interface slot of the I / O device 126 to the virtualization system 130 and presenting the assigned port range as an abstract I / O device. The guest OS may utilize an abstracted processing unit, abstracted memory, and / or one or more abstracted I / O devices to support execution of one or more applications 132 on the virtualization system 130 .

[0039] like Figure 1 As shown, the system 100 may include a processing unit test engine 151, which is configured to facilitate testing of one or more processing units 122 of the processor 120 of the client device 106. In some embodiments, the testing of the processing unit 122 may involve the operation of performing a test process. These operations may include one or more logical operations that cause the tested processing unit 122 to perform operations to access and / or process data and provide feedback (e.g., results) of the operation. The processing unit test engine 151 may analyze the feedback provided to determine the performance of the processing unit 122 (e.g., the efficiency of the processing unit 122, the availability of the processing unit 122, etc.). In some embodiments, the test process may correspond to a test protocol designed or otherwise provided for the client device 106. For example, the client device 106 may be included in a safety-critical system (e.g., an autonomous driving system, etc.) or otherwise accessible to the safety-critical system. The test process may include one or more operations for testing the performance of the processing unit 122 of the client device 106 (e.g., according to safety and efficacy standards related to safety-critical systems). In some embodiments, processing unit test engine 151 can perform test procedures while processor 120 is online (eg, available for operation of application 132). More details regarding processing unit test engine 151 and performing test procedures for processor 120 that is online are provided herein.

[0040] In some embodiments, processing unit test engine 151 may reside on computing device 102. As described above, computing device 102 may include computing resources (e.g., computing resources of a server machine, etc.) accessible to client device 106 (e.g., via network 110). In other or similar embodiments, processing unit test engine 151 may be a component of virtualization manager 134 of client device 106. In still other or similar embodiments, processing unit test engine 151 may be a component of another engine or component of client device 106 and / or any other device or system of system architecture 100, as described herein.

[0041] In some embodiments, computing device 102 and / or client device 106 may include processing unit allocation engine 151. Processing unit allocation engine 151 may be configured to allocate execution of one or more portions of an application to various processing units of client device 106. As described above, in some embodiments, client device 106 may include one or more iGPUs and one or more dGPUs. Processing unit allocation engine 151 may allocate one or more portions of an application (e.g., or all portions of an application) to be executed using one or more iGPUs and / or one or more dGPUs. It should be noted that although some embodiments of the present disclosure relate to allocating an application to be executed using an iGPU or dGPU of client device 106, embodiments of the present disclosure may be applied to allocating a portion of an application to be executed using an iGPU or dGPU or client device 106 (or any other type of processing unit at client device 106). For example, according to an embodiment of the present disclosure, processing unit allocation engine 151 may allocate one or more operations of an application to be executed using an iGPU of client device 106, and allocate one or more additional operations of the application to be executed using a dGPU of client device 106.

[0042] In some embodiments, the computing device 102, the client device 106, and / or the data repository 112 may be one or more computing devices (e.g., rack servers, router computers, server computers, personal computers, mainframe computers, laptop computers, tablet computers, desktop computers, etc.), data repositories (e.g., hard disks, memories, databases), networks, software components, and / or hardware components that may be used to distribute the execution of the application 132 using the various processing units of the client device 106. It should be noted that in some other implementations, the functionality of the computing device 102 and / or the client device 106 may be provided by a smaller number of machines. For example, in some implementations, the computing device 102 and / or the client device 106 may be integrated into a single machine, while in other implementations, the computing device 102 and / or the client device 106 may be integrated into multiple machines. Furthermore, in some implementations, one or more computing devices 102 may be integrated into the client device 106. In general, the functions described in the implementation as being performed by the computing device 102 and / or the client device 106 may also be performed on one or more edge devices (not shown) and / or other client devices (not shown), if appropriate. In addition, the functions attributed to a particular component may be performed by different or multiple components operating together. The computing device 102 and / or the client device 106 may also be accessed as a service provided to other systems or devices through an appropriate application programming interface.

[0043] Figure 2 is a block diagram of an example processing unit test engine 151 according to at least one embodiment. Figure 2 As shown, the processing unit test engine 151 may include a scheduler component 210, an execution transfer component 212, a test execution component 214 and / or a test achievement component 216. As described above, the processing unit test engine 151 may reside at the client device 106. In other or similar embodiments, the processing unit allocation engine 151 may reside at the computing device 102 and / or at another component of the system 100. The processing unit test engine 151 may be connected to the memory 250. In some embodiments, the memory 250 may include one or more areas of the data repository 112. In still other or similar embodiments, the memory 250 may include areas of other memory accessible to the client device 106, the computing device 102, and / or one or more other components of the system 100. Further details about the components of the processing unit allocation engine 151 are provided herein with reference to Figure 3 Give a description.

[0044] As described above, client device 106 may include one or more processors 120. In some embodiments, processor 120 may be a multi-core processor including multiple processing units 122, or another processor including multiple processing units 122. Figure 4A 1 shows an example processor 120 in accordance with at least one embodiment of the present disclosure. Figure 4A As shown, processor 120 may include a plurality of processing units 122 (referred to herein as PUs). In the illustrative example, processor 120 may include eight PUs (e.g., PUs 122A-122H). It should be noted that processor 120 may include any number of PUs 122. Each PU 122 may be divided into or otherwise associated with one or more logical processing units (LPUs) 402. As described above, LPU 402 may correspond to an execution thread for operations performed using processing unit 122. It should be noted that although Figure 4A Each PU 122 of the processor 120 is depicted as being divided into a single LPU 402 (e.g., PU 122A is divided into LPU 402A, PU 122B is divided into LPU 402B, etc.), but each PU 122 may be divided into any number of LPUs 402. It should also be noted that in additional or alternative embodiments, an LPU 402 may be associated with multiple PUs 122.

[0045] As about Figure 1 As described above, the virtualization manager 134 can abstract the computing resources (e.g., PU 122, LPU 402, etc.) of the client device 106 and can present the abstracted resources as virtualized resources to the virtualization system 130 running via the client device 106. For example, the virtualization manager 134 can abstract one or more PUs 122 and / or LPUs 402 and can present the abstracted PUs as virtual processing units (VPUs) 404 to the virtualization system 130. Figure 4A, the virtualization manager 134 may abstract PUs 122A-122F and / or LPUs 402A-402F and may present the abstracted PUs 122 and / or LPUs 402 as VPUs of the virtualization system 130A. Additionally or alternatively, the virtualization manager 134 may abstract PUs 122G-122H and / or LPUs 402G-402H and present the abstracted PUs 122G-122H and / or LPUs 402G-402H as VPUs of the virtualization system 130B. As described above, the virtualization system 130 may perform operations of one or more applications 132 (or application instances) through virtual resources abstracted for the virtual system. Each application 132 may include or otherwise be associated with one or more application threads 404 corresponding to tasks associated with the application 132 (or application instance). In some embodiments, a VPU of the virtualization system 130 may perform operations associated with the tasks of a particular application thread 404. In such embodiments, the lower level LPU 402 and / or PU 122 associated with the VPU performs operations associated with the application thread 404. Figure 4A In the example shown in , a VPU associated with LPU 402A and / or PU 122A may be dispatched to perform operations associated with thread 404A, a VPU associated with LPU 402B and / or PU 122B may be dispatched to perform operations associated with thread 404B, and so on.

[0046] Figure 3 A flowchart of an example method 300 for online fault detection in a safety-critical system using isolation and process migration according to at least one embodiment is shown. In at least one embodiment, the method 300 can be performed by a computing device 102, a client device 106, one or more edge devices, one or more endpoint devices, or some other computing device or combination of multiple computing devices. The method 300 can be performed by processing logic of one or more processing units (e.g., a CPU and / or GPU), which can include one or more memory devices (or communicate with one or more memory devices). In at least one embodiment, the method 300 can be executed by multiple processing threads (e.g., CPU threads and / or GPU threads), each thread executing one or more separate functions, routines, subroutines, or operations of the method. In at least one embodiment, the processing threads implementing the method 300 can be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization mechanisms). Alternatively, the processing threads implementing the method 300 can be executed asynchronously with each other. The various operations of the method 300 can be performed in accordance with Figure 3 Some operations of the method may be performed concurrently with other operations. In at least one embodiment, the method may not always be performed in the order shown in FIG. Figure 3 One or more operations shown and / or described in .

[0047] At block 310, processing logic receives a request to initiate a test process for a group of processing units. In some embodiments, processing unit test engine 151 may receive a request to initiate a test process. In some embodiments, the request may be received from a component of computing device 102 and / or client device 106 according to a test protocol for PU 122 of client device 106. In other or similar embodiments, the request may be received from another device of system 100 (e.g., a device associated with a system administrator). In some embodiments, the test process may be a fault detection process. Processing unit test engine 151 may determine whether a fault occurs at a corresponding PU based on the execution of the test process at each of the group of PUs. A fault refers to an error or failure that occurs during the execution of one or more operations by a PU. Examples of faults include, but are not limited to, failure of a PU to initiate and / or complete the execution of one or more operations, incorrect or unexpected results of the execution of one or more operations, and the like. In some embodiments, the test process may include one or more test instructions 252 corresponding to test operations for execution by PU 122 in the test process. The test operation may include operations specifically selected or designed to detect faults at a PU. In some embodiments, a system administrator or operator may provide test instructions 252 to processing unit test engine 151 (e.g., via a user device associated with the system administrator or operator). In other or similar embodiments, processing unit test engine 151 (or another component of system 100) may determine and / or generate test instructions based on historical activity of processor 120 and / or client device 106 in system 100. Figure 2 As shown, in some embodiments, test instructions 252 may be stored in memory 250 .

[0048] The scheduler component 210 of the processing unit test engine 151 can schedule the execution of one or more operations of the test instruction 252 by one or more PUs 122 of the processor 120. In some embodiments, the test instruction 252 can indicate one or more PUs 122 to be subjected to the test process. In other or similar embodiments, the scheduler component 210 can determine the PU 122 to be subjected to the test process based on the test protocol of the system 100 and / or the client device 106, as described above. In some embodiments, the PU 122 to be subjected to the test process can be in an online state during the time period when the request to perform the test process is received. In some embodiments, the scheduler 210 can identify the PU 122 to initiate the test process. In this case, the PU 122 can be taken offline (e.g., made unavailable to perform operations related to the thread 404 of one or more applications 132), while other PUs 122 of the processing unit will remain online, as described herein. In some embodiments, the scheduler 210 can identify the PU 122 to initiate the test process based on the test instruction 252 and / or the test protocol, as described above. In other or similar embodiments, the scheduler 210 may access an operation queue associated with each PU 122 subject to the test process, and may identify a PU 122 having an operation queue that satisfies one or more criteria. For example, the scheduler 210 identifies a PU 122 having an operation queue that includes a number of pending operations that is below a threshold and / or below the number of operations in the operation queues of other PUs 122. In another example, the scheduler 210 may identify a PU 122 having an operation queue that does not include any operations that are critical to the safety or functionality of the system 100. In response to identifying a PU 122 to initiate the test process, the scheduler 210 may provide a notification of the identified PU 122 to the execution transfer component 212. As described with respect to Figure 4B As shown, the scheduler 210 may identify the PU 122H to initiate the testing process.

[0049] review Figure 3, at block 312, processing logic causes execution of the first set of operations by the first virtual processor of the first processing unit to be transferred to the second virtual processor of the second processing unit. As described above, scheduler 210 can identify PU 122H to initiate the test process, and can provide an indication of PU 122H to execution transfer component 212. In response to receiving the indication, execution transfer component 212 can cause execution of operations of thread 404 (e.g., thread 404AB) by the VPU associated with PU 122H to be transferred to be executed by another VPU associated with another PU 122. In some embodiments, execution transfer component 212 can identify another VPU based on the VPU abstracted for virtualization system 130B. For example, execution transfer component 212 can determine (e.g., based on information associated with virtualization system 130B) that virtualization system 130B includes a VPU abstracted from LPUs 402H and 402G. The execution transfer component 212 may determine that the LPU 402H is associated with the PU 122H (e.g., the PU 122 being tested), and therefore may select the LPU 402G (e.g., associated with the PU 122G that is not currently being tested) to transfer the execution of the operations associated with the thread 404AB. In some embodiments, the execution transfer component 212 may determine that the virtualization system 130B does not include any additional VPUs abstracted from the LPU 402 associated with the PU 122 that is not being tested. In such embodiments, the execution transfer component 212 may identify a VPU of another virtualization system 130A supported by the processor 120 to transfer the execution of the operations associated with the thread 404AB. In some embodiments, the execution transfer component 212 may identify the VPU of the virtualization system 130A to be transferred by determining which VPUs are abstracted from PUs that meet one or more criteria (e.g., having a number of operations in an operation queue that is less than a threshold number and / or a number of operations that is less than a number of operations in other operation queues, etc.). In other or similar embodiments, the execution transfer component 212 can identify the VPU of the virtualized system 130A to be transferred by determining the VPU included in the sequence of PUs to be tested according to the test instructions 252 and / or the test protocol. In still other or similar embodiments, the execution transfer component 212 can identify the VPU of the virtualized system 130A according to other techniques.

[0050] according to Figure 4BIn the example shown, the execution transfer component 212 may identify or otherwise select a VPU associated with LPU 402G and / or PU 122G to perform operations associated with thread 404AB while executing the test process on PU 122H. In some embodiments, the execution transfer component 212 may transfer the execution of operations associated with thread 404AB (e.g., a first set of operations) from the VPU associated with LPU 402H (e.g., a first virtual processor) to the VPU associated with LPU 402G (e.g., a second virtual processor) by sending an instruction to the virtualization manager 134. Upon receiving the instruction, the virtualization manager 134 may stop the execution of operations by the VPU of LPU 402H (e.g., by issuing a terminate instruction to the VPU). In additional or alternative embodiments, the virtualization manager 134 and / or the execution transfer component 212 may obtain the status of operations executed by the VPU and / or the status of operations in the operation queue associated with the VPU, and may store the obtained status as the execution status 254 in the memory 250 in some embodiments. The execution state 254 may indicate operations performed by the VPU of LPU 402H, current or previous results of operations performed by the VPU and / or in the operation queue, the order of operations in the operation queue of the VPU, etc. The virtualization manager 134 may update the operation queue associated with the VPU of LPU 402G based on the obtained execution state 254 to include one or more operations related to thread 404AB. In some embodiments, the virtualization manager 134 may update the operation queue associated with the VPU of LPU 402G to include the operations being performed by the VPU when the execution of operations by the VPU of LPU 402H stops. The virtualization manager 134 may additionally or alternatively update the operation queue associated with the VPU of LPU 402G to include the operations in the operation queue associated with the VPU of LPU 402G. In some embodiments, the operation queue associated with the VPU of LPU 402G may also include operations related to thread 404AA, as described herein. Virtualization manager 134 may update an operation queue associated with the VPU of LPU 402G such that the ordering of operations related to threads 404AA and 404AB corresponds to an operation priority protocol associated with processor 120 (e.g., ordering operations based on criticality, time period in which the operations are received from application 132, etc.). After transferring execution of operations related to thread 404AB from the VPU of LPU 402H to the VPU of LPU 402G, the VPU of LPU 402G may execute operations related to threads 404AB and 404AA.

[0051] review Figure 3At block 314, the processing logic initiates execution of the test process at the first processing unit, while the second virtual processor executes the first set of operations (e.g., belonging to thread 404AB) and the second set of operations (e.g., belonging to thread AA). The test execution component 214 may initiate the test process at the PU 122H by executing the test instruction 252 at the PU 122H. In some embodiments, the test achievement component 216 may obtain one or more achievements of the test process. The achievements of the test process may include one or more signals received or otherwise obtained for the PU 122H before, during, or after executing the test instruction 252. These signals may include signals emitted by the PU 122H during the execution of the test (e.g., obtaining data from the memory 124, sending or receiving data through the I / O device 126, etc.) and / or signals detected by one or more sensors for the PU 122H (e.g., temperature sensors, voltage sensors, etc.). In additional or alternative embodiments, the achievements of the test process may include values, data items, or other such outputs of one or more functions operated by the test process.

[0052] At block 316, processing logic detects that execution of the test process is completed at the first test unit. In some embodiments, the test execution component 214 and / or the test achievement component 216 can detect that execution of the test process is completed at the first test unit (e.g., PU 122H) by determining that PU 122H has successfully executed each operation of the test instruction 252. In other or similar embodiments, the test execution component 214 and / or the test achievement component 216 can detect that execution of the test process is completed by determining that PU 112H has terminated execution of the operation of the test instruction 252 and / or cannot complete execution of the operation. In some embodiments, the test achievement component 216 can generate a test result 256 indicating the result of the test process based on the test achievement described for block 314. The test result 256 can indicate whether the test process is successfully completed (e.g., each operation of the test instruction 252 is executed and the expected results of the test instruction 252 are obtained), unsuccessfully completed (e.g., each operation of the test instruction 252 is executed and the unexpected results of the test instruction 252 are obtained) and / or uncompleted (e.g., each operation of the test instruction 252 is not executed). In some embodiments, the test achievement component 216 can generate a test result 252 based on the achievement of the test process performed for each tested PU 122 (e.g., PU 122H, PU 122G, etc.). In some embodiments, the test achievement component 216 can provide the test result 256 to a device associated with a system administrator for presentation to the system administrator. In other or similar embodiments, the test achievement component 216 can provide the test result 256 to another component of the system 100 (e.g., residing at the computing device 102 or other location within the system 100). In some embodiments, the other component can perform one or more operations to resolve one or more faults indicated by the test result 256.

[0053] review Figure 3 At block 318, processing logic causes execution of the first set of operations and the second set of operations to be transferred from the second virtual processor to the first virtual processor. As described above, the execution transfer component 212 of the processing unit test engine 151 may select or otherwise identify a VPU to transfer execution of operations associated with the threads 404AA and / or 404AB when executing a test procedure for the PU 122G. The execution transfer component 212 may select and / or identify a VPU in accordance with the previously described embodiments. Figure 4C In the example shown, execution transfer component 212 may select the VPU of LPU 402H to transfer execution of operations associated with thread 404AA and thread 404AB. As described above, execution transfer component 212 may transfer execution of operations by sending instructions to virtualization manager 134, thereby transferring execution of operations to the VPU of LPU 402H.

[0054] At block 320, while the first virtual processor is executing the first set of operations and the second set of operations, the processing logic initiates execution of the test process at the second processing unit. Figure 4C As shown, the test execution component 214 can execute the test instruction 252 at the PU 122G, as described above. The VPU of the LPU 402H can perform the operations of the threads 404AA and 404AB while the test instruction 252 is being executed, as described above. According to the previously described embodiments, the test result component 216 can obtain the results of the test process executed at the PU 122G and generate the test result 256.

[0055] The processing unit test engine 151 may perform a test process on each PU 122 to be tested in the processor 120 according to the received request. As described above, in some embodiments, the processing unit test engine 151 may transfer operations performed by a VPU of the virtualization system 130 to other VPUs of the virtualization system 130. For example, Figure 4D As shown, the execution of operations related to thread 404F of virtualized system 130A can be transferred to other VPUs associated with virtualized system 130A (e.g., the VPU of LPU 402E). In other or similar embodiments, processing unit test engine 151 can transfer operations performed by a VPU of virtualized system 130 to a VPU of another virtualized system 130. In another example, Figure 4D As shown, the execution of operations related to thread 404F of virtualization system 130A can be transferred to the VPU of LPU 402G associated with virtualization system 130B. The selection of the VPU for transferring the execution of operations can be performed according to the above-mentioned embodiments and / or according to the isolation protocol associated with each virtualization environment 130 of client device 106. In some embodiments, the execution of operations transferred to the VPU during the test process can be maintained until the test process is completed. For example, the VPU of LPU 402H can be used to perform operations related to thread 404AA until the test process is completed. After the test process is completed, according to the previously described embodiments, the execution of operations related to thread 404AA can be transferred back to the VPU of LPU 402G. In other or similar embodiments, the processing unit test engine 151 can transfer the execution of operations related to thread 404AA back to the VPU of LPU 402G after the test process at PU 122G is completed (for example, but before the test process at other PUs 122 of processor 120 is completed).

[0056] In some embodiments, the virtualization system 130 of the client device 106 may be associated with an isolation protocol that prohibits VPUs of other virtualization systems 130 of the client device 106 from performing operations associated with applications running through the VPUs of the virtualization system 130. For example, the isolation protocol associated with the virtualization system 130A may prohibit the execution of operations associated with the threads 404A-404F to be executed using the VPU of the virtualization system 130A. In such embodiments, the processing unit test engine 151 may identify the VPUs of each virtualization system 130 of the client device 106 to initiate a test process, as described above, and may initiate a test process at each identified VPU (e.g., simultaneously). For example, as Figure 4E As shown, according to an embodiment of the present disclosure, the processing unit test engine 151 may simultaneously initiate testing of the PU 122H (supporting the virtualization system 130B) and the PU 122F (supporting the virtualization system 130A).

[0057] Figure 5A-5B 5 shows additional examples of test processing units of a computing system according to at least one embodiment. In some embodiments, PUs 122 of processor 120 may be organized in cores 502, such as Figure 5A For example, core 502A may include PUs 122AA-122DA, core 502B may include PUs 122AB-122DB, and / or core 502C may include PUs 122AC-122DC. In some embodiments, each PU 122 of core 502 may share a common integrated circuit. Figure 5A-5B As depicted, the processing unit test engine 151 may select the PU 122 to initiate testing of each core, and may perform a test process at each core according to the above-described techniques. In some embodiments, the processing unit test engine 151 may simultaneously perform a test process at the PU 122 of each core 502 of the processor 120, such as Figure 5B shown.

[0058] As described above, the test process for PU 122 can be performed by transferring the execution of the operations performed by the VPU supported by PU 122 to other PUs 122 (e.g., PU 122 not under test) until each PU 122 is tested. However, in additional or alternative embodiments, the test process can be performed by transferring the VPU between PUs. In an illustrative example, the processing unit test engine 151 can receive a request to initiate a test process, as described above. Based on the test instructions 252 of the test process, the scheduler 210 can identify PU 122H to initiate the test process. The execution transfer component 212 can transfer (e.g., migrate) the VPU supported by PU 122H from PU 122H to PU 122G. During the operation of executing the test process at PU 122H, PU122G can support the VPUs that execute threads 404AA and threads 404AB, as described herein. After completing execution of the test process at PU 122H, the VPU resident at PU 122G may be transferred (eg, migrated) from PU 122G to PU 122H or another PU 122 as described herein.

[0059] Fig. 6A The hardware structure(s) 615 for performing reasoning and / or training logic associated with one or more embodiments is shown. Fig. 6A and / or Figure 6B Provide details about the inference and / or training logic.

[0060] In at least one embodiment, the hardware structure(s) 615 may include, but are not limited to, code and / or data storage 601 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic may include or be coupled to code and / or data storage 601 for storing graph code or other software to control timing and / or sequence, where weights and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads weights or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 601 stores input / output data during training and / or inference using aspects of one or more embodiments and / or weight parameters during forward propagation of each layer of a neural network trained or used in conjunction with one or more embodiments. In at least one embodiment, any portion of code and / or data storage 601 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0061] In at least one embodiment, any portion of code and / or data storage 601 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 601 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 601 is internal or external to a processor, e.g., or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage space on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0062] In at least one embodiment, the hardware structure(s) 615 may include, but are not limited to, code and / or data storage 605 for storing reverse and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 605 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during back propagation of input / output data and / or weight parameters. In at least one embodiment, the training logic may include or be coupled to code and / or data storage 605 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 605 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 605 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 605 is internal or external to the processor, for example, whether it is composed of DRAM, SRAM, flash memory, or some other storage type, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0063] In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be separate storage structures. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be the same storage structure. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 601, code and / or data storage 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0064] In at least one embodiment, the hardware structure(s) 615 may include, but are not limited to, one or more arithmetic logic units (“ALUs”) 610 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or as directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 620, which is a function of input / output and / or weight parameter data stored in code and / or data storage 601 and / or code and / or data storage 605. In at least one embodiment, activations are performed in response to executing instructions or other code, linear algebra and / or matrix-based mathematics performed by ALU 610 to generate activations stored in activation storage 620, where weight values ​​stored in code and / or data storage 605 and / or in code and / or data storage 601 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 605 or code and / or data storage 601 or other on-chip or off-chip storage.

[0065] In at least one embodiment, one or more ALUs 610 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 610 may be outside a processor or other hardware logic device or circuit that uses them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 610 may be included within an execution unit of a processor, or otherwise included in a group of ALUs accessible by an execution unit of a processor, which may be within the same processor or distributed between different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed function unit, etc.). In at least one embodiment, code and / or data storage 601, code and / or data storage 605, and activation storage 620 may be on the same processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 620 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0066] In at least one embodiment, activation storage 620 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 620 may be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, activation storage 620 may be selected to be internal or external to a processor, for example, or include DRAM, SRAM, flash memory, or other storage types, depending on the storage available on-chip or off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferencing and / or training neural networks, or some combination of these factors. In at least one embodiment, Fig. 6A The hardware structure(s) 615 and / or the inference and / or training logic shown in FIG. 614 may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp (e.g., "LakeCrest") processor. In at least one embodiment, Fig. 6A The (one or more) hardware structures and / or inference and / or training logic may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware (e.g., data processing unit (“DPU”) hardware or field programmable gate array (“FPGA”)).

[0067] Figure 6B (One or more) hardware structures 615 of reasoning and / or training logic according to at least one or more embodiments are shown. In at least one embodiment, (one or more) hardware structures 615 may include, but are not limited to, hardware logic in which computing resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 6B The hardware structure(s) 615 and / or the reasoning and / or training logic in the system may be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp (e.g., "LakeCrest") processor. In at least one embodiment, Figure 6BThe hardware structure(s) 615 and / or the reasoning and / or training logic in may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as data processing unit ("DPU") hardware or field programmable gate array (FPGA). In at least one embodiment, the reasoning and / or training logic includes, but is not limited to, code and / or data storage 601 and code and / or data storage 605, which may be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 6B In at least one embodiment shown in , each of code and / or data storage 601 and code and / or data storage 605 is associated with a dedicated computing resource (e.g., computing hardware 602 and computing hardware 606). In at least one embodiment, each of computing hardware 602 and computing hardware 606 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 601 and code and / or data storage 605, respectively, and the results of performing the functions are stored in activation storage 620.

[0068] In at least one embodiment, each of the code and / or data stores 601 and 605 and the corresponding computing hardware 602 and 606 corresponds to a different layer of the neural network, such that activations from one "storage / compute pair 601 / 602" of the code and / or data store 601 and computing hardware 602 are provided as inputs to the next "storage / compute pair 605 / 606" of the code and / or data store 605 and computing hardware 606, so as to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / compute pair 601 / 602 and 605 / 606 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the inference and / or training logic after or in parallel with the storage / compute pairs 601 / 602 and 605 / 606.

[0069] Figure 7 An example data center 700 is shown in which at least one embodiment may be used. In at least one embodiment, data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0070] In at least one embodiment, Figure 7As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources ("node CRs") 716(1)-716(N), where "N" represents any positive integer. In at least one embodiment, the node CRs 716(1)-716(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), data processing units, graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NWI / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 716(1)-716(N) may be a server having one or more of the above computing resources.

[0071] In at least one embodiment, the grouped computing resources 714 may include a separate grouping of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. The separate grouping of node CRs within the grouped computing resources 714 may include computing, networks, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0072] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may include a software design infrastructure ("SDI") management entity for data center 700. In at least one embodiment, resource coordinator 107 may include hardware, software, or some combination thereof.

[0073] In at least one embodiment, Figure 7As shown, the framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, the framework layer 720 may include a framework that supports software 732 of the software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 732 or the application 742 may include a web-based service software or application, such as a service or application provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a free and open source software network application framework, such as Apache SparkTM (hereinafter referred to as "Spark") that can utilize the distributed file system 728 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 732 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 700. In at least one embodiment, the configuration manager 724 may be able to configure different layers, such as the software layer 730 and the framework layer 720 including Spark and a distributed file system 728 for supporting large-scale data processing. In at least one embodiment, the resource manager 726 can manage cluster or group computing resources mapped to or allocated to support the distributed file system 728 and the job scheduler 722. In at least one embodiment, the cluster or group computing resources can include group computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 726 can coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0074] In at least one embodiment, software 732 included in software layer 730 may include software used by at least a portion of node CRs 716(1)-716(N), grouped computing resources 714, and / or distributed file system 728 of framework layer 720. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0075] In at least one embodiment, one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0076] In at least one embodiment, any of the configuration manager 724, resource manager 726, and resource coordinator 712 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of the data center 700 from making potentially bad configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0077] In at least one embodiment, the data center 700 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to the data center 700. In at least one embodiment, by using weight parameters calculated by one or more training techniques described herein, information may be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to the data center 700.

[0078] In at least one embodiment, the data center can use a CPU, an application-specific integrated circuit (ASIC), a GPU, a DPU, an FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0079] Reasoning and / or training logic is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BProvide details about the reasoning and / or training logic. In at least one embodiment, the reasoning and / or training logic can be in the system Figure 7 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0080] Such a component can be used to generate synthetic data that simulates fault conditions during network training, which can help improve the performance of the network while limiting the amount of synthetic data to avoid overfitting.

[0081] Figure 8 800 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, the computer system 800 may include, but is not limited to, components, such as a processor 802, whose execution unit includes logic to execute algorithms for processing data. In at least one embodiment, the computer system 800 may include a processor, such as a processor available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 800 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0082] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, an edge device, an Internet of Things ("IoT") device, or any other system that can execute one or more instructions according to at least one embodiment.

[0083] In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 to perform machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the computer system 800 is a single-processor desktop or server system, but in another embodiment, the computer system 800 may be a multi-processor system. In at least one embodiment, the processor 802 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which may transmit data signals between the processor 802 and other components in the computer system 800.

[0084] In at least one embodiment, processor 802 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to processor 802. Other embodiments may also include a combination of internal and external caches, depending on the given implementation and requirements. In at least one embodiment, register file 806 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and instruction pointer registers.

[0085] In at least one embodiment, logic execution unit 808 that performs integer and floating point operations is also located in processor 802, including, but not limited to, performing integer and floating point operations. In at least one embodiment, processor 802 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, execution unit 808 may include logic for processing a packed instruction set 809. In at least one embodiment, by including a packed instruction set 809 in the instruction set of a general purpose processor, and associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in processor 802. In one or more embodiments, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may not require the transfer of smaller units of data on the processor's data bus to perform one or more operations one data element at a time.

[0086] In at least one embodiment, execution unit 808 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, memory 820 may store instructions 819 and / or data 821 represented by data signals that may be executed by processor 802.

[0087] In at least one embodiment, the system logic chip can be coupled to the processor bus 810 and the memory 820. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 816, and the processor 802 can communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 can provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 can direct data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O 822. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 can be coupled to the memory 820 via a high-bandwidth memory path 818, and the graphics / video card 812 can be coupled to the MCH 816 via an Accelerated Graphics Port ("AGP") interconnect 814.

[0088] In at least one embodiment, the computer system 800 may use a system I / O 822, which is a proprietary hub interface bus to couple the MCH 816 to an I / O controller hub ("ICH") 830. In at least one embodiment, the ICH 830 may provide direct connections to certain I / O devices through a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 820, the chipset, and the processor 802. Examples may include, but are not limited to, an audio controller 829, a firmware hub ("FlashBIOS") 828, a wireless transceiver 826, a data store 824, a traditional I / O controller 823 including a user input and keyboard interface, a serial expansion port 827 (e.g., a universal serial bus (USB) port), and a network controller 834, which may include a data processing unit in some embodiments. The data store 824 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0089] In at least one embodiment, Figure 8 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 8An exemplary system on chip (SoC) may be shown. In at least one embodiment, the devices may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 800 are interconnected using a compute express link (CXL) interconnect.

[0090] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations related to one or more embodiments. Fig. 6A and / or Figure 6B Provide details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Figure 8 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0091] Such a component can be used to generate synthetic data that simulates fault conditions during network training, which can help improve the performance of the network while limiting the amount of synthetic data to avoid overfitting.

[0092] Fig. 9 is a block diagram illustrating an electronic device 900 for utilizing a processor 910 according to at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, an edge device, an Internet of Things (IoT) device, or any other suitable electronic device.

[0093] In at least one embodiment, system 900 may include, but is not limited to, a processor 910 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 910 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig. 9 A system is shown that includes interconnected hardware devices or "chips", while in other embodiments, Fig. 9 An exemplary system on chip (SoC) may be shown. In at least one embodiment, Fig. 9 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig. 9 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0094] In at least one embodiment, Fig. 9 The display 924, the touch screen 925, the touch pad 930, the near field communication unit ("NFC") 945, the sensor hub 940, the thermal sensor 946, the fast chipset ("EC") 935, the trusted platform module ("TPM") 938, the BIOS / firmware / flash memory ("BIOS, FWFlash") 922, the DSP 960, the drive 920 (for example, a solid state disk ("SSD") or a hard disk drive ("HDD")), the wireless local area network unit ("WLAN") 950, the Bluetooth unit 952, the wireless wide area network unit ("WWAN") 956, the global positioning system (GPS) 955, the camera ("USB3.0 camera") 954 (for example, a USB3.0 camera), and / or the low power double data rate ("LPDDR") memory unit ("LPDDR3") 915 implemented in, for example, the LPDDR3 standard. Each of these components can be implemented in any suitable manner.

[0095] In at least one embodiment, other components may be communicatively coupled to the processor 910 through the components described above. In at least one embodiment, the accelerometer 941, ambient light sensor ("ALS") 942, compass 943, and gyroscope 944 may be communicatively coupled to the sensor hub 940. In at least one embodiment, the thermal sensor 939, fan 937, keyboard 936, and touchpad 930 may be communicatively coupled to the EC 935. In at least one embodiment, the speaker 963, earphone 964, and microphone ("mic") 965 may be communicatively coupled to the audio unit ("audio codec and class D amplifier") 962, which in turn may be communicatively coupled to the DSP 960. In at least one embodiment, the audio unit 964 may include, for example, but not limited to, an audio encoder / decoder ("codec") and a class D amplifier. In at least one embodiment, the SIM card ("SIM") 957 may be communicatively coupled to the WWAN unit 956. In at least one embodiment, components such as the WLAN unit 950 and the Bluetooth unit 952 and the WWAN unit 956 may be implemented as a next generation form factor (NGFF).

[0096] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Provide details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Fig. 9Systems for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0097] Such a component can be used to generate synthetic data that simulates fault conditions during network training, which can help improve the performance of the network while limiting the amount of synthetic data to avoid overfitting.

[0098] Fig.10 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 1000 includes one or more processors 1002 and one or more graphics processors 1008, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1002 or processor cores 1007. In at least one embodiment, system 1000 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile device, handheld device, edge device, or embedded device.

[0099] In at least one embodiment, the system 1000 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console for gaming and media consoles. In at least one embodiment, the system 1000 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 1000 may also include a wearable device coupled to or integrated in a wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 1000 is a television or set-top box device having one or more processors 1002 and a graphical interface generated by one or more graphics processors 1008.

[0100] In at least one embodiment, one or more processors 1002 each include one or more processor cores 1007 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1007 is configured to process a specified instruction group 1009. In at least one embodiment, the instruction group 1009 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or calculate by very long instruction words (VLIW). In at least one embodiment, the processor cores 1007 can each process different instruction groups 1009, which can include instructions that help emulate other instruction groups. In at least one embodiment, the processor core 1007 can also include other processing devices, such as a digital signal processor (DSP).

[0101] In at least one embodiment, the processor 1002 includes a cache memory 1004. In at least one embodiment, the processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared between various components of the processor 1002. In at least one embodiment, the processor 1002 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can be shared between the processor cores 1007 using known cache coherence techniques. In at least one embodiment, the processor 1002 additionally includes a register file 1006, and the processor may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 1006 may include general registers or other registers.

[0102] In at least one embodiment, one or more processors 1002 are coupled to one or more interface buses 1010 to transmit communication signals, such as address, data, or control signals, between the processor 1002 and other components in the system 1000. In at least one embodiment, the interface bus 1010 may be a processor bus in one embodiment, such as a version of a direct media interface (DMI) bus. In at least one embodiment, the interface bus 1010 is not limited to a DMI bus, and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 1002 includes an integrated memory controller 1016 and a platform controller hub 1030. In at least one embodiment, the memory controller 1016 facilitates communication between memory devices and other components of the processing system 1000, while the platform controller hub (PCH) 1030 provides connections to I / O devices through a local I / O bus.

[0103] In at least one embodiment, the memory device 1020 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or have appropriate performance to be used as a processor memory. In at least one embodiment, the memory device 1020 may be used as a system memory of the processing system 1000 to store data 1022 and instructions 1021 for use when one or more processors 1002 execute applications or processes. In at least one embodiment, the memory controller 1016 is also coupled to an optional external graphics processor 1012, which may communicate with one or more graphics processors 1008 in the processor 1002 to perform graphics and media operations. In at least one embodiment, the display device 1011 may be connected to the processor 1002. In at least one embodiment, the display device 1011 may include one or more of the internal display devices, such as in a mobile electronic device or laptop device or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 1011 may include a head mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0104] In at least one embodiment, the platform controller hub 1030 enables peripheral devices to be connected to the memory device 1020 and the processor 1002 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1046, a network controller 1034, a firmware interface 1028, a wireless transceiver 1026, a touch sensor 1025, a data storage device 1024 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1024 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1025 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1026 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or long-term evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1028 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, the network controller 1034 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1010. In at least one embodiment, the audio controller 1046 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 1000 includes an optional legacy I / O controller 1040 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system 1000. In at least one embodiment, the platform controller hub 1030 can also be connected to one or more universal serial bus (USB) controllers 1042, which connect input devices such as a keyboard and mouse 1043 combination, a camera 1044, or other USB input devices.

[0105] In at least one embodiment, instances of memory controller 1016 and platform controller hub 1030 may be integrated into a discrete external graphics processor, such as external graphics processor 1011. In at least one embodiment, platform controller hub 1030 and / or memory controller 1016 may be external to one or more processors 1002. For example, in at least one embodiment, system 1000 may include external memory controller 1016 and platform controller hub 1030, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 1002.

[0106] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetail is provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the graphics processor 1008. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs that are embodied in the graphics processor. In addition, in at least one embodiment, the inference and / or training operations described herein may use a processor other than the ALU. Fig. 6A or Figure 6B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0107] This type of component can be used to generate synthetic data that simulates fault conditions during network training, which can help improve the performance of the network while limiting the amount of synthetic data to avoid overfitting.

[0108] Fig.11 is a block diagram of a processor 1100 having one or more processor cores 1102A-1102N, an integrated memory controller 1114, and an integrated graphics processor 1108 in accordance with at least one embodiment. In at least one embodiment, the processor 1100 may include additional cores, up to and including the additional core 1102N represented by the dashed box. In at least one embodiment, each processor core 1102A-1102N includes one or more internal cache units 1104A-1104N. In at least one embodiment, each processor core may also have access to one or more shared cache units 1106.

[0109] In at least one embodiment, the internal cache units 1104A-1104N and the shared cache unit 1106 represent a cache memory hierarchy within the processor 1100. In at least one embodiment, the cache memory units 1104A-1104N may include at least one level of instruction and data cache within each processor core and one or more levels of buffers in a shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is categorized as LLC. In at least one embodiment, cache coherency logic maintains coherency between the various cache units 1106 and 1104A-1104N.

[0110] In at least one embodiment, the processor 1100 may also include a set of one or more bus controller units 1116 and a system agent core 1110. In at least one embodiment, the one or more bus controller units 1116 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 1110 provides management functions for various processor components. In at least one embodiment, the system agent core 1110 includes one or more integrated memory controllers 1114 to manage access to various external memory devices (not shown).

[0111] In at least one embodiment, one or more processor cores 1102A-1102N include support for multiple threads simultaneously. In at least one embodiment, system agent core 1110 includes components for coordinating and operating cores 1102A-1102N during multithreaded processing. In at least one embodiment, system agent core 1110 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of processor cores 1102A-1102N and graphics processor 1108.

[0112] In at least one embodiment, the processor 1100 also includes a graphics processor 1108 for performing graphics processing operations. In at least one embodiment, the graphics processor 1108 is coupled to a shared cache unit 1106 and a system agent core 1110 including one or more integrated memory controllers 1114. In at least one embodiment, the system agent core 1110 also includes a display controller 1111 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 1111 may also be a separate module coupled to the graphics processor 1108 via at least one interconnect, or may be integrated within the graphics processor 1108.

[0113] In at least one embodiment, a ring-based interconnect unit 1112 is used to couple the internal components of the processor 1100. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 1108 is coupled to the ring interconnect 1112 via an I / O link 1113.

[0114] In at least one embodiment, I / O link 1113 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and a high-performance embedded memory module 1118 (e.g., an eDRAM module). In at least one embodiment, each of processor cores 1102A-1102N and graphics processor 1108 uses embedded memory module 1118 as a shared last level cache.

[0115] In at least one embodiment, the processor cores 1102A-1102N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 1102A-1102N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 1102A-1102N execute a common instruction set, while one or more other processor cores 1102A-1102N execute a subset or a different instruction set of the common instruction set. In at least one embodiment, the processor cores 1102A-1102N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 1100 can be implemented on one or more chips or implemented as a SoC integrated circuit.

[0116] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Detail is provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the processor 1100. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in Fig.11 In addition, in at least one embodiment, the inference and / or training operations described herein may use other than Fig. 6A or Figure 6B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 1100 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0117] Such a component can be used to generate synthetic data that simulates fault conditions during network training, which can help improve the performance of the network while limiting the amount of synthetic data to avoid overfitting.

[0118] Fig.12 is an example data flow diagram of a process 1200 for generating and deploying an image processing and inference pipeline according to at least one embodiment. In at least one embodiment, the process 1200 can be deployed for use with imaging devices, processing devices, and / or other device types at one or more facilities 1202. The process 1200 can be executed within a training system 1204 and / or a deployment system 1206. In at least one embodiment, the training system 1204 can be used to perform training, deployment, and implementation of machine learning models (e.g., neural networks, object detection algorithms, computer vision algorithms, etc.) for use with the deployment system 1206. In at least one embodiment, the deployment system 1206 can be configured to offload processing and computing resources in a distributed computing environment to reduce infrastructure requirements of the facility 1202. In at least one embodiment, one or more applications in the pipeline can use or call services (e.g., reasoning, visualization, computation, artificial intelligence (AI), etc.) of the deployment system 1206 during application execution.

[0119] In at least one embodiment, some applications used in the high-level processing and reasoning pipeline may use machine learning models or other AI to perform one or more processing steps. In at least one embodiment, the machine learning model may be trained at the facility 1202 using data 1208 (e.g., imaging data) generated at the facility 1202 (and stored on one or more picture archiving and communication system (PACS) servers at the facility 1202), the machine learning model may be trained using imaging or sequencing data 1208 from another one or more facilities, or a combination thereof. In at least one embodiment, the training system 1204 may be used to provide applications, services, and / or other resources to generate a working, deployable machine learning model for the deployment system 1206.

[0120] In at least one embodiment, model registry 1224 can be supported by object storage, which can support version control and object metadata. In at least one embodiment, the model registry 1224 can be accessed from within the cloud platform through, for example, cloud storage (e.g., Fig.13 The object store is accessed through an application programming interface (API) compatible with the cloud 1326 of the system. In at least one embodiment, the machine learning models within the model registry 1224 can be uploaded, listed, modified, or deleted by developers or partners of the system interacting with the API. In at least one embodiment, the API can provide access to methods that allow users with appropriate credentials to associate a model with an application so that the model can be executed as part of the execution of a containerized instantiation of the application.

[0121] In at least one embodiment, training pipeline 1304 ( Fig.13) may include situations where the facility 1202 is training their own machine learning model, or has an existing machine learning model that needs to be optimized or updated. In at least one embodiment, imaging data 1208 generated by an imaging device, a sequencing device, and / or other type of device may be received. In at least one embodiment, once the imaging data 1208 is received, the AI-assisted annotation 1210 may be used to assist in generating annotations corresponding to the imaging data 1208 to be used as ground truth data for the machine learning model. In at least one embodiment, the AI-assisted annotation 1210 may include one or more machine learning models (e.g., a convolutional neural network (CNN)) that may be trained to generate annotations corresponding to certain types of imaging data 1208 (e.g., from certain devices). In at least one embodiment, the AI-assisted annotation 1210 may then be used directly, or may be adjusted or fine-tuned using an annotation tool to generate ground truth data. In at least one embodiment, the AI-assisted annotation 1210, the labeled clinical data 1212, or a combination thereof may be used as ground truth data for training a machine learning model. In at least one embodiment, the trained machine learning model can be referred to as an output model 1216 and can be used by the deployment system 1206 as described herein.

[0122] In at least one embodiment, training pipeline 1304 ( Fig.13) may include situations where the facility 1202 requires a machine learning model for performing one or more processing tasks for one or more applications in the deployment system 1206, but the facility 1202 may not currently have such a machine learning model (or may not have a model that is optimized, efficient, or effective for that purpose). In at least one embodiment, an existing machine learning model may be selected from the model registry 1224. In at least one embodiment, the model registry 1224 may include machine learning models that are trained to perform a variety of different reasoning tasks on imaging data. In at least one embodiment, the machine learning models in the model registry 1224 may be trained on imaging data from a different facility (e.g., a facility located remotely) rather than the facility 1202. In at least one embodiment, the machine learning model may have been trained on imaging data from one location, two locations, or any number of locations. In at least one embodiment, when training on imaging data from a specified location, the training may be performed at that location, or at least in a manner that protects the confidentiality of the imaging data or restricts the transfer of the imaging data from off-site. In at least one embodiment, once a model is trained or partially trained at one location, the machine learning model may be added to the model registry 1224. In at least one embodiment, the machine learning model can then be retrained or updated at any number of other facilities, and the retrained or updated model can be used in the model registry 1224. In at least one embodiment, the machine learning model can then be selected from the model registry 1224 (and referred to as the output model 1216) and can be deployed in the deployment system 1206 to perform one or more processing tasks for one or more applications of the deployment system.

[0123] In at least one embodiment, in training pipeline 1304 ( Fig.13), the scenario may include a facility 1202 that requires a machine learning model for performing one or more processing tasks for one or more applications in the deployment system 1206, but the facility 1202 may not currently have such a machine learning model (or may not have an optimized, efficient, or effective model). In at least one embodiment, the machine learning model selected from the model registry 1224 may not be fine-tuned or optimized for the imaging data 1208 generated at the facility 1202 due to population differences, robustness of the training data used to train the machine learning model, diversity of training data anomalies, and / or other issues with the training data. In at least one embodiment, AI-assisted annotations 1210 can be used to assist in generating annotations corresponding to the imaging data 1208 for use as ground truth data for training or updating the machine learning model. In at least one embodiment, labeled clinical data 1212 can be used as ground truth data for training the machine learning model. In at least one embodiment, retraining or updating the machine learning model can be referred to as model training 1214. In at least one embodiment, model training 1214 (e.g., AI-assisted annotation 1210, labeled clinical data 1212, or a combination thereof) can be used as ground truth data to retrain or update the machine learning model. In at least one embodiment, the trained machine learning model can be referred to as an output model 1216 and can be used by the deployment system 1206, as described herein.

[0124] In at least one embodiment, the deployment system 1206 may include software 1218, services 1220, hardware 1222, and / or other components, features, and functions. In at least one embodiment, the deployment system 1206 may include a software "stack" such that the software 1218 may be built on top of the services 1220 and may use the services 1220 to perform some or all of the processing tasks, and the services 1220 and software 1218 may be built on top of the hardware 1222 and use the hardware 1222 to perform the processing, storage, and / or other computing tasks of the deployment system 1206. In at least one embodiment, the software 1218 may include any number of different containers, each of which may perform an instantiation of an application. In at least one embodiment, each application may perform one or more processing tasks (e.g., reasoning, object detection, feature detection, segmentation, image enhancement, calibration, etc.) in a high-level processing and reasoning pipeline. In at least one embodiment, in addition to receiving and configuring imaging data for use by each container and / or containers for use by facility 1202 after processing through the pipeline, a high-level processing and reasoning pipeline can also be defined based on the selection of different containers desired or required to process imaging data 1208 (e.g., to convert the output back into a usable data type. In at least one embodiment, the combination of containers within software 1218 (e.g., which constitute a pipeline) can be referred to as a virtual instrument (as described in more detail herein), and the virtual instrument can utilize services 1220 and hardware 1222 to perform some or all of the processing tasks of an application instantiated in a container.

[0125] In at least one embodiment, the data processing pipeline can receive input data (e.g., imaging data 1208) in a specific format in response to an inference request (e.g., a request from a user of the deployment system 1206). In at least one embodiment, the input data can represent one or more images, videos, and / or other data representations generated by one or more imaging devices. In at least one embodiment, the data can be pre-processed as part of the data processing pipeline to prepare the data for processing by one or more applications. In at least one embodiment, post-processing can be performed on the output of one or more inference tasks or other processing tasks of the pipeline to prepare output data for the next application and / or prepare the output data for transmission and / or use by the user (e.g., as a response to the inference request). In at least one embodiment, the inference task can be performed by one or more machine learning models, such as a trained or deployed neural network, which can include the output model 1216 of the training system 1204.

[0126] In at least one embodiment, tasks of a data processing pipeline may be encapsulated in containers, each container representing a discrete, fully functional instantiation of an application and a virtualized computing environment capable of referencing a machine learning model. In at least one embodiment, containers or applications may be published to a private (e.g., limited access) area of ​​a container registry (described in more detail herein), and trained or deployed models may be stored in the model registry 1224 and associated with one or more applications. In at least one embodiment, an image of an application (e.g., a container image) may be available in a container registry, and once a user selects an image from a container registry for deployment in a pipeline, the image may be used to generate an instantiated container for the application for use by the user's system.

[0127] In at least one embodiment, a developer (e.g., a software developer, a clinician, a physician, etc.) can develop, publish, and store applications (e.g., as containers) for performing image processing and / or reasoning on provided data. In at least one embodiment, the development, publishing, and / or storage can be performed using a software development kit (SDK) associated with the system (e.g., to ensure that the developed applications and / or containers conform to or are compatible with the system). In at least one embodiment, the developed applications can be tested locally (e.g., at a first facility, on data from the first facility) using the SDK, which is installed as part of the system (e.g., Fig.12 The system 1200 in FIG. 1200 may support at least some of the services 1220. In at least one embodiment, because a DICOM object may contain from one to hundreds of images or other data types, and because the data varies, the developer may be responsible for managing (e.g., setting up constructs for building pre-processing into the application, etc.) the extraction and preparation of the incoming data. In at least one embodiment, once validated by the system 1200 (e.g., for accuracy), the application is made available in the container registry for selection and / or implementation by the user to perform one or more processing tasks on the data at the user's facility (e.g., a second facility).

[0128] In at least one embodiment, the developer can then share the application or container over a network for use by a system (e.g., Fig.121200). In at least one embodiment, the completed and validated application or container can be stored in the container registry, and the associated machine learning model can be stored in the model registry 1224. In at least one embodiment, the requesting entity (which provides an inference or image processing request) can browse the container registry and / or the model registry 1224 to obtain applications, containers, data sets, machine learning models, etc., select the desired combination of elements to be included in the data processing pipeline, and submit the image processing request. In at least one embodiment, the request may include input data necessary to execute the request (and patient-related data in some examples), and / or may include a selection of applications and / or machine learning models to be executed when processing the request. In at least one embodiment, the request can then be passed to one or more components (e.g., a cloud) of the deployment system 1206 to perform processing of the data processing pipeline. In at least one embodiment, the processing performed by the deployment system 1206 may include referencing elements (e.g., applications, containers, models, etc.) selected from the container registry and / or the model registry 1224. In at least one embodiment, once the results are generated by the pipeline, the results may be returned to the user for reference (eg, for viewing in a viewing application suite executing locally, on a local workstation or terminal).

[0129] In at least one embodiment, to assist in processing or executing applications or containers in the pipeline, services 1220 may be utilized. In at least one embodiment, services 1220 may include computing services, artificial intelligence (AI) services, visualization services, and / or other service types. In at least one embodiment, services 1220 may provide functionality common to one or more applications in software 1218, and thus may abstract functionality into services that may be called or utilized by applications. In at least one embodiment, the functionality provided by services 1220 may run dynamically and more efficiently, while also allowing applications to process data in parallel (e.g., using Fig.13In at least one embodiment, rather than requiring that each application that shares the same functionality provided by the service 1220 must have a corresponding instance of the service 1220, the service 1220 can be shared between and among various applications. In at least one embodiment, as a non-limiting example, the service may include an inference server or engine that can be used to perform detection or segmentation tasks. In at least one embodiment, a model training service may be included that can provide machine learning model training and / or retraining capabilities. In at least one embodiment, a data enhancement service may be further included that can provide GPU-accelerated data (e.g., DICOM, RIS, CIS, REST-compliant, RPC, raw, etc.) extraction, resizing, scaling, and / or other enhancements. In at least one embodiment, a visualization service may be used that can add image rendering effects (e.g., ray tracing, rasterization, denoising, sharpening, etc.) to add realism to two-dimensional (2D) and / or three-dimensional (3D) models. In at least one embodiment, a virtual instrument service may be included that provides beamforming, segmentation, reasoning, imaging, and / or support for other applications within the pipeline of the virtual instrument.

[0130] In at least one embodiment, where the service 1220 includes an AI service (e.g., an inference service), as part of the execution of an application, one or more machine learning models can be executed by calling (e.g., as an API call) an inference service (e.g., an inference server) to execute one or more machine learning models or processing thereof. In at least one embodiment, where another application includes one or more machine learning models for a segmentation task, the application can call the inference service to execute the machine learning model for performing one or more processing operations associated with the segmentation task. In at least one embodiment, the software 1218 implementing the high-level processing and inference pipeline, which includes a segmentation application and anomaly detection application, can be pipelined because each application can call the same inference service to perform one or more inference tasks.

[0131] In at least one embodiment, the hardware 1222 may include a GPU, a CPU, a graphics card, an AI / deep learning system (e.g., an AI supercomputer such as NVIDIA's DGX), a cloud platform, or a combination thereof. In at least one embodiment, different types of hardware 1222 may be used to provide efficient, purpose-built support for the software 1218 and services 1220 in the deployment system 1206. In at least one embodiment, the use of GPU processing may be implemented to perform local processing (e.g., at the facility 1202) within the AI / deep learning system, in the cloud system, and / or other processing components of the deployment system 1206 to improve the efficiency, accuracy, and effectiveness of image processing and generation. In at least one embodiment, as a non-limiting example, with respect to deep learning, machine learning, and / or high-performance computing, the software 1218 and / or services 1220 may be optimized for GPU processing. In at least one embodiment, at least some of the computing environments of the deployment system 1206 and / or training system 1204 may be executed in a data center, one or more supercomputers, or high-performance computer systems with GPU-optimized software (e.g., a combination of hardware and software of an NVIDIA DGX system). In at least one embodiment, as described herein, hardware 1222 may include any number of GPUs that may be called to perform data processing in parallel. In at least one embodiment, the cloud platform may also include GPU processing for GPU-optimized execution of deep learning tasks, machine learning tasks, or other computing tasks. In at least one embodiment, the cloud platform may further include DPU processing to directly transmit data received over a network and / or through a network controller or other network interface to one or more GPUs (e.g., the memory of one or more GPUs). In at least one embodiment, an AI / deep learning supercomputer and / or GPU-optimized software (e.g., as provided on NVIDIA's DGX system) may be used as a hardware abstraction and scaling platform to execute a cloud platform (e.g., NVIDIA's NGC). In at least one embodiment, a cloud platform may integrate an application container cluster system or coordination system (e.g., KUBERNETES) on multiple GPUs to achieve seamless scaling and load balancing.

[0132] Fig.13 is a system diagram of an example system 1300 for generating and deploying an imaging deployment pipeline according to at least one embodiment. In at least one embodiment, the system 1300 can be used to implement Fig.12The process 1200 and / or other processes, including high-level processing and reasoning pipelines, may be implemented in the system 1300. In at least one embodiment, the system 1300 may include a training system 1204 and a deployment system 1206. In at least one embodiment, the training system 1204 and the deployment system 1206 may be implemented using software 1218, services 1220, and / or hardware 1222, as described herein.

[0133] In at least one embodiment, system 1300 (e.g., training system 1204 and / or deployment system 1206) can be implemented in a cloud computing environment (e.g., using cloud 1326). In at least one embodiment, system 1300 can be implemented locally (with respect to a healthcare provider facility) or as a combination of cloud computing resources and local computing resources. In at least one embodiment, access to the API in cloud 1326 can be limited to authorized users by establishing security measures or protocols.

[0134] In at least one embodiment, the security protocol can include a network token that can be signed by an authentication (e.g., AuthN, AuthZ, Gluecon, etc.) service and can carry appropriate authorization. In at least one embodiment, the API of the virtual instrument (described herein) or other instances of system 1300 can be restricted to a set of public IPs that have been audited or authorized for interaction.

[0135] In at least one embodiment, the various components of system 1300 can communicate with each other using any of a variety of different network types, including but not limited to local area networks (LANs) and / or wide area networks (WANs) via wired and / or wireless communication protocols. In at least one embodiment, communications between facilities and components of system 1300 (e.g., for sending inference requests, for receiving results of inference requests, etc.) can be transmitted via one or more data buses, wireless data protocols (Wi-Fi), wired data protocols (e.g., Ethernet), etc.

[0136] In at least one embodiment, similar to the present disclosure regarding Fig.12As described, the training system 1204 can execute the training pipeline 1304. In at least one embodiment, where the deployment system 1206 will use one or more machine learning models in the deployment pipeline 1310, the training pipeline 1304 can be used to train or retrain one or more (e.g., pre-trained) models, and / or implement one or more pre-trained models 1306 (e.g., without retraining or updating). In at least one embodiment, as a result of the training pipeline 1304, an output model 1216 can be generated. In at least one embodiment, the training pipeline 1304 can include any number of processing steps, such as, but not limited to, transformation or adaptation of imaging data (or other input data). In at least one embodiment, different training pipelines 1304 can be used for different machine learning models used by the deployment system 1206. In at least one embodiment, similar to the description regarding Fig.12 The first example training pipeline 1304 described may be used for a first machine learning model, similar to the training pipeline 1304 described with respect to FIG. Fig.12 The second example training pipeline 1304 described may be used for a second machine learning model, similar to that described with respect to Fig.12 The training pipeline 1304 of the third example described may be used for a third machine learning model. In at least one embodiment, any combination of tasks within the training system 1204 may be used according to the requirements of each corresponding machine learning model. In at least one embodiment, one or more machine learning models may have been trained and ready for deployment, so the training system 1204 may not perform any processing on the machine learning model, and one or more machine learning models may be implemented by the deployment system 1206.

[0137] In at least one embodiment, the output model 1216 and / or the pre-trained model 1306 may include any type of machine learning model, depending on the implementation or embodiment. In at least one embodiment and without limitation, the machine learning model used by the system 1300 may include using linear regression, logistic regression, decision tree, support vector machine (SVM), naive Bayes, k-nearest neighbor (Knn), k-means clustering, random forest, dimensionality reduction algorithm, gradient boosting algorithm, neural network (e.g., autoencoder, convolution, recursion, perceptron, long / short term memory (LSTM), Hopfield, Boltzmann, deep belief, deconvolution, generative adversarial, liquid state machine, etc.), and / or other types of machine learning models.

[0138] In at least one embodiment, the training pipeline 1304 may include AI-assisted annotation, as described herein with respect to at least Fig. 14BIn more detail. In at least one embodiment, the labeled clinical data 1212 (e.g., traditional annotations) can be generated by any number of techniques. In at least one embodiment, in some examples, labels or other annotations can be generated in a drawing program (e.g., an annotation program), a computer secondary design (CAD) program, a labeling program, another type of application suitable for generating ground-truth annotations or labels, and / or can be hand-drawn. In at least one embodiment, the ground-truth data can be synthetically generated (e.g., generated from a computer model or rendering), truly generated (e.g., designed and generated from real-world data), machine-generated (e.g., using feature analysis and learning to extract features from the data and then generate labels), manually annotated (e.g., a labeler or annotation expert, defining the location of the label), and / or a combination thereof. In at least one embodiment, for each instance of imaging data 1208 (or other data types used by machine learning models), there can be corresponding ground-truth data generated by the training system 1204. In at least one embodiment, AI-assisted annotations can be performed as part of the deployment pipeline 1310; supplementing or replacing the AI-assisted annotations included in the training pipeline 1304. In at least one embodiment, the system 1300 may include a multi-layer platform that may include a software layer (e.g., software 1218) of a diagnostic application (or other application type) that may perform one or more medical imaging and diagnostic functions. In at least one embodiment, the system 1300 may be communicatively coupled (e.g., via an encrypted link) to a PACS server network of one or more facilities. In at least one embodiment, the system 1300 may be configured to access and reference data from a PACS server to perform operations such as training a machine learning model, deploying a machine learning model, image processing, reasoning, and / or other operations.

[0139] In at least one embodiment, the software layer may be implemented as a secure, encrypted, and / or authenticated API through which an application or container may be invoked (e.g., called) from an external environment (e.g., facility 1202). In at least one embodiment, the application may then call or execute one or more services 1220 to perform computational, AI, or visualization tasks associated with the respective application, and the software 1218 and / or services 1220 may utilize the hardware 1222 to perform processing tasks in an effective and efficient manner.

[0140] In at least one embodiment, the deployment system 1206 can execute a deployment pipeline 1310. In at least one embodiment, the deployment pipeline 1310 can include any number of applications, which can be sequential, non-sequential, or otherwise applied to imaging data (and / or other data types) - including AI-assisted annotations, generated by imaging devices, sequencing devices, genomics devices, etc., as described above. In at least one embodiment, as described herein, the deployment pipeline 1310 for an individual device can be referred to as a virtual instrument for the device (e.g., a virtual ultrasound instrument, a virtual CT scanning instrument, a virtual sequencing instrument, etc.). In at least one embodiment, there can be more than one deployment pipeline 1310 for a single device, depending on the information desired from the data generated by the device. In at least one embodiment, there can be a first deployment pipeline 1310 in the case where an abnormality is desired to be detected from an MRI machine, and there can be a second deployment pipeline 1310 in the case where image enhancement is desired from the output of the MRI machine.

[0141] In at least one embodiment, the image generation application may include a processing task that includes the use of a machine learning model. In at least one embodiment, a user may wish to use their own machine learning model, or select a machine learning model from the model registry 1224. In at least one embodiment, a user may implement their own machine learning model or select a machine learning model to be included in an application that performs a processing task. In at least one embodiment, the application may be selectable and customizable, and by defining the construction of the application, the deployment and implementation of the application for a specified user is presented as a more seamless user experience. In at least one embodiment, by leveraging other features of the system 1300 (e.g., services 1220 and hardware 1222), the deployment pipeline 1310 may be more user-friendly, provide easier integration, and produce more accurate, efficient, and timely results. One or more embodiments of the application may be implemented as or include a game, a video streaming application, a machine control application, a machine motion application, a machine driving application, a synthetic data generation application, a model training application, a perception application, an augmented reality application, a virtual reality application, a mixed reality application, a robotics application, a security and surveillance application, an autonomous or semi-autonomous machine application, a deep learning application, an environmental simulation application, a data center processing application, a conversational AI application, a light transport simulation application (e.g., ray tracing, path tracing, etc.), a collaborative content creation application for 3D assets, a digital twin system application, a cloud computing application, and / or other types of applications or services.

[0142] In at least one embodiment, the deployment system 1206 may include a user interface 1314 (e.g., a graphical user interface, a web interface, etc.) that may be used to select applications to be included in the deployment pipeline 1310, to arrange applications, to modify or change applications or their parameters or configuration, to use and interact with the deployment pipeline 1310 during setup and / or deployment, and / or to otherwise interact with the deployment system 1206. In at least one embodiment, although not shown with respect to the training system 1204, the user interface 1314 (or a different user interface) may be used to select models for use in the deployment system 1206, to select models for training or retraining in the training system 1204, and / or to otherwise interact with the training system 1204.

[0143] In at least one embodiment, in addition to application coordination system 1328, pipeline manager 1312 can also be used to manage the interaction between the application or container in which pipeline 1310 is deployed and services 1220 and / or hardware 1222. In at least one embodiment, pipeline manager 1312 can be configured to facilitate interaction from application to application, from application to service 1220, and / or from application or service to hardware 1222. In at least one embodiment, although shown as included in software 1218, this is not intended to be limiting, and in some examples (e.g., as shown in FIG. 1 ), pipeline manager 1312 can be configured to facilitate interaction from application to application, from application to service 1220, and / or from application or service to hardware 1222. Fig.11 ), the pipeline manager 1312 may be included in the service 1220. In at least one embodiment, the application orchestration system 1328 (e.g., Kubernetes, Docker, etc.) may include a container orchestration system that can group applications into containers as a logical unit for coordination, management, scaling, and deployment. In at least one embodiment, by associating applications from the deployment pipeline 1310 (e.g., rebuilding applications, splitting applications, etc.) with individual containers, each application can be executed in a self-contained environment (e.g., at the kernel level) to improve speed and efficiency.

[0144] In at least one embodiment, each application and / or container (or its image) can be developed, modified, and deployed separately (e.g., a first user or developer can develop, modify, and deploy a first application, and a second user or developer can develop, modify, and deploy a second application separate from the first user or developer), which can allow for focus and attention on the tasks of a single application and / or container without being hindered by the tasks of another application or container. In at least one embodiment, the pipeline manager 1312 and the application coordination system 1328 can facilitate communication and collaboration between different containers or applications. In at least one embodiment, as long as the expected inputs and / or outputs of each container or application are known to the system (e.g., based on the construction of the application or container), the application coordination system 1328 and / or the pipeline manager 1312 can facilitate communication and sharing of resources between and among each application or container. In at least one embodiment, since one or more applications or containers in the deployment pipeline 1310 can share the same services and resources, the application coordination system 1328 can coordinate, load balance, and determine the sharing of services or resources between and among the various applications or containers. In at least one embodiment, the scheduler can be used to track resource requirements of applications or containers, current or planned use of those resources, and resource availability. Thus, in at least one embodiment, the scheduler can allocate resources to different applications and allocate resources between and among applications, taking into account the needs and availability of the system. In some examples, the scheduler (and / or other components of the application coordination system 1328) can determine resource availability and distribution based on constraints imposed on the system (e.g., user constraints), such as quality of service (QoS), the urgency of data output (e.g., to determine whether to perform real-time processing or delayed processing), etc.

[0145] In at least one embodiment, the services 1220 utilized and shared by the applications or containers in the deployment system 1206 may include computing services 1316, AI services 1318, visualization services 1320, and / or other service types. In at least one embodiment, an application may call (e.g., execute) one or more services 1220 to perform processing operations for the application. In at least one embodiment, an application may utilize computing services 1316 to perform supercomputing or other high performance computing (HPC) tasks. In at least one embodiment, one or more computing services 1316 may be utilized to perform parallel processing (e.g., using a parallel computing platform 1330) to process data substantially simultaneously by one or more applications and / or one or more tasks of a single application. In at least one embodiment, a parallel computing platform 1330 (e.g., NVIDIA's CUDA) may implement general computing on a GPU (GPGPU) (e.g., GPU 1322). In at least one embodiment, the software layer of the parallel computing platform 1330 may provide access to a virtual instruction set and parallel computing elements of a GPU to execute computing kernels. In at least one embodiment, the parallel computing platform 1330 may include memory, and in some embodiments, memory may be shared between and among multiple containers, and / or between and among different processing tasks within a single container. In at least one embodiment, inter-process communication (IPC) calls may be generated for multiple containers and / or multiple processes within a container to enable the same data (e.g., where multiple different stages of an application or multiple applications are processing the same information) to be used for a shared memory segment from the parallel computing platform 1330. In at least one embodiment, instead of copying data and moving the data to different locations in memory (e.g., read / write operations), the same data in the same location of the memory may be used for any number of processing tasks (e.g., at the same time, at different times, etc.). In at least one embodiment, since the data is used to generate new data as a result of processing, this information of the new location of the data may be stored and shared between various applications. In at least one embodiment, the location of the data and the location of the updated or modified data may be part of the definition of how to understand the payload in the container.

[0146] In at least one embodiment, the AI ​​service 1318 may be utilized to perform a reasoning service for executing a machine learning model associated with an application (e.g., a task is to execute one or more processing tasks of an application). In at least one embodiment, the AI ​​service 1318 may utilize the AI ​​system 1324 to execute a machine learning model (e.g., a neural network such as a CNN) for segmentation, reconstruction, object detection, feature detection, classification, and / or other reasoning tasks. In at least one embodiment, the application of the deployment pipeline 1310 may use one or more output models 1216 of the self-training system 1204 and / or other models of the application to perform reasoning on the imaging data. In at least one embodiment, two or more examples of reasoning using the application coordination system 1328 (e.g., a scheduler) may be available. In at least one embodiment, the first category may include a high priority / low latency path that can achieve a higher service level agreement, such as for performing reasoning on an urgent request in an emergency, or for a radiologist during a diagnostic process. In at least one embodiment, the second category may include a standard priority path that may be used for requests that may not be urgent or where analysis can be performed at a later time. In at least one embodiment, application coordination system 1328 can allocate resources (e.g., services 1220 and / or hardware 1222) for different reasoning tasks of AI service 1318 based on priority paths.

[0147] In at least one embodiment, the shared memory may be installed to the AI ​​service 1318 in the system 1300. In at least one embodiment, the shared memory may operate as a cache (or other storage device type) and may be used to process inference requests from applications. In at least one embodiment, when an inference request is submitted, a set of API instances of the deployment system 1206 may receive the request and may select one or more instances (e.g., for best fit, for load balancing, etc.) to process the request. In at least one embodiment, in order to process the request, the request may be entered into a database, and if it is not already in the cache, the machine learning model may be located from the model registry 1224, a verification step may ensure that the appropriate machine learning model is loaded into the cache (e.g., shared storage), and / or a copy of the model may be saved to the cache. In at least one embodiment, if the application is not yet running or there are not enough instances of the application, a scheduler (e.g., a scheduler of the pipeline manager 1312) may be used to start the application referenced in the request. In at least one embodiment, if the inference server has not yet been started to execute the model, the inference server may be started. Any number of inference servers may be started for each model. In at least one embodiment, in a pull model that clusters inference servers, the model can be cached whenever load balancing is beneficial. In at least one embodiment, the inference servers can be statically loaded into the corresponding distributed servers.

[0148] In at least one embodiment, inference can be performed using an inference server running in a container. In at least one embodiment, an instance of an inference server can be associated with a model (and optionally with multiple versions of a model). In at least one embodiment, if an instance of an inference server does not exist when a request is received to perform inference on a model, a new instance can be loaded. In at least one embodiment, when the inference server is started, the model can be passed to the inference server so that the same container can be used to serve different models as long as the inference server is running as a different instance.

[0149] In at least one embodiment, during application execution, a request for reasoning for a given application may be received, and a container (e.g., an instance of a hosting reasoning server) may be loaded (if not already loaded), and a launcher may be called. In at least one embodiment, preprocessing logic in the container may load, decode, and / or perform any additional preprocessing on the incoming data (e.g., using a CPU and / or GPU and / or DPU). In at least one embodiment, once the data is ready for reasoning, the container may perform reasoning on the data as needed. In at least one embodiment, this may include a single reasoning call for one image (e.g., a hand X-ray), or may require reasoning for hundreds of images (e.g., a chest CT). In at least one embodiment, the application may summarize the results before completion, which may include, but is not limited to, a single confidence score, pixel-level segmentation, voxel-level segmentation, generating visualizations, or generating text to summarize the results. In at least one embodiment, different priorities may be assigned to different models or applications. For example, some models may have a real-time (TAT less than 1 minute) priority, while other models may have a lower priority (e.g., TAT less than 12 minutes). In at least one embodiment, model execution time may be measured from a requesting mechanism or entity and may include collaborative network traversal time as well as execution time of an inference service.

[0150] In at least one embodiment, the transmission of requests between the service 1220 and the reasoning application can be hidden behind a software development kit (SDK), and robust transmission can be provided through queues. In at least one embodiment, requests will be placed in queues through an API for individual application / tenant ID combinations, and the SDK will pull requests from the queue and provide the request to the application. In at least one embodiment, the name of the queue can be provided in the environment where the SDK will pick up the queue. In at least one embodiment, asynchronous communication through queues may be useful because it can allow any instance of the application to pick up work when it is available. Results can be transmitted back through the queue to ensure that no data is lost. In at least one embodiment, the queue can also provide the ability to split the work, because the highest priority work can enter the queue connected to most instances of the application, and the lowest priority work can enter the queue connected to a single instance, which processes the tasks in the order received. In at least one embodiment, the application can run on a GPU-accelerated instance generated in the cloud 1326, and the reasoning service can perform reasoning on the GPU.

[0151] In at least one embodiment, visualization services 1320 may be utilized to generate visualizations for viewing application and / or deployment pipeline 1310 outputs. In at least one embodiment, visualization services 1320 may utilize GPU 1322 to generate visualizations. In at least one embodiment, visualization services 1320 may implement rendering effects such as ray tracing to generate higher quality visualizations. In at least one embodiment, visualizations may include, but are not limited to, 2D image rendering, 3D volume rendering, 3D volume reconstruction, 2D tomographic slices, virtual reality displays, augmented reality displays, and the like. In at least one embodiment, a virtualized environment may be used to generate a virtual interactive display or environment (e.g., a virtual environment) for system users (e.g., doctors, nurses, radiologists, etc.) to interact with. In at least one embodiment, visualization services 1320 may include internal visualizers, movies, and / or other rendering or image processing capabilities or functions (e.g., ray tracing, rasterization, internal optics, etc.).

[0152] In at least one embodiment, hardware 1222 may include GPUs 1322, AI systems 1324, cloud 1326, and / or any other hardware for executing training system 1204 and / or deployment system 1206. In at least one embodiment, GPUs 1322 (e.g., NVIDIA's TESLA and / or QUADRO GPUs) may include any number of GPUs that may be used to perform processing tasks for any feature or functionality of compute services 1316, AI services 1318, visualization services 1320, other services, and / or software 1218. For example, for AI services 1318, GPUs 1322 may be used to perform pre-processing on imaging data (or other data types used by machine learning models), post-processing on the output of machine learning models, and / or perform inference (e.g., to execute machine learning models). In at least one embodiment, cloud 1326, AI system 1324, and / or other components of system 1300 may use GPUs 1322. In at least one embodiment, cloud 1326 may include a GPU-optimized platform for deep learning tasks. In at least one embodiment, AI system 1324 can use a GPU, and cloud 1326 (or at least part of a task being deep learning or reasoning) can be executed using one or more AI systems 1324. Likewise, while hardware 1222 is shown as discrete components, this is not intended to be limiting, and any component of hardware 1222 can be combined with or utilized by any other component of hardware 1222.

[0153] In at least one embodiment, AI system 1324 may include a purpose-built computing system (e.g., a supercomputer or HPC) configured for reasoning, deep learning, machine learning, and / or other artificial intelligence tasks. In at least one embodiment, in addition to DPUs, CPUs, RAM, storage, and / or other components, features, or functions, AI system 1324 (e.g., NVIDIA's DGX) may also include software (e.g., a software stack) that can use multiple GPUs 1322 to perform GPU-optimized tasks. In at least one embodiment, one or more AI systems 1324 may be implemented in a cloud 1326 (e.g., in a data center) to perform some or all of the AI-based processing tasks of system 1300.

[0154] In at least one embodiment, cloud 1326 may include a GPU-accelerated infrastructure (e.g., NVIDIA's NGC) that may provide a GPU-optimized platform for executing processing tasks of system 1300. In at least one embodiment, cloud 1326 may include an AI system 1324 for executing one or more AI-based tasks of system 1300 (e.g., as a hardware abstraction and scaling platform). In at least one embodiment, cloud 1326 may be integrated with an application coordination system 1328 that utilizes multiple GPUs to enable seamless scaling and load balancing between and among applications and services 1220. In at least one embodiment, cloud 1326 may be responsible for executing at least some services 1220 of system 1300, including compute services 1316, AI services 1318, and / or visualization services 1320, as described herein. In at least one embodiment, cloud 1326 can perform inference of size batches (e.g., executing NVIDIA's TENSORRT), provide accelerated parallel computing APIs and platforms 1330 (e.g., NVIDIA's CUDA), execute application coordination system 1328 (e.g., Kubernetes), provide graphics rendering APIs and platforms (e.g., for ray tracing, 2D graphics, 3D graphics, and / or other rendering techniques to produce higher quality movie effects), and / or can provide other functionality for system 1300.

[0155] Fig.14A A data flow diagram of a process 1400 for training, retraining, or updating a machine learning model according to at least one embodiment is shown. In at least one embodiment, a non-limiting example may be used. Fig.13The process 1400 may be performed by the system 1300 of the deployment pipeline 1310. In at least one embodiment, the process 1400 may utilize the services 1220 and / or hardware 1222 of the system 1300, as described herein. In at least one embodiment, the refined model 1412 generated by the process 1400 may be executed by the deployment system 1206 for one or more containerized applications in the deployment pipeline 1310.

[0156] In at least one embodiment, model training 1214 may include retraining or updating an initial model 1404 (e.g., a pre-trained model) using new training data (e.g., new input data (such as customer dataset 1406), and / or new ground truth data associated with the input data). In at least one embodiment, to retrain or update the initial model 1404, the output or loss layers of the initial model 1404 may be reset or deleted, and / or replaced with updated or new output or loss layers. In at least one embodiment, the initial model 1404 may have previously fine-tuned parameters (e.g., weights and / or biases) retained from previous training, so training or retraining 1214 may not take as long or require as much processing as training the model from scratch. In at least one embodiment, during model training 1214, by resetting or replacing the output or loss layers of the initial model 1404, the model may be trained on a new customer dataset 1406 (e.g., Fig.12 When generating predictions on image data 1208), the parameters for the new dataset can be updated and re-adjusted based on the loss calculation associated with the accuracy of the output or loss layer.

[0157] In at least one embodiment, the pre-trained model 1306 may be stored in a data store or registry (e.g., Fig.12Model registry 1224 of the cloud 1326). In at least one embodiment, the pre-trained model 1306 may have been at least partially trained at one or more facilities other than the facility performing process 1400. In at least one embodiment, in order to protect the privacy and rights of patients, subjects, or customers of different facilities, the pre-trained model 1306 may have been trained locally using locally generated customer or patient data. In at least one embodiment, the cloud 1326 and / or other hardware 1222 may be used to train the pre-trained model 1306, but confidential, privacy-protected patient data may not be transmitted to, used by, or accessed by any component of the cloud 1326 (or other non-local hardware). In at least one embodiment, if the pre-trained model 1306 is trained using patient data from more than one facility, the pre-trained model 1306 may have been trained separately for each facility before training on patient or customer data from another facility. In at least one embodiment, for example where customer or patient data has been issued privacy issues (e.g., by being relinquished, used for experimental purposes, etc.), or where the customer or patient data is included in a public dataset, customer or patient data from any number of facilities can be used to train pre-trained model 1306 locally and / or externally, such as in a data center or other cloud computing infrastructure.

[0158] In at least one embodiment, when selecting an application to use in the deployment pipeline 1310, the user may also select a machine learning model for the specified application. In at least one embodiment, the user may not have a model to use, so the user may select a pre-trained model 1306 to use with the application. In at least one embodiment, the pre-trained model 1306 may not be optimized to generate accurate results on the customer data set 1406 of the user facility (e.g., based on patient diversity, demographics, types of medical imaging equipment used, etc.). In at least one embodiment, the pre-trained model 1306 may be updated, retrained, and / or fine-tuned for use at various facilities before deploying the pre-trained model 1306 into the deployment pipeline 1310 for use with one or more applications.

[0159] In at least one embodiment, a user may select a pre-trained model 1306 to be updated, retrained, and / or fine-tuned, and the pre-trained model 1306 may be referred to as the initial model 1404 for the training system 1204 in process 1400. In at least one embodiment, a customer data set 1406 (e.g., imaging data, genomic data, sequencing data, or other data type generated by equipment at a facility) may be used to perform model training 1214 (which may include, but is not limited to, transfer learning) on ​​the initial model 1404 to generate a refined model 1412. In at least one embodiment, ground truth data corresponding to the customer data set 1406 may be generated by the training system 1204. In at least one embodiment, the ground truth data may be generated, at least in part, at the facility by a clinician, scientist, physician, practitioner (e.g., Fig.12 Labeled clinical data 1212).

[0160] In at least one embodiment, AI-assisted annotation 1210 can be used in some examples to generate ground truth data. In at least one embodiment, AI-assisted annotation 1210 (e.g., implemented using an AI-assisted annotation SDK) can utilize a machine learning model (e.g., a neural network) to generate ground truth data for recommendations or predictions for a customer data set. In at least one embodiment, a user 1410 can use the annotation tool within a user interface (graphical user interface (GUI)) on a computing device 1408.

[0161] In at least one embodiment, user 1410 can interact with the GUI via computing device 1408 to edit or fine-tune annotations or automatic annotations. In at least one embodiment, a polygon editing feature can be used to move vertices of a polygon to a more precise or fine-tuned position.

[0162] In at least one embodiment, once the customer dataset 1406 has associated ground truth data, the ground truth data (e.g., from AI-assisted annotations, manual labeling, etc.) can be used during model training 1214 to generate a refined model 1412. In at least one embodiment, the customer dataset 1406 can be applied to the initial model 1404 any number of times, and the ground truth data can be used to update the parameters of the initial model 1404 until an acceptable level of accuracy is achieved for the refined model 1412. In at least one embodiment, once the refined model 1412 is generated, the refined model 1412 can be deployed within one or more deployment pipelines 1310 at a facility for use in performing one or more processing tasks with respect to medical imaging data.

[0163] In at least one embodiment, the refined model 1412 can be uploaded to the pre-trained models 1306 in the model registry 1224 for selection by another facility. In at least one embodiment, his process can be completed at any number of facilities, so that the refined model 1412 can be further refined any number of times on new data sets to generate a more general model.

[0164] Fig. 14B is an example illustration of a client-server architecture 1432 for augmenting an annotation tool with a pre-trained annotation model according to at least one embodiment. In at least one embodiment, an AI-assisted annotation tool 1436 can be instantiated based on the client-server architecture 1432. In at least one embodiment, the annotation tool 1436 in an imaging application can assist a radiographer, for example, in identifying organs and anomalies. In at least one embodiment, the imaging application can include a software tool that, as a non-limiting example, assists a user 1410 in identifying several extreme points on a specified organ of interest in an original image 1434 (e.g., in a 3D MRI or CT scan) and receiving automatic annotation results for all 2D slices of the specified organ. In at least one embodiment, the results can be stored in a data store as training data 1438 and used as, for example, but not limited to, ground truth data for training. In at least one embodiment, when the computing device 1408 sends extreme points for AI-assisted annotation 1210, for example, a deep learning model can receive the data as input and return an inference result for segmenting an organ or anomaly. In at least one embodiment, the pre-instantiated annotation tool (e.g., Fig. 14B The AI-assisted annotation tool 1436B in the example embodiment may be enhanced by making an API call (e.g., API call 1444) to a server (such as an annotation assistant server 1440), which may include a set of pre-trained models 1442 stored in, for example, an annotation model registry. In at least one embodiment, the annotation model registry may store pre-trained models 1442 (e.g., machine learning models, such as deep learning models) that are pre-trained to perform AI-assisted annotation on specified organs or abnormalities. In at least one embodiment, these models may be further updated using a training pipeline 1304. In at least one embodiment, the pre-installed annotation tools may be improved over time as newly labeled clinical data 1212 is added.

[0165] Such a component can be used to generate synthetic data that simulates fault conditions during network training, which can help improve the performance of the network while limiting the amount of synthetic data to avoid overfitting.

[0166] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described in detail above. However, it should be understood that there is no intention to limit the disclosure to one or more specified forms disclosed, but on the contrary, it is intended to cover all modifications, alternative constructions, and equivalents that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0167] Unless otherwise noted or clearly contradictory to the context, in the context of describing the disclosed embodiments (particularly in the context of the appended claims), the use of the terms "one" and "an" and "the" and similar references should be interpreted as covering the singular and plural, rather than as a definition of the term. Unless otherwise noted, the terms "include", "have", "include" and "contain" should be interpreted as open terms (meaning "including but not limited to") unless otherwise noted. "Connected" (when unmodified and referring to a physical connection) should be interpreted as partially or completely included, attached to or connected together, even if there is some intervention. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, respectively, and each individual value is incorporated into the specification as if it were individually narrated herein. In at least one embodiment, unless otherwise noted or contradictory to the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set including one or more members. Furthermore, unless otherwise noted or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0168] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B and C" are understood in context to be generally used to refer to an item, clause, or the like, which may be A or B or C, or any non-empty subset of the set of A and B and C. For example, in the illustrative example of a set having three members, the conjunction phrases "at least one of A, B, and C" and "at least one of A, B and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunction language is not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to a plural state (e.g., "plurality of items" means a plurality of items). In at least one embodiment, the number of items in the plurality of items is at least two, but may be more if expressly indicated or indicated by context. Additionally, unless otherwise specified or clear from context, the phrase "based on" means "based at least in part on" rather than "based solely on."

[0169] Unless otherwise indicated herein or clearly contradictory to the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are jointly executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions), but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) on which executable instructions are stored, which, when executed by one or more processors of a computer system (i.e., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all of the code, but rather the plurality of non-transitory computer-readable storage media stores all of the code together. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors.

[0170] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the implementation of the operations. In addition, the computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system that includes multiple devices operating in different ways, so that the distributed computer system performs the operations described herein, and so that a single device does not perform all operations.

[0171] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating that any non-claimed element is essential to practicing the disclosure.

[0172] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0173] In the specification and claims, the terms "coupled" and "connected," as well as their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Instead, in a given example, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0174] Unless explicitly stated otherwise, it is understood that throughout the specification, terms such as "processing", "computing", "calculating", "determining", etc. refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electronic) in the registers and / or memories of the computing system into other data similarly represented as physical quantities in the memories, registers or other such information storage, transmission or display devices of the computing system.

[0175] In a similar manner, the term "processor" may refer to any device or part of a memory that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Similarly, each process may refer to multiple processes to execute instructions sequentially or in parallel, continuously or intermittently. In at least one embodiment, the terms "system" and "method" may be used interchangeably herein, as long as a system may embody one or more methods, and a method may be considered a system.

[0176] In this document, reference may be made to obtaining, acquiring, receiving or inputting analog or digital data into a subsystem, a computer system or a computer-implemented machine. In at least one embodiment, the process of obtaining, acquiring, receiving or inputting analog and digital data may be achieved in a variety of ways, such as by receiving data as a parameter of a function call or a call to an application programming interface. In at least one embodiment, the process of obtaining, acquiring, receiving or inputting analog or digital data may be accomplished by transmitting data via a serial or parallel interface. In at least one embodiment, the process of obtaining, acquiring, receiving or inputting analog or digital data may be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. In at least one embodiment, reference may also be made to providing, outputting, transmitting, sending or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending or presenting analog or digital data may be accomplished by transmitting data as an input or output parameter of a function call, an application programming interface or an inter-process communication mechanism.

[0177] Although the description herein sets forth example embodiments of the described technology, other architectures may be used to implement the described functionality and are intended to fall within the scope of the present disclosure. In addition, although specific responsibilities may be defined above for descriptive purposes, the various functions and responsibilities may be allocated and divided in different ways depending on the circumstances.

[0178] In addition, although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

1. A method comprising: receiving a request to initiate a test process for each of a plurality of processing units, wherein a first processing unit of the plurality of processing units performs a first set of operations via a first virtual processor and a second processing unit of the plurality of processing units performs a second set of operations via a second virtual processor; causing execution of the first set of operations by the first virtual processor to be transferred from the first processing unit to the second processing unit; initiating execution of the test process at the first processing unit while the first set of operations is executed at the second processing unit by the first virtual processor and the second set of operations is executed by the second virtual processor; in response to detecting completion of execution of the test procedure at the first processing unit, causing execution of the first set of operations by the first virtual processor and execution of the second set of operations by the second virtual processor to be transferred from the second processing unit to the first processing unit; as well as Execution of the test process is initiated at the second processing unit while the first processing unit executes the first set of operations through the first virtual processor and executes the second set of operations through the second virtual processor.

2. The method of claim 1 , wherein a third processing unit of the plurality of processing units hosts a third virtual processor that performs a third set of operations, and wherein the method further comprises: causing execution of the third set of operations to be transferred from the third virtual processor to the second virtual processor in response to detecting completion of execution of the test procedure at the second processing unit; as well as Execution of the test process is initiated at the third processing unit while the first virtual processor executes at least one of the first set of operations or the second set of operations and the second virtual processor executes the third set of operations.

3. The method according to claim 1, wherein the testing process is a fault detection process, and wherein the method further comprises: determining, based on execution of the test procedure of at least one processing unit among the plurality of processing units, whether a failure has occurred at the at least one processing unit; as well as In response to determining that a fault has occurred at the at least one processing unit, an alarm is sent indicating the fault. 4 . The method of claim 1 , wherein the first processing unit and the second processing unit are components of a first processor core of a system that includes the plurality of processing units.

5. The method of claim 4, wherein the plurality of processing units further comprises a fourth processing unit and a fifth processing unit, the fourth processing unit and the fifth processing unit being components of a second processor core of the system, wherein the fourth processing unit performs a fourth set of operations associated with a fourth virtual processor and the fifth processing unit performs a fifth set of operations associated with a fifth virtual processor, and wherein the method further comprises: causing execution of the fourth set of operations to be transferred from the fourth virtual processor to the fifth virtual processor in response to the request to initiate the test process; as well as While the test process is being executed simultaneously using at least one of the first processing unit or the second processing unit of the first processor core, execution of the test process is initiated at the fourth processing unit.

6. The method of claim 1, wherein the first virtual processor and the second virtual processor are associated with a virtual computing system executing on the plurality of processing units.

7. The method of claim 6, wherein the virtual computing system comprises at least one of a virtual machine or a container.

8. The method of claim 1 , wherein causing execution of the first set of operations to be transferred from the first virtual processor to the second virtual processor comprises: sending a first instruction to a virtual system manager associated with the first virtual processor and the second virtual processor to transfer execution of the first set of operations from the first virtual processor to the second virtual processor, and Wherein transferring execution of the first set of operations and the second set of operations from the second virtual processor to the first virtual processor comprises: sending a second instruction to the virtual system manager to transfer execution of the first set of operations and the second set of operations from the first virtual processor to the second virtual processor.

9. The method of claim 1, wherein the plurality of processing units are included in at least one of the following: control systems for autonomous or semi-autonomous machines; Perception systems for autonomous or semi-autonomous machines; A system for performing simulation operations; Systems for performing digital twin operations; A system for performing light transport simulations; A system for performing collaborative content creation of 3D assets; Systems for performing deep learning operations; Systems implemented using edge devices; Systems implemented using robots; Systems for performing conversational AI operations; Systems for generating synthetic data; a system for presenting at least one of virtual reality content, augmented reality content, or mixed reality content; A system implemented at least in part in a data center; or A system implemented at least in part using cloud computing resources.

10. A system comprising: A processing device, the processing device is used to perform operations, the operations comprising: receiving a request to initiate a test process for each of a plurality of processing units, wherein a first processing unit of the plurality of processing units includes a first virtual processor that performs a first set of operations and a second processing unit of the plurality of processing units includes a second virtual processor that performs a second set of operations; causing execution of the first set of operations to be transferred from the first virtual processor to the second virtual processor; initiating execution of the test process at the first processing unit when the second virtual processor running on the second processing unit executes the first set of operations and the second set of operations; In response to detecting completion of execution of the test procedure at the first processing unit, transferring execution of the first set of operations and the second set of operations from the second virtual processor to the first virtual processor; and Execution of the test process is initiated at the second processing unit while the first virtual processor running on the first processing unit executes the first set of operations and the second set of operations.

11. The system of claim 10, wherein a third processing unit of the plurality of processing units hosts a third virtual processor that performs a third set of operations, and wherein the operations further comprise: causing execution of the third set of operations to be transferred from the third virtual processor to the second virtual processor in response to detecting completion of execution of the test procedure at the second processing unit; as well as Execution of the test process is initiated at the third processing unit while the first virtual processor executes at least one of the first set of operations or the second set of operations and the second virtual processor executes the third set of operations.

12. The system of claim 10, wherein the testing process is a fault detection process, and wherein the operations further comprise: determining, based on execution of a test process for at least one of the plurality of processing units, whether a failure has occurred at the at least one processing unit; as well as In response to determining that a fault has occurred at the at least one processing unit, an alarm is sent indicating the fault.

13. The system of claim 10, wherein the first processing unit and the second processing unit are components of a first processor core of a system including the plurality of processing units.

14. The system of claim 13, wherein the plurality of processing units further comprises a fourth processing unit and a fifth processing unit, the fourth processing unit and the fifth processing unit being components of a second processor core of the system, wherein the fourth processing unit performs a fourth set of operations associated with a fourth virtual processor and the fifth processing unit performs a fifth set of operations associated with a fifth virtual processor, and wherein the operations further comprise: causing execution of the fourth set of operations to be transferred from the fourth virtual processor to the fifth virtual processor in response to the request to initiate the test process; as well as While the test process is being executed simultaneously using at least one of the first processing unit or the second processing unit of the first processor core, execution of the test process is initiated at the fourth processing unit.

15. The system of claim 10, wherein the first virtual processor and the second virtual processor are associated with a virtual computing system running on the plurality of processing units.

16. The system of claim 15, wherein the virtual computing system comprises at least one of a virtual machine or a container.

17. A processor, comprising: Multiple processing units; as well as A controller, the controller being used to: receiving a request to initiate a test process for each of a plurality of processing units, wherein a first processing unit of the plurality of processing units includes a first virtual processor that performs a first set of operations and a second processing unit of the plurality of processing units includes a second virtual processor that performs a second set of operations; causing execution of the first set of operations to be transferred from the first virtual processor to the second virtual processor; initiating execution of the test process at the first processing unit when the second virtual processor running on the second processing unit executes the first set of operations and the second set of operations; in response to detecting completion of execution of the test procedure at the first processing unit, causing execution of the first set of operations and the second set of operations to be transferred from the second virtual processor to the first virtual processor; as well as Execution of the test process is initiated at the second processing unit while the first virtual processor running on the first processing unit executes the first set of operations and the second set of operations.

18. The processor of claim 17, wherein a third processing unit of the plurality of processing units hosts a third virtual processor that performs a third set of operations, and wherein the controller is further configured to: In response to detecting completion of execution of the test procedure at the second processing unit, causing execution of the third set of operations to be transferred from the third virtual processor to the second virtual processor; and Execution of the test process is initiated at the third processing unit while the first virtual processor executes at least one of the first set of operations or the second set of operations and the second virtual processor executes the third set of operations.

19. The processor of claim 18, wherein the testing process is a fault detection process, and wherein the controller is further configured to: determining whether a failure has occurred at at least one of the plurality of processing units based on execution of a test process of the at least one processing unit; and In response to determining that a fault has occurred at the at least one processing unit, an alarm is sent indicating the fault.

20. The processor of claim 18, wherein the first processing unit and the second processing unit are components of a first processor core of a system including the plurality of processing units.

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