Data processing method and device in sparse matrix multiplication, equipment and storage medium
By dynamically selecting the accumulator type based on the number of non-zero elements of the sparse matrix, the problem of low performance in sparse matrix multiplication is solved, and a significant improvement in computing performance is achieved.
Patent Information
- Application Number
- CN202411830127.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-04-22
AI Technical Summary
In the sparse matrix multiplication, the prior art cannot adapt to the variability of the sparse matrix data distribution, resulting in poor performance.
The type of the accumulator is dynamically determined based on the number of non-zero elements in the first sparse matrix processing unit, including a direct index accumulator, a hash accumulator and a dense accumulator, and performs corresponding accumulative sum and storage operations.
By adaptively selecting the appropriate accumulator type, the calculation performance of sparse matrix multiplication is significantly improved, and the accumulator performance bottleneck caused by the diversity of sparse matrix data distribution is solved.
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Figure CN119862357A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method, device, equipment and storage medium in sparse matrix multiplication. Background Art
[0002] General Sparse Matrix-Matrix Multiplication (SpGEMM) is a computational process of multiplying two sparse matrices (A and B) to obtain a sparse matrix (C). Due to the irregularity of the distribution of non-zero elements in sparse matrices, the distribution of non-zero elements in each row of the output matrix can vary between a single element, a small dense area, or widely distributed elements in the row. In the related art, a single fixed accumulator is used to process the intermediate data in the coefficient matrix multiplication process, which has the following disadvantages: using a sparse accumulator for processing may generate more hash conflicts for relatively dense rows, thereby reducing performance. Using a dense accumulator for processing consumes a lot of space. Summary of the invention
[0003] In order to overcome the problems existing in the related art, the present disclosure provides a data processing method, device, equipment and storage medium in sparse matrix multiplication to solve the problem of poor performance in the related art due to the use of a single accumulator that cannot adapt to the variable data distribution in the sparse matrix.
[0004] According to a first aspect of an embodiment of the present disclosure, a data processing method in sparse matrix multiplication is provided, comprising:
[0005] determining the number of non-zero elements in a processing unit of the first sparse matrix;
[0006] Determining the type of the accumulator according to the number of non-zero elements;
[0007] The types of the accumulators include: direct index accumulator, hash accumulator and dense accumulator;
[0008] Using the accumulator of the type described above, cumulatively sum the product of the number of non-zero elements in the processing unit and the number of non-zero elements in the corresponding processing unit in the second sparse matrix to obtain a sum value;
[0009] storing the sum value in an intermediate process;
[0010] After the sum value is stored in an intermediate process, the sum value is input into a third sparse matrix as a value in the third sparse matrix.
[0011] In one implementation, determining the type of the accumulator according to the number of non-zero elements includes:
[0012] When the number of non-zero elements in the processing unit of the sparse matrix is less than a predetermined threshold, the type of the accumulator is determined to be a direct index accumulator.
[0013] In one implementation, when it is determined that the type of the accumulator is a direct index accumulator, the method further includes:
[0014] In the case of the symbol calculation stage, the number of elements corresponding to the processing unit in the second sparse matrix is the number of non-zero elements corresponding to the processing unit in the third sparse matrix.
[0015] In one implementation, determining the type of the accumulator according to the number of non-zero elements includes:
[0016] When the proportion of the number of non-zero elements in the processing unit of the sparse matrix is less than or equal to the first proportion threshold, it is determined that the type of the accumulator is a hash accumulator.
[0017] In one implementation, when it is determined that the type of the accumulator is a hash accumulator, the intermediate storage of the sum value includes:
[0018] Determining a hash value according to the index of the processing unit and the index of the corresponding processing unit in the second sparse matrix;
[0019] A position in a hash table is determined according to the hash value, and the sum value is stored at the position in the hash table.
[0020] In one implementation, determining the type of the accumulator according to the number of non-zero elements includes:
[0021] When the proportion of the number of non-zero elements in the processing unit of the sparse matrix is greater than the first proportion threshold, it is determined that the type of the accumulator is a dense accumulator.
[0022] In one implementation, when it is determined that the type of the accumulator is a dense accumulator, the intermediate process storage of the sum value includes: inputting the sum value into a preset array space.
[0023] In a second aspect, the present application further proposes a data processing device in sparse matrix multiplication, comprising:
[0024] A first determination module, used to determine the number of non-zero elements in a processing unit of a first sparse matrix;
[0025] A second determination module, configured to determine a type of an accumulator according to the number of non-zero elements;
[0026] The types of the accumulators include: direct index accumulator, hash accumulator and dense accumulator;
[0027] A processing module, configured to use an accumulator of the type described above to accumulate and sum the product of the number of non-zero elements in the processing unit and the number of non-zero elements in the corresponding processing unit in the second sparse matrix to obtain a sum value;
[0028] A first storage module, used for storing the sum value in an intermediate process;
[0029] The second storage module is used to input the sum value into a third sparse matrix as a value in the third sparse matrix after intermediate process storage of the sum value.
[0030] In some embodiments, the second determination module is further used to determine that the type of the accumulator is a direct index accumulator when the number of non-zero elements in the processing unit of the sparse matrix is less than a predetermined threshold.
[0031] In some embodiments, a third determination module is also included, which is used when the second determination module determines that the type of the accumulator is a direct index accumulator. In the case of the symbol calculation stage, the number of elements of the corresponding processing units in the above-mentioned second sparse matrix is the number of non-zero elements of the corresponding processing units in the third sparse matrix.
[0032] In some embodiments, the second determination module is further used to determine that the type of the accumulator is a hash accumulator when the proportion of the number of non-zero elements in the processing unit of the sparse matrix is less than or equal to the first proportion threshold.
[0033] In some embodiments, the first storage module is further used to determine the hash value according to the index of the processing unit and the index of the corresponding processing unit in the second sparse matrix when the second determination module determines that the type of the accumulator is a hash accumulator;
[0034] The position in the hash table is determined according to the hash value, and the sum value is stored at the position in the hash table.
[0035] In some embodiments, the second determination module is further used to determine that the type of the accumulator is a dense accumulator when the proportion of the number of non-zero elements in the processing unit of the sparse matrix is greater than the first proportion threshold.
[0036] In some embodiments, the first storage module is further used to input the above sum value into a preset array space when the second determination module determines that the type of the accumulator is a dense accumulator.
[0037] In a third aspect, the present application also proposes an electronic device comprising at least one processor and at least one memory; the memory is used to store one or more program instructions; the processor is used to run one or more program instructions to execute the data processing method in the sparse matrix multiplication described in any one of the above items.
[0038] According to a fourth aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium contains one or more program instructions, and the one or more program instructions are used to execute the data processing method in the sparse matrix multiplication described in any one of the above items.
[0039] The technical solution disclosed herein may have the following beneficial effects:
[0040] The present application determines the number of non-zero elements in the processing unit of the first sparse matrix; determines the type of accumulator according to the number of non-zero elements, and performs subsequent data processing and storage steps, which will significantly improve the computing performance of SpGEMM. It solves the accumulator performance bottleneck problem caused by the sparse diversity of sparse matrices. It determines the appropriate accumulator for each processing unit in a lightweight and dynamic manner, solving the problem of unsatisfactory performance caused by unreasonable accumulator design.
[0041] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0043] Figure 1 is a flow chart of a data processing method in sparse matrix multiplication according to an exemplary embodiment;
[0044] Figure 2 is a block diagram of a data processing device in sparse matrix multiplication according to an exemplary embodiment;
[0045] Figure 3 It is a block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION
[0046] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.
[0047] The terms "first" or "second" used in this specification to refer to numbers or ordinals are used for descriptive purposes only and should not be understood as explicitly or implicitly indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this specification, the meaning of "plurality" is at least two, such as two, three or more, etc., unless otherwise clearly and specifically defined.
[0048] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0049] This application proposes a data processing method in sparse matrix multiplication, see the attached Figure 1 , the method may include the following steps:
[0050] In step S102, the number of non-zero elements in the processing unit of the first sparse matrix is determined.
[0051] In this embodiment, the processing unit may be a row or a column, or may be a combination of any multiple rows or multiple columns in the first sparse matrix.
[0052] In step S104, the type of the accumulator is determined according to the number of non-zero elements.
[0053] The types of accumulators mentioned above include: direct index accumulator, hash accumulator, and dense accumulator.
[0054] In step S106, the above-mentioned type of accumulator is used to accumulate and sum the product of the number of non-zero elements in the above-mentioned processing unit and the non-zero elements in the corresponding processing unit in the second sparse matrix to obtain a sum value.
[0055] In this embodiment, the accumulator can accumulate and sum the products of multiple non-zero elements of the input. For example, each element in the first row of the first sparse matrix is multiplied with each corresponding element in the first column of the second sparse matrix. For example, the first column element A1 in the first row of the first sparse matrix corresponds to the first element B1 in the first column of the second sparse matrix, and the product of element A1 and element B1 is calculated. The second element A2 in the first row of the first sparse matrix corresponds to the second element B2 in the first column of the second sparse matrix, and the product of element A2 and element B2 is calculated. And so on, the Nth element A in the first row of the first sparse matrix N , corresponding to the second element in the first column of the second sparse matrix B N , calculate element A N With element B N The accumulator performs the sum operation, Wherein, N is an integer greater than or equal to 1.
[0056] In step S108, the above sum is stored in an intermediate process.
[0057] In this embodiment, the above sum value C 11 Perform intermediate process storage. Store in a shared space.
[0058] In step S110, the sum value is input into the third sparse matrix as the value in the third sparse matrix.
[0059] In this embodiment, the above sum C 11 Input into the first row and first column of the third coefficient matrix.
[0060] When the i-th row of the first coefficient matrix is element-wise multiplied by the j-th column of the second sparse matrix, the sum is accumulated and stored at the i-th row and j-th column of the third coefficient matrix.
[0061] The above technical solution of the present invention determines the type of accumulator according to the number of non-zero elements. The types of accumulators include: direct index accumulator, hash accumulator and dense accumulator. Using the above type of accumulator for processing, this adaptive selection mechanism will significantly improve the computing performance of SpGEMM. Solve the accumulator performance bottleneck problem caused by the sparse diversity of sparse matrices. In view of the sparse diversity of sparse matrices, a hybrid accumulator is designed, including three types of accumulators including direct index, hash and dense accumulators, which can meet a variety of sparse characteristics and can dynamically determine the most suitable accumulator for each processing unit in a lightweight manner, thereby solving the problem of unsatisfactory performance of SpGEMM due to unreasonable accumulator design.
[0062] In one implementation, in step S104, determining the type of the accumulator according to the number of non-zero elements may further include the following steps:
[0063] When the number of non-zero elements in the processing unit of the sparse matrix is less than a predetermined threshold, the type of the accumulator is determined to be a direct index accumulator.
[0064] In this embodiment, the above-mentioned predetermined threshold can be flexibly set, for example, set to 2. When the predetermined threshold is 2, when the number of non-zero elements in the processing unit of the above-mentioned sparse matrix is 1, the type of the accumulator is determined to be a direct index accumulator. The direct index accumulator is suitable for use in the case where the number of non-zero elements in the sparse matrix is relatively small.
[0065] In some embodiments, when it is determined that the type of the accumulator is a direct index accumulator, the above method may further include the following steps:
[0066] In the case of the symbol calculation stage, the number of elements corresponding to the processing unit in the second sparse matrix is the number of non-zero elements corresponding to the processing unit in the third sparse matrix.
[0067] In this embodiment, when a direct index accumulator is used, for example, if there is only one non-zero element in this row of the first sparse matrix A, the column subscript of this non-zero element is directly used as an index to determine the corresponding row in the second sparse matrix B. If it is in the symbol calculation stage, the number of non-zero elements in the corresponding row of the third sparse matrix C is directly determined according to the number of elements in the corresponding row of the second sparse matrix B. If it is in the numerical calculation stage, the non-zero element in the first sparse matrix A is multiplied by each non-zero element in this row of the second sparse matrix B, and the specific value of the corresponding row in the third sparse matrix C can be obtained.
[0068] In some embodiments, in step S104, determining the type of the accumulator according to the number of non-zero elements may further include the following steps:
[0069] When the proportion of the number of non-zero elements in the processing unit of the sparse matrix is less than or equal to the first proportion threshold, it is determined that the type of the accumulator is a hash accumulator.
[0070] In this embodiment, the first ratio threshold can be flexibly set, for example, set to 66%. When the proportion of non-zero elements in the processing unit of the sparse matrix is less than or equal to 66%, the type of the accumulator is determined to be a hash accumulator.
[0071] When using hash accumulators, the size of the hash table needs to be designed. For example, when running sparse matrix multiplication calculations on a graphics processing unit (GPU), and the hash accumulator is in shared memory, the size of the hash table should be reasonably set according to the number of thread blocks to be processed on each streaming multiprocessor (SM). For example, if the total available shared memory size of each SM is share_mem, and the number of thread blocks to be processed by each SM is n, then the hash table size should be share_mem / n minus the amount of shared memory required for each thread block, and the rest is the space used by the hash table, so that the shared memory can be fully utilized.
[0072] In some embodiments, when the type of the accumulator is determined to be a hash accumulator, in step S108, the intermediate storage of the sum value may further include the following steps:
[0073] A hash value is determined according to the index of the processing unit and the index of the corresponding processing unit in the second sparse matrix.
[0074] In this embodiment, the processing unit in the first sparse matrix A is the first row, and the corresponding processing unit in the second sparse matrix B is the first column. For example, a hash operation is performed according to (1, 1) to obtain a hash value. The hash value is uniquely corresponding to the string (1, 1).
[0075] The position in the hash table is determined according to the hash value, and the sum value is stored at the position in the hash table.
[0076] In this embodiment, each position in the hash table corresponds to a hash value, and the hash value corresponds to a specific position label in the processing unit in the first sparse matrix A, such as the position label is the i-th row, and the specific position label of the corresponding processing unit in the second sparse matrix B, such as the position label is the j-th column, and the two position label strings are (i, j). The two position label strings are (i, j) and a corresponding unique hash value can be generated by using a hash algorithm, and the storage location in the hash accumulator can be quickly located by the hash value.
[0077] In some embodiments, determining the type of the accumulator according to the number of non-zero elements may further include the following steps:
[0078] When the proportion of the number of non-zero elements in the processing unit of the sparse matrix is greater than the first proportion threshold, it is determined that the type of the accumulator is a dense accumulator.
[0079] In this embodiment, the dense accumulator uses dense vectors to cache intermediate results. Three vectors are usually used in the calculation process: the first vector stores the actual value; the second vector is used as a tag array to check whether the position index has been inserted before; and the third vector stores the position index.
[0080] In some embodiments, when it is determined that the type of the accumulator is a dense accumulator, in step S108, the above sum value is stored in an intermediate process, which may further include the following steps: inputting the above sum value into a preset array space.
[0081] In this embodiment, when a dense accumulator is used, an array space is opened in advance, and the accumulated sum values of the above-mentioned processing units are directly placed in the corresponding array positions according to the column index of each element, and finally the specific position of the corresponding processing unit in the third sparse matrix is determined according to the position in the array.
[0082] In some embodiments, in order to reduce the use of space, the change range of the position label of the final non-zero element in the above processing unit can be recorded during preprocessing, and array space can be opened according to the above change range. At the same time, priority is given to opening up array space in shared memory to use dense accumulators. If it is determined that the space required for the elements in the above processing unit exceeds the shared memory, sufficient space is used in the global memory to implement the hash accumulator.
[0083] The technical solution of the present application proposes a selection mechanism for different accumulators. Taking the processing unit as a single row or column as an example, if a row or column of the first sparse matrix A has only one non-zero element, then the calculation of the row uses a direct index accumulator, and directly takes out the non-zero element column index and element of the row corresponding to the non-zero element in the second sparse matrix B for calculation. For relatively sparse rows with multiple non-zero elements, a hash accumulator is used to reasonably design the size of the hash table, make full use of the space and keep the hash conflict rate at a low level; for large and dense rows, a dense accumulator is used to store the elements directly in a linear array, which can store more elements. In addition, because all data is stored in order, no sorting or conflict processing is required.
[0084] The hybrid accumulator algorithm and dynamic selection mechanism for sparse matrix multiplication proposed in the present invention solve the performance bottleneck problem in the accumulation of intermediate results of sparse matrix multiplication due to unreasonable accumulator design and selection, and creatively propose to use direct index accumulators for rows or columns with only one non-zero element in the first sparse matrix, providing a new solution to the diverse characteristics of sparse matrices. Experiments were conducted using a large number of matrices as data sets, and it was found that the hybrid accumulator and selection mechanism proposed in the present invention would bring significant performance improvements, improve the performance of the sparse matrix, a basic computing kernel, and can bring performance optimization to many applications. The setting and dynamic selection of hybrid accumulators including direct indexing, hashing and dense accumulators for sparse matrix multiplication are realized, and the performance improvement of sparse matrix multiplication in the step of accumulating intermediate results is achieved.
[0085] Based on the same inventive concept, the present application also proposes a data processing device for sparse matrix multiplication, see the attached Figure 2 A structural schematic diagram of a data processing device in a sparse matrix multiplication is shown; the device comprises:
[0086] The first determination module 21 is used to determine the number of non-zero elements in the processing unit of the first sparse matrix.
[0087] The second determination module 22 is used to determine the type of the accumulator according to the number of non-zero elements.
[0088] The types of accumulators mentioned above include: direct index accumulator, hash accumulator, and dense accumulator.
[0089] The processing module 23 is used to use the above-mentioned type of accumulator to accumulate and sum the product of the number of non-zero elements in the above-mentioned processing unit and the number of non-zero elements in the corresponding processing unit in the second sparse matrix to obtain a sum value.
[0090] The first storage module 24 is used to store the above-mentioned sum value in an intermediate process.
[0091] The second storage module 25 is used to store the above-mentioned sum value in the intermediate process, and then input the above-mentioned sum value into the third sparse matrix as the value in the above-mentioned third sparse matrix.
[0092] In some embodiments, the second determination module 22 is further configured to determine that the type of the accumulator is a direct index accumulator when the number of non-zero elements in the processing unit of the sparse matrix is less than a predetermined threshold.
[0093] In some embodiments, a third determination module is also included, which is used to determine the number of elements of the corresponding processing units in the above-mentioned second sparse matrix as the number of non-zero elements of the corresponding processing units in the third sparse matrix in the case of the symbol calculation stage when the second determination module 22 determines that the type of the accumulator is a direct index accumulator.
[0094] In some embodiments, the second determination module 22 is further used to determine that the type of the accumulator is a hash accumulator when the proportion of the number of non-zero elements in the processing unit of the sparse matrix is less than or equal to the first proportion threshold.
[0095] In some embodiments, the first storage module 24 is also used to determine the hash value according to the index of the above processing unit and the index of the corresponding processing unit in the second sparse matrix when the second determination module 22 determines that the type of the accumulator is a hash accumulator.
[0096] The position in the hash table is determined according to the hash value, and the sum value is stored at the position in the hash table.
[0097] In some embodiments, the second determination module 22 is further used to determine that the type of the accumulator is a dense accumulator when the proportion of the number of non-zero elements in the processing unit of the sparse matrix is greater than the first proportion threshold.
[0098] In some embodiments, the first storage module 24 is further configured to input the above sum value into a preset array space when the second determination module 22 determines that the type of the accumulator is a dense accumulator.
[0099] According to the third aspect of this application, see the attached Figure 3 , an electronic device 3 is provided, comprising at least one processor 31 and at least one memory 32. The memory 32 is used to store one or more program instructions. The processor 31 is used to run one or more program instructions to execute the steps of the data processing method in any one of the above sparse matrix multiplication.
[0100] For example Figure 1 Alternatively, when the processor 30 executes the computer program 32, the functions of the modules in the above-mentioned device embodiments are realized, for example, Figure 2 The functions of the first determination module 21 to the second storage module 25 are shown.
[0101] Exemplarily, the computer program 32 may be divided into one or more modules / units, which are stored in the memory 31 and executed by the processor 30 to complete the present application. The one or more modules / units may be a series of computer program instruction segments capable of completing specific functions, which are used to describe the execution process of the computer program 32 in the electronic device 3.
[0102] The electronic device 3 may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The electronic device may include, but is not limited to, a processor 30 and a memory 31. Those skilled in the art will appreciate that Figure 3 It is only an example of the electronic device 3 and does not constitute a limitation of the electronic device 3. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the above-mentioned electronic device may also include input and output devices, network access devices, buses, etc.
[0103] The processor 30 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.
[0104] The memory 31 may be an internal storage unit of the electronic device 3, such as a hard disk or memory of the electronic device 3. The memory 31 may also be an external storage device of the electronic device 3, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 3. Further, the memory 31 may include both an internal storage unit and an external storage device of the electronic device 3. The memory 31 is used to store the computer program and other programs and data required by the electronic device. The memory 31 may also be used to temporarily store data that has been output or is to be output.
[0105] In a fourth aspect, the present application also proposes a computer-readable storage medium, which contains one or more program instructions, and the one or more program instructions are used to execute the steps of the data processing method in the sparse matrix multiplication described in any of the above items.
[0106] For example, the computer-readable storage medium may be the above-mentioned memory 31 including program instructions, and the above-mentioned program instructions may be executed by the processor 30 of the electronic device 3 to complete the above-mentioned data processing method in the sparse matrix multiplication.
[0107] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.
[0108] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0109] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0110] In the embodiments provided in the present application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0111] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0112] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0113] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.
[0114] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.
Claims
1. A data processing method in sparse matrix multiplication, characterized in that: include: determining the number of non-zero elements in a processing unit of the first sparse matrix; Determining the type of the accumulator according to the number of non-zero elements; The types of the accumulators include: direct index accumulator, hash accumulator and dense accumulator; Using the accumulator of the type described above, cumulatively sum the product of the number of non-zero elements in the processing unit and the number of non-zero elements in the corresponding processing unit in the second sparse matrix to obtain a sum value; storing the sum value in an intermediate process; After the sum value is stored in an intermediate process, the sum value is input into a third sparse matrix as a value in the third sparse matrix.
2. The data processing method in sparse matrix multiplication according to claim 1, characterized in that: The determining the type of the accumulator according to the number of non-zero elements comprises: When the number of non-zero elements in the processing unit of the sparse matrix is less than a predetermined threshold, the type of the accumulator is determined to be a direct index accumulator.
3. The data processing method in sparse matrix multiplication as claimed in claim 2, characterized in that: When it is determined that the type of the accumulator is a direct index accumulator, the method further includes: In the case of the symbol calculation stage, the number of elements corresponding to the processing unit in the second sparse matrix is the number of non-zero elements corresponding to the processing unit in the third sparse matrix.
4. The data processing method in sparse matrix multiplication according to claim 1, characterized in that: The determining the type of the accumulator according to the number of non-zero elements comprises: When the proportion of the number of non-zero elements in the processing unit of the sparse matrix is less than or equal to the first proportion threshold, it is determined that the type of the accumulator is a hash accumulator.
5. The data processing method in sparse matrix multiplication according to claim 4, characterized in that: When it is determined that the type of the accumulator is a hash accumulator, the intermediate process of storing the sum value includes: Determining a hash value according to the index of the processing unit and the index of the corresponding processing unit in the second sparse matrix; A position in a hash table is determined according to the hash value, and the sum value is stored at the position in the hash table.
6. The data processing method in sparse matrix multiplication according to claim 1, characterized in that: The determining the type of the accumulator according to the number of non-zero elements comprises: When the proportion of the number of non-zero elements in the processing unit of the sparse matrix is greater than the first proportion threshold, it is determined that the type of the accumulator is a dense accumulator.
7. The data processing method in sparse matrix multiplication according to claim 6, characterized in that: When it is determined that the type of the accumulator is a dense accumulator, the intermediate process storage of the sum value includes: inputting the sum value into a preset array space.
8. A data processing device for sparse matrix multiplication, characterized in that: include: A first determination module, used to determine the number of non-zero elements in a processing unit of a first sparse matrix; A second determination module, configured to determine a type of an accumulator according to the number of non-zero elements; The types of the accumulators include: direct index accumulator, hash accumulator and dense accumulator; A processing module, configured to use an accumulator of the type described above to accumulate and sum the product of the number of non-zero elements in the processing unit and the number of non-zero elements in the corresponding processing unit in the second sparse matrix to obtain a sum value; A first storage module, used for storing the sum value in an intermediate process; The second storage module is used to input the sum value into a third sparse matrix as a value in the third sparse matrix after intermediate process storage of the sum value.
9. An electronic device, characterized in that: It comprises at least one processor and at least one memory; the memory is used to store one or more program instructions; the processor is used to run one or more program instructions to execute the data processing method in the sparse matrix multiplication as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium contains one or more program instructions, and the one or more program instructions are used to execute the data processing method in the sparse matrix multiplication according to any one of claims 1 to 7.