Pixel circuit

Abstract

The invention relates to a pixel circuit. The pixel circuit includes: a first transistor including a gate terminal receiving a first gate signal, a first terminal connected to a first node, and a second terminal connected to a second node; an inverter including: a first sub-transistor including a gate terminal connected to the first node, a first terminal receiving a driving voltage, and a second terminal connected to the second node; and a second sub-transistor including a gate terminal connected to the first node, a first terminal receiving a ground voltage, and a second terminal connected to the second node; and a light emitting element including an anode connected to the second node and a cathode receiving the ground voltage.

Description

Technical Field

[0001] Embodiments of the present invention relate to a pixel circuit. More particularly, the present invention relates to a pixel circuit for displaying an image using a pulse width modulation (PWM) method. Background Art

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel may include a gate line, a data line, and a pixel circuit. The display panel driver may include a gate driver for providing a gate signal to the gate line, a data driver for providing a data voltage to the data line, and a drive controller for controlling the gate driver and the data driver.

[0003] The pixel circuit can display an image using a pulse amplitude modulation (PAM) method or a pulse width modulation (PWM) method. The PAM method can express grayscale by adjusting the pulse amplitude of the driving current flowing in the pixel circuit, and the PWM method can express grayscale by adjusting the pulse width of the driving current. Summary of the invention

[0004] In a display device using a pulse width modulation (PWM) method, a generation time of a driving current corresponding to a pulse width of the driving current may be important for expressing grayscales. However, a delay time may occur in a rising period of the driving current and a falling period of the driving current.

[0005] An embodiment of the present invention provides a pixel circuit for displaying an image using a pulse width modulation method and reducing a delay time of a rising period of a driving current and a delay time of a falling period of the driving current.

[0006] In an embodiment of a pixel circuit according to the present invention, the pixel circuit includes: a first transistor including a gate terminal receiving a first gate signal, a first terminal connected to a first node, and a second terminal connected to a second node; an inverter including: a first sub-transistor including a gate terminal connected to the first node, a first terminal receiving a driving voltage, and a second terminal connected to the second node; and a second sub-transistor including a gate terminal connected to the first node, a first terminal receiving a ground voltage, and a second terminal connected to the second node; and a light-emitting element including an anode connected to the second node and a cathode receiving a ground voltage. In such an embodiment, the first sub-transistor is a P-type transistor and also includes a back-gate terminal receiving a first back-gate voltage, and the second sub-transistor is an N-type transistor and also includes a back-gate terminal receiving a second back-gate voltage.

[0007] In an embodiment, each of the first backgate voltage and the second backgate voltage may be equal to a voltage of the first node.

[0008] In an embodiment, the pixel circuit may further include: a second transistor including a gate terminal receiving a second gate signal, a first terminal receiving a data voltage including a pulse width modulated data voltage and a scan voltage, and a second terminal connected to a third node; and a boost capacitor including a first terminal connected to the third node and a second terminal connected to the first node.

[0009] In an embodiment, an input terminal of the inverter may be connected to the first node, and an output terminal of the inverter may be connected to the second node.

[0010] In an embodiment, the driving current may be generated based on the data voltage, and the generation time of the driving current may be determined according to the voltage level of the PWM data voltage.

[0011] In an embodiment, the inverter may invert a voltage of a first node and output the inverted voltage of the first node to a second node.

[0012] In an embodiment, the inverter can reduce the delay time of the rising period of the driving current and the delay time of the falling period of the driving current.

[0013] In an embodiment, a threshold voltage of the first sub-transistor may be determined based on the first back-gate voltage, and a threshold voltage of the second sub-transistor may be determined based on the second back-gate voltage.

[0014] In an embodiment, when the first back gate voltage decreases, the threshold voltage of the first sub-transistor may increase.

[0015] In an embodiment, when the second back gate voltage increases, the threshold voltage of the second sub-transistor may decrease.

[0016] In an embodiment, when the difference between the threshold voltage of the first sub-transistor and the threshold voltage of the second sub-transistor decreases, the delay time of the rising period of the driving current and the delay time of the falling period of the driving current may decrease.

[0017] In an embodiment, the P-type transistor may be a polysilicon thin film transistor, and the N-type transistor may be an oxide thin film transistor.

[0018] In an embodiment of a pixel circuit according to the present invention, the pixel circuit includes: a pulse width modulation circuit that generates a pulse width modulation (PWM) signal, wherein the pulse width modulation circuit includes an inverter, the inverter including: a first sub-transistor including a gate terminal connected to a first node, a first terminal receiving a driving voltage, and a second terminal connected to a second node; and a second sub-transistor including a gate terminal connected to the first node, a first terminal connected to a third node, and a second terminal connected to the second node; and a drive current generating circuit that generates a drive current, the generation time of the drive current being determined based on the pulse width modulation signal, wherein the drive current generating circuit includes a light-emitting element that emits light based on the drive current. In such an embodiment, the first sub-transistor is a P-type transistor and also includes a back-gate terminal that receives a first back-gate voltage, and the second sub-transistor is an N-type transistor and also includes a back-gate terminal that receives a second back-gate voltage.

[0019] In an embodiment, each of the first backgate voltage and the second backgate voltage may be equal to a voltage of the first node.

[0020] In an embodiment, the driving current generating circuit may further include: a first transistor including a gate terminal connected to a fourth node, a first terminal receiving a driving voltage, and a second terminal connected to a fifth node; a second transistor including a gate terminal receiving a first gate signal, a first terminal connected to the fourth node, and a second terminal connected to the fifth node; and a third transistor including a gate terminal receiving a pulse width modulation signal output from the second node, a first terminal connected to the sixth node, and a second terminal connected to the seventh node. In such an embodiment, the pulse width modulation circuit may further include: a fourth transistor including a gate terminal receiving a first gate signal, a first terminal connected to the first node, and a second terminal connected to the second node, and the light emitting element including an anode connected to the seventh node and a cathode receiving a ground voltage.

[0021] In an embodiment, the driving current generating circuit may further include: a fifth transistor including a gate terminal receiving a first gate signal, a first terminal connected to a current source, and a second terminal connected to a fifth node; a sixth transistor including a gate terminal receiving a second gate signal, a first terminal connected to the fifth node, and a second terminal connected to a sixth node; and a storage capacitor including a first terminal receiving a driving voltage and a second terminal connected to a fourth node. In such an embodiment, the pulse width modulation circuit may further include: a seventh transistor including a gate terminal receiving a third gate signal, a first terminal receiving a ground voltage, and a second terminal connected to a third node; and a boost capacitor including a first terminal receiving a data voltage and a second terminal connected to the first node.

[0022] In an embodiment, an input terminal of the inverter may be connected to the first node, and an output terminal of the inverter may be connected to the second node.

[0023] In an embodiment, the inverter may invert a voltage of a first node and output the inverted voltage of the first node to a second node.

[0024] In an embodiment, the inverter can reduce the delay time of the rising period of the driving current and the delay time of the falling period of the driving current.

[0025] In an embodiment, a threshold voltage of the first sub-transistor may be determined based on the first back-gate voltage, and a threshold voltage of the second sub-transistor may be determined based on the second back-gate voltage.

[0026] In an embodiment, when the difference between the threshold voltage of the first sub-transistor and the threshold voltage of the second sub-transistor decreases, the delay time of the rising period of the driving current and the delay time of the falling period of the driving current may decrease.

[0027] In an embodiment, the P-type transistor may be a polysilicon thin film transistor, and the N-type transistor may be an oxide thin film transistor.

[0028] According to embodiments of a pixel circuit and a display device including the pixel circuit, the pixel circuit may include an inverter so that a delay time of a rising period of a driving current and a delay time of a falling period of the driving current may be reduced.

[0029] In such an embodiment, the pixel circuit can adjust the first back gate voltage of the first sub-transistor included in the inverter and the second back gate voltage of the second sub-transistor included in the inverter, so that the delay time of the rising cycle and / or the delay time of the falling cycle of the driving current can be further reduced.

[0030] Therefore, the reliability of grayscale achieved by a pixel circuit that displays an image using a pulse width modulation method can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the embodiments of the present invention will become more apparent by describing the embodiments of the present invention in detail with reference to the accompanying drawings, in which:

[0032] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention;

[0033] Figure 2 It is shown that the Figure 1 A circuit diagram of an example of a pixel circuit in a display panel;

[0034] Figure 3 It is shown that the Figure 1A circuit diagram of another example of a pixel circuit in a display panel;

[0035] Figure 4 Is shown driving Figure 2 A timing diagram of an example of a pixel circuit;

[0036] Figure 5 It shows the inflow Figure 2 A diagram showing an ideal example of a driving current in a light emitting element;

[0037] Figure 6 It shows the inflow Figure 2 A diagram showing a practical example of a driving current in a light emitting element of FIG. 1 ;

[0038] Figure 7 It is shown Figure 2 Circuit diagram of the inverter;

[0039] Figure 8 It is shown that the Figure 7 A circuit diagram of a first sub-transistor and a second sub-transistor as switches in an inverter;

[0040] Fig. 9 It is shown Figure 8 Graph of the input voltage and output voltage of the inverter;

[0041] Fig.10 It is shown that the Figure 7 A diagram of gate voltage-drain current of a first sub-transistor and a second sub-transistor in an inverter;

[0042] Fig.11 It is shown that the Figure 1 A circuit diagram of another example of a pixel circuit in a display panel;

[0043] Fig.12 It is shown that the Figure 1 A circuit diagram of another example of a pixel circuit in a display panel;

[0044] Fig.13 Is shown driving Fig.11 A timing diagram of an example of a pixel circuit in FIG.

[0045] Fig.14 is a block diagram illustrating an embodiment of an electronic device; and

[0046] Fig.15 It is shown Fig.14 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a smart watch. DETAILED DESCRIPTION

[0047] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. The same reference numerals always refer to the same elements.

[0048] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0049] It will be understood that, although the terms "first", "second", "third", etc., may be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as "second element", "second component", "second region", "second layer" or "second part".

[0050] The term used herein is only for the purpose of describing a specific embodiment, and is not intended to limit. As used herein, unless the context clearly indicates otherwise, "one (kind / person)", "described (the)" and "at least one (kind / person)" do not represent the limitation of quantity, and are intended to include both singular and plural. Therefore, the reference to "described" element after the reference to "one" element in the claim includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "one element" has the same meaning as "at least one element". "At least one (kind / person)" should not be interpreted as limiting "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when the term "including" and / or "comprising" or "containing" and / or "having" is used in this specification, it means that there are stated features, regions, wholes, steps, operations, elements and / or components, but it is not excluded that there are or add one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0051] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in one of the accompanying drawings is turned over, the element described as being on the "lower" side of the other element will then be positioned on the "upper" side of the other element. Therefore, depending on the specific orientation of the accompanying drawings, the term "lower" can include both "lower" and "upper" orientations. Similarly, if the device in one of the accompanying drawings is turned over, the element described as being "below" or "below" the other element will then be positioned "above" the other element. Therefore, the term "below..." or "below..." can cover both upper and lower orientations.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0053] The embodiments described herein should not be construed as being limited to the specific shapes of the regions shown herein, but will include deviations in shape, for example, due to manufacturing. For example, a region shown or described as flat may generally have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, and are not intended to limit the scope of the claims.

[0054] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 is a block diagram showing a display device 10 according to an embodiment of the present invention.

[0056] Reference Figure 1 , an embodiment of the display device 10 may include a display panel 100 and a display panel driver. The display panel driver may include a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0057] The display panel 100 may include a display area for displaying an image and a peripheral area disposed adjacent to the display area.

[0058] The display panel 100 may include gate lines GL, data lines DL, and pixel circuits P electrically connected to the gate lines GL and the data lines DL, respectively. The gate lines GL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 crossing the first direction D1.

[0059] The driving controller 200 may receive input image data IMG and an input control signal CONT from an external device (not shown). In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. In another embodiment, for example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0060] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0061] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0062] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0063] The driving controller 200 may generate a data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 500.

[0064] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and output the third control signal CONT3 to the gamma reference voltage generator 400 .

[0065] The gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate line GL.

[0066] The gamma reference voltage generator 400 may generate the gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 may provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF may have a value corresponding to each data signal DATA.

[0067] In an embodiment, for example, the gamma reference voltage generator 400 may be provided in the driving controller 200 , or may be provided in the data driver 500 .

[0068] The data driver 500 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200, and receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into a data voltage of an analog type using the gamma reference voltage VGREF. The data driver 500 may output the data voltage to the data line DL.

[0069] Figure 2 It is shown that the Figure 1 1 is a circuit diagram of an example of a pixel circuit P (pixel circuit Pa) in the display panel 100. Figure 3 It is shown that the Figure 1 1 is a circuit diagram of another example (pixel circuit Pa′) of the pixel circuit P in the display panel 100 .

[0070] Reference Figures 1 to 3, an embodiment of the pixel circuit Pa may include a first transistor T1, an inverter INV, and a light emitting element EE, the first transistor T1 including a gate terminal receiving a first gate signal GS1[n] (where n is a natural number greater than 0), a first terminal connected to a first node N1, and a second terminal connected to a second node N2, the inverter INV includes: a first sub-transistor TS1 including a gate terminal connected to the first node N1, a first terminal receiving a driving voltage VDD, and a second terminal connected to a second node N2; and a second sub-transistor TS2 including a gate terminal connected to the first node N1, a first terminal receiving a ground voltage VGND, and a second terminal connected to the second node N2, the light emitting element EE including an anode connected to the second node N2 and a cathode receiving the ground voltage VGND. The first sub-transistor TS1 may be a P-type transistor, and further include a back gate terminal receiving a first back gate voltage VBML1, and the second sub-transistor TS2 may be an N-type transistor, and further include a back gate terminal receiving a second back gate voltage VBML2. In an embodiment, the P-type transistor may be a polysilicon thin film transistor, and the N-type transistor may be an oxide thin film transistor.

[0071] The pixel circuit Pa may further include: a second transistor T2 including a gate terminal receiving a second gate signal GS2[n], a first terminal receiving a data voltage VDATA, and a second terminal connected to a third node N3; and a boost capacitor CBOOST including a first terminal connected to the third node N3 and a second terminal connected to the first node N1. The data voltage VDATA may include a pulse width modulated (PWM) data voltage and a scan voltage.

[0072] In an embodiment, the first gate signal GS1[n] and the second gate signal GS2[n] may be sequentially applied row by row to the pixel circuits Pa. That is, the pixel circuits Pa may sequentially emit light.

[0073] In another embodiment, the first gate signal GS1[n] and the second gate signal GS2[n] may be substantially simultaneously applied to the pixel circuits Pa arranged in two or more rows. In an embodiment, for example, the first gate signal GS1[n] and the second gate signal GS2[n] may be substantially simultaneously applied to all pixel circuits Pa of the display panel 100. In such an embodiment, the pixel circuits Pa may emit light simultaneously.

[0074] An input terminal of the inverter INV may be connected to the first node N1 , and an output terminal of the inverter INV may be connected to the second node N2 .

[0075] like Figure 3As shown in, in another embodiment, in the pixel circuit Pa', the back gate terminal of the first sub-transistor TS1 may be connected to the first node N1. That is, the first back gate voltage VBML1 may be the voltage of the first node N1. In such an embodiment, the back gate terminal of the second sub-transistor TS2 may be connected to the first node N1. That is, the second back gate voltage VBML2 may be the voltage of the first node N1.

[0076] Figure 4 Is shown driving Figure 2 A timing diagram of an example of a pixel circuit Pa.

[0077] Reference Figures 1 to 4 In the initialization period IP, the first transistor T1 may be turned on in response to the first gate signal GS1[n] having a high level. When the first transistor T1 is turned on, the first node N1 and the second node N2 may be initialized.

[0078] In the PWM data writing period PWMDWP, the second transistor T2 may be turned on in response to the second gate signal GS2 [n] having a high level, and the second transistor T2 may provide the PWM data voltage VPWM to the third node N3 .

[0079] In the scan voltage write period SWEEPWP, the second transistor T2 may be turned on in response to the second gate signal GS2[n] having a high level, and the second transistor T2 may provide the scan voltage VSWEEP to the third node N3. In addition, the first transistor T1 may be turned off in response to the first gate signal GS1[n] having a low level. The voltage of the first node N1 may be boosted by the scan voltage VSWEEP by the boost capacitor CBOOST.

[0080] The light emitting period EP may be determined according to the voltage level of the PWM data voltage VPWM. Specifically, when the PWM data voltage VPWM has a relatively high voltage level, the first sub-transistor TS1 may be turned off until the scan voltage VSWEEP becomes a relatively low voltage level. The second sub-transistor TS2 may be turned on, and the inverter INV may provide the ground voltage VGND to the second node N2. Because the light emitting element EE emits light in response to the voltage of the second node N2 having the driving voltage VDD (or the driving current IEE), the light emitting time may be relatively short.

[0081] Figure 5 It shows the inflow Figure 2 Graph of an ideal example of the driving current IEE in the light emitting element EE. Figure 6 It shows the inflow Figure 2 Graph of a practical example of the drive current IEE in the light emitting element EE. Figure 5shows an ideal example of the driving current IEE varying with time t, and Figure 6 A practical example of the variation of the drive current IEE with time t is shown.

[0082] Reference Figures 1 to 6 , the second transistor T2 may apply the data voltage VDATA to the third node N3, and the boost capacitor CBOOST may apply a voltage corresponding to the data voltage VDATA to the first node N1. The inverter INV may provide the driving voltage VDD or the ground voltage VGND to the second node N2 in response to the voltage of the first node N1. The light emitting element EE may emit light in response to the voltage of the second node N2 having the driving voltage VDD (or the driving current IEE). The generation time tg of the driving current IEE may correspond to the light emitting period EP.

[0083] The pixel circuit Pa may display an image using a PWM method. The PWM method may express a grayscale by adjusting the generation time tg of the driving current IEE. Therefore, in the PWM method, the generation time tg of the driving current IEE may be important for expressing the grayscale.

[0084] like Figure 5 As shown in FIG. 1 , when the driving current IEE does not include the delay time tdr, tdf, the reliability of the grayscale achieved by the pixel circuit Pa can be increased, and the driving current IEE can be ideal. However, the actual driving current IEE may include the delay time tdr, tdf, as shown in FIG. Figure 6 As shown in . As the delay time tdr, tdf of the driving current IEE becomes longer, the reliability of the grayscale achieved by the pixel circuit Pa may decrease.

[0085] In an embodiment, the pixel circuit Pa may include an inverter INV so that the delay times tdr, tdf of the driving current IEE may be reduced.

[0086] Figure 7 It is shown Figure 2 Circuit diagram of inverter INV. Figure 8 It is shown that the Figure 7 Circuit diagram of a first sub-transistor TS1 and a second sub-transistor TS2 as switches in an inverter INV. Fig. 9 It is shown Figure 8 Graph of the input voltage VIN and output voltage VOUT of the inverter INV.

[0087] In the following, please refer to Figures 1 to 9 The operation of the pixel circuit Pa to minimize the delay times tdr, tdf of the driving current IEE by including the inverter INV is described.

[0088] like Figure 7As shown in , the inverter INV may include a first sub-transistor TS1 and a second sub-transistor TS2. Figure 8 As shown in , for ease of description, the first sub-transistor TS1 and the second sub-transistor TS2 can be expressed as switches. In an embodiment, as described above, the first sub-transistor TS1 can be a P-type transistor, and the second sub-transistor TS2 can be an N-type transistor. Therefore, when the voltage of the first node N1 is less than a specific voltage, the first sub-transistor TS1 can be turned on, and the second sub-transistor TS2 can be turned off. In this case, the driving voltage VDD can be applied to the second node N2. When the voltage of the first node N1 is greater than a specific voltage, the first sub-transistor TS1 can be turned off, and the second sub-transistor TS2 can be turned on. In this case, the ground voltage VGND can be applied to the second node N2. In this way, the inverter INV can invert the voltage of the first node N1 and output the inverted voltage of the first node N1 to the second node N2. The voltage of the first node N1 can be the input voltage VIN of the inverter INV, and the voltage of the second node N2 can be the output voltage VOUT of the inverter INV. Therefore, the relationship between the input voltage VIN of the inverter INV and the output voltage VOUT of the inverter INV according to the operation of the inverter INV can be Fig. 9 Shown in.

[0089] The inverter INV may control the voltage of the first node N1 and the voltage of the second node N2. Therefore, the pixel circuit Pa may include the inverter INV so that the delay time tdr of the rising period RP of the driving current IEE and the delay time tdf of the falling period FP of the driving current IEE may be reduced.

[0090] Fig.10 It is shown that the Figure 7 Graph showing gate voltage Vg-drain current Id of the first sub-transistor TS1 and the second sub-transistor TS2 in the inverter INV.

[0091] Reference Figures 1 to 10 As described above, the operation of the inverter INV can be determined based on a specific voltage. However, this is the case when the operation of the inverter INV is ideal, and the actual operation may be different from this.

[0092] The transistor can be turned on or off based on the threshold voltage. Fig.10As shown in , generally, the threshold voltage Vthp of the P-type transistor may have a negative value, and the threshold voltage Vthn of the N-type transistor may have a positive value. Because the first sub-transistor TS1 is a P-type transistor and the second sub-transistor TS2 is an N-type transistor, the threshold voltage of the first sub-transistor TS1 and the threshold voltage of the second sub-transistor TS2 may be different from each other, and therefore, the voltage at which the first sub-transistor TS1 is turned on and the voltage at which the second sub-transistor TS2 is turned on may be different from each other. Therefore, the actual operation of the inverter INV may be different from Figures 7 to 9 The operations described in .

[0093] In an embodiment, in order to make the operation of the inverter INV Figures 7 to 9 Similar to the operation described in, the difference between the threshold voltage of the first sub-transistor TS1 and the threshold voltage of the second sub-transistor TS2 can be reduced. The threshold voltage of the transistor can be determined based on the back gate voltage of the transistor. When the back gate voltage of the P-type transistor decreases, the threshold voltage of the P-type transistor can increase. When the back gate voltage of the N-type transistor increases, the threshold voltage of the N-type transistor can decrease. Therefore, the threshold voltage of the first sub-transistor TS1 can be determined based on the first back gate voltage VBML1, and the threshold voltage of the second sub-transistor TS2 can be determined based on the second back gate voltage VBML2. When the first back gate voltage VBML1 decreases, the threshold voltage of the first sub-transistor TS1 can increase. When the second back gate voltage VBML2 increases, the threshold voltage of the second sub-transistor TS2 can decrease.

[0094] When the difference between the threshold voltage of the first sub-transistor TS1 and the threshold voltage of the second sub-transistor TS2 decreases, the delay time tdr of the rising period RP and the delay time tdf of the falling period FP of the driving current IEE can be reduced. In an embodiment, the difference between the threshold voltage of the first sub-transistor TS1 and the threshold voltage of the second sub-transistor TS2 can be reduced by adjusting the first back gate voltage VBML1 and / or the second back gate voltage VBML2, so that the delay time tdr of the rising period RP and the delay time tdf of the falling period FP of the driving current IEE can be reduced.

[0095] In an embodiment, as described above, the pixel circuit Pa may include an inverter INV, so that the delay time tdr of the rising period RP of the driving current IEE and the delay time tdf of the falling period FP of the driving current IEE can be reduced. The pixel circuit Pa can adjust the first back gate voltage VBML1 of the first sub-transistor TS1 included in the inverter INV and the second back gate voltage VBML2 of the second sub-transistor TS2 included in the inverter INV, so that the delay time tdr of the rising period RP of the driving current IEE and / or the delay time tdf of the falling period FP can be further reduced. Therefore, the reliability of the grayscale achieved by the pixel circuit Pa that displays an image using the PWM method can be increased.

[0096] Fig.11 It is shown that the Figure 1 1 is a circuit diagram of another example (pixel circuit Pb) of the pixel circuit P in the display panel 100. Fig.12 It is shown that the Figure 1 1 is a circuit diagram of another example (pixel circuit Pb′) of the pixel circuit P in the display panel 100 .

[0097] Figure 2 The inverter INV and Fig.11 The inverters INV' may be substantially identical to each other in that the reliability of the grayscale implemented by the pixel circuit may be increased by reducing the delay time of the driving current by adjusting the back gate voltage. Therefore, any repeated detailed description of the same or similar contents as those described above will be omitted.

[0098] Reference Figures 1 to 12, an embodiment of the pixel circuit Pb may include a pulse width modulation circuit CPWM and a driving current generating circuit CCUR, the pulse width modulation circuit CPWM is configured to generate a pulse width modulation signal PWM and includes a first sub-transistor TS1' and a second sub-transistor TS2', the first sub-transistor TS1' includes a gate terminal connected to the first node N1', a first terminal receiving a driving voltage VDD and a second terminal connected to the second node N2', the second sub-transistor TS2' includes a gate terminal connected to the first node N1', a first terminal connected to the third node N3' and a second terminal connected to the second node N2', the driving current generating circuit CCUR is configured to generate a driving current IEE' and includes a light emitting element EE that emits light based on the driving current IEE', and the generation time of the driving current IEE' is determined based on the pulse width modulation signal PWM. The first sub-transistor TS1' may be a P-type transistor and also include a back gate terminal receiving a first back gate voltage VBML1', and the second sub-transistor TS2' may be an N-type transistor and also include a back gate terminal receiving a second back gate voltage VBML2'. In an embodiment, the P-type transistor may be a polysilicon thin film transistor, and the N-type transistor may be an oxide thin film transistor.

[0099] The driving current generating circuit CCUR may also include: a first transistor T1', including a gate terminal connected to the fourth node N4', a first terminal receiving the driving voltage VDD, and a second terminal connected to the fifth node N5'; a second transistor T2', including a gate terminal receiving the first gate signal GS1', a first terminal connected to the fourth node N4', and a second terminal connected to the fifth node N5'; and a third transistor T3', including a gate terminal receiving the pulse width modulation signal PWM output from the second node N2', a first terminal connected to the sixth node N6', and a second terminal connected to the seventh node N7'.

[0100] The pulse width modulation circuit CPWM may further include a fourth transistor T4 ′ including a gate terminal receiving the first gate signal GS1 ′, a first terminal connected to the first node N1 ′, and a second terminal connected to the second node N2 ′.

[0101] The light emitting element EE may include an anode connected to the seventh node N7 ′ and a cathode receiving the ground voltage VGND.

[0102] The driving current generating circuit CCUR may also include: a fifth transistor T5', including a gate terminal receiving a first gate signal GS1', a first terminal connected to a current source CS', and a second terminal connected to a fifth node N5'; a sixth transistor T6', including a gate terminal receiving a second gate signal GS2', a first terminal connected to a fifth node N5', and a second terminal connected to a sixth node N6'; and a storage capacitor CST', including a first terminal receiving a driving voltage VDD and a second terminal connected to a fourth node N4'.

[0103] The pulse width modulation circuit CPWM may further include: a seventh transistor T7', including a gate terminal receiving a third gate signal GS3'[n], a first terminal receiving a ground voltage VGND, and a second terminal connected to a third node N3'; and a boost capacitor CBOOST', including a first terminal receiving a data voltage VDATA' and a second terminal connected to a first node N1'. The data voltage VDATA' may include a PWM data voltage and a scan voltage.

[0104] In an embodiment, the first gate signal GS1' and the second gate signal GS2' may be applied substantially simultaneously to the pixel circuits Pb arranged in two or more rows. In an embodiment, for example, the first gate signal GS1' and the second gate signal GS2' may be applied substantially simultaneously to all pixel circuits Pb of the display panel 100.

[0105] In an embodiment, the third gate signal GS3 ′[n] may be sequentially applied to the pixel circuits Pb row by row.

[0106] like Fig.12 As shown in, in another embodiment, in the pixel circuit Pb', the back gate terminal of the first sub-transistor TS1' may be connected to the first node N1'. That is, the first back gate voltage VBML1' may be the voltage of the first node N1'. In addition, in an embodiment, the back gate terminal of the second sub-transistor TS2' may be connected to the first node N1'. That is, the second back gate voltage VBML2' may be the voltage of the first node N1'.

[0107] Fig.13 Is shown driving Fig.11 A timing diagram of an example of a pixel circuit Pb in FIG.

[0108] Reference Figures 1 to 13, in the initialization period IP', the fourth transistor T4' may be turned on in response to the first gate signal GS1' having a high level. When the fourth transistor T4' is turned on, the first node N1' and the second node N2' may be initialized. In addition, the seventh transistor T7' may be turned on in response to the third gate signal GS3'[n] having a high level. When the seventh transistor T7' is turned on, the seventh transistor T7' may provide the ground voltage VGND to the inverter INV' to control the operation of the inverter INV'.

[0109] In the PWM data write period PWMDWP′, the PWM data voltage VPWM′ may be provided to the first terminal of the boosting capacitor CBOOST′.

[0110] In the scan voltage write period SWEEPWP', the scan voltage VSWEEP' may be supplied to the first terminal of the boosting capacitor CBOOST'. The voltage of the first node N1' may be boosted by the scan voltage VSWEEP' by the boosting capacitor CBOOST'.

[0111] The pulse width of the pulse width modulation signal PWM may be determined according to the voltage level of the PWM data voltage VPWM'. Specifically, when the PWM data voltage VPWM' has a relatively high voltage level, the first sub-transistor TS1' may be turned off, the second sub-transistor TS2' may be turned on, and the inverter INV' may provide the ground voltage VGND to the second node N2' until the scan voltage VSWEEP' becomes a relatively low voltage level. Therefore, the pulse width of the pulse width modulation signal PWM may be relatively short.

[0112] The second transistor T2' and the fifth transistor T5' may be turned on in response to the first gate signal GS1' having a high level. The second transistor T2' may connect the fourth node N4' and the fifth node N5' to compensate for the threshold voltage of the first transistor T1'. The current source CS' may provide a constant current to the fifth node N5' and the fourth node N4'. The first transistor T1' may generate a driving current IEE'.

[0113] The third transistor T3' can be turned on in response to the pulse width modulation signal PWM. The third transistor T3' can provide a driving current IEE' to the light emitting element EE. Therefore, the light emitting period EP' can be determined according to the pulse width of the pulse width modulation signal PWM. That is, the generation time of the driving current IEE' can be determined based on the pulse width modulation signal PWM.

[0114] The threshold voltage of the first sub-transistor TS1' may be determined based on the first back-gate voltage VBML1', and the threshold voltage of the second sub-transistor TS2' may be determined based on the second back-gate voltage VBML2'. When the difference between the threshold voltage of the first sub-transistor TS1' and the threshold voltage of the second sub-transistor TS2' decreases, the inverter INV' may reduce the delay time of the rising period of the pulse width modulation signal PWM and the delay time of the falling period of the pulse width modulation signal PWM.

[0115] When the difference between the threshold voltage of the first sub-transistor TS1 ′ and the threshold voltage of the second sub-transistor TS2 ′ decreases, the delay time of the rising period of the driving current IEE′ and the delay time of the falling period of the driving current IEE′ may be reduced.

[0116] In an embodiment, as described above, the pixel circuit Pb may include an inverter INV' so that the delay time of the rising cycle of the driving current IEE' and the delay time of the falling cycle of the driving current IEE' can be reduced. The pixel circuit Pb may adjust the first back gate voltage VBML1' of the first sub-transistor TS1' included in the inverter INV' and the second back gate voltage VBML2' of the second sub-transistor TS2' included in the inverter INV' so that the delay time of the rising cycle of the driving current IEE' and / or the delay time of the falling cycle can be further reduced. Therefore, the reliability of the grayscale achieved by the pixel circuit Pb that displays an image using a pulse width modulation method can be increased.

[0117] Fig.14 is a block diagram illustrating an embodiment of an electronic device 1000 . Fig.15 It is shown Fig.14 FIG. 1 is a diagram of an embodiment in which the electronic device 1000 is implemented as a smart watch.

[0118] Reference Fig.14 and Fig.15 , an embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 The display device 10. In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, and other electronic devices.

[0119] In an embodiment, Fig.15As shown in , the electronic device 1000 can be implemented as a smart watch. However, the electronic device 1000 is not limited thereto. In an embodiment, for example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet computer, a car navigation system, a computer monitor, a laptop computer, or a head mounted display (HMD) device, etc.

[0120] The processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, or a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0121] The memory device 1020 may store data for operation of the electronic device 1000. In an embodiment, for example, the memory device 1020 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, or a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or a mobile DRAM device.

[0122] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, or a compact disk read only memory (CD-ROM) device, etc.

[0123] I / O devices 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touch pad, and a touch screen, and output devices such as a printer or a speaker, etc. In some embodiments, I / O devices 1040 may include a display device 1060 .

[0124] The power supply 1050 may provide power for the operation of the electronic device 1000 .

[0125] The display device 1060 may be connected to other components via a bus or other communication links.

[0126] The present invention can be applied to any display device and any electronic device including a touch panel, for example, a mobile phone, a smart phone, a digital television (TV), a three-dimensional (3D) TV, a personal computer (PC) (such as a tablet computer or a laptop computer), a home appliance, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

[0127] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0128] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A pixel circuit, wherein: The pixel circuit comprises: a first transistor including a gate terminal receiving a first gate signal, a first terminal connected to a first node, and a second terminal connected to a second node; Inverter, including: a first sub-transistor including a gate terminal connected to the first node, a first terminal receiving a driving voltage, and a second terminal connected to the second node; and a second sub-transistor including a gate terminal connected to the first node, a first terminal receiving a ground voltage, and a second terminal connected to the second node; and a light emitting element including an anode connected to the second node and a cathode receiving the ground voltage, wherein the first sub-transistor is a P-type transistor and further includes a back gate terminal receiving a first back gate voltage, and The second sub-transistor is an N-type transistor and further includes a back-gate terminal for receiving a second back-gate voltage.

2. The pixel circuit according to claim 1, wherein: Each of the first backgate voltage and the second backgate voltage is equal to a voltage of the first node.

3. The pixel circuit according to claim 1, wherein: The pixel circuit further includes: a second transistor including a gate terminal receiving a second gate signal, a first terminal receiving a data voltage including a pulse width modulated data voltage and a scan voltage, and a second terminal connected to a third node; and A boost capacitor includes a first terminal connected to the third node and a second terminal connected to the first node.

4. The pixel circuit according to claim 3, wherein: An input terminal of the inverter is connected to the first node, and an output terminal of the inverter is connected to the second node.

5. The pixel circuit according to claim 4, wherein: A driving current is generated based on the data voltage, and a generation time of the driving current is determined according to a voltage level of the pulse width modulated data voltage.

6. The pixel circuit according to claim 5, wherein: The inverter inverts the voltage of the first node and outputs the inverted voltage of the first node to the second node.

7. The pixel circuit according to claim 5, wherein: The inverter reduces a delay time of a rising period of the driving current and a delay time of a falling period of the driving current.

8. The pixel circuit according to claim 1, wherein: A threshold voltage of the first sub-transistor is determined based on the first back-gate voltage, and a threshold voltage of the second sub-transistor is determined based on the second back-gate voltage.

9. The pixel circuit according to claim 8, wherein: When the first back gate voltage decreases, the threshold voltage of the first sub-transistor increases.

10. The pixel circuit according to claim 8, wherein: When the second back gate voltage increases, the threshold voltage of the second sub-transistor decreases.

11. The pixel circuit according to claim 8, wherein: When the difference between the threshold voltage of the first sub-transistor and the threshold voltage of the second sub-transistor decreases, a delay time of a rising period of a driving current and a delay time of a falling period of the driving current decrease.

12. The pixel circuit according to claim 1, wherein: The P-type transistor is a polysilicon thin film transistor, and the N-type transistor is an oxide thin film transistor.

13. A pixel circuit, wherein: The pixel circuit comprises: A pulse width modulation circuit generates a pulse width modulation signal, wherein the pulse width modulation circuit includes an inverter, and the inverter includes: a first sub-transistor including a gate terminal connected to a first node, a first terminal receiving a driving voltage, and a second terminal connected to a second node; and a second sub-transistor including a gate terminal connected to the first node, a first terminal connected to a third node, and a second terminal connected to the second node; and a driving current generating circuit for generating a driving current, wherein a generation time of the driving current is determined based on the pulse width modulation signal, wherein the driving current generating circuit comprises a light emitting element that emits light based on the driving current, wherein the first sub-transistor is a P-type transistor and further includes a back-gate terminal receiving a first back-gate voltage, and The second sub-transistor is an N-type transistor and further includes a back-gate terminal for receiving a second back-gate voltage.

14. The pixel circuit according to claim 13, wherein: Each of the first backgate voltage and the second backgate voltage is equal to a voltage of the first node.

15. The pixel circuit according to claim 13, in, The driving current generating circuit further includes: a first transistor including a gate terminal connected to the fourth node, a first terminal receiving the driving voltage, and a second terminal connected to the fifth node; a second transistor including a gate terminal receiving a first gate signal, a first terminal connected to the fourth node, and a second terminal connected to the fifth node; and a third transistor including a gate terminal receiving the pulse width modulation signal output from the second node, a first terminal connected to a sixth node, and a second terminal connected to a seventh node, Wherein, the pulse width modulation circuit further includes: a fourth transistor including a gate terminal receiving the first gate signal, a first terminal connected to the first node, and a second terminal connected to the second node, and The light emitting element includes an anode connected to the seventh node and a cathode receiving a ground voltage.

16. The pixel circuit according to claim 15, in, The driving current generating circuit further includes: a fifth transistor comprising a gate terminal receiving the first gate signal, a first terminal connected to a current source, and a second terminal connected to the fifth node; a sixth transistor including a gate terminal receiving a second gate signal, a first terminal connected to the fifth node, and a second terminal connected to the sixth node; and a storage capacitor including a first terminal receiving the driving voltage and a second terminal connected to the fourth node, Wherein, the pulse width modulation circuit further includes: a seventh transistor including a gate terminal receiving a third gate signal, a first terminal receiving the ground voltage, and a second terminal connected to the third node; and The boosting capacitor includes a first terminal receiving a data voltage and a second terminal connected to the first node.

17. The pixel circuit according to claim 13, wherein: An input terminal of the inverter is connected to the first node, and an output terminal of the inverter is connected to the second node.

18. The pixel circuit according to claim 17, wherein: The inverter inverts the voltage of the first node and outputs the inverted voltage of the first node to the second node.

19. The pixel circuit according to claim 18, wherein: The inverter reduces a delay time of a rising period of the driving current and a delay time of a falling period of the driving current.

20. The pixel circuit according to claim 13, wherein: A threshold voltage of the first sub-transistor is determined based on the first back-gate voltage, and a threshold voltage of the second sub-transistor is determined based on the second back-gate voltage.

21. The pixel circuit according to claim 20, wherein: When the difference between the threshold voltage of the first sub-transistor and the threshold voltage of the second sub-transistor decreases, a delay time of a rising period of the driving current and a delay time of a falling period of the driving current decrease.

22. The pixel circuit according to claim 13, wherein: The P-type transistor is a polysilicon thin film transistor, and the N-type transistor is an oxide thin film transistor.

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