A molding process for an LSI chip package structure

Abstract

The application discloses a forming process of an LSI chip packaging structure and belongs to the technical field of semiconductor packaging. The process is as follows: an LSI chip monomer is prepared; a first dummy chip monomer with low-density copper columns is prepared; a second dummy chip monomer with high-density copper columns is prepared; the LSI chip monomer, the first dummy chip monomer and the second dummy chip monomer are sequentially mounted on a carrier (400) in a normal way to form a first plastic encapsulation body (301); and the first plastic encapsulation body (301) is reduced in parallel through a thinning process, and a first redistribution metal layer (510) and a second redistribution metal layer (530) are formed on the front surface and the back surface of the first plastic encapsulation body (301) respectively. The application provides a design structure with multiple metal column structure densities integrated, and satisfies the design requirements of products in multiple directions.

Description

TECHNICAL FIELD

[0001] The present application relates to a forming process of LSI chip packaging structure, and belongs to the technical field of semiconductor packaging. BACKGROUND

[0002] LSI is a kind of bridge chip (Bridge Die). In the forming process of the existing LSI chip, the thickness of the bridge chip (Si bridge Die) is 50 microns to 80 microns due to the influence of thinning and dicing process, and then the bridge chip is pasted on a temporary glass carrier through the pasting process. The bridge chip cannot be thinned again in the chip packaging process. The copper column on the LSI chip is operated by the copper column planting method. Because the LSI bridge chip cannot be thinned again, the diameter of the copper column of the current product in the industry is 60 microns to 80 microns, and the pitch is 110 microns to 140 microns. It is impossible to form a high-density layout of the copper column (the diameter of the copper column needs to be reduced to 50 microns, and the minimum pitch needs to be reduced to 100 microns), which hinders the development of market demand for product performance. At the same time, the temporary bonding and debonding process (TB / DB process) of the glass carrier uses expensive equipment and materials, resulting in high production cost. SUMMARY

[0003] In order to overcome the shortcomings of the existing packaging process, the present application provides a forming process of LSI chip packaging structure to reduce the thickness of the packaging structure, improve product performance, and reduce process cost.

[0004] The technical scheme of the present application is as follows:

[0005] The present application provides a forming process of LSI chip packaging structure, and the implementation steps are as follows:

[0006] Step one, making LSI chip monomer, the LSI chip monomer includes LSI chip body and LSI chip lower metal column arranged on the front surface of the LSI chip body;

[0007] Step two, making first false chip monomer with low-density copper column, the first false chip monomer includes first false chip body and a plurality of first metal columns, the first metal columns are perpendicular to the first false chip body, forming a low-density metal column group, and the thickness of the first false chip body is less than or equal to the current thickness of the LSI chip body minus the target thickness of the LSI chip body;

[0008] Step three, making second false chip monomer with high-density copper column, the second false chip monomer includes second false chip body and a plurality of second metal columns, the second metal columns are perpendicular to the second false chip body, forming a high-density metal column group, and the thickness of the second false chip body is less than or equal to the current thickness of the LSI chip body minus the target thickness of the LSI chip body;

[0009] Step four, prepare a carrier, which is pasted with a thermal release film;

[0010] Step five, sequentially mount the LSI chip monomer, the first dummy chip monomer and the second dummy chip monomer to the carrier in sequence, the LSI chip monomer is even, wherein the first dummy chip monomer is arranged in the outer side area of the LSI chip monomer, and the second dummy chip monomer is arranged in the inner side area of the adjacent two LSI chip monomers;

[0011] Step six, encapsulate the LSI chip monomer, the first dummy chip monomer and the second dummy chip monomer with an encapsulating material to form a first plastic encapsulation body;

[0012] Step seven, separate the first plastic encapsulation body from the carrier by a thermal debonding process to expose a separation surface;

[0013] Step eight, parallelly reduce the first plastic encapsulation body by a thinning process to form a first plastic encapsulation body front surface and a first plastic encapsulation body back surface, respectively, wherein the first plastic encapsulation body removes the first dummy chip body of the first dummy chip monomer and the second dummy chip body of the second dummy chip monomer, respectively, leaves a low-density metal column group and a high-density metal column group, and removes a part of the back surface thickness of the LSI chip body to form a thinned body of the LSI chip body to achieve a target thickness of the LSI chip body;

[0014] Step nine, form a first rewiring metal layer on the first plastic encapsulation body front surface by a rewiring process, wherein the first rewiring metal layer is arranged on the front surface of the plastic encapsulation body, the metal layer thereof is electrically connected with the LSI chip lower metal column, the first metal column of the low-density metal column group and the second metal column of the high-density metal column group, respectively, the outermost layer of the first rewiring metal layer is a passivation layer, and a first signal port is arranged on the passivation layer;

[0015] Step ten, form a second rewiring metal layer on the first plastic encapsulation body back surface by a rewiring process, wherein the second rewiring metal layer is arranged on the back surface of the plastic encapsulation body, the metal layer thereof is electrically connected with the LSI chip body back surface, the first metal column of the low-density metal column group and the second metal column of the high-density metal column group, respectively, the outermost layer of the second rewiring metal layer is a passivation layer, and a second signal port is arranged on the passivation layer.

[0016] As an implementation manner, in step two, the first dummy chip monomer with low-density copper columns is prepared as follows: a first dummy wafer is taken, and a low-density metal column group is formed on the first dummy wafer by wafer-level metal column plating process steps of wafer electroplating, photolithography, etching and deposition in sequence; then the back surface of the first dummy wafer is ground and thinned, and the first dummy wafer is cut into a plurality of first dummy chip monomers.

[0017] As an implementable manner of the present application, the first metal column of the low-density metal column group has a diameter ranging from 60 microns to 80 microns and a spacing ranging from 110 microns to 140 microns.

[0018] As an implementable manner of the present application, in step three, the second dummy chip monomer with high-density copper columns is manufactured, and the manufacturing process is as follows: a second dummy wafer is taken, and high-density metal column groups are formed on the second dummy wafer by wafer electroplating, photolithography, etching, and deposition in sequence; then, the back of the second dummy wafer is thinned by grinding, and the second dummy wafer is cut into a plurality of second dummy chip monomers.

[0019] As an implementable manner of the present application, the second metal column of the high-density metal column group has a diameter ranging from 50 microns to 60 microns and a spacing ranging from 100 microns to 110 microns.

[0020] As an implementable manner of the present application, the photoresist aspect ratio of the first metal column of the low-density metal column group is less than the photoresist aspect ratio of the second metal column of the high-density metal column group, and the minimum resolution feature size of the photoresist resolution of the first metal column of the low-density metal column group is greater than the minimum resolution feature size of the photoresist resolution of the second metal column of the high-density metal column group.

[0021] Beneficial effects

[0022] The present application provides a forming process of an LSI chip packaging structure, the thickness of the LSI chip packaging structure is further reduced to a target thickness, achieving the target of an ultra-thin LSI structure, and the height of the low-density metal column group and the high-density metal column group on the side is reduced, which can improve the corresponding electrical performance (because a lower metal column height means smaller loss);

[0023] The high-density Cu Post structure of the LSI chip packaging structure of the present application has a metal column diameter that can be reduced to 50 microns and a minimum spacing of 100 microns, which improves the performance of the product;

[0024] The LSI chip packaging structure of the present application provides a design structure that integrates multiple metal column structure densities, meeting the design needs of the product in multiple directions;

[0025] The forming process of the LSI chip packaging structure of the present application uses a thermal release film + metal carrier to achieve reconstruction, does not use a glass carrier TB / DB and TSV process, and does not need to use a temporary bonding device, thereby reducing the process cost. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a schematic diagram of the existing LSI chip packaging structure;

[0027] Figure 2A process flow chart of a molding process of the LSI chip packaging structure of the present application:

[0028] Figure 3 A sectional view of the LSI chip packaging structure of the present application;

[0029] Figure 4 A sectional view of the further packaging structure of Figure 3

[0030] Figure 5 A top view schematic of Figure 4

[0031] Figures 6A to 6J A process flow chart of the molding process of the pattern; Figure 3

[0032] wherein the LSI chip body 101

[0033] the LSI chip body front surface 110

[0034] the LSI chip body back surface 130

[0035] the LSI chip body 111

[0036] the LSI chip lower metal pillar 121

[0037] the LSI chip lower metal pillar outer end surface 123

[0038] the low density metal pillar group 210

[0039] the first metal pillar first end surface 211

[0040] the first metal pillar second end surface 213

[0041] the high density metal pillar group 230

[0042] the second metal pillar first end surface 231

[0043] the second metal pillar second end surface 233

[0044] the plastic encapsulation body 301

[0045] the plastic encapsulation body front surface 310

[0046] the plastic encapsulation body back surface 330

[0047] the carrier 400

[0048] the thermal glass film 410

[0049] the first re-wiring metal layer 510

[0050] the first signal port 511

[0051] ​​​Second re-wiring metal layer 530

[0052] Second signal port 531

[0053] SOC chip 610

[0054] HBM chip 630. DETAILED DESCRIPTION

[0055] The application will be further described below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that only the parts related to the application are shown in the drawings for ease of description. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0056] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0057] The forming process of the LSI chip packaging structure of the present application is shown in Figure 2 The process flow is as follows:

[0058] S1: making LSI chip monomer;

[0059] S2: making first dummy chip monomer with low-density copper pillars;

[0060] S3: making second dummy chip monomer with high-density copper pillars;

[0061] S4: preparing a carrier, and pasting a thermal release film on the carrier;

[0062] S5: sequentially mounting the LSI chip monomer, the first dummy chip monomer and the second dummy chip monomer to the carrier in a face-up manner

[0063] S6: encapsulating the LSI chip monomer, the first dummy chip monomer and the second dummy chip monomer to form a first plastic encapsulation body

[0064] S7: separating the first plastic encapsulation body from the carrier by a heating debonding process

[0065] S8: reducing the first plastic encapsulation body in parallel by a thinning process

[0066] S9: forming a first re-wiring metal layer on the front surface of the first plastic encapsulation body by a re-wiring process

[0067] S10: forming a second re-wiring metal layer on the back surface of the first plastic encapsulation body by a re-wiring process

[0068] An LSI chip packaging structure can be provided by the molding process of the LSI chip packaging structure described above, as shown in Figures 3 to 5 The LSI chip packaging structure includes an even number of LSI chip bodies 101, a low-density metal column group 210 and a high-density metal column group 230, and a first re-wiring metal layer 510 and a second re-wiring metal layer 530. The number of LSI chip bodies 101 is ≥ 2. The LSI chip body 101 includes an LSI chip body front surface 110 and an LSI chip body back surface 130 opposite to the LSI chip body front surface 110, and the LSI chip lower metal column 121 is arranged on the LSI chip body front surface 110. Figure 5 The four LSI chip bodies 101 are arranged in an array.

[0069] The low-density metal column group 210 is arranged on the outer side of the LSI chip body 101. The low-density metal column group 210 is composed of a plurality of first metal columns arranged in an array and parallel to the LSI chip lower metal column 121. The two end surfaces of each first metal column are a first metal column first end surface 211 and a first metal column second end surface 213.

[0070] The high-density metal column group 230 is arranged on the inner side of the adjacent two LSI chip bodies 101. The high-density metal column group 230 is composed of a plurality of second metal columns arranged in an array and parallel to the LSI chip lower metal column 121. The diameter range of the second metal column is < the diameter range of the first metal column, and the pitch range of the second metal column is < the pitch range of the first metal column. The two end surfaces of each second metal column include a second metal column first end surface 231 and a second metal column second end surface 233. In this embodiment, the first metal column adopts the industry conventional value, with a diameter range of 60-80 microns and a pitch range of 110-140 microns, and the second metal column has a diameter range of 50-60 microns and a pitch range of 100-110 microns, so as to reduce the loss and enhance the via efficiency.

[0071] The encapsulating material encapsulates the LSI chip body 101, the high-density metal column group 230, and the low-density metal column group 210 to form a plastic encapsulation body 301. The front surface and the back surface of the plastic encapsulation body 301 are parallelly thinned. The LSI chip body back surface 130, the first metal column second end surface 213 of the low-density metal column group 210, and the second metal column second end surface 233 of the high-density metal column group 230 are exposed on the back surface of the plastic encapsulation body 301. The LSI chip lower metal column outer end surface 123, the first metal column first end surface 211 of the low-density metal column group 210, and the second metal column first end surface 231 of the high-density metal column group 230 are exposed on the front surface of the plastic encapsulation body 301.

[0072] The first re-wiring metal layer 510 is arranged on the front surface of the plastic package 301, and includes a plurality of metal layers and dielectric layers, the dielectric layers are provided with dielectric layer openings, and the upper and lower adjacent metal layers are electrically connected through the dielectric layer openings. Figure 3 The metal layer of the first re-wiring metal layer 510 is electrically connected with the first end surface 211 of the first metal column, the first end surface 231 of the second metal column and the lower end surface 123 of the LSI chip, and the outermost layer of the first re-wiring metal layer 510 is a dielectric layer and is provided with a first signal port 511, and the specific form of the first signal port 511 includes a signal terminal array, a pad or an opening, etc. The skilled in the art can select the module according to the needs, and no specific limitation is made. Figure 3 The pad is used for selectively fixing the functional chip through the lower metal column of the chip, and the functional chip is plastic-sealed by the encapsulating material, and only the back surface of the functional chip is exposed. Figure 4 And Figure 5 The three functional chips are inverted, the central chip is an SOC chip 610, the SOC chip 610 is provided with a lower metal column of the chip, and four HBM chips 630 are distributed around the SOC chip 610 and are provided with a lower metal column of the chip. The SOC chip 610 is electrically connected with all the LSI chip bodies 101 through the first re-wiring metal layer 510 and is electrically connected with the second re-wiring metal layer 530 through the high-density metal column group 230. The HBM chip 630 is selectively electrically connected with the LSI chip body 101 through the first re-wiring metal layer 510, and is selectively electrically connected with the low-density metal column group 210 and the second re-wiring metal layer 530.

[0073] The second re-wiring metal layer 530 is arranged on the back surface of the plastic package 301, and includes a plurality of metal layers and dielectric layers, the dielectric layers are provided with dielectric layer openings, and the upper and lower adjacent metal layers are electrically connected through the dielectric layer openings. Figure 3 The metal layer of the second re-wiring metal layer 530 is electrically connected with the first end surface 213 of the first metal column, the second end surface 233 of the second metal column and the back surface 130 of the LSI chip body.

[0074] The metal layer of the second re-wiring metal layer 530 is electrically connected with the first end surface 213 of the first metal column, the second end surface 233 of the second metal column and the back surface 130 of the LSI chip body. Figure 4 The pad is used for selectively fixing the functional chip through the lower metal column of the chip, and the functional chip is plastic-sealed by the encapsulating material, and only the back surface of the functional chip is exposed.

[0075] The above-mentioned LSI chip packaging structure can be realized through the process flow of the forming process of the LSI chip packaging structure of the application, as shown in Figures 6A to 6J The process is as follows:

[0076] Step one, see Figure 6A As shown, the LSI chip monomer is made, which includes the LSI chip body 101 and the LSI chip under metal column 121 arranged on the front surface. Take the LSI chip wafer, and form the LSI chip under metal column 121 on the LSI chip wafer by wafer electroplating, photoetching, etching, deposition and other wafer-level electroplating metal column process steps in sequence; the back surface of the LSI chip wafer is ground and thinned, and then cut into a plurality of LSI chip monomers, the front surface of the LSI chip monomer has the LSI chip under metal column 121. The function of the LSI chip under metal column 121 is electrical transmission, and its material is preferably copper.

[0077] Step two, see Figure 6B As shown, the first false chip monomer with low-density copper column is made, which includes the first false chip body and a plurality of first metal columns, the first metal column is perpendicular to the first false chip body, and the first metal column is arrayed to form a low-density metal column group 210. The two end surfaces of the first metal column are the first metal column first end surface 211 and the first metal column second end surface 213. The process is as follows: take the first false wafer, and its conventional thickness range is 150-200 microns. Form the low-density metal column group 210 on the first false wafer by wafer electroplating, photoetching, etching, deposition and other wafer-level electroplating metal column process steps in sequence, the first metal column of the low-density metal column group 210 has a diameter range of 60-80 microns, a pitch range of 110-140 microns, and is vertically distributed with the first false wafer, and its material is preferably copper. The back surface of the first false wafer is ground and thinned, and then cut into a plurality of first false chip monomers. The thickness of the first false chip body is ≤ the current thickness of the LSI chip body 101-target thickness of the LSI chip body 101.

[0078] Step three, see Figure 6CAs shown, a second dummy chip monomer with high-density copper pillars is made, which includes a second dummy chip body and a plurality of second metal pillars vertically arranged on the second dummy chip body, forming a high-density metal pillar group 230. The two end faces of the second metal pillars include a second metal pillar first end face 231 and a second metal pillar second end face 233, respectively. The process is as follows: take a second dummy wafer, which has a conventional thickness ranging from 150 microns to 200 microns. The high-density metal pillar group 230 is formed on the second dummy wafer through wafer electroplating, photolithography, etching, and deposition, etc. The diameter of the second metal pillars ranges from 50 microns to 60 microns, the pitch ranges from 100 microns to 110 microns, and the material is preferably copper. The back of the second dummy wafer is ground and thinned, and then cut into a plurality of second dummy chip monomers. The thickness of the second dummy chip body is ≤ the current thickness of the LSI chip body 101 - the target thickness of the LSI chip body 101.

[0079] In order to obtain second metal pillars with smaller diameter and smaller pitch, a photoresist capable of forming a larger aspect ratio needs to be selected, and a CD size with smaller resolution needs to be used.

[0080] Step four, see Figure 6D As shown, a carrier 400 is prepared, and a thermal release film 410 is attached to the carrier 400. The carrier 400 can be a wafer carrier or a conventional metal carrier.

[0081] Step five, see Figure 6D and Figure 6E As shown, the LSI chip monomers, the first dummy chip monomers, and the second dummy chip monomers are sequentially mounted on the carrier 400. Specifically, four LSI chip monomers are sequentially mounted on the front side of the carrier 400, the first dummy chip monomers are arranged on the outer side of the LSI chip monomers, and the second dummy chip monomers are arranged on the inner side of the adjacent two LSI chip monomers.

[0082] Step six, see Figure 6F As shown, the LSI chip monomers, the first dummy chip monomers, and the second dummy chip monomers are encapsulated with an encapsulating material to form a first plastic package 301.

[0083] Step seven, see Figure 6G As shown, the first plastic package 301 is separated from the carrier 400 by a heating debonding process, exposing a separation surface. During heating, the thermal release film 410 is debonded in a foamed layer foaming and peeling manner.

[0084] Step eight, see Figure 6HAs shown, by thinning process, the first plastic package 301 is thinned in parallel to form the first plastic package front surface 310 and the first plastic package back surface 330. The first plastic package 301 removes the first dummy chip body of the first dummy chip monomer and the second dummy chip body of the second dummy chip monomer, respectively leaving the low-density metal column group 210 and the high-density metal column group 230, while removing part of the thickness of the LSI chip body, so that the thickness of the LSI chip body is reduced to the target thickness: 40 microns, forming a thinned body. Of course, the target thickness of the LSI chip body 101 can also be determined according to the actual needs of the product. The two ends of the first metal column of the low-density metal column group 210 and the second metal column of the high-density metal column group 230 can also be appropriately modified. The thinned body exposes the first end surface 211 of the first metal column of the low-density metal column group 210, the first end surface 213 of the first metal column, and the first end surface 231 of the second metal column of the high-density metal column group 230, the first end surface 233 of the second metal column, as well as the back surface of the LSI chip body and the outer end surface 123 of the LSI chip lower metal column. The thinned body also reduces the height of the adjacent low-density metal column group and high-density metal column group, which can improve the corresponding electrical performance (because a shorter metal column height means less loss).

[0085] Step nine, see Figure 6I and Figure 6J As shown, a first redistribution metal layer 510 is formed on the first plastic package front surface 310 using a redistribution process. The first redistribution metal layer 510 is disposed on the front surface of the plastic package 301, and the metal layer thereof is electrically connected to the outer end surface 123 of the LSI chip lower metal column, the first end surface 211 of the first metal column of the low-density metal column group 210, and the first end surface 231 of the second metal column of the high-density metal column group 230, respectively. The outermost layer of the first redistribution metal layer 510 is a passivation layer, and a first signal port 511 is provided thereon. Specifically, the first signal port 511 specifically includes a signal terminal array, a pad, or an opening, etc. Those skilled in the art can select according to the modules to be connected, and no specific limitation is made. Figure 6J The pad is shown in the middle. The functional chip is selectively fixed to the pad through the metal column under the chip, and is plasticized with an encapsulating material to form a further packaging structure, and only the back surface of the functional chip is exposed for heat dissipation.

[0086] Step ten, see Figure 6I and Figure 6JAs shown, the second redistribution metal layer 530 is formed on the back of the first plastic package 330 by a redistribution process. The second redistribution metal layer 530 is arranged on the back of the plastic package 301, and the metal layer thereof is respectively electrically connected with the back 130 of the LSI chip body, the second end surface 213 of the first metal column of the low-density metal column group 210, and the second end surface 233 of the second metal column of the high-density metal column group 230. The outermost layer of the second redistribution metal layer 530 is a passivation layer, and a second signal port 531 is arranged thereon. Specifically, the first signal port 531 specifically includes a signal terminal array, a pad, or an opening, etc. Those skilled in the art can select according to the modules to be connected, and no specific limitation is made. In the figure, the pad is shown by way of example, and the solder ball is selectively fixed with the pad, such as Figure 6J As shown, the second redistribution metal layer 530 is formed on the back of the first plastic package 330 by a redistribution process. The second redistribution metal layer 530 is arranged on the back of the plastic package 301, and the metal layer thereof is respectively electrically connected with the back 130 of the LSI chip body, the second end surface 213 of the first metal column of the low-density metal column group 210, and the second end surface 233 of the second metal column of the high-density metal column group 230. The outermost layer of the second redistribution metal layer 530 is a passivation layer, and a second signal port 531 is arranged thereon. Specifically, the first signal port 531 specifically includes a signal terminal array, a pad, or an opening, etc. Those skilled in the art can select according to the modules to be connected, and no specific limitation is made. In the figure, the pad is shown by way of example, and the solder ball is selectively fixed with the pad, such as

[0087] The above is only the preferred embodiment of the present application, but the protection scope of the present application is not limited to this. Any change or replacement within the technical range disclosed by the embodiments of the present application can be easily thought by those skilled in the art, and should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A forming process for an LSI chip packaging structure, the implementation steps of which are as follows: Step 1: Fabricate an LSI chip unit, which includes an LSI chip body (101) and an LSI chip under metal pillar (121) disposed on its front side; Step 2: Fabricate a first dummy chip unit with low-density copper pillars. The first dummy chip unit includes a first dummy chip body and several first metal pillars. The first metal pillars are perpendicular to the first dummy chip body to form a low-density metal pillar group (210). The thickness of the first dummy chip body is ≤ the current thickness of the LSI chip body (101) - the target thickness of the LSI chip body (101). Step 3: Fabricate a second dummy chip unit with high-density copper pillars. The second dummy chip unit includes a second dummy chip body and several second metal pillars. The second metal pillars are perpendicular to the second dummy chip body to form a high-density metal pillar group (230). The thickness of the second dummy chip body is ≤ the current thickness of the LSI chip body (101) - the target thickness of the LSI chip body (101). Step 4: Prepare a carrier (400), and attach a heat-release film (410) to the carrier (400); Step 5: The LSI chip unit, the first dummy chip unit, and the second dummy chip unit are sequentially mounted onto the carrier (400). There is an even number of LSI chip units. The first dummy chip unit is located in the outer region of the LSI chip unit, and the second dummy chip unit is located in the inner region of two adjacent LSI chip units. Step 6: Encapsulate the LSI chip unit, the first dummy chip unit, and the second dummy chip unit with encapsulation material to form the first molding compound (301); Step 7: The first encapsulated body (301) is separated from the carrier (400) by a heating debonding process, exposing the separation surface; Step 8: Through a thinning process, the first molding compound (301) is cut in parallel to form the front side (310) and the back side (330) of the first molding compound. The first molding compound (301) removes the first dummy chip body of the first dummy chip and the second dummy chip body of the second dummy chip, leaving a low-density metal pillar group (210) and a high-density metal pillar group (230), respectively. At the same time, part of the back side thickness of the LSI chip body (101) is removed to form a thinned body of the LSI chip body (101) to achieve the target thickness of the LSI chip body (101). Step nine: A redistribution process is used on the front side (310) of the first molding compound to form a first redistribution metal layer (510). The first redistribution metal layer (510) is disposed on the front side of the molding compound (301), and its metal layer is electrically connected to the metal pillars (121) under the LSI chip, the first metal pillars of the low-density metal pillar group (210), and the second metal pillars of the high-density metal pillar group (230), respectively. The outermost layer of the first redistribution metal layer (510) is a passivation layer and is provided with a first signal port (511). Step 10: A redistribution process is used on the back side (330) of the first molding compound to form a second redistribution metal layer (530). The second redistribution metal layer (530) is disposed on the back side of the molding compound (301), and its metal layer is electrically connected to the back side (130) of the LSI chip body, the first metal pillar of the low-density metal pillar group (210), and the second metal pillar of the high-density metal pillar group (230), respectively. The outermost layer of the second redistribution metal layer (530) is a passivation layer and is provided with a second signal port (531).

2. The forming process according to claim 1, characterized in that, In step two, the fabrication of the first dummy chip unit with low-density copper pillars is specifically as follows: take the first dummy wafer, and form a low-density metal pillar group (210) on the first dummy wafer by sequentially performing wafer-level electroplating metal pillar processes such as wafer electroplating, photolithography, etching, and deposition; then thin the back side of the first dummy wafer by grinding, and then cut it into multiple first dummy chip units.

3. The forming process according to claim 2, characterized in that, The first metal column of the low-density metal column group (210) has a diameter ranging from 60 micrometers to 80 micrometers and a spacing ranging from 110 micrometers to 140 micrometers.

4. The forming process according to claim 3, characterized in that, In step three, the fabrication of the second dummy chip unit with high-density copper pillars is specifically as follows: a second dummy wafer is taken, and a high-density metal pillar group (230) is formed on the second dummy wafer by sequentially performing wafer-level electroplating metal pillar processes such as wafer electroplating, photolithography, etching, and deposition; then the back side of the second dummy wafer is thinned by grinding and then cut into multiple second dummy chip units.

5. The forming process according to claim 4, characterized in that, The diameter of the second metal column of the high-density metal column group (230) ranges from 50 micrometers to 60 micrometers, and the spacing ranges from 100 micrometers to 110 micrometers.

6. The forming process according to any one of claims 1 to 4, characterized in that, The aspect ratio of the photoresist of the first metal pillar of the low-density metal pillar group (210) is less than the aspect ratio of the photoresist of the second metal pillar of the high-density metal pillar group (230), and the minimum resolution feature size of the photoresist resolution of the first metal pillar of the low-density metal pillar group (210) is greater than the minimum resolution feature size of the photoresist resolution of the second metal pillar of the high-density metal pillar group (230).

7. The forming process according to claim 6, characterized in that, The LSI chip packaging structure includes an even number of LSI chip bodies (101). The LSI chip body (101) includes an LSI chip body front side (110) and an LSI chip body back side (130) opposite to it. The LSI chip body front side (110) is provided with LSI chip under metal pillars (121). It also includes a low-density metal column cluster (210), a high-density metal column cluster (230), a first redistribution metal layer (510), and a second redistribution metal layer (530); The low-density metal pillar group (210) is disposed in the outer region of the LSI chip body (101). The low-density metal pillar group (210) is composed of several first metal pillars, which are parallel to the lower metal pillar (121) of the LSI chip. The high-density metal pillar group (230) is disposed in the inner region of two adjacent LSI chip bodies (101). The high-density metal pillar group (230) is composed of several second metal pillars, which are parallel to the lower metal pillar (121) of the LSI chip respectively. The diameter range of the second metal column is less than the diameter range of the first metal column, and the spacing range of the second metal column is less than the spacing range of the first metal column; The encapsulating material encapsulates the LSI chip body (101), the LSI chip under metal pillar (121), the low-density metal pillar group (210), and the high-density metal pillar group (230) to form a molded body (301). The front and back sides of the molded body (301) are both thinned in parallel, exposing only the upper and lower ends of the first metal pillar, the upper and lower ends of the second metal pillar, the back side of the LSI chip body (101), and the outer end face (123) of the LSI chip under metal pillar. The first redistribution metal layer (510) is disposed on the front side of the molding compound (301), electrically connected to the first metal pillar, the second metal pillar and the lower metal pillar (121) of the LSI chip, and is provided with a first signal port (511); the second redistribution metal layer (530) is disposed on the back side of the molding compound (301), electrically connected to the first metal pillar, the second metal pillar and the back side (130) of the LSI chip body, and is provided with a second signal port (531).

8. The forming process according to claim 7, characterized in that, The number of LSI chip bodies (101) is ≥2.

9. The forming process according to claim 8, characterized in that, It also includes several SOC chips (610) and several HBM chips (630). The SOC chips (610) are distributed in the center, and the HBM chips (630) are distributed around the SOC chips (610). The SOC chips (610) are electrically connected to all LSI chip bodies (101) through a first redistribution metal layer (510) and electrically connected to a second redistribution metal layer (530) through a high-density metal pillar group (230). The HBM chips (630) are selectively electrically connected to the LSI chip bodies (101) through the first redistribution metal layer (510) and selectively electrically connected to the low-density metal pillar group (210) and the second redistribution metal layer (530).

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