Deep and shallow trench isolation structure and process

Abstract

The invention relates to a deep and shallow trench isolation structure and process, and the process comprises the steps: providing a substrate, and depositing a multifunctional layer on the surface of the substrate; forming a first pattern on a partial region of the multifunctional layer through a photoetching technology; etching for the first time by using the first pattern, removing a part of material of the multifunctional layer and etching the substrate to form a shallow trench structure, and removing the first pattern mask; forming a second pattern on the non-etched region through the photoetching technology again; performing second etching by using the second pattern, removing the multifunctional layer in an unetched region to the surface of the substrate, and removing the second pattern mask; and under the protection effect of the multifunctional layer, carrying out third etching on the exposed region, and processing the exposed region to a designed depth to form a shallow trench structure and a deep trench structure with different depths. According to the invention, the height difference of the etching stop layer after STI etching in different areas is eliminated, so that the subsequent oxide filling and chemical mechanical polishing processes are easy to control, and the quality of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing, and specifically relates to a deep and shallow trench isolation structure and process, in particular to a technology for improving the height difference of an etch stop layer in deep and shallow trench processing, and for realizing high-precision deep and shallow trench isolation in integrated circuits. Background Art

[0002] Silicon trench isolation (STI) technology is an isolation process widely used in semiconductor manufacturing, mainly used to isolate different device areas in an integrated circuit to reduce electrical interference between devices. Traditional silicon trench isolation technology usually includes the combined processing of shallow trenches and deep trenches. However, the following problems still exist in the prior art:

[0003] In the process of processing deep trenches and shallow trenches, due to the difference in etching times and etching processes, there is often a height difference between the etch stop layer (such as silicon nitride layer) in the deep trench area and the shallow trench area. This height difference affects the uniformity of subsequent oxide filling and causes defects in the chemical mechanical polishing (CMP) process, reducing product quality.

[0004] Therefore, how to effectively reduce the height difference of the etch stop layer and improve the deep trench processing accuracy becomes a key issue in silicon trench isolation technology. Summary of the invention

[0005] The present invention relates to a deep and shallow trench isolation process and a deep and shallow trench isolation structure prepared therefrom, aiming to solve the problems of excessive height difference of the etch stop layer and insufficient processing precision of the deep and shallow trenches in the prior art. The present invention eliminates the height difference of the etch stop layer after STI etching in different regions by combining photolithography technology and multi-stage etching process, making the subsequent oxide filling and chemical mechanical polishing processes easy to control, thereby improving the device quality.

[0006] Specifically, the present invention forms a shallow groove area by the first etching, removes the multifunctional layer in the unetched area by the second etching, and further processes the deep and shallow grooves to the designed depth by the third etching. At the same time, the uniformity of the deep and shallow grooves and the optimization of the sidewall morphology can be achieved by controlling the etching parameters. The process flow of the present invention is simplified and the etching precision is high. The deep and shallow trench isolation structure finally formed is suitable for integrated circuit manufacturing, and especially exhibits excellent performance in high-density device isolation.

[0007] According to a first aspect of the present invention, a deep and shallow trench isolation process is provided, comprising the following steps:

[0008] Providing a substrate, and depositing a multifunctional layer on the surface of the substrate, including an isolation layer and an etch stop layer;

[0009] forming a first pattern on a partial area of ​​the multifunctional layer by photolithography;

[0010] Performing a first etching using the first pattern to remove part of the material of the multifunctional layer and to etch the substrate to form a shallow trench structure, and removing the first pattern mask;

[0011] forming a second pattern on the unetched area again by photolithography technology;

[0012] Performing a second etching using the second pattern to remove the multifunctional layer in the unetched area to the substrate surface, and removing the second pattern mask;

[0013] Under the selective protection of the etch stop layer, the exposed area is etched for the third time and processed to a designed depth to form shallow trench and deep trench structures with different depths.

[0014] In some technical solutions, the specific steps of forming the first pattern on a partial area of ​​the multifunctional layer by photolithography technology are:

[0015] uniformly coating a photoresist on the surface of the multifunctional layer;

[0016] Exposing the photoresist through a photomask to transfer the deep groove area pattern to the photoresist layer C;

[0017] The exposed photoresist is developed to form a photoresist pattern corresponding to the deep trench area.

[0018] In some technical solutions, the specific steps of forming the second pattern again by photolithography on the unetched area are:

[0019] uniformly coating a photoresist on the surface of the multifunctional layer;

[0020] The photoresist is exposed through a photomask to transfer the shallow groove area pattern to the photoresist layer D;

[0021] The exposed photoresist is developed to form a photoresist pattern corresponding to the shallow trench area.

[0022] In some technical solutions, the first etching, the second etching and the third etching are all performed by wet etching, dry etching or a combination thereof.

[0023] In some technical solutions, the step of removing the first pattern mask and the second pattern mask includes:

[0024] A wet cleaning process is used to selectively dissolve the photoresist using an acidic or alkaline solution;

[0025] Combined with the plasma ashing process, the photoresist remaining on the surface of the multifunctional layer is completely removed to avoid contamination of subsequent processing areas;

[0026] After cleaning, the surface of the multifunctional layer is dried to ensure the cleanliness of the processing area.

[0027] In some technical solutions, during the third etching process, the uniformity and side wall angles of the deep and shallow grooves are controlled by controlling the etching gas flow ratio, etching time and power.

[0028] In some technical solutions, the isolation layer is made of silicon dioxide material, has electrical isolation performance, and is formed by a chemical vapor deposition process;

[0029] The etching stop layer is made of silicon nitride material, has selective etching protection performance, and is formed by a plasma enhanced chemical vapor deposition process.

[0030] Some technical solutions also include the following steps:

[0031] Filling the shallow trench and the deep trench with oxide material to form an isolation region;

[0032] polishing the oxide surface using a chemical mechanical polishing process to remove excess oxide and expose the etch stop layer;

[0033] The etch stop layer is removed to obtain a complete isolation structure.

[0034] According to another aspect of the present invention, a deep and shallow trench isolation structure is further provided, which is prepared by the above-mentioned deep and shallow trench isolation process, comprising:

[0035] A substrate having a surface having a shallow trench region and a deep trench region;

[0036] The isolation structure is filled in the shallow trench area and the deep trench area to provide electrical isolation.

[0037] As a preferred solution, the deep and shallow trench isolation structure is applied to device isolation in integrated circuit manufacturing.

[0038] The present invention adopts the above technical solution to have at least the following beneficial effects:

[0039] 1. The present invention optimizes the etching steps and adopts a three-stage etching process to achieve independent processing of shallow grooves and deep grooves without adding an additional mask layer. The unetched area is etched to the surface of the Si substrate by the second etching to form a uniform initial reference surface; then the third etching is performed using the silicon nitride layer as a mask to further process the deep and shallow groove areas. This design effectively eliminates the problem of silicon nitride height differences caused by differences in etching depth in different areas, significantly improves the flatness between deep and shallow groove areas, and provides a stable foundation for subsequent filling and CMP processes;

[0040] 2. The present invention adopts a phased etching strategy in deep trench processing, which significantly improves the uniformity of STI trench oxide filling. After the second and third etchings, the sidewall morphology of the deep and shallow trenches is more regular, reducing the thickness difference of the filling material in the deep trench and the shallow trench, and avoiding the gap or material accumulation problem caused by uneven filling in the traditional process. In addition, the flatness after oxide filling directly improves the uniformity of the CMP (chemical mechanical polishing) process, effectively reducing the risk of local over-polishing or residue, and providing protection for the overall performance of the isolation structure;

[0041] 3. The present invention makes full use of the existing mask design of the etching process, avoiding the addition of an additional mask layer, thereby reducing the number of times the photolithography mask is used during the manufacturing process. The second etching is precisely controlled to stop at the surface of the Si substrate, and the third etching is performed using silicon nitride as a natural mask layer, which not only ensures the etching accuracy, but also avoids additional process steps, significantly reducing the overall manufacturing cost. At the same time, this process strategy reduces resource consumption and operational complexity in device manufacturing, and improves production efficiency;

[0042] 4. The design of the three-step etching process of the present invention combines different etching targets and protection measures at each stage to ensure the flexibility and high controllability of the process. In the second etching, the processing benchmarks of the deep and shallow trench areas are defined by precisely stopping on the surface of the Si substrate; and in the third etching, the deep trench is further processed to the designed depth by adjusting the etching gas flow, time and power, while the selective protection function of silicon nitride is used to avoid over-processing of the shallow trench area. This step-by-step strategy significantly improves the processing accuracy and consistency of the deep and shallow trench isolation structure;

[0043] 5. The present invention improves the process to make the isolation structure of the deep and shallow trench areas more regular and flat, reducing the possibility of local stress concentration and electrical interference. The uniformity of oxide filling and the smooth surface after CMP jointly ensure the stability of device isolation and avoid device failure caused by manufacturing defects. In addition, this process strategy is applicable to a variety of semiconductor manufacturing scenarios, especially in the isolation processing of high-density integrated circuits and three-dimensional memories, showing significant advantages, and comprehensively improving device performance and long-term reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings and their marks required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 A schematic diagram of a structure in which a shallow trench pattern is defined by photolithography in a conventional silicon trench isolation process;

[0046] Figure 2 A schematic diagram of forming a shallow trench structure in a conventional silicon trench isolation process;

[0047] Figure 3 A schematic diagram of a structure in which a deep trench pattern is defined by photolithography technology in a conventional silicon trench isolation process;

[0048] Figure 4 A schematic diagram of forming a deep trench structure in a conventional silicon trench isolation process;

[0049] Figure 5 A schematic diagram of completing a deep and shallow trench structure in a conventional silicon trench isolation process;

[0050] Figure 6 A flowchart of a deep and shallow trench isolation process according to an embodiment of the present invention;

[0051] Figure 7 It is a schematic diagram of a structure for forming a first pattern according to an embodiment of the present invention;

[0052] Figure 8 This is a schematic diagram of the structure of performing the first etching according to the embodiment of the present invention;

[0053] Fig. 9 This is a schematic diagram of a structure for forming a second pattern and performing a second etching according to an embodiment of the present invention;

[0054] Fig.10 It is a structural schematic diagram of removing the second pattern mask according to an embodiment of the present invention;

[0055] Fig.11 This is a schematic diagram of the structure of performing the third etching as described in the embodiment of the present invention.

[0056] The meanings of the symbols in the figure are as follows:

[0057] 10—silicon substrate, 20—isolation layer, 30—etching stop layer, 41—photoresist layer A, 42—photoresist layer B, 43—photoresist layer C, 43—photoresist layer D. DETAILED DESCRIPTION

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0059] In order to simplify the drawings, only the parts related to the invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0060] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0061] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0062] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0063] In the traditional silicon trench isolation technology, the processing requirements of shallow trenches and deep trenches are different, and the traditional process is realized through two lithography and etching steps. However, due to the difference in the etching depth designed for the shallow trench and deep trench areas, after the second etching in the deep trench area, the etch stop layer 30 (such as a silicon nitride layer) produces a significant height difference between the two areas. This height difference has an adverse effect on the subsequent oxide filling and planarization processing. The following is a detailed description of the process method:

[0064] Step 11, depositing an isolation layer 20 and an etch stop layer 30 on the surface of the silicon substrate 10 in sequence. The isolation layer 20 is usually made of silicon dioxide (SiO2) material, and its function is to provide electrical isolation and prevent signal interference between different device regions. The etch stop layer 30 is usually made of silicon nitride (Si3N4), and its main function is to protect the silicon substrate 10 and the isolation layer 20 from damage during the subsequent etching process, and to provide mechanical support during the chemical mechanical polishing (CMP) stage. Both the isolation layer 20 and the etch stop layer 30 are formed by chemical vapor deposition (CVD) method to ensure the thickness uniformity and process stability of the material.

[0065] Step 12, defining a pattern of a shallow groove region on the surface of the etch stop layer 30 by photolithography, referring to Figure 1 The specific steps include coating photoresist, exposing through a photomask, and developing to form a photolithography pattern corresponding to the shallow groove.

[0066] Step 13, such as Figure 2 As shown, under the protection of the photolithography pattern, dry etching (such as reactive ion etching, RIE) is used to remove the etch stop layer 30 and part of the silicon substrate material in the shallow trench area to form a shallow trench of designed depth. After the shallow trench etching is completed, the photoresist layer A41 is removed by wet cleaning or plasma ashing to expose the shallow trench structure, providing a basis for subsequent deep trench processing.

[0067] Step 14, after the shallow groove processing is completed, the photoresist is coated again and the pattern of the deep groove area is defined on the surface of the etch stop layer 30 by photolithography technology, referring to Figure 3 Through exposure and development, the deep groove pattern is transferred to the photoresist layer B42, providing a processing basis for subsequent deep groove etching.

[0068] Step 15, such as Figure 4 As shown, during the deep trench etching process, the deep trench region is etched twice using the silicon nitride layer (ie, the etching stop layer 30) as a mask to remove the silicon substrate material to a designed depth below the shallow trench, thereby forming a complete deep trench structure; finally, as shown in FIG. Figure 5 As shown, the photoresist layer B42 is removed by wet cleaning or other processes.

[0069] During the secondary etching of the deep trench, the etching of the shallow trench area has been completed, so the etch stop layer 30 of the shallow trench is protected, while the etch stop layer 30 of the deep trench area is exposed on the surface. This difference in etching steps results in the etch stop layer 30 in the shallow trench area maintaining its original thickness, while the thickness of the etch stop layer 30 in the deep trench area is reduced due to the longer exposure time, thereby forming a significant height difference between the shallow trench and deep trench areas. This height difference has many effects on subsequent processes.

[0070] First, in the subsequent silicon dioxide oxide filling process, the height difference of the etch stop layer 30 causes uneven distribution of the filling material in the shallow trench and deep trench areas, increasing the risk of local defects and affecting the final isolation performance. Second, in the chemical mechanical polishing (CMP) stage, the height difference exacerbates the difficulty of surface flattening, ultimately leading to surface unevenness and reduced device performance.

[0071] In addition, it is difficult for traditional processes to balance depth control and sidewall morphology optimization in deep trench etching. Over-etching may cause the sidewall to tilt excessively, while under-etching will prevent the deep trench from reaching the target depth, affecting the isolation effect. These problems not only limit the manufacturing efficiency of high-density integrated circuits, but also significantly increase process complexity and production costs.

[0072] In summary, although the two-time photolithography and etching process of the prior art can complete the processing of shallow grooves and deep grooves, it still has obvious deficiencies in the height difference control of the etch stop layer 30, the depth accuracy of the deep groove and the optimization of the sidewall morphology. These technical bottlenecks have become the main motivation for the present invention to improve the deep groove processing technology. By adjusting and optimizing the etching steps, the present invention fundamentally solves the above problems, and the specific implementation methods will be described in detail in the subsequent content.

[0073] According to an embodiment of the present invention, a deep and shallow trench isolation process is provided. By combining photolithography technology and a multi-stage etching process, the difference in etching depth in different regions is eliminated, the filling of the STI trench and the uniformity of the CMP process are optimized, and the device quality is improved. The following is a detailed description of the specific implementation steps:

[0074] Step 1: Providing a silicon substrate 10 and depositing a multifunctional layer

[0075] Multifunctional layers are sequentially deposited on a standard silicon substrate 10. The multifunctional layer includes two parts: an isolation layer 20 and an etch stop layer 30, which work together to process deep and shallow grooves. The isolation layer 20 is usually made of silicon dioxide (SiO2) material, which has good electrical isolation performance and can effectively isolate different device areas. The isolation layer 20 is deposited by a chemical vapor deposition (CVD) method to meet the etching requirements of deep and shallow grooves.

[0076] The etching stop layer 30 is usually made of silicon nitride (Si3N4), which has excellent selective etching protection performance. During the deposition process, silicon nitride can be deposited by a plasma enhanced chemical vapor deposition (PECVD) process.

[0077] When selecting materials, other materials with similar properties may be used as substitutes according to specific requirements. For example, the isolation layer 20 may be made of silicon nitride (Si3N4), and the etch stop layer 30 may be made of silicon carbide (SiC) or other materials with good selectivity.

[0078] Step 2: If Figure 7 As shown, the first pattern is formed

[0079] The first pattern is formed by photolithography. The multifunctional layer surface is uniformly coated with photoresist to ensure uniform coating thickness. The photoresist is usually coated by spin coating. The photoresist is exposed through a photomask so that the pattern of the deep groove area is accurately transferred to the photoresist layer C43. After exposure,

[0080] After the development step, a photoresist pattern corresponding to the deep groove area is obtained.

[0081] When choosing a photoresist, different types of photoresists can be selected according to the process requirements. For example, positive photoresist or negative photoresist can be used for this step, but positive photoresist is generally more common in integrated circuit manufacturing because it can provide higher resolution.

[0082] Step 3: If Figure 8 As shown, the first etching

[0083] The first etching is performed using the first pattern mask to remove part of the multifunctional layer and etch the substrate. The etching stop layer 30 and the isolation layer material of the multifunctional layer are removed by dry etching (such as reactive ion etching RIE) or wet etching (such as hydrofluoric acid etching), and the substrate is etched to form a shallow trench structure.

[0084] The accuracy of this etching step is critical to the subsequent steps, so it is necessary to precisely control the etching parameters, such as gas flow, power, and time, to ensure that the depth and shape of the groove meet the design requirements. Depending on different processing requirements, dry etching or wet etching can be selected. Dry etching is suitable for precise control of sidewalls and depth, while wet etching is usually used in large areas or areas that do not require high precision.

[0085] After the first etch is completed, the photoresist mask is removed and the residual photoresist is completely removed using a solvent or plasma ashing to ensure cleanliness in subsequent steps.

[0086] Step 4: Fig. 9 As shown, a second pattern is formed

[0087] After the first etching, for the unetched area, it is necessary to form a second pattern again by photolithography. This process is similar to step 2. The photoresist is exposed through a photomask so that the pattern of the shallow groove area is accurately transferred to the photoresist layer D44. After exposure, after the development step, a photoresist pattern corresponding to the shallow groove area is obtained. The formation of the second pattern ensures the accurate division of the deep and shallow groove areas, so that the deep groove area is protected in the second etching.

[0088] Depending on the needs, different designs of photomasks can be selected to optimize the pattern accuracy and etching effect.

[0089] Step 5: Perform the second etching

[0090] like Fig. 9 As shown, a second etching is performed using the second pattern to remove the multifunctional layer in the unetched area to the surface of the silicon substrate 10. At this time, the depth of the designed shallow groove area is preliminarily processed, and it is ensured that the deep groove area is not etched. To this end, a selective etching process (such as plasma etching or wet etching) is used to accurately remove the multifunctional layer.

[0091] The etching stop point needs to be strictly controlled in this stage to prevent over-etching into the shallow trench area and causing unnecessary damage. Since the second etching still needs to maintain high selectivity, a highly selective etching gas combination (such as CHF3, O2, etc.) can be used to avoid affecting the shallow trench.

[0092] In this step, if Fig.10 The steps of removing the second pattern mask are similar to those of the first pattern mask, and are removed by wet cleaning or plasma ashing.

[0093] Step 6: Fig.11 As shown, the third etching is performed

[0094] Under the protection of the multifunctional layer, the exposed area is etched for the third time. The goal of this etching step is to further process the initially processed deep trenches and shallow trenches to the designed depth. In this step, the self-masking SiN layer is used as a mask layer.

[0095] The third etching usually uses deep reactive ion etching (DRIE) technology, and the depth control accuracy is very critical. In this process, by adjusting the etching gas flow, etching time and power, the precise depth control of the deep and shallow trench areas is achieved, and the sidewall morphology of the deep and shallow trenches is optimized to ensure their verticality and uniformity.

[0096] Step 7: Oxide filling and CMP treatment

[0097] After all etching steps are completed, oxide materials (such as SiO2) are filled into shallow trenches and deep trenches to form electrical isolation areas. The filling process uses chemical vapor deposition (CVD) technology to ensure that the oxide material is evenly distributed in each trench.

[0098] Afterwards, a chemical mechanical polishing (CMP) process is used to planarize the oxide surface, remove excess oxide, expose the etch stop layer 30, ensure a smooth surface, and provide a stable substrate for subsequent processes (such as metallization or deposition of other layers).

[0099] Step 8: Finally remove the etch stop layer 30 to complete the preparation of the deep and shallow trench isolation structure.

[0100] This embodiment uses a three-stage etching process, combined with the selective protection function of the etching stop layer 30 and the natural mask, to eliminate the height difference, improve the uniformity of filling, and significantly reduce the cost in the deep and shallow trench isolation process. It not only improves the flatness and processing accuracy of the isolation structure, but also significantly improves the device performance while significantly optimizing the cost-effectiveness of the manufacturing process, providing reliable and economical technical support for applications such as high-density integrated circuits.

[0101] According to another embodiment of the present invention, based on the former embodiment, a deep trench isolation structure is further provided, including: a silicon substrate 10, whose surface has a shallow trench area and a deep trench area; an isolation structure filled in the shallow trench area and the deep trench area to provide electrical isolation.

[0102] The trench isolation structure of this embodiment is applicable to a variety of semiconductor manufacturing scenarios, and in particular exhibits outstanding technical advantages in the manufacturing of high-density integrated circuits, power devices, and memories.

[0103] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims

1. A deep and shallow trench isolation process, characterized in that: The following steps are involved: Providing a substrate, and depositing a multifunctional layer on the surface of the substrate, including an isolation layer and an etch stop layer; forming a first pattern on a partial area of ​​the multifunctional layer by photolithography; Performing a first etching using the first pattern to remove part of the material of the multifunctional layer and to etch the substrate to form a shallow trench structure, and removing the first pattern mask; forming a second pattern on the unetched area again by photolithography technology; Performing a second etching using the second pattern to remove the multifunctional layer in the unetched area to the substrate surface, and removing the second pattern mask; Under the selective protection of the etch stop layer, the exposed area is etched for the third time and processed to a designed depth to form shallow trench and deep trench structures with different depths.

2. The deep and shallow trench isolation process according to claim 1, characterized in that: The specific steps of forming the first pattern on a partial area of ​​the multifunctional layer by photolithography technology are as follows: uniformly coating a photoresist on the surface of the multifunctional layer; Exposing the photoresist through a photomask to transfer the deep groove area pattern to the photoresist layer C; The exposed photoresist is developed to form a photoresist pattern corresponding to the deep trench area.

3. The deep and shallow trench isolation process according to claim 1, characterized in that: The specific steps of forming the second pattern again by photolithography on the unetched area are: uniformly coating a photoresist on the surface of the multifunctional layer; The photoresist is exposed through a photomask to transfer the shallow groove area pattern to the photoresist layer D; The exposed photoresist is developed to form a photoresist pattern corresponding to the shallow trench area.

4. The deep and shallow trench isolation process according to claim 1, characterized in that: The first etching, the second etching and the third etching are all performed by wet etching, dry etching or a combination thereof.

5. The deep and shallow trench isolation process according to claim 1, characterized in that: The step of removing the first pattern mask and the second pattern mask comprises: A wet cleaning process is used to selectively dissolve the photoresist using an acidic or alkaline solution; Combined with the plasma ashing process, the photoresist remaining on the surface of the multifunctional layer is completely removed to avoid contamination of subsequent processing areas; After cleaning, the surface of the multifunctional layer is dried to ensure the cleanliness of the processing area.

6. The deep and shallow trench isolation process according to claim 1, characterized in that: During the third etching process, the uniformity and side wall angle of the deep and shallow grooves are regulated by controlling the etching gas flow ratio, etching time and power.

7. The deep and shallow trench isolation process according to claim 1, characterized in that: The isolation layer is made of silicon dioxide material, has electrical isolation performance, and is formed by a chemical vapor deposition process; The etching stop layer is made of silicon nitride material, has selective etching protection performance, and is formed by a plasma enhanced chemical vapor deposition process.

8. The deep and shallow trench isolation process according to claim 1, characterized in that: The following steps are also included: Filling the shallow trench and the deep trench with oxide material to form an isolation region; polishing the oxide surface using a chemical mechanical polishing process to remove excess oxide and expose the etch stop layer; The etch stop layer is removed to obtain a complete isolation structure.

9. A deep and shallow trench isolation structure, characterized in that: The deep and shallow trench isolation process according to claim 8 is used for preparation, comprising: A substrate having a surface having a shallow trench region and a deep trench region; The isolation structure is filled in the shallow trench area and the deep trench area to provide electrical isolation.

10. The deep and shallow trench isolation structure according to claim 9, characterized in that: Used for device isolation in integrated circuit manufacturing.

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