Connecting plate of flash memory chip and preparation method thereof, and flash memory chip

Abstract

This disclosure provides a connection board for a flash memory chip, its fabrication method, and the flash memory chip itself, relating to the field of semiconductor technology. The connection board includes: an insulating layer having opposing first and second surfaces; a semiconductor substrate disposed on the first surface of the insulating layer; and a conductive layer disposed on the second surface of the insulating layer. The conductive layer includes multiple conductive sheets of different shapes, distributed at different positions on the second surface of the insulating layer, so that the pads of the flash memory chip are coupled to external pins through the conductive sheets, thereby reducing the proportion of bonding wires across the flash memory chip. This disclosure connects signals on the pads of the flash memory chip to external pins through the conductive sheets of the conductive layer of the connection board, which can reduce the proportion of bonding wires across the flash memory chip, resulting in low wire arcing and low packaging risk.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a flash memory chip interconnect board, a method for fabricating the interconnect board, and a flash memory chip. Background Technology

[0002] In the field of semiconductor technology, static memory (such as flash memory chips) plays a crucial role in recording and storing data, and is widely used in many industries such as computers, communications, consumer electronics, and automotive electronics, becoming one of the core components of modern technology. With the continuous development of technology, the packaging design of flash memory chips is also constantly being optimized to improve performance and meet the ever-increasing application demands.

[0003] However, when the flash memory chip's pads are designed to be located on one side of the lead frame, and signals are connected to external pins outside the frame via bonding wires—for example, connecting a pad on one side of the lead frame to an external pin on the other side—this typically requires spanning more than 90% of the flash memory chip's length. This design results in excessively long and high bonding wire arcs, increasing the risk of wire breakage or collapse during packaging. Simultaneously, this structure leads to an increase in overall package thickness, thus affecting package compactness and reliability.

[0004] How to reduce the proportion of wire bonding across flash memory chips and reduce packaging risks is an urgent problem to be solved. Summary of the Invention

[0005] This disclosure provides a connection board for a flash memory chip and its fabrication method, as well as the flash memory chip itself. It reduces the cross-chip ratio to at least a certain extent, has low line arc, low packaging risk, and can also reduce packaging thickness, thereby improving packaging compactness and reliability.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a connection board for a flash memory chip is provided, comprising: an insulating layer 142 having opposing first and second surfaces; a semiconductor substrate 143 disposed on the first surface of the insulating layer 142; and a conductive layer 141 disposed on the second surface of the insulating layer 142, the conductive layer 141 comprising a plurality of conductive sheets of different shapes distributed at different positions on the second surface of the insulating layer 142, such that the pads 120 of the flash memory chip 110 are coupled to external pins 206 through the conductive sheets, thereby reducing the proportion of bonding wires crossing the flash memory chip 110.

[0008] In one embodiment of this disclosure, the insulating layer 142 includes a first insulating layer, which is a polymer material layer or an oxide layer.

[0009] In one embodiment of this disclosure, the insulating layer 142 includes: a first insulating layer having opposing first and second surfaces, wherein the second surface of the first insulating layer is the second surface of the insulating layer 142; and a second insulating layer disposed on the first surface of the first insulating layer; wherein the first insulating layer is a polymer material layer and the second insulating layer is an oxide layer.

[0010] In one embodiment of this disclosure, the connecting plate 140 further includes a third insulating layer 144 disposed on the conductive layer 141, wherein the third insulating layer 144 is a polymer material layer.

[0011] In one embodiment of this disclosure, the conductive sheet is provided with a plurality of position marks 1416, which are used to locate the bonding positions so that the conductive sheet is coupled to the pad 120 of the flash memory chip 110 or the external pin 206 at the position marks 1416.

[0012] In one embodiment of this disclosure, the width of the conductive sheet at the location mark 1416 is greater than the width of the conductive sheet at the location mark 1416 that is not marked.

[0013] In one embodiment of this disclosure, the conductive sheet includes one or more of the following: L-shaped conductive sheet 1411, I-shaped conductive sheet 1412, U-shaped conductive sheet 1413, and C-shaped conductive sheet 1414.

[0014] In one embodiment of this disclosure, the conductive sheet includes an L-shaped conductive sheet 1411, a straight conductive sheet 1412, a U-shaped conductive sheet 1413, and a U-shaped conductive sheet 1414. A plurality of L-shaped conductive sheets 1411 and a plurality of straight conductive sheets 1412 are located inside the U-shaped conductive sheet 1413, and a plurality of spaced-apart balance plates 1415 are provided at the opening of the U-shaped conductive sheet 1413.

[0015] In one embodiment of this disclosure, the semiconductor substrate 143 is a bare silicon wafer or a bare silicon wafer, and the bare silicon wafer is a P-type silicon wafer or an N-type silicon wafer.

[0016] According to another aspect of this disclosure, a flash memory chip is also provided, including a chip body and a connection board for the flash memory chip in any of the above embodiments. The connection board 140 has opposing first and second surfaces. The chip body is disposed on the first surface of the connection board 140. The connection board 140 is coupled to the chip body. The overall size of the connection board 140 is smaller than the overall size of the chip body.

[0017] In one embodiment of this disclosure, the connection board 140 is located at the center of the chip body.

[0018] In one embodiment of this disclosure, the connection plate 140 further includes: a first connection point group 201 and a second connection point group 202, the first connection point group 201 and the second connection point group 202 being disposed on a second surface of the connection plate 140 and distributed on both sides of the second surface of the connection plate 140; each of the first connection point group 201 and the second connection point group 202 includes a plurality of connection points 203, the connection points 203 being coupled to the conductive layer 141 of the connection plate 140; the chip body includes a plurality of pads 120, the plurality of pads 120 being disposed on the surface of the chip body near the first surface of the connection plate 140; the distance of the plurality of pads 120 to the first connection point group 201 is less than the distance to the second connection point group 202, and M of the plurality of pads 120 are coupled to the connection points 203 in the first connection point group 201. Connection point 203 is coupled to connection point 203 in the second connection point group 202 through the conductive layer 141; the flash memory chip 110 further includes: a first pin group 204 and a second pin group 205, the first pin group 204 and the second pin group 205 are distributed on opposite sides of the chip body, the first pin group 204 and the second pin group 205 each include a plurality of external pins 206, the distance of the first pin group 204 from the plurality of pads 120 is less than the distance of the second pin group 205 from the plurality of pads 120, K of the plurality of pads 120 are coupled to the external pins 206 in the first pin group 204, and the connection point 203 in the second connection point group 202 is coupled to the external pins 206 in the second pin group 205; wherein, M and K are both integers greater than or equal to 1, and the sum of M and K is less than or equal to the total number of the plurality of pads 120.

[0019] In one embodiment of this disclosure, the plurality of external pins 206 and the plurality of pads 120 in the first pin group 204 are uniformly distributed in a line, and the two outer pads 120 of the plurality of pads 120 are respectively coupled to the two outer external pins 206 in the first pin group 204. The plurality of external pins 206 in the first pin group 204 correspond one-to-one with the K pads 120 of the plurality of pads 120 along the length direction of the chip body, and the bonding wires between each corresponding pad 120 and the external pins 206 are parallel to the length direction of the chip body.

[0020] In one embodiment of this disclosure, the connection board 140 further includes: a plurality of connection points 203, the plurality of connection points 203 being disposed on the second surface of the connection board 140 and distributed on the outer edge of the connection board 140, the connection points 203 being coupled to the conductive layer 141 of the connection board 140; the flash memory chip 110 further includes: a first pin group 204 and a second pin group 205, the first pin group 204 and the second pin group 205 being distributed on opposite sides of the chip body, the first pin group 204 and the second pin group 205 each including a plurality of external pins 206; the chip body includes a plurality of pads 120, the plurality of pads 120 being... 20 is disposed on one side of the chip body near the first surface of the connection plate 140. The plurality of pads 120 are located between the first pin group 204 and the second pin group 205. T pads 120 of the plurality of pads 120 are coupled to a portion of the external pins 206 in the first pin group 204. E pads 120 of the plurality of pads 120 are coupled to a portion of the external pins 206 in the second pin group 205. Q pads 120 of the plurality of pads 120 are coupled to the connection point 203. Wherein, T, E and Q are all integers greater than or equal to 1, and the sum of T, E and Q is less than or equal to the total number of the plurality of pads 120.

[0021] According to another aspect of this disclosure, a method for preparing a bonding plate is also provided, comprising: providing a semiconductor substrate 143; coating an insulating layer solution on the semiconductor substrate 143 and performing a curing treatment to form an insulating layer 142; coating a photoresist on the insulating layer 142 and performing exposure, development, electroplating, photoresist removal, and etching treatment through a mask to form a conductive layer 141.

[0022] In one embodiment of this disclosure, after the insulating layer solution is coated on the semiconductor substrate 143 and cured to form the insulating layer 142, the method for preparing the connecting plate further includes: forming a connecting layer between the insulating layer 142 and the conductive layer 141; wherein the connecting layer includes a first metal layer 1610 and a second metal layer 1620, the first metal layer 1610 being made of titanium and the second metal layer 1620 being made of copper.

[0023] In one embodiment of this disclosure, the conductive layer 141 includes a plurality of conductive sheets of different shapes, including one or more of L-shaped conductive sheets 1411, I-shaped conductive sheets 1412, U-shaped conductive sheets 1413 and C-shaped conductive sheets 1414, and the conductive sheets are copper sheets.

[0024] In embodiments of this disclosure, the flash memory chip interconnect includes an insulating layer, a semiconductor substrate, and a conductive layer. The insulating layer has opposing first and second surfaces; the semiconductor substrate is disposed on the first surface of the insulating layer; the conductive layer is disposed on the second surface of the insulating layer and includes multiple conductive sheets of different shapes distributed at different positions on the second surface of the insulating layer, so that the pads of the flash memory chip are coupled to external pins through the conductive sheets, thereby reducing the proportion of the bonding wire spanning the flash memory chip. This disclosure connects signals on the pads of the flash memory chip to external pins via the conductive sheets of the conductive layer in the interconnect, for example, connecting signals from pads located on one side of the frame to external pins on the other side of the frame via the conductive sheets. This shortens the length of the bonding wire used for coupling between the pads and external pins, reduces the proportion spanning the flash memory chip, results in low wire arc, and lowers packaging risk.

[0025] Furthermore, the conductive layer includes multiple conductive sheets of different shapes, distributed at different locations on the second surface of the insulating layer. This arrangement allows the flash memory chip's pads to be coupled to external pins at any location via the conductive sheets of the connector board, thereby expanding the board's applicability. The insulating layer also reduces the risk of high-temperature leakage.

[0026] Furthermore, this disclosure reduces the package thickness and improves the compactness and reliability of the package by forming a small interconnect plate with insulating and conductive layers on a semiconductor substrate.

[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0029] Figure 1 This diagram illustrates the location of a flash memory chip and its pads.

[0030] Figure 2 This diagram illustrates the connection of a flash memory chip provided in an embodiment of the present disclosure.

[0031] Figure 3 This diagram illustrates the structure of a connection board for a flash memory chip according to an embodiment of the present disclosure.

[0032] Figure 4 A schematic diagram of the structure of a connection board for a flash memory chip provided in another embodiment of this disclosure is shown.

[0033] Figure 5 This diagram illustrates the structure of a connection board for a flash memory chip provided in another embodiment of the present disclosure.

[0034] Figure 6 This diagram illustrates the structure of a connection board for a flash memory chip according to yet another embodiment of the present disclosure.

[0035] Figure 7 This diagram illustrates the structure of a connection board for a flash memory chip according to yet another embodiment of the present disclosure.

[0036] Figure 8 This diagram illustrates the structure of a connection board for a flash memory chip according to yet another embodiment of the present disclosure.

[0037] Figure 9 This diagram illustrates the structure of a connection board for a flash memory chip according to yet another embodiment of the present disclosure.

[0038] Figure 10 A schematic diagram of the structure of a conductive layer provided in an embodiment of this disclosure is shown.

[0039] Figure 11 A schematic diagram of the structure of a conductive layer provided in another embodiment of this disclosure is shown.

[0040] Figure 12 A schematic diagram of the structure of the conductive layer provided in another embodiment of the present disclosure is shown.

[0041] Figure 13 This diagram illustrates a structural schematic of a flash memory chip connected to a connector board according to an embodiment of the present disclosure.

[0042] Figure 14 This diagram illustrates a structural schematic of a flash memory chip connected to a connector board according to an embodiment of the present disclosure.

[0043] Figure 15 The present disclosure provides a flowchart of a method for preparing a connecting plate according to an embodiment.

[0044] Figure 16 A schematic diagram illustrating the fabrication process of a connecting plate provided in an embodiment of this disclosure is shown.

[0045] The reference numerals in the attached figures are explained as follows:

[0046] 110. Flash memory chip; 120. Pad; 130. Frame; 140. Connector plate; 141. Conductive layer; 1410. Copper layer; 1411. L-shaped conductive sheet; 1412. Linear conductive sheet; 1413. U-shaped conductive sheet; 1414. U-shaped conductive sheet; 1415. Balance sheet; 1416. Position marker; 142. Insulating layer; 1421. Silicon oxide insulating layer; 1422. Polyimide layer; 143. Semiconductor substrate; 1431. Silicon substrate; 144. Third insulating layer; 201. First connection point group; 202. Second connection point group; 203. Connection point; 204. First pin group; 205. Second pin group; 206. External pin; 1610. First metal layer; 1620. Second metal layer; 1630. Photoresist layer; 1640. RDL layer. Detailed Implementation

[0047] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0048] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly stated.

[0049] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0050] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0051] As used in this disclosure, the term "semiconductor substrate 143" refers to a material on which subsequent materials are added or otherwise disposed. Semiconductor substrate 143 may also be referred to as a core layer. The material disposed on semiconductor substrate 143 (e.g., the first and second surfaces of semiconductor substrate 143) may be patterned or may remain unpatterned. Furthermore, semiconductor substrate 143 may be a silicon substrate 1431, a silicon-carbon substrate, a gallium nitride substrate, a gallium arsenide substrate, etc., and the material type of semiconductor substrate 143 may be determined according to the application scenario.

[0052] As used in this disclosure, the term "layer" refers to a portion of material comprising a region of thickness, which may extend over the entirety of the underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. Layers may extend horizontally, vertically, and / or along inclined surfaces. Semiconductor substrate 143 may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. Layers may include multiple layers. For example, insulating layer 142 may include a first insulating layer and a second insulating layer.

[0053] As used herein, a “connector plate 140” has a plurality of vertically oriented material layers on a laterally oriented semiconductor substrate 143 such that the material layers extend in a vertical direction relative to the semiconductor substrate 143. As used herein, the term “vertical / perpendicularly” refers to a surface perpendicular to the lateral surface of the semiconductor substrate 143.

[0054] As used herein, the terms “horizontal / horizontally / laterally” denote a lateral surface parallel to the semiconductor substrate 143, such as the opposing first or second surface of the insulating layer 142, i.e., the surface defined by the plane containing the first direction D1 and the second direction D2 in the figures; and the terms “vertical” or “perpendicularly” denote a direction perpendicular to the lateral surface of the insulating layer 142, such as the direction represented by the third direction D3 in the figures.

[0055] It should be noted that wire bonding refers to a type of metal wire used in the electronic packaging process to connect the flash memory chip 110 to external circuitry (such as the pins of the external circuitry, referred to as external pins 206). It can be made of materials such as gold, silver, or aluminum, and has good conductivity and a high melting point to ensure a stable electrical connection during electronic device operation.

[0056] In the field of semiconductor technology, such as Figure 1 As shown, when the pad 120 of the flash memory chip 110 is located on one side of the flash memory chip 110, and since the flash memory chip 110 is mounted on the frame 130, the pad 120 of the flash memory chip 110 is also located on one side of the frame 130. External pins 206 (pins 1, 2, 3, and 4) located on one side of the frame 130 are coupled to the pad 120 on the flash memory chip 110 via bonding wires. External pins 206 (pins 5, 6, 7, and 8) located on the other side of the frame 130 are also coupled to the pad 120 on the flash memory chip 110 via bonding wires. When these bonding wires connect signals to the external pins 206 (pins 5, 6, 7, and 8) on the other side of the frame 130, the bonding wires typically need to span more than 90% of the entire length of the flash memory chip 110. This design results in excessively long and high bonding wire arcs, increasing the risk of wire breakage or collapse during the packaging process. Simultaneously, this structure leads to an increase in the overall package thickness, thus affecting the compactness and reliability of the package.

[0057] In related technologies, the above problem is solved by modifying the flash memory chip 110 to add pads 120, which increases the size of the flash memory chip 110 and leads to increased costs.

[0058] The connection board 140 in this disclosure can be used to connect different chips, interconnect lines, and change the connection position of the pads 120 to enhance the packaging performance of the centralized circuitry. For example... Figure 2 As shown, this disclosure adds a connection board 140 to the flash memory chip 110 to connect the signal to the external pin 206 on the other side of the frame 130 instead of a long solder wire, thereby reducing the cross-flash memory chip 110 ratio.

[0059] In one embodiment, the connecting plate 140 is a substrate-type adapter plate, which is manufactured by a lamination process. For example, the lamination process can be a tenting process or a modified semi-additive process (MSAP process).

[0060] The inventors discovered that substrate-type adapter boards manufactured through lamination processes are complex in process, large in size, and not conducive to packaging. In flash memory chips 110 with high-density interconnect requirements, using substrate-type adapter boards to change the position of pads 120 cannot meet the interconnection requirements of high-performance flash memory chips 110.

[0061] To address the aforementioned issues, this disclosure provides a connection board 140 for a flash memory chip 110, comprising an insulating layer 142 having opposing first and second surfaces; a semiconductor substrate 143 disposed on the first surface of the insulating layer 142; and a conductive layer 141 disposed on the second surface of the insulating layer 142. The conductive layer 141 includes a plurality of conductive sheets of different shapes, distributed at different positions on the second surface of the insulating layer 142, so that the pads 120 of the flash memory chip 110 are coupled to external pins 206 through the conductive sheets, thereby reducing the proportion of bonding wires crossing the flash memory chip 110. This disclosure not only meets the size requirements of the flash memory chip 110 but also meets the requirements of high-density interconnection. Since the conductive layer 141 includes multiple conductive sheets distributed at different positions on the insulating layer 142, the flash memory chip 110 can connect the signals on the pads 120 of the flash memory chip 110 to external pins 206 at different positions through the conductive sheets of the conductive layer 141 of the connecting board 140 according to different needs. Moreover, the bonding wires of the external pins 206 and the connecting board 140 do not cross, thereby reducing coupling interference. This further improves the performance of the flash memory chip 110 while meeting the size requirements of the flash memory chip 110.

[0062] Furthermore, since the conductive layer 141 of the connector 140 has multiple conductive sheets with different shapes and distribution positions, the applicability of the connector 140 can be increased. In other words, the connector 140 can be used on different types of flash memory chips 110.

[0063] In this embodiment of the present disclosure, the thickness of the connecting plate 140 formed by providing an insulating layer 142 and a conductive layer 141 on the semiconductor substrate 143 is small, thereby reducing the package thickness and improving the compactness and reliability of the package.

[0064] The present disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0065] Figure 3 This diagram illustrates the structure of a connection board for a flash memory chip according to an embodiment of the present disclosure, as shown below. Figure 3 As shown, the connection board 140 of the flash memory chip 110 includes a conductive layer 141, an insulating layer 142, and a semiconductor substrate 143.

[0066] In this disclosure, the first direction D1 is the long side direction of the connecting plate 140, the second direction D2 is the short side direction of the connecting plate 140, and the third direction D3 is the thickness direction of the connecting plate 140, wherein the first direction, the second direction, and the third direction are perpendicular to each other.

[0067] The insulating layer 142 has opposing first and second surfaces; the first and second surfaces are arranged along a third direction D3. The insulating layer 142 can be an oxide layer or a polymer layer. Exemplarily, the oxide layer may be made of any one of silicon oxide (e.g., silicon dioxide), titanium oxide, aluminum oxide, zirconium oxide, copper oxide, and chromium oxide. The polymer layer may be made of any one of polyethylene, polyvinyl chloride, polytetrafluoroethylene, and polyimide. It should be noted that the oxide layer is made of an oxide material, and the polymer layer is made of a polymer material.

[0068] A semiconductor substrate 143 is disposed on the first surface of the insulating layer 142. The semiconductor substrate 143 serves as a support portion of the connecting plate 140, supporting other connecting layers (such as the conductive layer 141 and the insulating layer 142). The semiconductor substrate 143 can be a rectangular block. The semiconductor substrate 143 can be made of any one of silicon, silicon-carbon, gallium nitride, and gallium arsenide, and the material type can be determined according to the application scenario. The semiconductor substrate 143 can be a bare silicon wafer or a bare silicon die. The bare silicon wafer can be a P-type silicon wafer or an N-type silicon wafer. It should be noted that P-type silicon wafers are manufactured by doping silicon crystals with trivalent elements (such as boron), and N-type silicon wafers are manufactured by doping silicon crystals with pentavalent elements (such as phosphorus).

[0069] A conductive layer 141 is disposed on the second surface of the insulating layer 142. The conductive layer 141 may include a plurality of conductive sheets of different shapes, which are distributed at different positions on the second surface of the insulating layer 142, so that the flash memory chip 110 is coupled to the conductive sheet from at least one direction of the connection plate 140. It should be noted that there is a gap between any two adjacent conductive sheets.

[0070] The material of the conductive layer 141 may include one or more combinations of copper, silver, and gold. In this embodiment of the disclosure, the conductive layer 141 may be a patterned circuit layer formed by etching according to actual needs.

[0071] It should be noted that, in order to increase the adhesion between the conductive layer 141 and the insulating layer 142, a first metal layer 1610 and a second metal layer 1620 can be sputtered (a semiconductor process) between the conductive layer 141 and the insulating layer 142. The first metal layer 1610 is made of titanium, and the second metal layer 1620 is made of copper. Exemplarily, the insulating layer 142, the first metal layer 1610, the second metal layer 1620, and the conductive layer 141 are distributed from bottom to top on the third direction D3.

[0072] It should be noted that in this embodiment, the connector 140 is fabricated by forming an insulating layer 142 and a conductive layer 141 on a semiconductor substrate 143 (such as a silicon wafer). That is, a redistribution layer (RDL) is formed on the semiconductor substrate 143, and the insulating layer 142 and conductive layer 141 are the redistribution layer. Therefore, the thickness of the connector 140 is very small. For example, the thickness of the connector 140 is between 200 micrometers and 800 micrometers (0.2 millimeters to 0.8 millimeters), thereby reducing the package thickness and improving the compactness and reliability of the package.

[0073] The connection board 140 of this embodiment not only meets the size requirements of the flash memory chip 110, but also meets the requirements of high-density interconnection. Since the conductive layer 141 includes multiple conductive sheets distributed at different positions on the insulating layer 142, the pads 120 and external pins 206 of the flash memory chip 110 can be connected to different or the same conductive sheets on the connection board 140 from different positions as needed, and the bonding wires used for connection do not cross, thereby reducing coupling interference. This further improves the performance of the flash memory chip 110 while meeting the size requirements of the flash memory chip 110.

[0074] Furthermore, since the conductive layer 141 of the connector 140 has multiple conductive sheets with different shapes and distribution positions, the applicability of the connector 140 can be increased. In other words, the connector 140 can be used on different types of flash memory chips 110.

[0075] In this embodiment of the present disclosure, the thickness of the connecting plate 140 formed by providing an insulating layer 142 and a conductive layer 141 on the semiconductor substrate 143 is small, thereby reducing the package thickness and improving the compactness and reliability of the package.

[0076] In this embodiment of the present disclosure, the flash memory chip 110 connects the signal to the external pin 206 on the other side of the frame 130 by replacing the long bonding wire with a connecting board 140, which can reduce the cross-fraction ratio of the flash memory chip 110, reduce the line arc, and reduce the packaging risk.

[0077] In an exemplary embodiment, the insulating layer 142 may include a first insulating layer, which is a polymer material layer or an oxide layer. For example, the first insulating layer is a polyimide layer 1422 or a silicon oxide insulating layer 1421.

[0078] In one embodiment, such as Figure 4 As shown, the first insulating layer is a silicon oxide insulating layer 1421, the semiconductor substrate 143 is a silicon substrate 1431, and the conductive layer 141 is a copper layer 1410. The connection board 140 of the flash memory chip 110 provided in this embodiment may include a silicon substrate 1431, a silicon oxide insulating layer 1421, and a copper layer 1410 arranged from bottom to top along the third direction D3.

[0079] The connection board 140 in this embodiment has a simple structure and is easy to manufacture. By connecting the connection board 140 to the flash memory chip 110, the cross-span ratio of the flash memory chip 110 can be reduced, the line arc is low, and the packaging risk is low.

[0080] In another embodiment, such as Figure 5 As shown, the first insulating layer is a polyimide layer 1422 (also known as a PI insulating layer), the semiconductor substrate 143 is a silicon substrate 1431, and the conductive layer 141 is a copper layer 1410. The connection board 140 of the flash memory chip 110 provided in this embodiment may include a silicon substrate 1431, a polyimide layer 1422, and a copper layer 1410 arranged from bottom to top along the third direction D3.

[0081] This embodiment of the disclosure provides a polyimide layer 1422 between the conductive layer 141 and the semiconductor substrate 143, thus solving the problem of high-temperature leakage risk associated with the silicon oxide insulating layer 1421. By connecting the connector board 140 of this embodiment to the flash memory chip 110, the cross-chip ratio can be reduced, resulting in lower line arc and lower packaging risk.

[0082] In another exemplary embodiment, the insulating layer 142 may include a first insulating layer and a second insulating layer. The first insulating layer has opposing first and second surfaces, the second surface of the first insulating layer being the second surface of the insulating layer 142; the second insulating layer is disposed on the first surface of the first insulating layer; wherein the first insulating layer is a polymer material layer, and the second insulating layer is an oxide layer. For example, as... Figure 6 As shown, the first insulating layer is a polyimide layer 1422, and the second insulating layer is a silicon oxide insulating layer 1421. An embodiment of this disclosure provides a connection board 140 for a flash memory chip 110, which may include a silicon substrate 1431, a silicon oxide insulating layer 1421, a polyimide layer 1422, and a copper layer 1410 arranged from bottom to top along a third direction D3.

[0083] In this embodiment, a polymer material layer and an oxide layer are disposed between the conductive layer 141 and the semiconductor substrate 143, which can further enhance the insulation effect.

[0084] In this embodiment, a polyimide layer 1422 and a silicon oxide insulating layer 1421 are disposed between the conductive layer 141 and the semiconductor substrate 143, which solves the problem of high-temperature leakage risk of the silicon oxide insulating layer 1421. By connecting the connector board 140 of this embodiment to the flash memory chip 110, the cross-span ratio of the flash memory chip 110 can be reduced, resulting in lower line arc and lower packaging risk.

[0085] In yet another exemplary embodiment, the connecting plate 140 may further include a third insulating layer 144 disposed on the conductive layer 141. That is, the third insulating layer 144 is disposed on the side of the conductive layer 141 away from the insulating layer 142. The third insulating layer 144 is a polymer material layer. For example, the third insulating layer 144 is a polyimide layer 1422.

[0086] In this embodiment of the present disclosure, a third insulating layer 144 is provided on the conductive layer 141 to prevent the conductive layer 141 from being exposed to the outside, thereby solving the risk of short circuit caused by metallic foreign objects.

[0087] In this embodiment, the third insulating layer 144 extends downward along the third direction D3 and fills the space between two adjacent conductive sheets on the conductive layer 141, thereby further isolating the two adjacent conductive sheets, reducing the coupling effect between the conductive sheets, and further improving the working performance of the connection board 140 and the flash memory chip 110 using the connection board 140.

[0088] In one embodiment, such as Figure 7 As shown, the connection board 140 may further include a third insulating layer 144, the semiconductor substrate 143 is a silicon substrate 1431, and the conductive layer 141 is a copper layer 1410. The connection board 140 of the flash memory chip 110 provided in this embodiment may include a silicon substrate 1431, a silicon oxide insulating layer 1421, a copper layer 1410 and a third insulating layer 144 arranged from bottom to top along the third direction D3. The third insulating layer 144 may be a polyimide layer 1422, but this embodiment is not limited to this.

[0089] The third insulating layer 144 in this embodiment is used to protect the conductive layer 141 and prevent the conductive layer 141 from being exposed, thereby solving the problem of short circuit risk caused by foreign matter in the conductive layer 141.

[0090] In another embodiment, such as Figure 8As shown, the connection board 140 may further include a third insulating layer 144, the semiconductor substrate 143 is a silicon substrate 1431, and the conductive layer 141 is a copper layer 1410. The connection board 140 of the flash memory chip 110 provided in this embodiment may include a silicon substrate 1431, a polyimide layer 1422, a copper layer 1410 and a third insulating layer 144 arranged from bottom to top along the third direction D3, wherein the third insulating layer 144 is a polyimide layer 1422. This embodiment is not limited to this.

[0091] The third insulating layer 144 in this embodiment is used to protect the conductive layer 141 and prevent the conductive layer 141 from being exposed, thereby solving the problem of short circuit risk caused by foreign matter in the conductive layer 141. The polyimide layer 1422 located between the silicon substrate 1431 and the copper layer 1410 can effectively prevent the risk of high temperature leakage.

[0092] In yet another embodiment, such as Figure 9 As shown, the connection board 140 may further include a third insulating layer 144, the semiconductor substrate 143 is a silicon substrate 1431, and the conductive layer 141 is a copper layer 1410. The connection board 140 of the flash memory chip 110 provided in this embodiment may include a silicon substrate 1431, a silicon oxide insulating layer 1421, a polyimide layer 1422, a copper layer 1410 and a third insulating layer 144 arranged from bottom to top along the third direction D3, wherein the third insulating layer 144 is a polyimide layer 1422.

[0093] The third insulating layer 144 in this embodiment is used to protect the conductive layer 141 and prevent the conductive layer 141 from being exposed, thereby solving the problem of short circuit risk caused by foreign matter in the conductive layer 141. The polyimide layer 1422 located between the silicon substrate 1431 and the copper layer 1410 can effectively prevent the risk of high temperature leakage.

[0094] The layered structure of the connecting plate 140 has been described above. The conductive layer 141 of the connecting plate 140 will be described below through an exemplary embodiment.

[0095] like Figure 10-12 As shown, the conductive layer 141 may include multiple conductive sheets of different shapes, which are distributed at different positions on the second surface of the insulating layer 142. It should be noted that... Figures 10 to 12 This is a schematic diagram showing the gradual improvement of the conductive layer 141 of this disclosure.

[0096] like Figure 10 As shown, the third insulating layer 144 covers the conductive layer 141 (due to being covered, Figure 10 (Not shown in the image) A window is made on the third insulating layer 144. Figure 10The rectangular frame in the diagram is used to create the wire bonding pads, which are then electroplated with NiAu (nickel-gold alloy) to complete the wire bonding pod. It should be noted that the wire bonding pod is located on the connector board 140, not on the pad 120 of the flash memory chip 110. Figure 10 For illustrative purposes only, the third insulating layer 144 covers the conductive layer 141. Because the conductive sheet is positioned high, its protrusion is visible. Furthermore, the position of the conductive sheet can be determined based on the design dimensions of the conductive layer 141, thereby determining the location of the window. To improve the insulation performance of the insulating layer 142 in the above embodiment at high temperatures and to prevent high-temperature leakage, a method is provided as follows... Figure 11 The conductive layer 141 structure is shown. A polyimide layer 1422 and a silicon oxide insulating layer 1421 are disposed between the conductive layer 141 and the semiconductor substrate 143. The polyimide layer 1422 has excellent high-temperature resistance and excellent electrical insulation, thereby improving the high-temperature insulation of the insulating layer 142 and eliminating high-temperature leakage. To reduce metal coverage and accurately determine the wire bonding position, a structure such as... Figure 12 The conductive layer 141 shown.

[0097] In an exemplary embodiment, such as Figure 12 As shown, the conductive layer 141 may include multiple conductive sheets of different shapes, which are distributed at different positions on the second surface of the insulating layer 142. Multiple position marks 1416 are provided on the conductive sheets, which are used to locate the bonding positions so that the conductive sheets are coupled to the pads 120 or external pins 206 of the flash memory chip 110 at the position marks 1416.

[0098] For example, the width of the conductive sheet at location mark 1416 is greater than the width of the conductive sheet at locations without location mark 1416. Adding location mark 1416, that is, specifically marking the wire bonding location, facilitates the wire bonding (WB) process. Adding location mark 1416 allows for a reduction in the coverage of the conductive layer 141 metal material while still meeting requirements. Because the width of the conductive sheet at location mark 1416 is greater than the width of other locations on the conductive sheet (locations without location mark 1416), the risk of warpage after wafer thinning can be reduced. It should be noted that this wafer can be the wafer used to fabricate the semiconductor substrate 143.

[0099] In one embodiment, such as Figure 12 As shown, the conductive sheet may include one or more of the following: L-shaped conductive sheet 1411, straight conductive sheet 1412, U-shaped conductive sheet 1413, and U-shaped conductive sheet 1414. However, the embodiments disclosed herein are not limited to these. The conductive sheet of the required shape may be designed according to the needs.

[0100] The linear conductive sheet 1412, parallel to the first direction D1, facilitates the coupling of the pads 120 on the flash memory chip 110 at one end of the linear conductive sheet 1412 with the external pins 206 outside the flash memory chip 110 / frame 130 at the other end of the linear conductive sheet 1412 (see...). Figure 14 It should be noted that frame 130 is an indispensable part of the integrated circuit packaging process, responsible for connecting the flash memory chip 110 to the external circuit interface. For example, the flash memory chip 110 connects to the external circuit interface via external pin 206. The linear conductive strip 1412 can connect multiple bonding wires extending in the same direction (e.g., along the first direction D1), or it can connect multiple bonding wires extending in multiple directions.

[0101] The U-shaped conductive sheet 1413 facilitates the connection of multiple bonding wires located on the outer side of the U-shaped conductive sheet 1413. Similarly, the U-shaped conductive sheet 1414 and the L-shaped conductive sheet 1411 can also connect multiple bonding wires together to achieve signal transmission, and there is no phenomenon of multiple bonding wires crossing, thereby facilitating the packaging of the flash memory chip 110 while reducing interference.

[0102] For example, such as Figure 13 As shown, Figure 13 The connecting lines in the diagram represent solder lines. The conductive layer 141 of the connecting board 140 connects the solder pads 120 on one side of the flash memory chip 110 to the external pins 206 at various locations, preventing solder lines from crossing. It should be noted that the conductive layer 141 of the connecting board 140 can also connect the solder pads 120 on one side of the flash memory chip 110 to the required connection locations on the flash memory chip 110 (except where the connecting board 140 overlaps with the flash memory chip 110), further preventing solder lines from crossing.

[0103] In this embodiment, multiple conductive sheets are distributed at different positions on the second surface of the insulating layer 142, thereby minimizing the crossing between multiple bonding wires, facilitating the subsequent packaging of the flash memory chip 110, reducing electromagnetic interference, and increasing the performance of the flash memory chip 110.

[0104] In this embodiment of the disclosure, the number of position markers 1416 is not limited and can be set according to the actual application scenario and specific application experience. For example, at least two position markers 1416 can be provided on each conductive sheet.

[0105] In this embodiment of the disclosure, such as Figure 14 As shown, a position mark 1416 is added to the conductive sheet, which connects the signal located on one side of the flash memory chip 110 to the external pin 206 on the other side of the frame 130, thereby reducing the cross-flash memory chip 110 ratio, resulting in low line arc and low packaging risk.

[0106] The present disclosure does not specifically limit the method of adding the position mark 1416. For example, the RDL wiring can be specially designed to add the position mark 1416. The position mark 1416 is added to the layer structure on the mask for manufacturing the conductive layer 141, so that the manufactured conductive layer 141 also carries the position mark 1416. The position mark 1416 facilitates the encapsulation WB operation, improves production efficiency, and reduces production costs.

[0107] It should be noted that during the wire bonding process, a wire bonding pad is made at the required location marked 1416 and then electroplated with NiAu. Electroplating with NiAu can provide good electrical properties, thermal stability and reliable mechanical adhesion.

[0108] In another embodiment, such as Figure 12 As shown, the conductive sheet includes an L-shaped conductive sheet 1411, a straight conductive sheet 1412, a U-shaped conductive sheet 1413, and a U-shaped conductive sheet 1414. Multiple L-shaped conductive sheets 1411 and multiple straight conductive sheets 1412 are located inside the U-shaped conductive sheet 1413. Multiple spaced balancing plates 1415 are provided at the opening of the U-shaped conductive sheet 1413.

[0109] In this embodiment, the method for manufacturing the balancing plate 1415 is the same as the method for manufacturing the conductive plate, and the material of the balancing plate 1415 can also be the same as that of the conductive plate. It is used to balance the conductive layer 141. For example, as... Figure 12 As shown, when the U-shaped conductive sheet 1413 is large (e.g., the U-shaped conductive sheet 1413 surrounds more than 70% of the area of ​​the conductive layer 141), a plurality of balancing sheets 1415 are provided at the opening of the U-shaped conductive sheet 1413 to support other layers (e.g., the third insulating layer 144) or the package housing for encapsulating the flash memory chip 110 located on the conductive layer 141 distributed along the third direction D3.

[0110] The conductive layer 141 has been described above. The following describes how to wire bond the connector board 140.

[0111] In one embodiment, Figure 7 and Figure 10 The connecting plate 140 is described in conjunction with the copper layer 1410, on which a third insulating layer 144 is covered, and a window is made in the third insulating layer 144. Figure 10 The rectangular frame in the diagram is used to create the wire bonding pad, which is then electroplated with NiAu to complete the wire bonding Pod. It should be noted that the position of the conductive sheet can be determined based on the design dimensions of the conductive layer 141, thus determining the location of the window.

[0112] To improve the insulation performance of the insulation layer 142 in the above embodiment at high temperatures and to avoid high-temperature leakage, the next embodiment is provided.

[0113] In one embodiment, for Figure 6 and Figure 11 The connecting plate 140 is described in conjunction with the copper layer 1410 and the silicon substrate 1431. A polyimide layer 1422 and a silicon oxide insulating layer 1421 are disposed between the copper layer 1410 and the silicon substrate 1431. The polyimide layer 1422 has excellent high temperature resistance and excellent electrical insulation, thereby improving the high temperature insulation of the insulating layer 142 and eliminating the phenomenon of high temperature leakage.

[0114] In another embodiment, to avoid exposing the copper layer 1410, in Figure 6 Based on this, a third insulating layer 144 is added to form a structure like Figure 9 The connecting plate 140 structure is shown. A window is made in the third insulating layer 144. Figure 10 The rectangular frame in the middle is used to make the wire bonding pad and electroplated with NiAu to complete the wire bonding Pod. The third insulating layer 144 is used to protect the copper layer 1410 and prevent the copper layer 1410 from being exposed, thereby solving the problem of short circuit risk caused by foreign objects in the conductive layer 141.

[0115] The connecting plate 140 produced by the above two embodiments can improve the high-temperature insulation of the insulation layer 142 and there is no high-temperature leakage phenomenon.

[0116] like Figure 11 Because the conductive layer 141 shown lacks a wire bonding pad, the WB equipment cannot accurately locate the wire bonding point (i.e., the wire bonding position) during the packaging process. To solve this... Figure 11 To address the issues with the conductive layer 141, the following embodiments are provided.

[0117] In one embodiment, for Figure 5 and Figure 12 Referring to the connecting plate 140, a position mark 1416 is added to the conductive sheet of the conductive layer 141. This position mark 1416 serves as a special marker for the wire bonding position, facilitating the wafer bonding (WB) process. Adding the position mark 1416 allows for a reduction in the metal material coverage of the conductive layer 141 while still meeting requirements. Since the width of the conductive sheet at the position mark 1416 is greater than the width at other locations on the conductive sheet (where the position mark 1416 is not marked), the risk of warpage after wafer thinning can be reduced. It should be noted that this wafer can be the wafer used to fabricate the semiconductor substrate 143.

[0118] In this embodiment of the disclosure, to avoid exposing the conductive layer 141, it is possible to... Figure 5 A third insulating layer 144 is added on top of the existing one.

[0119] In another embodiment, for Figure 6 and Figure 12Referring to the connecting board 140, position marks 1416 are added to the conductive sheets of the conductive layer 141. These position marks 1416 are special markings for wire bonding positions, facilitating the wafer bonding (WB) process. Adding position marks 1416 allows for a reduction in the metal material coverage of the conductive layer 141 while still meeting requirements. Since the width of the conductive sheet with position marks 1416 is greater than the width of other locations on the conductive sheet, the risk of warpage after wafer thinning can be reduced. It should be noted that this wafer can be the wafer used to fabricate the semiconductor substrate 143.

[0120] In this embodiment of the disclosure, to avoid exposing the conductive layer 141, it is possible to... Figure 6 A third insulating layer 144 is added on top of the existing one.

[0121] The connecting plate 140 manufactured in the above four embodiments can improve the high-temperature insulation of the insulation layer 142 and there is no high-temperature leakage phenomenon.

[0122] It should be noted that the connection board 140 disclosed herein is not limited to application on static memory, but can also be applied to other chips.

[0123] Based on the same inventive concept, this disclosure also provides a flash memory chip 110, which includes the connection board 140 described in the above embodiments, as shown in the following embodiments. Therefore, the implementation of this flash memory chip 110 embodiment can refer to the implementation of the connection board 140 embodiment described above, and repeated details will not be described again.

[0124] This disclosure provides a flash memory chip 110, including a chip body and a connection board 140 as described above. The connection board 140 has opposing first and second surfaces. The chip body is disposed on the first surface of the connection board 140, and the connection board 140 is coupled to the chip body. The overall size of the connection board 140 is smaller than the overall size of the chip body. It should be noted that the chip body can be understood as the flash memory chip 110 excluding the connection board 140. Since flash memory chips 110 in related technologies do not have a connection board 140, the term "chip body" here refers to the flash memory chip 110 excluding the connection board 140.

[0125] In this embodiment, the overall size of the connecting board 140 is smaller than the overall size of the chip body; that is, the length of the connecting board 140 is less than the length of the chip body, and the width of the connecting board 140 is less than the width of the chip body. It should be noted that the connecting board 140 and the chip body are connected by wire bonding, thereby facilitating signal transmission.

[0126] Regarding the location of the connector plate 140 on the chip body, this embodiment of the disclosure is not limited, as long as it is a location that ensures that the bonding wires used for connection do not cross or have minimal crossover (e.g., fewer than 5 crossovers) and that the wire arc is low. For example, the connector plate 140 is located at the center of the chip body. Figure 13 and Figure 14 As shown, the bonding board 140 is located at the center of the chip body, which can cause the bonding wires to converge towards the center and have a low arc, thereby further reducing the size of the bonding board 140 and increasing the number of bonding boards 140 fabricated on the same wafer, thereby reducing production costs.

[0127] It should be noted that the geometric center of the connecting board 140 and the geometric center of the flash memory chip 110 are distributed vertically along the third direction D3.

[0128] In one embodiment, the insulating layer 142 includes a first insulating layer, which is a polymer material layer or an oxide layer.

[0129] In one embodiment, the insulating layer 142 includes: a first insulating layer having opposing first and second surfaces, the second surface of the first insulating layer being the second surface of the insulating layer 142; and a second insulating layer disposed on the first surface of the first insulating layer; wherein the first insulating layer is a polymer material layer and the second insulating layer is an oxide layer. For example, the first insulating layer is a polyimide layer 1422, and the second insulating layer is a silicon oxide insulating layer 1421.

[0130] In one embodiment, the connecting plate 140 further includes a third insulating layer 144 disposed on the conductive layer 141, wherein the third insulating layer 144 is a polymer material layer.

[0131] In one embodiment, a plurality of position marks 1416 are provided on the conductive sheet. The position marks 1416 are used to locate the bonding positions so that the conductive sheet is coupled to the pad 120 or external pin 206 of the flash memory chip 110 at the position marks 1416.

[0132] In one embodiment, the width of the conductive sheet at location mark 1416 is greater than the width of the conductive sheet at location mark 1416 that is not marked.

[0133] In one embodiment, the conductive sheet includes one or more of the following: L-shaped conductive sheet 1411, I-shaped conductive sheet 1412, U-shaped conductive sheet 1413, and C-shaped conductive sheet 1414.

[0134] In one embodiment, the conductive sheet includes an L-shaped conductive sheet 1411, a straight conductive sheet 1412, a U-shaped conductive sheet 1413, and a U-shaped conductive sheet 1414. The plurality of L-shaped conductive sheets 1411 and the plurality of straight conductive sheets 1412 are located inside the U-shaped conductive sheet 1413, and the opening of the U-shaped conductive sheet 1413 is provided with a plurality of spaced-apart balance plates 1415.

[0135] In one embodiment, the semiconductor substrate 143 is a bare silicon wafer or a bare silicon wafer, which can be a P-type silicon wafer or an N-type silicon wafer.

[0136] In one embodiment, the connection board 140 may further include: a first connection point group 201 and a second connection point group 202, the first connection point group 201 and the second connection point group 202 being disposed on the second surface of the connection board 140 and distributed on both sides of the second surface of the connection board 140, the first connection point group 201 and the second connection point group 202 each including a plurality of connection points 203, the connection points 203 being coupled to the conductive layer 141 of the connection board 140. It should be noted that, in some embodiments, the connection points 203 are coupled to the position marks 1416 of the conductive sheets of the conductive layer 141; the chip body includes a plurality of pads 120, the plurality of pads 120 being disposed on the surface side of the chip body near the first surface of the connection board 140; the distance from the plurality of pads 120 to the first connection point group 201 is less than the distance to the second connection point group 202, and M of the plurality of pads 120 are coupled to the first connection point group 201. Connection point 203 is coupled, and connection point 203 in the first connection point group 201 is coupled to connection point 203 in the second connection point group 202 through conductive layer 141; the flash memory chip 110 also includes: a first pin group 204 and a second pin group 205, the first pin group 204 and the second pin group 205 are distributed on opposite sides of the chip body, the first pin group 204 and the second pin group 205 each include multiple external pins 206, the distance of the first pin group 204 from the multiple pads 120 is less than the distance of the second pin group 205 from the multiple pads 120, K of the multiple pads 120 are coupled to the external pins 206 in the first pin group 204, and the connection point 203 in the second connection point group 202 is coupled to the external pins 206 in the second pin group 205; wherein, M and K are both integers greater than or equal to 1, and the sum of M and K is less than or equal to the total number of multiple pads 120.

[0137] In this embodiment, the number of M and K is not specifically limited, but can be determined adaptively as needed.

[0138] For example, such as Figure 2As shown, M=4, K=4, there are 10 pads 120 on the chip body, and a first connection point group 201 and a second connection point group 202 are provided on the second surface (e.g., the top surface) of the connection board 140. The first connection point group 201 and the second connection point group 202 are distributed on both sides of the second surface of the connection board 140. That is, the first connection point group 201 and the second connection point group 202 are distributed on both sides of the top surface of the connection board 140. The first connection point group 201 and the second connection point group 202 both include multiple connection points 203. Multiple pads 120 are disposed on one side of the chip body near the first surface of the connection plate 140; the distance of the multiple pads 120 from the first connection point group 201 is less than the distance of the multiple pads 120 from the second connection point group 202; four of the multiple pads 120 are coupled to the connection points 203 in the first connection point group 201; the connection points 203 in the first connection point group 201 are coupled to the connection points 203 in the second connection point group 202 through the conductive layer 141; it should be noted that the connection points 203 in the first connection point group 201 and the connection points 203 in the second connection point group 202 are coupled through the conductive sheet in the conductive layer 141. The flash memory chip 110 also includes a first pin group 204 (pin 1, pin 2, pin 3, pin 4) and a second pin group 205 (pin 5, pin 6, pin 7, pin 8). The first pin group 204 and the second pin group 205 are distributed on opposite sides of the chip body. Both the first pin group 204 and the second pin group 205 include multiple external pins 206. The distance between the first pin group 204 and the multiple pads 120 is less than the distance between the second pin group 205 and the multiple pads 120. Four of the multiple pads 120 are coupled to the external pins 206 in the first pin group 204. The connection point 203 in the second connection point group 202 is coupled to the external pins 206 in the second pin group 205. The multiple pads 120 are coupled to the external pins 206 in the second pin group 205, which are located at a greater distance, through the connection plate 140, spanning the flash memory chip 110. This reduces the proportion of the flash memory chip 110 spanned, resulting in low line arc and low packaging risk. In addition, the connection board 140 has a heat dissipation function, which can accelerate the heat dissipation of the flash memory chip 110 and ensure the working performance of the flash memory chip 110.

[0139] It should be noted that connection point 203 is the point that connects to the conductive sheet in the conductive layer 141 (such as the wire bonding Pod at the wire bonding position mentioned above).

[0140] To increase the packaging strength of the flash memory chip 110, the flash memory chip 110 may further include a frame 130 for mounting the chip body. The chip body is disposed on the frame 130, and the frame 130 supports the chip body, thereby increasing the mechanical strength of the flash memory chip 110 and reducing the probability of damage to the flash memory chip 110. In this embodiment, signals can be connected to external pins 206 outside the frame 130 via a connection board 140, reducing the cross-sectional area of ​​the flash memory chip 110, resulting in lower line arc and lower packaging risk.

[0141] To further reduce packaging risks, such as Figure 2 As shown, the multiple external pins 206 and multiple pads 120 in the first pin group 204 are all evenly distributed in a line, and the two outer pads 120 of the multiple pads 120 are respectively coupled to the two outer external pins 206 in the first pin group 204. The multiple external pins 206 in the first pin group 204 are coupled to the K (e.g., ...) of the multiple pads 120. Figure 2 In the embodiment where K=4 (but not limited to this), each pad 120 corresponds one-to-one along the length direction of the chip body (e.g., the first direction D1), and the bonding wires coupling between each group of corresponding pads 120 and the external pins 206 are parallel to the length direction of the chip body. It should be noted that aligning the multiple external pins 206 in the first pin group 204 with their corresponding pads 120 along the length direction of the chip body not only shortens the length of the bonding wires used for coupling between the multiple external pins 206 in the first pin group 204 and their corresponding pads 120, saving production costs, but also reduces packaging risks.

[0142] The above exemplary embodiments are one implementation of this disclosure, and the embodiments of this disclosure are not limited thereto. For example, another implementation of this disclosure is as follows: Figure 13 As shown, multiple pads 120 on the chip body are located on one side of the chip body. The bonding wires on the pads 120 can be coupled to the external pins 206 (pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7 and pin 8) distributed on both sides of the pads 120 through the connecting board 140.

[0143] In one embodiment, the connecting plate 140 may further include a plurality of connection points 203. The plurality of connection points 203 are disposed on the second surface of the connecting plate 140 and distributed along the outer edge of the connecting plate 140. The connection points 203 are coupled to the conductive layer 141 of the connecting plate 140. It should be noted that in some embodiments, the connection points 203 are located at the position mark 1416 of the conductive sheet of the conductive layer 141. Figure 13 As shown, the connection points 203 are distributed on the outer edge of the connection board 140, which is beneficial for connecting external pins 206, thereby reducing the proportion of the connection between the pad 120 and the external pins 206 across the flash memory chip 110, resulting in low line arc and low packaging risk.

[0144] The flash memory chip 110 also includes a first pin group 204 and a second pin group 205, which are distributed on opposite sides of the chip body. Both the first pin group 204 and the second pin group 205 include multiple external pins 206.

[0145] The chip body includes multiple pads 120, which are disposed on one side of the chip body near the first surface of the connection board 140. The multiple pads 120 are located between the first pin group 204 and the second pin group 205. T pads 120 are coupled to some external pins 206 in the first pin group 204, E pads 120 are coupled to some external pins 206 in the second pin group 205, and Q pads 120 are coupled to connection points 203. Wherein, T, E, and Q are all integers greater than or equal to 1, and the sum of T, E, and Q is less than or equal to the total number of multiple pads 120.

[0146] In this embodiment, the number of T, E, and Q is not limited. It can be set according to the actual application scenario and specific application experience.

[0147] The embodiments disclosed herein add a connection board 140 to the chip body to connect signals, resulting in a low proportion of wire bonding across the flash memory chip 110, low wire arc, and low packaging risk.

[0148] Based on the same inventive concept, this disclosure also provides a method for preparing a connecting plate 140, as described in the following embodiments. Therefore, the implementation of the preparation method embodiment can refer to the implementation of the connecting plate 140 embodiment described above, and repeated details will not be repeated.

[0149] Figure 15 This diagram illustrates a method for preparing a connecting plate according to an embodiment of the present disclosure. Figure 15 As shown, the method for preparing a connecting plate 140 provided in this disclosure may include the following steps S1501 to S1503.

[0150] S1501 provides a semiconductor substrate 143.

[0151] In this embodiment of the disclosure, the semiconductor substrate 143 can be any one of the following: silicon substrate 1431, silicon-carbon substrate, gallium nitride substrate, and gallium arsenide substrate. The material type of the semiconductor substrate 143 can be determined according to the application scenario.

[0152] For example, the semiconductor substrate 143 can be a bare silicon wafer or a bare silicon wafer, and the bare silicon wafer can be a P-type silicon wafer or an N-type silicon wafer.

[0153] S1502, an insulating layer solution is coated on the semiconductor substrate 143 and cured to form an insulating layer 142.

[0154] In this embodiment of the disclosure, the insulating layer solution is the solution used to form the insulating layer 142. The specific type of solution is not limited in this embodiment. For example, the insulating layer solution can be a polyimide (PI) solution.

[0155] S1503, photoresist is coated on insulating layer 142, and then exposed, developed, electroplated, removed from photoresist and etched through a mask to form conductive layer 141.

[0156] In one embodiment, after coating the insulating layer solution onto the semiconductor substrate 143 and performing a curing process to form the insulating layer 142 (i.e., S1502), the method for preparing the connecting plate 140 further includes: forming a connecting layer between the insulating layer 142 and the conductive layer 141; wherein the connecting layer includes a first metal layer 1610 and a second metal layer 1620, the first metal layer 1610 being made of titanium and the second metal layer 1620 being made of copper.

[0157] For example, a first metal layer 1610 and a second metal layer 1620 are sputtered onto the insulating layer 142 to form a bonding layer. Photoresist is coated on the bonding layer, and the bonding layer is exposed, developed, electroplated, the photoresist is removed, and etched through a mask to form a conductive layer 141.

[0158] In this embodiment, sputtering a first metal layer 1610 and a second metal layer 1620 onto the insulating layer 142 increases the adhesion between the insulating layer 142 and the conductive layer 141 fabricated in subsequent processes. Good adhesion between the insulating layer 142 and the conductive layer 141 helps ensure the stability of the electrical connection, avoids poor electrical contact due to poor adhesion, and thus improves the conductivity and reliability of the circuit. It also effectively prevents interlayer separation caused by mechanical stress or differences in thermal expansion, thereby extending the service life of the connector plate 140.

[0159] The conductive layer 141 may include multiple conductive sheets of different shapes. The conductive sheets may include one or more of the following: L-shaped conductive sheet 1411, I-shaped conductive sheet 1412, U-shaped conductive sheet 1413, and C-shaped conductive sheet 1414. The conductive sheets are copper sheets.

[0160] It should be noted that the mask is the mask corresponding to the conductive layer 141 on the connecting plate 140 in this embodiment. Through the mask and subsequent processes, the conductive layer 141 including multiple conductive sheets of different shapes in this embodiment can be formed.

[0161] In this embodiment of the disclosure, in order to further increase the adhesion between the insulating layer 142 and the conductive layer 141, the material of the second metal layer 1620, which is bonded to the conductive layer 141, is the same as that of the conductive layer 141. For example, the material of the second metal layer 1620 is copper, and the material of the conductive layer 141 is also copper, thereby increasing the adhesion between the insulating layer 142 and the conductive layer 141.

[0162] For example, such as Figure 16 As shown, the preparation process of the connecting plate 140 may include the following steps A1 to A9.

[0163] Step A1: Apply a polyimide (PI) solution onto the silicon substrate 1431 to form a PI coating.

[0164] In this embodiment of the disclosure, a PI solution is coated on the silicon substrate 1431 to create a polyimide coating, thereby improving the high-temperature insulation of the connector 140 and solving the problem of high-temperature leakage.

[0165] It should be noted that the silicon substrate 1431 may be covered with a silicon dioxide insulating layer 1421, or it may not be covered with a silicon dioxide insulating layer 1421.

[0166] Step A2, the PI coating is cured to form polyimide layer 1422.

[0167] In this embodiment of the disclosure, curing the PI coating is beneficial to enhancing the stability of the polyimide layer 1422.

[0168] Step A3 involves sputtering a first metal layer 1610 and a second metal layer 1620 (i.e., a bonding layer) onto the polyimide layer 1422. The bonding layer is used to improve the adhesion between the polyimide layer 1422 and the conductive layer 141 to be fabricated.

[0169] In this embodiment of the disclosure, the first metal layer 1610 may be made of titanium, and the second metal layer 1620 is made of the same material as the conductive layer 141, and the second metal layer 1620 may be made of copper.

[0170] Step A4: Spin-coat (cover) a layer of photoresist (PR) onto the second metal layer 1620 to form a photoresist layer 1630.

[0171] Step A5: Expose the photoresist layer 1630 using a mask.

[0172] Step A6: Develop the exposed photoresist layer 1630 using a developer.

[0173] In this embodiment, during the development process, the photoresist layer 1630 forms a groove structure that matches the shape of the conductive layer 141, depending on the exposure pattern. This process is based on the selective exposure and development of the photoresist in the photolithography process. After exposure, the unexposed portions of the photoresist are removed during development, leaving grooves corresponding to the pattern. These grooves precisely match the structure of the conductive layer 141, forming a template suitable for subsequent metal electroplating.

[0174] Step A7: Electroplating is performed on the photoresist layer 1630 after development to form the RDL layer 1640.

[0175] In this embodiment, metal electroplating can be performed within the aforementioned groove to form a conductive layer 141 connected to the second metal layer 1620. In this way, metal can be precisely deposited into specific areas (e.g., areas forming conductive sheets), ensuring adhesion between the conductive layer 141 and the second metal layer 1620, while reducing unnecessary metal waste and forming precise conductive channels.

[0176] It should be noted that the metal used for electroplating can be any of copper, nickel, and gold.

[0177] Step A8: Remove the photoresist on RDL layer 1640.

[0178] Step A9 involves etching the first metal layer 1610 and the second metal layer 1620 surrounding the RDL layer 1640 until the polyimide layer 1422 is reached, thereby completing the fabrication of the conductive layer 141.

[0179] In this embodiment, the first metal layer 1610 and the second metal layer 1620 surrounding the RDL layer 1640 are etched to precisely remove excess metal layers until the polyimide layer 1422 is etched, thus completing the pattern definition of the conductive layer 141. This is based on a selective etching process. For example, the conductive layer 141 includes multiple conductive sheets of different shapes, which may include one or more of the following: L-shaped conductive sheet 1411, I-shaped conductive sheet 1412, U-shaped conductive sheet 1413, and U-shaped conductive sheet 1414. Multiple position marks 1416 are provided on the conductive sheets, and the width of the conductive sheet at the position mark 1416 is greater than the width at other locations on the conductive sheet. This reduces the risk of warping of the conductive sheet, facilitates reducing the width of the conductive sheet, reduces metal coverage, and thus reduces production costs. The conductive layer 141 may also include multiple balancing plates 1415.

[0180] In one embodiment, etching technology is used to remove the metal layer through chemical reaction or physical action. The depth and extent of etching are precisely controlled by adjusting the etching time and the choice of chemical agent. To ensure that etching only affects the metal layer without damaging the underlying polyimide layer 1422, embodiments of this disclosure employ relatively mild etching conditions or a staged etching process. The polyimide layer 1422, as a high-temperature resistant and chemically resistant insulating material layer, is designed as an etching stop layer; that is, once etching reaches the polyimide layer 1422, the etching process stops, protecting the underlying structure (such as the silicon substrate 1431) from damage. Through this etching method, the shape and size of the conductive layer 141 can be precisely controlled, providing the necessary circuit patterns and connection structures for subsequent process steps (such as interconnects, packaging, etc.), thereby completing the fabrication of the conductive layer 141 and ensuring its electrical performance and structural stability.

[0181] The connecting plate 140 manufactured by the above-described preparation method in this embodiment exhibits good electrical performance and structural stability.

[0182] In the embodiments of this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application based on the specific circumstances.

[0183] In the description of the embodiments of the application, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the application and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the application.

[0184] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the claims. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0185] The above are merely preferred embodiments of the application examples and are not intended to limit the application examples. For those skilled in the art, the application examples can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the application examples should be included within the protection scope of the application examples.

Claims

1. A connector board for a flash memory chip, characterized in that, include: An insulating layer (142) has opposing first and second surfaces; A semiconductor substrate (143) is disposed on the first surface of the insulating layer (142); A conductive layer (141) is disposed on the second surface of the insulating layer (142). The conductive layer (141) includes a plurality of conductive sheets of different shapes. The conductive sheets are distributed at different positions on the second surface of the insulating layer (142) so that the pads (120) of the flash memory chip (110) are coupled to external pins (206) through the conductive sheets, thereby reducing the proportion of bonding wires across the flash memory chip (110). The conductive sheet includes an L-shaped conductive sheet (1411), a straight conductive sheet (1412), a U-shaped conductive sheet (1413), and a U-shaped conductive sheet (1414). A plurality of L-shaped conductive sheets (1411) and a plurality of straight conductive sheets (1412) are located inside the U-shaped conductive sheet (1413), and a plurality of spaced-apart balance plates (1415) are provided at the opening of the U-shaped conductive sheet (1413).

2. The interconnect board for the flash memory chip according to claim 1, characterized in that, The insulating layer (142) includes a first insulating layer, which is a polymer material layer or an oxide layer.

3. The interconnect board for the flash memory chip according to claim 1, characterized in that, The insulating layer (142) comprises: The first insulating layer has a first surface and a second surface opposite to each other, wherein the second surface of the first insulating layer is the second surface of the insulating layer (142); A second insulating layer is disposed on the first surface of the first insulating layer; The first insulating layer is a polymer material layer, and the second insulating layer is an oxide layer.

4. The interconnect board for the flash memory chip according to claim 2 or 3, characterized in that, The connecting plate (140) also includes: A third insulating layer (144) is disposed on the conductive layer (141), wherein the third insulating layer (144) is a polymer material layer.

5. The interconnect board for the flash memory chip according to claim 1, characterized in that, The conductive sheet is provided with a plurality of position marks (1416), which are used to locate the bonding position so that the conductive sheet is coupled to the pad (120) of the flash memory chip (110) or the external pin (206) at the position mark (1416).

6. The interconnect board for the flash memory chip according to claim 5, characterized in that, The width of the conductive sheet at the location mark (1416) is greater than the width of the conductive sheet at the location mark (1416) where the location mark (1416) is not marked.

7. The interconnect board for the flash memory chip according to claim 1, characterized in that, The semiconductor substrate (143) is a bare silicon wafer or a bare silicon wafer, and the bare silicon wafer is a P-type silicon wafer or an N-type silicon wafer.

8. A flash memory chip, characterized in that, The device includes a chip body and a connection board for the flash memory chip as described in any one of claims 1-7. The connection board (140) has a first surface and a second surface opposite to each other. The chip body is disposed on the first surface of the connection board (140). The connection board (140) is coupled to the chip body. The overall size of the connection board (140) is smaller than the overall size of the chip body.

9. The flash memory chip according to claim 8, characterized in that, The connecting plate (140) is located at the center of the chip body.

10. The flash memory chip according to claim 8, characterized in that, The connecting plate (140) further includes: a first connection point group (201) and a second connection point group (202), the first connection point group (201) and the second connection point group (202) are disposed on the second surface of the connecting plate (140) and distributed on both sides of the second surface of the connecting plate (140), the first connection point group (201) and the second connection point group (202) each include a plurality of connection points (203), and the connection points (203) are coupled to the conductive layer (141) of the connecting plate (140); The chip body includes a plurality of pads (120), which are disposed on one side of the chip body near the first surface of the connection plate (140); the distance of the plurality of pads (120) to the first connection point group (201) is less than the distance to the second connection point group (202); M of the plurality of pads (120) are coupled to the connection points (203) in the first connection point group (201); the connection points (203) in the first connection point group (201) are coupled to the connection points (203) in the second connection point group (202) through the conductive layer (141); The flash memory chip (110) further includes: a first pin group (204) and a second pin group (205), the first pin group (204) and the second pin group (205) are distributed on opposite sides of the chip body, the first pin group (204) and the second pin group (205) each include a plurality of external pins (206), the distance of the first pin group (204) from the plurality of pads (120) is less than the distance of the second pin group (205) from the plurality of pads (120), K of the plurality of pads (120) are coupled to the external pins (206) in the first pin group (204), and the connection point (203) in the second connection point group (202) is coupled to the external pins (206) in the second pin group (205); Where M and K are both integers greater than or equal to 1, and the sum of M and K is less than or equal to the total number of the plurality of pads (120).

11. The flash memory chip according to claim 10, characterized in that, The multiple external pins (206) and the multiple pads (120) in the first pin group (204) are all evenly distributed in a line. The two outer pads (120) of the multiple pads (120) are respectively coupled to the two outer external pins (206) of the first pin group (204). The multiple external pins (206) in the first pin group (204) correspond one-to-one with the K pads (120) of the multiple pads (120) along the length direction of the chip body. The bonding wires between each corresponding pad (120) and the external pins (206) are parallel to the length direction of the chip body.

12. The flash memory chip according to claim 8, characterized in that, The connecting plate (140) further includes: a plurality of connection points (203), the plurality of connection points (203) are disposed on the second surface of the connecting plate (140) and distributed on the outer edge of the connecting plate (140), and the connection points (203) are coupled to the conductive layer (141) of the connecting plate (140); The flash memory chip (110) further includes: a first pin group (204) and a second pin group (205), the first pin group (204) and the second pin group (205) are distributed on opposite sides of the chip body, and both the first pin group (204) and the second pin group (205) include multiple external pins (206); The chip body includes a plurality of pads (120), which are disposed on one side of the chip body near the first surface of the connecting plate (140). The plurality of pads (120) are located between the first pin group (204) and the second pin group (205). T pads (120) of the plurality of pads (120) are coupled to a portion of the external pins (206) in the first pin group (204). E pads (120) of the plurality of pads (120) are coupled to a portion of the external pins (206) in the second pin group (205). Q pads (120) of the plurality of pads (120) are coupled to the connection point (203). Where T, E, and Q are all integers greater than or equal to 1, and the sum of T, E, and Q is less than or equal to the total number of the plurality of pads (120).

13. A method for preparing a connecting plate, characterized in that, include: Provides a semiconductor substrate (143); An insulating layer solution is coated on the semiconductor substrate (143) and cured to form an insulating layer (142); Photoresist is coated on the insulating layer (142), and the conductive layer (141) is formed by exposure, development, electroplating, photoresist removal and etching through a mask. The conductive layer (141) includes multiple conductive sheets of different shapes, including L-shaped conductive sheets (1411), straight conductive sheets (1412), U-shaped conductive sheets (1413), and U-shaped conductive sheets (1414). Multiple L-shaped conductive sheets (1411) and multiple straight conductive sheets (1412) are located inside the U-shaped conductive sheet (1413), and multiple spaced balancing sheets (1415) are provided at the opening of the U-shaped conductive sheet (1413).

14. The method for preparing the connecting plate according to claim 13, characterized in that, After coating the insulating layer solution onto the semiconductor substrate (143) and performing a curing process to form an insulating layer (142), the method for preparing the connecting plate further includes: A connecting layer is formed between the insulating layer (142) and the conductive layer (141); The connecting layer includes a first metal layer (1610) and a second metal layer (1620), wherein the first metal layer (1610) is made of titanium and the second metal layer (1620) is made of copper.

15. The method for preparing the connecting plate according to claim 13, characterized in that, The conductive sheet is a copper sheet.

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