Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a substrate structure; the substrate structure comprises a patterned substrate and an interlayer dielectric layer located on the upper surface of the substrate; a contact hole is formed in the interlayer dielectric layer; the thin film resistor is positioned on the interlayer dielectric layer; the two ends of the thin film resistor are in ohmic contact with the patterned substrate through the contact holes respectively; the first metal layers are located on the interlayer dielectric layer and arranged on the two sides of the thin film resistor; the first metal layer forms ohmic contact with the patterned substrate through the contact holes respectively; and the metal interconnection layer covers the first metal layer, the thin film resistor and part of the interlayer dielectric layer. According to the structure, only one-time dry etching is needed in the process of preparing the thin-film resistor, and a contact hole etching stop layer does not need to be prepared on the surface of the thin-film resistor, so that the process steps of preparing the semiconductor structure with the thin-film resistor are simplified, and the cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Integrated resistors are important components in many analog circuits. The performance of analog circuits is easily affected by the electrical properties of integrated resistors. Researchers continue to study and improve the electrical properties of integrated resistors such as mismatch, temperature coefficient of resistance (TCR), and resistivity. In order to improve the electrical performance of integrated resistors, thin film resistors (TFRs) have been widely studied due to their various advantages such as near-zero TCR, low noise, good matching performance, and electrical trimming capabilities.

[0003] In the prior art, a thin film resistor is embedded in a first metal layer and a second metal layer so that it can be compatible with BEOL (back end of line) processes, such as Figure 1 As shown, during the preparation of existing thin film resistors, two dry etchings and one wet etching are performed, which not only consumes two masks and is costly, but also requires chemical mechanical polishing of the surface of the thin film resistor. When performing through-hole etching, it is necessary to stop at the surfaces of the TFR layer and the first metal layer at the same time. Due to problems such as small etching window and inconsistent etching height, over-etching is easily caused, which contaminates the TFR layer. Summary of the invention

[0004] In order to solve the above technical problems, the present application proposes a semiconductor structure and a preparation method thereof.

[0005] On the one hand, an embodiment of the present application provides a semiconductor structure, including:

[0006] Substrate structure; the substrate structure comprises a patterned substrate and an interlayer dielectric layer located on the upper surface of the patterned substrate; the interlayer dielectric layer is provided with a contact hole;

[0007] A thin film resistor is located on the interlayer dielectric layer; two ends of the thin film resistor respectively pass through the contact holes to form ohmic contacts with the patterned substrate;

[0008] A first metal layer is located on the interlayer dielectric layer and is disposed on both sides of the thin film resistor; the first metal layer forms an ohmic contact with the patterned substrate through the contact holes respectively;

[0009] The metal interconnection layer covers the first metal layer, the thin film resistor and a portion of the interlayer dielectric layer.

[0010] In one embodiment, the number of the thin film resistors is n, and the number of the contact holes is 4n; wherein n≥1, and n is a positive integer.

[0011] In one embodiment, the patterned substrate includes a first substrate and a second substrate spaced apart from each other;

[0012] The contact holes include a first contact hole, a second contact hole, a third contact hole and a fourth contact hole;

[0013] The first metal layer includes a first portion and a second portion; the first portion is disposed on one side of the thin film resistor, and the second portion is disposed on the other side of the thin film resistor;

[0014] The first portion forms an ohmic contact with the first substrate through the first contact hole; the second portion forms an ohmic contact with the second substrate through the fourth contact hole;

[0015] The thin film resistor includes a first end and a second end, the second contact hole is arranged on a side close to the first end, and the third contact hole is arranged on a side close to the second end; and the thin film resistor forms an ohmic contact with the first substrate through the second contact hole, and forms an ohmic contact with the second substrate through the third contact hole.

[0016] In one embodiment, the distance between the second contact hole and the third contact hole is ≥ 0.135 μm;

[0017] The distance between the first contact hole and the second contact hole, and the distance between the third contact hole and the fourth contact hole are both ≥ 0.135 μm;

[0018] The distance between the first contact hole and the first end, and the distance between the fourth contact hole and the second end are both ≥ 0.11 μm;

[0019] A distance between the second contact hole and the first end, and a distance between the third contact hole and the second end, are both ≥0.03 μm.

[0020] The distance between the first end and the side of the first portion close to the first end, and the position between the second end and the side of the second portion close to the second end are both ≥0.04 μm.

[0021] In one embodiment, the semiconductor structure further includes a dielectric layer and a first metal hard mask layer;

[0022] The dielectric layer is located on the upper surface of the thin film resistor;

[0023] The first metal hard mask layer is disposed on an upper surface of the first metal layer.

[0024] In one embodiment, the metal interconnect layer includes a metal interlayer dielectric layer, a second metal layer, and a second metal hard mask layer;

[0025] The intermetallic dielectric layer covers the first metal layer, the thin film resistor and part of the interlayer dielectric layer; the intermetallic dielectric layer has through holes arranged at intervals; the through holes include a first through hole and a second through hole;

[0026] The second metal layer is located on the intermetallic dielectric layer and connected to the first metal layer through the through hole; the second metal layer includes a third portion and a fourth portion which are separately arranged; the third portion is connected to the first metal layer through the first through hole; the fourth portion is connected to the first layer through the second through hole;

[0027] The second metal hard mask layer is disposed on the upper surface of the second metal layer.

[0028] On the other hand, an embodiment of the present application further provides a method for preparing a semiconductor structure, the method comprising:

[0029] A substrate structure is provided; the substrate structure comprises a patterned substrate and an interlayer dielectric layer located on the upper surface of the patterned substrate; a contact hole is provided in the interlayer dielectric layer;

[0030] Forming a thin film resistor located on the surface of the interlayer dielectric layer, so that two ends of the thin film resistor respectively pass through the contact holes to form ohmic contacts with the patterned substrate, and so that the contact holes located on both sides of the thin film resistor are exposed;

[0031] forming a first metal layer located on both sides of the thin film resistor; the first metal layer forms an ohmic contact with the patterned substrate through the contact holes, thereby achieving connection with the thin film resistor;

[0032] A metal interconnection layer is formed covering the first metal layer, the thin film resistor and a portion of the interlayer dielectric layer.

[0033] In one embodiment, the step of forming a thin film resistor located on the surface of the interlayer dielectric layer so that both ends of the thin film resistor respectively pass through the contact holes to form ohmic contacts with the patterned substrate, and so that the contact holes located on both sides of the thin film resistor are exposed, comprises:

[0034] forming the thin film resistor layer located on the upper surface of the interlayer dielectric layer;

[0035] forming a dielectric layer on the upper surface of the thin film resistor layer;

[0036] forming a mask layer on the dielectric layer;

[0037] Performing photolithography on the mask layer to form a first etching window in the mask layer;

[0038] Along the first etching window, using the upper surface of the interlayer dielectric layer as a stop layer, etching the thin film resistor layer and the dielectric layer that are not covered by the mask layer;

[0039] The mask layer is removed to obtain the thin film resistor, and the contact holes located on both sides of the thin film resistor are exposed.

[0040] In one embodiment, the forming of the first metal layer located on both sides of the thin film resistor includes:

[0041] forming an initial first metal layer covering the thin film resistor and the interlayer dielectric layer;

[0042] forming a first metal hard mask layer located on a surface of the initial first metal layer;

[0043] Patterning the first metal hard mask layer to form a second etching window in the first metal hard mask layer;

[0044] Along the second etching window, the initial first metal layer not covered by the first metal hard mask layer is etched with the upper surface of the dielectric layer and the upper surface of the interlayer dielectric layer as stop layers to obtain the first metal layer located on both sides of the thin film resistor.

[0045] In one embodiment, forming a metal interconnect layer covering the first metal layer, the thin film resistor and a portion of the interlayer dielectric layer includes:

[0046] forming an intermetallic dielectric layer covering the first metal layer and the thin film resistor; the intermetallic dielectric layer is provided with a through hole; the through hole penetrates the intermetallic dielectric layer and is connected to the first metal layer;

[0047] an initial second metal layer formed on a surface of the intermetallic dielectric layer;

[0048] forming a second metal hard mask layer located on the initial second metal layer;

[0049] Patterning the second metal hard mask layer to form a third etching window located in the second metal hard mask layer;

[0050] Along the third etching window, the initial second metal layer not covered by the second metal hard mask layer is etched using the upper surface of the intermetallic dielectric layer as a stop layer to obtain a second metal layer; the second metal layer is connected to the first metal layer through the through hole.

[0051] The present application provides a semiconductor structure and a method for manufacturing the same. Compared with the prior art, the present invention has the following beneficial technical effects:

[0052] A thin film resistor is formed on the surface of the interlayer dielectric layer, and a first metal layer is formed on both sides of the thin film resistor, and the first metal layer is not connected to the thin film resistor, and the thin film resistor forms an ohmic contact with the substrate downward through a contact hole located in the interlayer dielectric layer, and another contact hole on the substrate forms an ohmic contact with the first metal layer, thereby realizing the connection between the thin film resistor and the first metal layer. In the above structure, the preparation process of the thin film resistor only requires one etching, so only one mask layer is required, which simplifies the process steps for preparing a semiconductor structure with a thin film resistor, reduces costs, and improves the stability of the preparation process and the qualified rate of the semiconductor structure; and a metal interconnection layer is arranged on the surface of the first metal layer, which can not only ensure a stable circuit connection between the thin film resistor and other circuits, but also optimize the performance of the circuit, reduce resistance and capacitance, reduce signal transmission delay, and improve signal integrity through the layout of the metal interconnection layer. In addition, the introduction of the metal interconnection layer also helps to realize more complex circuit designs and improve the integration and functionality of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 A semiconductor structure with a thin film resistor in the prior art is provided in an embodiment of the present application.

[0055] Figure 2 is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0056] Figure 3 is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0057] Figure 4 It is a schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0058] Figure 5 is a cross-sectional schematic diagram of a substrate structure provided in an embodiment of the present application;

[0059] Figure 6 is a cross-sectional view of a thin film resistor after being formed provided by an embodiment of the present application;

[0060] Figure 7 It is a structural schematic diagram of a preparation process of a thin film resistor provided in an embodiment of the present application;

[0061] Figure 8 is a cross-sectional view after forming a first metal layer provided by an embodiment of the present application;

[0062] Fig. 9 is a structural schematic diagram of a preparation process of a first metal layer provided in an embodiment of the present application;

[0063] Fig.10 is a cross-sectional view after a metal interconnection layer is formed, provided in an embodiment of the present application;

[0064] Fig.11 It is a structural schematic diagram of a preparation process of a metal interconnection layer provided in the present application.

[0065] The following is an explanation of the reference numerals:

[0066] 10-substrate structure; 11-patterned substrate; 111-first substrate; 112-second substrate; 12-interlayer dielectric layer; 13-contact hole; 131-first contact hole; 132-second contact hole; 133-third contact hole; 134-fourth contact hole;

[0067] 20 - thin film resistor; 200 - thin film resistor layer; 201 - first end; 202 - second end;

[0068] 30 - first metal layer; 300 - initial first metal layer; 31 - first metal hard mask layer; 301 - first portion; 302 - second portion;

[0069] 40 - metal interconnect layer; 41 - intermetallic dielectric layer; 42 - through hole; 421 - first through hole; 422 - second through hole; 43 - second metal layer; 430 - initial second metal layer; 431 - third part; 432 - fourth part; 44 - second metal hard mask layer;

[0070] 50 - Dielectric layer. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0072] It should be noted that the diagrams provided in the present embodiment only illustrate the basic concept of the present application in a schematic manner, so the diagram only shows the components related to the present application rather than drawing according to the number, shape and size of the components during actual implementation. The type, quantity and proportion of each component during actual implementation can be a random change, and the component layout type may also be more complicated. In addition, the orientation or position relationship indicated by the terms "upper", "lower", "top" and "bottom" is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. Moreover, the terms "first" and "second" are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of being practiced in sequences other than those illustrated or described herein.

[0073] In the semiconductor field, thin film resistors (FTRs) have attracted widespread attention due to their various advantages, including near-zero TCR, low noise, good matching performance, and electrical trimming capability.

[0074] like Figure 1As shown, in the prior art, when preparing a semiconductor structure including a thin film resistor, it is necessary to form a first interlayer dielectric layer on the substrate, and form a first metal layer M1 in the first interlayer dielectric layer, and deposit the first dielectric layer on the upper surface of the first interlayer dielectric layer; then deposit a CrSi layer (thin film resistor layer) and a TIN layer in sequence on the upper surface of the first dielectric layer, and then deposit a first mask (not shown in the figure), and use dry etching to remove the CrSi layer (thin film resistor layer) above the first metal layer to obtain a CrSi functional area (i.e., the thin film resistor in the figure), and remove the first mask after the etching is completed; then deposit a second dielectric layer on the surface of the TIN layer, and deposit a second mask (not shown in the figure) on the surface of the second dielectric layer, and then remove the middle TIN layer through dry etching and wet etching, retain the TIN layer at both ends of the CrSi functional area, and perform chemical mechanical polishing (CMP) on the CrSi functional area. The above-mentioned CrSi functional area is a thin film resistor. Then, a second interlayer dielectric layer is deposited on the surface of the structure obtained above, and a mask is deposited, and the second interlayer dielectric layer is etched to prepare as shown in the figure. Figure 1 The first contact hole and the conventional first contact hole of the thin film resistor shown in the figure have a smaller etching window, and the etching needs to stop at the TIN layer on the upper surface of the first metal layer and the TIN layer on the upper surface of the thin film resistor at the same time, so it is easy to cause over-etching, resulting in over-etching of the TIN layer on the upper surface of the thin film resistor, which contaminates the thin film resistor. After the etching of the contact hole and the through hole is completed, the second interlayer dielectric layer, the second metal layer, the top metal and other structures are deposited.

[0075] Based on this, the present application embodiment provides a semiconductor structure, such as Figure 2 As shown, the semiconductor structure includes: a substrate structure 10; the substrate structure 10 includes a patterned substrate 11, and an interlayer dielectric layer 12 located on the upper surface of the patterned substrate 11; a contact hole 13 is provided in the interlayer dielectric layer 12; a thin film resistor 20 is located on the interlayer dielectric layer 12; both ends of the thin film resistor 20 respectively form an ohmic contact with the patterned substrate 11 through the contact holes 13; a first metal layer 30 is located on the interlayer dielectric layer 12 and is provided on both sides of the thin film resistor 20; the first metal layer 30 forms an ohmic contact with the patterned substrate 11 through the contact holes 13; a metal interconnection layer 40 covers the first metal layer 30, the thin film resistor 20 and part of the interlayer dielectric layer 12.

[0076] In the present application embodiment, Figure 2 As shown, the semiconductor structure includes:

[0077] The patterned substrate 11 refers to an arrayed substrate obtained by etching the substrate. The substrate is used to provide physical support for the thin film resistor 20 and to achieve electrical isolation and connection between the thin film resistor 20 and other electronic components. Optionally, the substrate material can be Si, SiC or CoSi compound, preferably CoSi compound.

[0078] Optionally, the thickness of the substrate is 10 nm±8 nm, preferably less than 10 nm.

[0079] The interlayer dielectric layer 12 is located on the surface of the patterned substrate 11 and is used to improve the electrical insulation of the semiconductor structure, and is used to place the thin film resistor 20 and the first metal layer 30 located on both sides of the thin film resistor 20. In the embodiment of the present application, the material of the interlayer dielectric layer 12 can be SiO2. A contact hole 13 is provided in the interlayer dielectric layer 12. The contact hole 13 is obtained by etching the interlayer dielectric layer 12, and the contact hole 13 is filled with metal as a lead of the thin film resistor 20. The contact hole 13 extends downward to connect with the patterned substrate 11, and extends upward to connect with the thin film resistor 20 or the first metal layer 30. Optionally, the thickness of the interlayer dielectric layer 12 is Best

[0080] Optionally, the filling metal in the contact hole 13 is tungsten.

[0081] Optionally, the critical dimension (CD) of the contact hole 13 is 0.135 μm±0.05 μm, preferably 0.135 μm.

[0082] The thin film resistor 20 (FER) is located on the surface of the interlayer dielectric layer 12, and the two ends of the thin film resistor 20 are connected to the patterned substrate 11 downward through the contact holes 13 located in the interlayer dielectric layer 12 to form an ohmic contact. Here, it should be noted that the contact holes 13 connected to the two ends of the thin film resistor 20 are located on different arrays in the arrayed substrate.

[0083] Optionally, the material of the thin film resistor 20 may be CrSiN, CrSi, etc., wherein the ratio of elements in CrSiN and CrSi is adjustable, and the specific ratio of elements is not specifically limited in this application.

[0084] Optionally, the thickness of the thin film resistor 20 is The width and length are not limited, but preferably the width is 0.5 nm ± 0.2 nm and the length is 200 μm ± 100 μm.

[0085] The first metal layer 30 is located on the upper surface of the interlayer dielectric layer 12 and is disposed on both sides of the thin film resistor 20, and is not connected to the thin film resistor 20; the first metal layer 30 is connected to the patterned substrate 11 through the contact holes 13 to form an ohmic contact, thereby realizing that the first metal layer 30 located on both sides of the thin film resistor 20 is respectively connected to the two ends of the thin film resistor 20. Optionally, the material of the first metal layer 30 can be aluminum, copper, cobalt, etc., preferably aluminum.

[0086] It should be noted that if Figure 2 As shown, the first metal layer 30 is shown in the figure as a trapezoid with a narrow top and a wide bottom. This can be a specific choice, because the trapezoidal profile with a narrow top and a wide bottom is conducive to the subsequent metal electrode connection and can prevent the metal electrode from breaking. In addition, in some cases, this profile is helpful for the subsequent filling process, such as when forming metal interconnections, it can reduce the generation of voids and defects. This shape can be achieved by precisely controlling the etching conditions (such as RF power, pressure, gas flow, etc.) during the preparation of the first metal layer 30, so as to achieve fine control of the etching morphology, thereby obtaining a trapezoidal profile with a narrow top and a wide bottom. Specifically, reducing the process pressure can increase the mean free path of the ions and reduce the probability of collision between the ions and other particles in the sheath layer, thereby enhancing the directionality of the ions and helping to form a trapezoidal profile with a narrow top and a wide bottom; or by controlling different etching gases and their proportions, the selectivity of the etching and the sidewall passivation effect will be affected. For example, in metal etching, using chlorine as the main etchant and simultaneously using gases such as BCl3 for sidewall passivation can effectively control the etching rate of the sidewalls and form a trapezoidal profile with a narrow top and a wide bottom.

[0087] Optionally, the sidewalls of the first metal layer 30 may also be vertical, which is not limited in the present application.

[0088] Therefore, the thin film resistor 20 in the semiconductor structure provided in the embodiment of the present application forms an ohmic contact with the patterned substrate 11 downward through the contact hole 13 located in the interlayer dielectric layer 12, and forms an ohmic contact with the first metal layer 30 upward through another contact hole 13 on the patterned substrate 11, thereby realizing the use of the contact hole 13 and the patterned substrate 11 to lead out the thin film resistor 20. This is different from the prior art of preparing a through hole 42 above the thin film resistor 20. Therefore, the process flow can be simplified, and there is no need to deposit a through hole 42 stop layer above the thin film resistor 20, and the probability of the thin film resistor 20 being contaminated is reduced.

[0089] In the embodiment of the present application, the method of leading out the thin film resistor 20 through the patterned substrate 11 and the contact hole 13 will not affect the resistance of the thin film resistor 20. Specifically, the resistance of the thin film resistor 20 is generally 30000Ω-120000Ω, and an ohmic contact is formed between the contact hole 13 and the patterned substrate 11, and the resistance is about 90Ω. The resistance between the contact hole 13 and the thin film resistor 20 is less than 10Ω, and the resistance between the contact hole 13 and the first metal layer (M1) 30 can be controlled within 1Ω by controlling the width of M1. Therefore, the above structure will not affect the resistance of the thin film resistor 20.

[0090] The metal interconnection layer 40, located on the surface of the first metal layer 30, refers to a key structure of the semiconductor structure for connecting different electronic components. The metal interconnection layer 40 may include multiple metal layers, an intermetallic dielectric layer 41, and a through hole 42 located in the intermetallic dielectric layer 41 for connecting the upper and lower metal layers. In the embodiment of the present application, in the metal interconnection layer 40, the number of metal layers is not limited.

[0091] From the above description, it can be seen that in the implementation of the present application, the number of contact holes 13 is at least 4, two of which are used to connect the patterned substrate 11 and the two ends of the thin film resistor 20, and two of which are used to connect the first metal layer 30 located at the two ends of the thin film resistor 20 and the patterned substrate 11.

[0092] Thus, in the above structure, the thin film resistor 20 forms an ohmic contact with the substrate downward through the contact hole 13 located in the interlayer dielectric layer 12, and forms an ohmic contact with the first metal layer 30 through another contact hole 13 on the substrate, thereby realizing the connection between the thin film resistor 20 and the first metal layer 30. Because the surface of the thin film resistor 20 in the above structure does not need to be etched with a through hole 42, the preparation process of the above structure only requires one etching, which simplifies the process steps for preparing the semiconductor structure with the thin film resistor 20, reduces the etching of the thin film resistor 20 and reduces the cost; and a metal interconnection layer 40 is arranged on the surface of the first metal layer 30, which can not only ensure the stable circuit connection between the thin film resistor 20 and other circuits, but also optimize the performance of the circuit, reduce resistance and capacitance, reduce signal transmission delay, and improve signal integrity through the layout of the metal interconnection layer 40. In addition, the introduction of the metal interconnection layer 40 also helps to realize more complex circuit design and improve the integration and functionality of semiconductor devices.

[0093] As an optional implementation, the number of the thin film resistors 20 is n, and the number of the contact holes 13 is 4n; wherein n≥1, and n is a positive integer.

[0094] In the embodiment of the present application, multiple thin film resistors 20 can also be integrated in the semiconductor device at one time. When there are multiple thin film resistors 20, in order to make each thin film resistor 20 lead out using the substrate and the contact hole 13, the number of contact holes 13 is set to 4 times the thin film resistor 20, that is, the contact holes 13 in the semiconductor structure lead out the corresponding thin film resistors 20 in groups of 4, and the position setting relationship is the same as Figure 1 That is, there are two contact holes 13 connected to the two ends of the thin film resistor 20, and the other two are not connected to the thin film resistor 20 and are located on both sides of the thin film resistor 20, for connecting the thin film resistor 20 and the metal layer corresponding to the thin film resistor 20.

[0095] As an optional embodiment, the patterned substrate 11 includes a first substrate 111 and a second substrate 112 arranged at intervals; the contact hole 13 includes a first contact hole 131, a second contact hole 132, a third contact hole 133 and a fourth contact hole 134; the first metal layer 30 includes a first part 301 and a second part 302; the first part 301 is arranged on one side of the thin film resistor 20, and the second part 302 is arranged on the other side of the thin film resistor 20; the first part 301 forms an ohmic contact with the first substrate 111 through the first contact hole 131; the second part 302 forms an ohmic contact with the second substrate 112 through the fourth contact hole 134; the thin film resistor 20 includes a first end 201 and a second end 202, the second contact hole 132 is arranged on a side close to the first end 201, and the third contact hole 133 is arranged on a side close to the second end 202; and the thin film resistor 20 forms an ohmic contact with the first substrate 111 through the second contact hole 132, and forms an ohmic contact with the second substrate 112 through the third contact hole 133.

[0096] In the embodiments of the present application, for the convenience of description, Figure 3 As shown, the patterned substrate 11, that is, different arrays in the arrayed substrate are named as the first substrate 111 and the second substrate 112 respectively; the contact holes 13 are named as the first contact hole 131, the second contact hole 132, the third contact hole 133 and the fourth contact hole 134 from left to right respectively; the first metal layer 30 located on both sides of the thin film resistor 20 is named as the first part 301 and the second part 302, and the first part 301 and the second part 302 are separately arranged; the two ends of the thin film resistor 20 are named as the first end 201 and the second end 202 respectively.

[0097] Specifically, Figure 3As shown, the first end 201 of the thin film resistor 20 forms an ohmic contact with the first substrate 111 through the second contact hole 132; the second end 202 of the thin film resistor 20 forms an ohmic contact with the second substrate 112 through the third contact hole 133. Then the first substrate 111 forms an ohmic contact with the first part 301 of the first metal layer 30 through the first contact hole 131; the second substrate 112 forms an ohmic contact with the fourth part 302 of the first metal layer 30 through the fourth contact hole 134. Then the first part 301 and the second part 302 of the first metal layer 30 are connected to the two ends of the thin film resistor 20 respectively.

[0098] As an optional embodiment, the distance between the second contact hole 132 and the third contact hole 133 is ≥0.135μm; the distance between the first contact hole 131 and the second contact hole 132, and the distance between the third contact hole 133 and the fourth contact hole 134 are both ≥0.135μm; the distance between the first contact hole 131 and the first end 201, and the distance between the fourth contact hole 134 and the second end 202 are both ≥0.11μm; the distance between the side of the first portion 301 close to the first end 201 and the first end 201, and the distance between the side of the second portion 302 close to the second end 202 and the second end 202 are both ≥0.04μm; the distance between the second contact hole and the first end, and the distance between the third contact hole and the second end are both ≥0.03μm.

[0099] In the present application embodiment, Figure 3 As shown, in order to control the resistance value of the thin film resistor 20, the distance between the second contact hole 132 and the third contact hole 133 is controlled to be ≥ 0.135 μm; the distance between the first contact hole 131 and the second contact hole 132, and the distance between the third contact hole 133 and the fourth contact hole 134 are all ≥ 0.135 μm.

[0100] In order to achieve that the thin film resistor 20 covers the second contact hole 132 and the third contact hole 133, but does not cover the first contact hole 131 and the fourth contact hole 134, the distance between the first contact hole 131 and the first end 201, and the distance between the fourth contact hole 134 and the second end 202 are controlled to be ≥0.11μm; and the distance between the second contact hole and the first end, and the distance between the third contact hole and the second end are controlled to be ≥0.03μm.

[0101] In order to achieve the goal that the thin film resistor 20 is not in contact with the first metal layer 30, and the two are connected only through the contact hole 13 and the patterned substrate 11, thereby improving the stability and reliability of the connection between the thin film resistor 20 and the first metal layer 30, the distance between the side of the first part 301 close to the first end 201 and the distance between the first end 201 and the side of the second part 302 close to the second end 202 and the position of the second end 202 are controlled to be ≥0.04μm.

[0102] The embodiment of the present application realizes the one-time integration of multiple thin film resistors 20 in the semiconductor structure through the above-mentioned structure, and can realize the resistance control of the thin film resistor 20 by controlling the distance between different contact holes 13. It can also optimize the semiconductor structure design by controlling the distance between the thin film resistor 20 and the first metal layer 30, which is beneficial to optimize the semiconductor structure with the thin film resistor 20, and can simplify the preparation process of the semiconductor structure and improve the performance of the semiconductor structure.

[0103] As an optional implementation, Figure 2 and Figure 3 As shown, the semiconductor structure further includes a dielectric layer 50 and a first metal hard mask layer 31 ; the dielectric layer 50 is located on the upper surface of the thin film resistor 20 ; and the first metal hard mask layer 31 is disposed on the upper surface of the first metal layer 30 .

[0104] In the embodiment of the present application, the dielectric layer 50 is located on the upper surface of the thin film resistor layer 200, and is used to isolate and protect the thin film resistor 20, and its area is consistent with the area of ​​the thin film resistor layer 200. Optionally, the dielectric layer 50 is made of silicon oxide nitride film (SiON), and its performance can be adjusted by changing the element ratio in the silicon oxide nitride film.

[0105] The first metal hard mask layer 31 is located on the upper surface of the first metal layer 30 and is made of a TIN layer (titanium nitride layer). Its main functions are: (1) to serve as a mask during the etching process to protect the first metal layer 30; and (2) to protect the first metal layer 30, to efficiently reduce the wear on the surface of the metal layer, and to extend its service life.

[0106] As an optional implementation, Figure 3 As shown, the metal interconnection layer 40 at least includes an intermetallic dielectric layer 41, a second metal layer 43 and a second metal hard mask layer 44;

[0107] The intermetallic dielectric layer 41 covers the first metal layer 30, the thin film resistor 20 and a part of the interlayer dielectric layer 12; the intermetallic dielectric layer 41 has through holes 42 arranged at intervals; the through holes 42 include a first through hole 421 and a second through hole 422;

[0108] The second metal layer 43 is located on the intermetallic dielectric layer 41 and connected to the first metal layer 30 through the through hole 42; the second metal layer 43 includes a third portion 431 and a fourth portion 432 which are separately arranged; the third portion 431 is connected to the first metal layer 30 through the first through hole 421; the fourth portion 432 is connected to the first metal layer 30 through the second through hole 422;

[0109] The second metal hard mask layer 44 is disposed on the upper surface of the second metal layer 43 .

[0110] In the embodiment of the present application, the intermetallic dielectric layer 41 (IMD) completely covers the first metal layer 30, the thin film resistor 20 and the interlayer dielectric layer 12 on its surface, and the exposed portion of the interlayer dielectric layer 12 between the first metal layer 30 and the thin film resistor 20, and is used to isolate the first metal layer 30 and the second metal layer 43. Optionally, the IMD material can be an organic polymer, an organic silicon material, a fluorinated carbon polymer, a low dielectric constant material, a silicon oxide, etc.

[0111] The second metal layer 43 is located on the surface of the intermetallic dielectric layer 41, and includes a third portion 431 and a fourth portion 432 that are separately arranged. Optionally, the second metal layer 43 may be made of aluminum, copper, cobalt, etc., preferably aluminum.

[0112] The intermetallic dielectric layer 41 has through holes 42 arranged at intervals for connecting different metal layers. Figure 3 The through hole 42 is named as the first through hole 421 and the second through hole 422. The first through hole 421 extends downward to connect with the first part 301 of the first metal layer 30, and extends upward to connect with the third part 431 of the second metal layer 43; the second through hole 422 extends downward to connect with the second part 302 of the first metal layer 30, and extends upward to connect with the fourth part 432 of the second metal layer 43, thereby realizing the interconnection between the first metal layer 30 and the second metal layer 43.

[0113] Optionally, the number of the second through holes 422 is greater than or equal to 2, and may be more than 2, specifically determined according to a specific structure in the metal interconnection layer 40 .

[0114] like Figure 3 As shown, the metal interconnect layer 40 also includes a second metal hard mask layer 44 disposed on the surface of the second metal layer 43. The material of the second metal hard mask layer 44 is a TIN layer (titanium nitride layer). Its main functions are: (1) serving as a mask for the etching process to protect the first metal layer 30; and (2) protecting the second metal layer 43, thereby efficiently reducing the wear on the surface of the metal layer and extending its service life.

[0115] Optionally, the metal interconnect layer 40 may further include more metal layers, a TIN layer on the surface of the metal layer, and an intermetallic dielectric layer 41 for isolating the metal layer. The specific structure may be set according to actual needs and is not specifically limited in this application.

[0116] Optionally, when the second metal layer 43 is not the top metal (TM), that is, when a metal layer is further disposed on the upper layer of the second metal layer 43, the thickness range of the second metal layer 43 is When the second metal layer 43 is the top metal layer, that is, the upper layer of the second metal layer 43 does not include other metal layers, the thickness range of the second metal layer 43 is

[0117] In the embodiment of the present application, a metal interconnection layer 40 is provided on the surface of the first metal layer 30, and the metal interconnection layer at least includes a second metal layer 43, an intermetallic dielectric layer 41, a through hole 42 located in the intermetallic dielectric layer 41, and a TIN layer located on the surface of the second metal layer 43, thereby achieving connection between the second metal layer 43 and the first metal layer 30, while ensuring electrical isolation and mechanical protection. This structure helps to improve the performance and reliability of the integrated circuit.

[0118] It should be noted that each layer in the semiconductor structure provided in the embodiment of the present application is an integral structure, and the terms such as “first contact hole 131 ”, “second contact hole 132 ”, “first substrate 111 ”, etc. in the above description are only for the convenience of describing the specific structure of the semiconductor.

[0119] On the other hand, Figure 4 As shown, the embodiment of the present application also provides a method for preparing a semiconductor structure, the preparation method comprising:

[0120] S10: providing a substrate structure 10; the substrate structure 10 comprises a patterned substrate 11 and an interlayer dielectric layer 12 located on the upper surface of the patterned substrate 11; and a contact hole 13 is disposed in the interlayer dielectric layer 12.

[0121] Figure 5 The cross-sectional view of the substrate structure 10 provided in the embodiment of the present application, the substrate structure 10 includes, from bottom to top, a patterned substrate 11, an interlayer dielectric layer 12, and a contact hole 13 located in the interlayer dielectric layer 12. The preparation method of the substrate structure 10 includes the following steps:

[0122] S11: providing a substrate, depositing a patterned mask on the surface of the substrate, etching the portion not covered by the patterned mask to obtain a patterned substrate 11, that is, an arrayed substrate; and then removing the mask on the surface of the patterned substrate 11.

[0123] S12: Depositing an interlayer dielectric layer (ILD) 12 on the surface of the patterned substrate 11. In the embodiment of the present application, the interlayer dielectric material is SiO2, and the interlayer dielectric layer (ILD) 12 is deposited by using PETEOS technology (Plasma Enhanced Tetraethylorthosilicate, plasma enhanced chemical vapor deposition), by reacting TEOS (tetraethoxysilane) with oxygen to generate a silicon dioxide film and deposit it on the substrate. Optionally, the thickness of the interlayer dielectric layer 12 is Best It is a 90nm standard process.

[0124] S13: depositing a mask on the surface of the interlayer dielectric layer 12 and etching the mask to obtain a mask including an etching window, wherein the etching window defines the position and critical dimension of the contact hole 13. Specifically, the position of the contact hole 13 is determined according to the position, quantity and resistance value of the thin film resistor 20.

[0125] In the above steps, the number of the thin film resistors 20 is n, and the number of the contact holes 13 is 4n; wherein n≥1, and n is a positive integer.

[0126] S14: the interlayer dielectric layer 12 is etched along the etching window and stops at the surface of the patterned substrate 11 to obtain a contact hole 13 located in the interlayer dielectric layer 12; then, the contact hole 13 is filled with metal, and the filling metal is tungsten to obtain the above-mentioned substrate structure 10.

[0127] S30: forming a thin film resistor 20 on the surface of the interlayer dielectric layer 12, so that both ends of the thin film resistor 20 form ohmic contacts with the patterned substrate 11 through the contact holes 13, and so that the contact holes 13 on both sides of the thin film resistor 20 are exposed.

[0128] Figure 6 The cross-sectional schematic diagram after the thin film resistor 20 is formed in the embodiment of the present application is shown. In this step, the thin film resistor 20 can be obtained by depositing a thin film resistor layer 200 on the surface of the interlayer dielectric layer 12 and then etching. During the etching process, each thin film resistor 20 is controlled to cover the second contact hole 132 and the third contact hole 133 in each group of contact holes 13 corresponding to the device, exposing the first contact hole 131 and the fourth contact hole 134, and controlling the distance between the second contact hole 132 and the third contact hole 133 to be ≥0.135μm; the distance between the first contact hole 131 and the second contact hole 132, and the distance between the third contact hole 133 and the fourth contact hole 134 are all ≥0.135μm, and the distance between the first contact hole 131 and the first end 201, and the distance between the fourth contact hole 134 and the second end 202 are all controlled to be ≥0.11μm. Figure 7A schematic diagram of a process for preparing a thin film resistor 20 is shown, and the process includes:

[0129] S31 : forming a thin film resistor layer 200 on the upper surface of the interlayer dielectric layer 12 .

[0130] In this step, the thin film resistor layer 200 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods, preferably PVD. The thin film resistor layer 200 can be made of CrSiN, CrSi, etc., wherein the element ratio of CrSiN and CrSi is adjustable, and the specific element ratio is not specifically limited in this application.

[0131] S32 : forming a dielectric layer 50 on the upper surface of the thin film resistance layer 200 .

[0132] In this step, a dielectric layer 50 is deposited on the surface of the thin film resistor layer 200 by CVD (chemical vapor deposition) or other methods. The dielectric layer 50 is made of silicon oxynitride film (SiON), and its performance can be adjusted by changing the element ratio in the silicon oxynitride film.

[0133] Optionally, the thickness of the dielectric layer 50 is

[0134] S33 : forming a mask layer on the dielectric layer 50 .

[0135] In this step, a mask layer (not shown) is deposited on the surface of the dielectric layer 50 to serve as a mask for etching the thin film resistor layer 200. Optionally, the mask layer may be made of TiN or other photoresist materials.

[0136] S34: performing photolithography on the mask layer to form a first etching window in the mask layer.

[0137] In this step, the mask layer is photolithographically processed to form a patterned mask layer (not shown in the figure). The first etching window on the patterned mask layer exposes the surface of the dielectric layer 50 .

[0138] By controlling the size of the first etching window, not only can the first contact hole 131 and the fourth contact hole 134 located on both sides of the thin film resistor 20 be exposed by etching along the first etching window, but also it can be ensured that the thin film resistor layer 200 can be connected to the second contact hole 132 and the third contact hole 133.

[0139] S35: along the first etching window, using the upper surface of the interlayer dielectric layer 12 as a stop layer, etching the thin film resistor layer 200 and the dielectric layer 50 that are not covered by the mask layer.

[0140] In this step, the area not covered by the mask layer is etched along the first etching window and with the upper surface of the interlayer dielectric layer 12 as a stop layer, so as to etch out the functional area of ​​the thin film resistor layer 200 .

[0141] S36: remove the mask layer to obtain the thin film resistor 20 and expose the contact holes 13 located on both sides of the thin film resistor 20, so that the thin film resistor 20 forms an ohmic contact with the patterned substrate 11 downward through the contact hole 13, and then leads the thin film resistor 20 upward through another contact hole 13 on the patterned substrate 11.

[0142] In this step, after etching is completed, the mask layer on the surface of the dielectric layer 50 is removed to expose the surface of the dielectric layer 50. The unetched thin film resistor layer 200, i.e., the functional area, is the thin film resistor 20, and the thin film resistor 20 can cover the second contact hole 132 and the third contact hole 133 in each group of contact holes 13.

[0143] In the above steps, the key point is to ensure that the exposed contact hole 13 is not over-etched, so as not to affect the connection effect between the first metal layer 30 and the contact hole 13 in the subsequent process. Specifically, the above etching method for the thin film resistor layer 200 can adopt dry etching, and the contact hole 13 is prevented from being over-etched by increasing the selectivity of the thin film resistor layer 200 to the contact hole 13.

[0144] The embodiment of the present application obtains the thin film resistor 20 by depositing a thin film resistor layer 200, a dielectric layer 50 and a mask layer, and then performs photolithography and etching steps, thereby realizing the lead-out of the thin film resistor 20 by using the contact hole 13 and the substrate. In this process, only one dry etching is required, so one mask is used, which reduces the cost and does not require a chemical mechanical polishing step, thereby simplifying the process flow.

[0145] S50 : forming a first metal layer 30 on both sides of the thin film resistor 20 ; the first metal layer 30 forms an ohmic contact with the patterned substrate 11 through the contact holes 13 , thereby achieving connection with the thin film resistor 20 .

[0146] Figure 8The cross-sectional schematic diagram after the first metal layer 30 is formed in the embodiment of the present application is shown. In this step, the first metal layer 30 is obtained by steps such as deposition and etching, and the first part 301 and the second part 302 of the first metal layer 30 obtained by etching are controlled to be not in contact with the thin film resistor 20. Specifically, the distance between the side of the first part 301 close to the first end 201 and the first end 201, and the distance between the side of the second part 302 close to the second end 202 and the second end 202 are both ≥ 0.04 μm. Fig. 9 The schematic diagram of the process of preparing the first metal layer 30 is shown. The method of preparing the first metal layer 30 includes the following steps:

[0147] S51: forming an initial first metal layer 300 covering the thin film resistor 20 and the interlayer dielectric layer 12;

[0148] In this step, an initial first metal layer 300 is deposited on the structure obtained in step S30, and the area of ​​the initial first metal layer 300 can completely cover the thin film resistor 20 and the exposed interlayer dielectric layer 12. The material of the initial first metal layer 300 can be aluminum, copper, cobalt, etc., preferably aluminum.

[0149] S52 : forming a first metal hard mask layer 31 on the surface of the initial first metal layer 300 .

[0150] In this step, a first metal hard mask layer 31 is deposited on the surface of the initial first metal layer 300 . The first metal hard mask layer 31 serves as a mask for etching the initial first metal layer 300 , and its material is TiN.

[0151] S53 : patterning the first metal hard mask layer 31 to form a second etching window in the first metal hard mask layer 31 .

[0152] In this step, a first photoresist layer is first deposited on the surface of the first metal hard mask layer 31, and then the first photoresist layer (not shown in the figure) is etched using a photolithography process to form a patterned first photoresist layer; then the first metal hard mask layer 31 not covered by the patterned first photoresist layer is etched to transfer the pattern of the photoresist to the first metal hard mask layer 31, that is, the first metal hard mask layer 31 is patterned to form a second etching window, exposing the surface of the initial first metal layer 300.

[0153] S54: along the second etching window, using the upper surface of the dielectric layer 50 and the upper surface of the interlayer dielectric layer 12 as stop layers, etching the initial first metal layer 300 not covered by the first metal hard mask layer 31 to obtain the first metal layer 30 located on both sides of the thin film resistor 20.

[0154] In this step, along the second etching window, the initial first metal layer 300 not covered by the first metal hard mask layer 31 is etched with the upper surface of the dielectric layer 50 and the interlayer dielectric as the etching stop layer to obtain the first metal layer 30. The first metal layer 30 includes a first part 301 and a second part 302. The first part 301 is connected to the first contact hole 131, and the second part 302 is connected to the fourth contact hole 134, thereby realizing the connection between the first metal layer 30 and the thin film resistor 20.

[0155] Optionally, the thickness of the first metal layer 30 is The thickness of the first metal hard mask layer 31 is

[0156] Optionally, after etching, the first metal layer 30 satisfies that the distance between the first portion 301 close to the first end 201 and the first end 201, and the position between the second portion 302 close to the second end 202 and the second end 202 are both ≥ 0.04 μm.

[0157] It should be noted that if Fig. 9 As shown, the first metal layer 30 is shown in the figure as a trapezoid with a narrow top and a wide bottom. This can be a specific choice, because the trapezoidal profile with a narrow top and a wide bottom is conducive to the subsequent metal electrode connection and can prevent the metal electrode from breaking. In addition, in some cases, this profile is helpful for the subsequent filling process, such as when forming metal interconnections, it can reduce the generation of voids and defects. This shape can be achieved by precisely controlling the etching conditions (such as RF power, pressure, gas flow, etc.) during the preparation of the first metal layer 30, so as to achieve fine control of the etching morphology, thereby obtaining a trapezoidal profile with a narrow top and a wide bottom. Specifically, reducing the process pressure can increase the mean free path of the ions and reduce the probability of collision between the ions and other particles in the sheath layer, thereby enhancing the directionality of the ions and helping to form a trapezoidal profile with a narrow top and a wide bottom; or by controlling different etching gases and their proportions, the selectivity of the etching and the sidewall passivation effect will be affected. For example, in metal etching, using chlorine as the main etchant and simultaneously using gases such as BCl3 for sidewall passivation can effectively control the etching rate of the sidewalls and form a trapezoidal profile with a narrow top and a wide bottom.

[0158] Optionally, the sidewalls of the first metal layer 30 may also be vertical, which is not limited in the present application.

[0159] In the above process, etching and deposition etc. adopt the 90nm standard process or other existing technologies in the prior art.

[0160] In the above process, in order to ensure the performance of the thin film resistor 20, it is necessary to ensure that there is no residue of the initial first metal layer 300 on the side wall of the thin film resistor 20. First, the embodiment of the present application provides a method for confirming the residue on the side wall of the thin film resistor 20, which can be: (1) After the etching of the initial first metal layer 300 is completed, it can be confirmed by slicing technology whether there is any residue of the initial first metal layer 300 on the side wall of the thin film resistor 20; (2) Through WAT (Wafer Acceptance Test), the electrical parameters of the semiconductor structure are tested, and it is determined whether there is metal residue on the side wall of the thin film resistor 20 based on the electrical parameters; (3) Image analysis technology is used to detect and identify whether there is metal residue on the side wall of the thin film resistor 20.

[0161] Secondly, if it is confirmed that there is metal residue on the side wall of the thin film resistor 20, it can be solved by adjusting the etching process of the first metal layer 30, such as the etching rate, etching gas, etching power of the middle and lower electrodes, etc.; or by adjusting the inclination of the etching interface of the thin film resistor layer 200 to finally determine the appropriate process range.

[0162] In the above process, in order to ensure the performance of the thin film resistor 20, it is also necessary to ensure that the dielectric layer 50 on the surface of the thin film resistor layer 200 is not completely etched, that is, to ensure that the thin film resistor layer 200 is not exposed, and the determination method can refer to the determination method of the sidewall metal residue of the thin film resistor 20. In order to ensure that the dielectric layer 50 is not completely etched, the etching rate and etching time should be strictly controlled, that is, by adjusting the etching process.

[0163] The embodiment of the present application obtains the first metal layer 30 by depositing an initial first metal layer 300 and a first metal hard mask layer 31, and then through photolithography and etching steps, thereby realizing the connection between the thin film resistor 20 and the first metal layer 30 by using the contact hole 13 and the substrate. There is no need to prepare a through hole 42 stop layer on the surface of the thin film resistor 20, thereby simplifying the process flow and the semiconductor structure.

[0164] S70 : forming a metal interconnection layer 40 covering the first metal layer 30 , the thin film resistor 20 and a portion of the interlayer dielectric layer 12 .

[0165] The cross-sectional schematic diagram after the metal interconnection layer 40 is formed in the embodiment of the present application is as follows Fig.10 As shown, in this step, the metal interconnection layer 40 completely covers the first metal layer 30, the thin film resistor 20 and the part of the interlayer dielectric layer 12 exposed in the previous step. The metal interconnection layer 40 at least includes a second metal layer 43, an intermetallic dielectric layer 41 and a through hole 42 (VIA) for connecting the first metal layer 30 and the second metal layer 43. The metal interconnection layer 40 is obtained by alternately performing steps such as deposition and etching. Specifically, the structure of the metal interconnection layer 40 is as follows: Fig.10 When the structure shown is Fig.11 A schematic diagram of a preparation process of a metal interconnection layer 40 is shown, and the preparation process includes:

[0166] S71 : forming an intermetallic dielectric layer 41 covering the first metal layer 30 and the thin film resistor 20 ; a through hole 42 is provided in the intermetallic dielectric layer; the through hole 42 penetrates the intermetallic dielectric layer and is connected to the first metal layer 30 .

[0167] In this step, an intermetallic dielectric layer 41 is deposited on the structure obtained in step S60, and then a mask layer of the intermetallic dielectric layer 41 is deposited on the surface of the metal dielectric layer, and then the mask layer of the intermetallic dielectric layer 41 is etched to obtain a patterned mask layer of the intermetallic dielectric layer 41, and the patterned mask layer of the intermetallic dielectric layer 41 defines the diameter and position of the through hole 42. With the patterned mask layer of the intermetallic dielectric layer 41 as a mask and the first hard mask layer on the surface of the first metal layer 30 as a stop layer, the intermetallic dielectric layer 41 is etched to obtain a through hole 42, and metal is filled into the through hole 42, and the filling metal is tungsten, so that the through hole 42 is connected downward to the first metal layer 30.

[0168] S72 : forming an initial second metal layer 430 on the surface of the intermetallic dielectric layer 41 .

[0169] In this step, an initial second metal layer 430 is deposited on the structure obtained in the above step S50, and the area of ​​the initial second metal layer 430 can completely cover the thin film resistor 20, the first metal layer 30 and the exposed interlayer dielectric layer 12. The material of the initial second metal layer 430 can be aluminum, copper, cobalt, etc., preferably aluminum.

[0170] S73: forming a second metal hard mask layer 44 located on the initial second metal layer 430;

[0171] In this step, a second metal hard mask layer 44 is deposited on the surface of the initial second metal layer 430 . The second metal hard mask layer 44 serves as a mask for etching the initial second metal layer 430 , and its material is TiN.

[0172] S74 : patterning the second metal hard mask layer 44 to form a third etching window located in the second metal hard mask layer 44 .

[0173] In this step, first, a second photoresist layer (not shown in the figure) is deposited on the surface of the second metal hard mask layer 44, and then the second photoresist layer is etched by a photolithography process to form a patterned second photoresist layer; then the second metal hard mask layer 44 not covered by the patterned second photoresist layer is etched to transfer the pattern of the photoresist to the second metal hard mask layer 44, that is, the second metal hard mask layer 44 is patterned to form a third etching window, exposing the surface of the initial second metal layer 430.

[0174] S75: along the third etching window, using the upper surface of the intermetallic dielectric layer 41 as a stop layer, etching the initial second metal layer 430 not covered by the second metal hard mask layer 44 to obtain a second metal layer 43, and the second metal layer 43 is connected to the first metal layer 30 through the through hole 42.

[0175] In this step, along the third etching window, the initial second metal layer 430 not covered by the second metal hard mask layer 44 is etched with the upper surface of the intermetallic dielectric layer 41 as an etching stop layer to obtain a second metal layer 43. The second metal layer 43 includes a third portion 431 and a fourth portion 432. The third portion 431 is connected to the first through hole 421, and the fourth portion 432 is connected to the second through hole, thereby realizing the interconnection between the second metal layer 43 and the first metal layer 30.

[0176] In an optional implementation method, the above step S70 is repeated to obtain more metal layers or a more complex metal interconnection structure.

[0177] Optionally, the shape of the second metal layer 43 may be as follows: Fig.10 The trapezoid shown may also be a rectangle, which is not limited in this application.

[0178] It should be noted that the etching, photolithography, deposition and other processes described in the preparation process provided in the embodiments of the present application adopt existing technologies, such as 90nm standard process, and are not specifically limited in the present application.

[0179] The embodiment of the present application obtains the metal interconnection layer 40 by depositing the intermetallic dielectric layer 41, etching the through hole 42, and depositing and etching the initial second metal layer 430, thereby realizing the connection between the metal interconnection layer 40 and the first metal layer 30 and the thin film resistor 20, not only obtaining a new semiconductor structure, but also avoiding etching the contact hole 13 on the surface of the thin film resistor 20, simplifying the process flow and reducing the production cost. The metal interconnection layer 40 is arranged on the surface of the first metal layer 30, which not only ensures the stable circuit connection between the thin film resistor 20 and other circuits, but also optimizes the performance of the circuit, reduces the resistance and capacitance, reduces the signal transmission delay, and improves the signal integrity through the layout of the metal interconnection layer 40. In addition, the introduction of the metal interconnection layer 40 also helps to realize more complex circuit design and improve the integration and functionality of semiconductor devices.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit the scope of protection of the present invention. Although the present invention is described in detail with reference to the preferred embodiments, it is not limited to those listed in the embodiments. Those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the essence and scope of the technical solution of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: Substrate structure; The substrate structure includes a patterned substrate and an interlayer dielectric layer located on the upper surface of the patterned substrate; A contact hole is provided in the interlayer dielectric layer; A thin film resistor is located on the interlayer dielectric layer; two ends of the thin film resistor respectively pass through the contact holes to form ohmic contacts with the patterned substrate; A first metal layer is located on the interlayer dielectric layer and is arranged on both sides of the thin film resistor; The first metal layer forms an ohmic contact with the patterned substrate through the contact holes respectively; The metal interconnection layer covers the first metal layer, the thin film resistor and a portion of the interlayer dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that: The number of the thin film resistors is n, and the number of the contact holes is 4n; Wherein, n≥1, and n is a positive integer.

3. The semiconductor structure according to claim 2, characterized in that: The patterned substrate includes a first substrate and a second substrate that are spaced apart; The contact holes include a first contact hole, a second contact hole, a third contact hole and a fourth contact hole; The first metal layer includes a first portion and a second portion; the first portion is disposed on one side of the thin film resistor, and the second portion is disposed on the other side of the thin film resistor; The first portion forms an ohmic contact with the first substrate through the first contact hole; the second portion forms an ohmic contact with the second substrate through the fourth contact hole; The thin film resistor includes a first end and a second end, the second contact hole is arranged on a side close to the first end, and the third contact hole is arranged on a side close to the second end; and the thin film resistor forms an ohmic contact with the first substrate through the second contact hole, and forms an ohmic contact with the second substrate through the third contact hole.

4. The semiconductor structure according to claim 3, characterized in that: The distance between the second contact hole and the third contact hole is ≥0.135 μm; The distance between the first contact hole and the second contact hole, and the distance between the third contact hole and the fourth contact hole are both ≥ 0.135 μm; The distance between the first contact hole and the first end, and the distance between the fourth contact hole and the second end are both ≥ 0.11 μm; The distance between the first end and the side of the first portion close to the first end, and the position between the second end and the side of the second portion close to the second end are both ≥ 0.04 μm; A distance between the second contact hole and the first end, and a distance between the third contact hole and the second end, are both ≥0.03 μm.

5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure also includes a dielectric layer and a first metal hard mask layer; The dielectric layer is located on the upper surface of the thin film resistor; The first metal hard mask layer is disposed on an upper surface of the first metal layer.

6. The semiconductor structure according to claim 1, characterized in that The metal interconnect layer includes a metal interlayer dielectric layer, a second metal layer and a second metal hard mask layer; The intermetallic dielectric layer covers the first metal layer, the thin film resistor and a portion of the interlayer dielectric layer; The intermetallic dielectric layer has through holes arranged at intervals; the through holes include a first through hole and a second through hole; The second metal layer is located on the intermetallic dielectric layer and connected to the first metal layer through the through hole; the second metal layer includes a third portion and a fourth portion which are separately arranged; the third portion is connected to the first metal layer through the first through hole; the fourth portion is connected to the first metal layer through the second through hole; The second metal hard mask layer is disposed on the upper surface of the second metal layer.

7. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: A substrate structure is provided; the substrate structure comprises a patterned substrate and an interlayer dielectric layer located on the upper surface of the patterned substrate; a contact hole is provided in the interlayer dielectric layer; Forming a thin film resistor located on the surface of the interlayer dielectric layer, so that two ends of the thin film resistor respectively pass through the contact holes to form ohmic contacts with the patterned substrate, and so that the contact holes located on both sides of the thin film resistor are exposed; forming a first metal layer located on both sides of the thin film resistor; the first metal layer forms an ohmic contact with the patterned substrate through the contact holes, thereby achieving connection with the thin film resistor; A metal interconnection layer is formed covering the first metal layer, the thin film resistor and a portion of the interlayer dielectric layer.

8. The preparation method according to claim 7, characterized in that: The step of forming a thin film resistor located on the surface of the interlayer dielectric layer so that both ends of the thin film resistor respectively pass through the contact holes to form ohmic contacts with the patterned substrate, and so that the contact holes located on both sides of the thin film resistor are exposed, comprises: forming the thin film resistor layer located on the upper surface of the interlayer dielectric layer; forming a dielectric layer on the upper surface of the thin film resistor layer; forming a mask layer on the dielectric layer; Performing photolithography on the mask layer to form a first etching window in the mask layer; Along the first etching window, using the upper surface of the interlayer dielectric layer as a stop layer, etching the thin film resistor layer and the dielectric layer that are not covered by the mask layer; The mask layer is removed to obtain the thin film resistor, and the contact holes located on both sides of the thin film resistor are exposed.

9. The preparation method according to claim 8, characterized in that: The forming of the first metal layer located on both sides of the thin film resistor comprises: forming an initial first metal layer covering the thin film resistor and the interlayer dielectric layer; forming a first metal hard mask layer located on a surface of the initial first metal layer; Patterning the first metal hard mask layer to form a second etching window in the first metal hard mask layer; Along the second etching window, the initial first metal layer not covered by the first metal hard mask layer is etched with the upper surface of the dielectric layer and the upper surface of the interlayer dielectric layer as stop layers to obtain the first metal layer located on both sides of the thin film resistor.

10. The preparation method according to claim 7, characterized in that: The forming of a metal interconnect layer covering the first metal layer, the thin film resistor and a portion of the interlayer dielectric layer comprises: forming an intermetallic dielectric layer covering the first metal layer and the thin film resistor; the intermetallic dielectric layer is provided with a through hole; the through hole penetrates the intermetallic dielectric layer and is connected to the first metal layer; an initial second metal layer formed on a surface of the intermetallic dielectric layer; forming a second metal hard mask layer located on the initial second metal layer; Patterning the second metal hard mask layer to form a third etching window located in the second metal hard mask layer; Along the third etching window, the initial second metal layer not covered by the second metal hard mask layer is etched using the upper surface of the intermetallic dielectric layer as a stop layer to obtain a second metal layer; the second metal layer is connected to the first metal layer through the through hole.

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