Slope compensation circuit for DC-DC converter and DC-DC converter

Abstract

The invention provides a slope compensation circuit for a DC-DC converter and the DC-DC converter, the slope compensation circuit is arranged in the DC-DC converter, and the slope compensation circuit comprises a first current source, a first transistor, a first switch, a first capacitor and a second capacitor; a first end of the first current source is coupled with a working voltage end, a second end is respectively coupled with a first electrode of the first transistor, a first electrode of the first capacitor and a first end of the first switch through a first node, and the first current source charges the first capacitor; a clock signal is input into a control electrode of the first transistor, a second electrode of the first transistor is respectively coupled with a second electrode of the first capacitor, a second electrode of the second capacitor and a grounding end, and when the first transistor is in a first time period of the clock signal, the upper power tube is switched on, the lower power tube is switched off, and the first switch is switched off; the first capacitor is instantaneously and completely discharged, and then the short circuit of the first capacitor is cut off, and a first slope compensation signal is generated at the first node.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a slope compensation circuit for a DC-DC converter and a DC-DC converter. Background Art

[0002] With the increasing expansion of the integrated circuit market, direct current to direct current (DC-DC) converters have also developed rapidly. As a switching power supply technology, DC-DC converters have the advantages of fast dynamic response and simple control, and have a wide range of applications.

[0003] A DC-DC converter with a constant on-time (COT) architecture determines whether to turn on a power tube by detecting the difference between a feedback voltage and a reference voltage. After turning on the power tube, the power tube is turned off for a fixed on-time, and then another power tube is turned on. Therefore, the output voltage is usually required to have a larger ripple. However, as the parasitic series resistance on the output capacitor decreases, the output voltage ripple is smaller, resulting in the inability to guarantee the stability of the circuit.

[0004] With regard to the problem that circuit stability cannot be guaranteed in related technologies, no effective technical solution has been proposed so far. Summary of the invention

[0005] The main purpose of the present disclosure is to provide a slope compensation circuit for a DC-DC converter and a DC-DC converter to solve the problem in the related art that the circuit stability cannot be guaranteed.

[0006] In order to achieve the above-mentioned object, a first aspect of the present disclosure provides a slope compensation circuit for a DC-DC converter, wherein the slope compensation circuit is arranged in the DC-DC converter, and the slope compensation circuit includes a first current source, a first transistor, a first switch, a first capacitor, and a second capacitor;

[0007] A first terminal of the first current source is coupled to the working voltage terminal, a second terminal of the first current source is respectively coupled to the first electrode of the first transistor, the first electrode of the first capacitor and the first terminal of the first switch via the first node, and the first current source is configured to charge the first capacitor;

[0008] The second terminal of the first switch is coupled to the first electrode of the second capacitor;

[0009] The control electrode of the first transistor inputs a clock signal, and the second electrode of the first transistor is respectively coupled to the second electrode of the first capacitor, the second electrode of the second capacitor and the ground terminal. The first transistor is configured such that in a first time period of the clock signal, the upper power tube in the DC-DC converter is turned on, the lower power tube is turned off, the first switch is disconnected, the first capacitor is firstly short-circuited instantaneously, the first capacitor is instantaneously fully discharged, and then the short circuit of the first capacitor is disconnected, so as to generate a first slope compensation signal at the first node.

[0010] Optionally, the slope compensation circuit further includes a second current source, a second transistor and a third current source;

[0011] A first end of the second current source is respectively coupled to the working voltage end and the first end of the first current source, a second end of the second current source is respectively coupled to the control electrode and the first electrode of the second transistor, and the second current source is configured to charge the second capacitor via the second transistor and the second node;

[0012] The second electrode of the second transistor is respectively coupled to the second end of the first switch, the first electrode of the second capacitor and the first end of the third current source via the second node;

[0013] The second end of the third current source is respectively coupled to the second electrode of the second capacitor, the second electrode of the first capacitor, the second electrode of the first transistor and the ground end, and the third current source is configured to discharge the second capacitor.

[0014] Further, in the first time period of the clock signal, the upper power tube is turned on, the lower power tube is turned off, the first switch is disconnected, and a second slope compensation signal is generated at the second node.

[0015] Further, in the first time period of the clock signal, the upper power tube is turned on, the lower power tube is turned off, the first switch is disconnected, and the charging current of the second capacitor by the second current source is controlled to be equal to the discharging current of the second capacitor by the third current source, so that the second slope compensation signal maintains the voltage value of the first slope compensation signal before the upper power tube is turned on.

[0016] Further, in the first time period of the clock signal, the upper power tube is turned on, the lower power tube is turned off, the first switch is disconnected, and the charging current of the second capacitor by the second current source is controlled to be less than the discharging current of the second capacitor by the third current source, so that the second capacitor is discharged, so that the second slope compensation signal decreases linearly from the voltage value of the first slope compensation signal before the upper power tube is turned on.

[0017] Further, when the duty cycle of the clock signal is greater than 0.5, in the first time period of the clock signal, the upper power tube is turned on, the lower power tube is turned off, the first switch is disconnected, and the charging current of the second capacitor by the second current source is controlled to be less than the discharging current of the second capacitor by the third current source, so that the second capacitor is discharged, so that the second slope compensation signal linearly decreases from the voltage value of the first slope compensation signal before the upper power tube is turned on to 0, and the voltage value of the second slope compensation signal is maintained at 0 unchanged.

[0018] Optionally, in the second time period of the clock signal, the upper power tube is turned off, the lower power tube is turned on, the first switch is closed, the second capacitor and the first capacitor are short-circuited, the first capacitor charges the second capacitor, and the voltage of the second capacitor is instantaneously pulled up to the same as that of the first capacitor, wherein the capacitance value of the first capacitor is much larger than the capacitance value of the second capacitor.

[0019] Optionally, the slope compensation circuit further includes a third transistor;

[0020] The control terminal of the third transistor is respectively coupled to the control terminal and the first terminal of the second transistor, the first terminal of the third transistor is coupled to the working voltage terminal, and the second terminal of the third transistor is coupled to the voltage dividing resistor;

[0021] The second transistor and the third transistor form a current mirror, and the current mirror is configured to proportionally reduce the voltage value of the second slope compensation signal and generate a third slope compensation signal through a voltage-dividing resistor.

[0022] Further, the slope compensation circuit further includes a second switch, and the voltage dividing resistor includes a first resistor and a second resistor;

[0023] A first terminal of the second switch is coupled to the second terminal of the first current source, and a second terminal of the second switch is coupled to the second terminal of the second current source;

[0024] The first end of the first resistor is coupled to the second electrode of the third transistor, the second end of the first resistor is coupled to the first end of the second resistor via the third node, the second end of the second resistor is respectively coupled to the second electrode of the second capacitor, the second end of the third current source and the ground terminal, and a third slope compensation signal is generated at the third node.

[0025] A second aspect of the present disclosure provides a DC-DC converter, comprising the slope compensation circuit for a DC-DC converter according to any one of the first aspects above, the DC-DC converter further comprising a ripple generation circuit, a PWM comparator, an on-time control circuit, a logic circuit, a driver, an upper power tube, a lower power tube, an inductor, and an output circuit;

[0026] The output end of the slope compensation circuit outputs a slope compensation signal, and the slope compensation signal is superimposed on a reference voltage to obtain an output signal;

[0027] The output end of the ripple generating circuit outputs a ripple voltage, and the ripple voltage and the feedback voltage are superimposed to obtain a comparison signal;

[0028] The output signal is input to the non-inverting input terminal of the PWM comparator, the comparison signal is input to the inverting non-inverting input terminal of the PWM comparator, and the output terminal of the PWM comparator outputs a control signal to the logic circuit;

[0029] The on-time control circuit is used to set the on-time of the upper power tube, the logic circuit is used to output a PWM signal to the driver according to the on-time and the control signal, and the driver is used to drive the upper power tube and the lower power tube according to the PWM signal;

[0030] The first end of the inductor is respectively coupled to the first pole of the upper power tube and the first pole of the lower power tube, and the second end of the inductor is respectively coupled to the ripple generating circuit and the output circuit.

[0031] In the slope compensation circuit for a DC-DC converter provided in an embodiment of the present disclosure, the slope compensation circuit includes a first current source, a first transistor, a first switch, a first capacitor, and a second capacitor. The first current source is configured to charge the first capacitor. The first transistor is configured to turn on the upper power tube and turn off the lower power tube in the DC-DC converter in the first time period of the clock signal, and the first switch is disconnected. The first capacitor is first short-circuited instantaneously, and the first capacitor is completely discharged instantaneously, and then the short-circuit of the first capacitor is disconnected, and a first slope compensation signal is generated at the first node. The first transistor in the present disclosure generates a first slope compensation signal by first short-circuiting the first capacitor instantaneously and then disconnecting the short-circuit. The first slope compensation signal is used for compensation, so as to improve the stability of the DC-DC converter circuit and solve the problem that the circuit stability cannot be guaranteed in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 is a waveform diagram of a compensation signal in the related art;

[0034] Figure 2 It is a stable waveform diagram under a large duty cycle in the related technology;

[0035] Figure 3 This is a waveform diagram showing instability caused by increasing the ramp voltage at a large duty cycle in the related art;

[0036] Figure 4 An exemplary circuit diagram of a slope compensation circuit provided for the first embodiment of the present disclosure;

[0037] Figure 5 An exemplary circuit diagram of a slope compensation circuit provided for a second embodiment of the present disclosure;

[0038] Figure 6 An exemplary waveform diagram of a second slope compensation signal provided in an embodiment of the present disclosure;

[0039] Figure 7 An exemplary waveform diagram of a second slope compensation signal at a large duty cycle provided by an embodiment of the present disclosure;

[0040] Figure 8 An exemplary circuit diagram of a DC-DC converter provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0043] In all embodiments of the present disclosure, since the source and drain of the metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of the N-type transistor and the P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle end of the MOS transistor is referred to as the control electrode, and the remaining two ends of the MOS transistor are referred to as the first electrode and the second electrode, respectively. The transistors used in the embodiments of the present disclosure are mainly switching transistors. In addition, for the convenience of unified expression, in the context, the base of the bipolar junction transistor (BJT) is referred to as the control electrode, the emitter of the BJT is referred to as the first electrode, and the collector of the BJT is referred to as the second electrode. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0044] A DC-DC converter with a constant on-time (COT) architecture determines whether to turn on a power tube by detecting the difference between a feedback voltage and a reference voltage. After turning on the power tube, the power tube is turned off for a fixed on-time, and then another power tube is turned on. Therefore, the output voltage is usually required to have a larger ripple. However, as the parasitic series resistance on the output capacitor decreases, the output voltage ripple is smaller, resulting in the inability to guarantee the stability of the circuit.

[0045] When the output voltage ripple is very small, in order to maintain the stability of the DC-DC converter system loop, the relevant technology adopts an additional compensation method. Usually, a ripple voltage Vripple and a ramp voltage Vramp in the same phase as the inductor current are introduced. Taking the BUCK circuit as an example, the compensation waveform diagram is as follows: Figure 1 As shown, the clock signal CLK turns high to trigger the upper power tube drive signal MAIN_ON to control the upper power tube to turn on. At this time, the inductor is charged and the inductor current is upward. After a fixed time, the upper power tube drive signal MAIN_ON turns low, the inductor is discharged, and the inductor current decreases. The ripple voltage Vripple is in the same direction as the inductor current, so it also rises when the upper power tube drive signal MAIN_ON is high and decreases when it is low. The ramp voltage Vramp will be pulled down when the upper power tube drive signal MAIN_ON just turns high, and then gradually rises throughout the cycle, forming a ramp voltage.

[0046] The larger the amplitude of the compensated ripple voltage Vripple, the more stable the system will be, but at the same time it will reduce the bandwidth of the loop and reduce the dynamic response of the system, such as the response to load jump. The compensated ramp voltage Vramp is usually not affected by this, and the same effect as increasing the ripple voltage Vripple can be achieved by increasing the amplitude of the ramp voltage Vramp without significantly affecting the bandwidth of the loop and sacrificing dynamic performance. However, increasing the ramp voltage Vramp will cause other problems. For example, increasing the amplitude of the slope compensation signal Vramp and still pulling the slope compensation signal Vramp down to zero when the clock signal CLK comes may cause instability.

[0047] Because of the introduction of the ramp voltage Vramp and the ripple voltage Vripple, the condition for the clock signal CLK to turn high to turn on the upper power tube changes from VFB=VREF to VFB+Vripple=VREF+Vramp. The ramp voltage Vramp is quickly pulled down after the clock signal CLK turns high, ensuring that the above equation is not easy to trigger again, so that the clock signal CLK is not easy to mistakenly turn high just after MAIN_ON ends, so as to maintain the stability of the loop. However, for a relatively high duty cycle, such as when the duty cycle is close to 100%, since the input voltage Vin and the output voltage Vout are very close, it takes a long time to charge the inductor Lx. At this time, the clock signal CLK is usually wider, even wider than the MAIN_ON signal. At this time, the system can automatically reduce the frequency to ensure that the inductor is charged with enough energy. The example of a stable waveform under a large duty cycle is shown in the figure below. Figure 2 shown.

[0048] However, increasing the ramp voltage Vramp amplitude and still keeping Vramp pulled down to zero when CLK comes may cause instability. The waveform diagram of instability caused by increasing the ramp voltage Vramp under a large duty cycle is shown in the figure below. Figure 3 As shown in the figure, since the condition for CLK to turn high is VFB+Vripple=VREF+Vramp, the pull-down of Vramp causes CLK to drop easily, which enhances the stability of the system under small duty cycle. However, under large duty cycle, since Vin and Vout are close, the charging speed is slow, the feedback voltage VFB rises slowly, and Vripple also rises slowly, which may cause the above equation to be established again as Vramp gradually rises, causing CLK to turn high again. In this way, the previous charging cycle may just end, but CLK turns high again, causing the upper power tube to be turned on again for charging, until MAIN_ON becomes low and CLK becomes low again, and then charging stops. If this continues, it will lead to uneven output and system instability.

[0049] At the same time, since the slope of the ripple voltage Vripple is related to the input voltage Vin and the output voltage Vout, and the ramp voltage Vramp is a fixed slope, under certain input voltage and output voltage, there is a situation where the rising slope of Vripple is similar to that of Vramp. In this case, after CLK, in the rising stage, Vramp and Vripple rise with the same slope, and the equation VFB+Vripple=VREF+Vramp becomes a comparison between the feedback voltage VFB and the reference voltage VREF, which may also cause instability.

[0050] In order to solve the above problems, the present disclosure provides a slope compensation circuit for a DC-DC converter. Figure 4 As shown, the slope compensation circuit is arranged in the DC-DC converter, and the slope compensation circuit includes a first current source I1, a first transistor M1, a first switch S1, a first capacitor C1 and a second capacitor C2;

[0051] A first terminal of the first current source I1 is coupled to the working voltage terminal Vdd, a second terminal of the first current source I1 is respectively coupled to the first electrode of the first transistor M1, the first electrode of the first capacitor C1 and the first terminal of the first switch S1 via the first node N1, and the first current source I1 is configured to charge the first capacitor C1;

[0052] A second terminal of the first switch S1 is coupled to a first electrode of the second capacitor C2;

[0053] The control electrode of the first transistor M1 inputs the clock signal, and the second electrode of the first transistor M1 is respectively coupled to the second electrode of the first capacitor C1, the second electrode of the second capacitor C2 and the ground terminal. The first transistor M1 is configured such that in the first time period of the clock signal, the upper power tube in the DC-DC converter is turned on, the lower power tube is turned off, the first switch S1 is turned off, the first capacitor C1 is first short-circuited instantaneously, the first capacitor C1 is instantly fully discharged, and then the short-circuit of the first capacitor C1 is disconnected, and the first slope compensation signal RAMP1 is generated at the first node N1. The first time period is the period when the upper power tube is turned on and the lower power tube is turned off.

[0054] The first current source I1 charges the first capacitor C1 and discharges the first capacitor C1 according to a cycle determined by the clock signal to generate a first slope compensation signal RAMP1.

[0055] The first transistor in the present disclosure generates a first slope compensation signal by first momentarily short-circuiting the first capacitor and then disconnecting the short circuit. The first slope compensation signal is used for compensation, thereby improving the stability of the DC-DC converter circuit and solving the problem in the related art that the circuit stability cannot be guaranteed.

[0056] Based on the above embodiments, in an optional implementation manner of the present disclosure, an exemplary circuit diagram of a slope compensation circuit is as follows: Figure 5 As shown, the slope compensation circuit further includes a second current source I2, a second transistor M2 and a third current source I3;

[0057] A first terminal of the second current source I2 is respectively coupled to the working voltage terminal Vdd and the first terminal of the first current source I1, a second terminal of the second current source I2 is respectively coupled to the control electrode and the first electrode of the second transistor M2, and the second current source I2 is configured to charge the second capacitor C2 via the second transistor M2 and the second node N2;

[0058] The second electrode of the second transistor M2 is respectively coupled to the second end of the first switch S1, the first electrode of the second capacitor C2 and the first end of the third current source I3 via the second node N2;

[0059] A second end of the third current source I3 is respectively coupled to the second electrode of the second capacitor C2 , the second electrode of the first capacitor C1 , the second electrode of the first transistor M1 and the ground end, and the third current source I3 is configured to discharge the second capacitor C2 .

[0060] The duty cycle information can be added to the third current source I3. Under a small duty cycle, the current of the third current source I3 is very large and is pulled down quickly, so that the same waveform as the first slope compensation signal RAMP can be obtained; under a large duty cycle, the current of the third current source I3 is small and is pulled down slowly, so that the second slope compensation signal RAMP2 which is an improvement on the first slope compensation signal RAMP can be obtained.

[0061] In an optional implementation of the present disclosure, in the first time period of the clock signal, the upper power tube is turned on, the lower power tube is turned off, the first switch S1 is disconnected, and a second slope compensation signal RAMP2 is generated at the second node N2. Different second slope compensation signals RAMP2 can be generated under different conditions such as different duty cycles.

[0062] In an optional implementation of the present disclosure, in a first time period of the clock signal, the upper power tube is turned on, the lower power tube is turned off, the first switch S1 is disconnected, and the charging current of the second capacitor C2 by the second current source I2 is controlled to be equal to the discharging current of the second capacitor C2 by the third current source I3, so that the second slope compensation signal RAMP2 maintains the voltage value of the first slope compensation signal RAMP1 before the upper power tube is turned on.

[0063] When the charging current of the second current source I2 on the second capacitor C2 and the discharging current of the third current source I3 on ​​the second capacitor C2 are equal, the second capacitor C2 is neither charged nor discharged, and the second slope compensation signal RAMP2 remains unchanged.

[0064] Figure 6 An exemplary waveform diagram of a second slope compensation signal provided in an embodiment of the present disclosure is shown in FIG. Figure 6 In the example, ON is the driving signal or control signal of the upper power tube, which controls the opening and closing of the upper power tube; Figure 6 As shown in the path 1 of the second slope compensation signal RAMP2, when the clock signal CLK turns on the upper power tube, the second slope compensation signal RAMP2 does not need to be directly pulled low like the first slope compensation signal RAMP1, but is kept at the original voltage value to avoid the second slope compensation signal RAMP2 being pulled down too quickly and causing the upper power tube to be turned on frequently; when the upper power tube is turned off and the lower power tube is turned on, the second slope compensation signal RAMP2 rises with the first slope compensation signal RAMP1, and then the process is repeated periodically.

[0065] The first switch S1 is disconnected when the upper power tube is turned on, and the voltage of the second capacitor C2 is maintained at the previous state. This situation corresponds to Figure 6 Path 1; if necessary Figure 6 For path 2, it is necessary to use the third current source I3 to gradually discharge the second capacitor C2.

[0066] In an optional embodiment of the present disclosure, in the first time period of the clock signal, the upper power tube is turned on, the lower power tube is turned off, the first switch S1 is disconnected, and the charging current of the second current source I2 to the second capacitor C2 is controlled to be less than the discharging current of the third current source I3 to the second capacitor C2, and the second capacitor C2 is discharged, so that the second slope compensation signal RAMP2 decreases linearly from the voltage value of the first slope compensation signal RAMP1 before the upper power tube is turned on. When the second current source I2 is less than the third current source I3, the second capacitor C2 is discharged;

[0067] like Figure 6 As shown in the path 2 of the second slope compensation signal RAMP2, when the clock signal CLK turns on the upper power tube, the second slope compensation signal RAMP2 is not directly pulled low like the first slope compensation signal RAMP1, but the second capacitor C2 is gradually discharged. Since the duty cycle is small and the discharge time is short, the second capacitor C2 is not completely discharged, and the second slope compensation signal RAMP2 is not pulled down to 0; when the upper power tube is turned off and the lower power tube is turned on, the second slope compensation signal RAMP2 rises with the first slope compensation signal RAMP1, and then the process is repeated periodically.

[0068] In an optional embodiment of the present disclosure, when the duty cycle of the clock signal is greater than 0.5, in the first time period of the clock signal, the upper power tube is turned on and the lower power tube is turned off, the first switch S1 is disconnected, and the charging current of the second current source I2 to the second capacitor C2 is controlled to be less than the discharging current of the third current source I3 to the second capacitor C2, so that the second capacitor C2 is discharged, so that the second slope compensation signal RAMP2 linearly decreases from the voltage value of the first slope compensation signal RAMP1 before the upper power tube is turned on to 0, and the voltage value of the second slope compensation signal RAMP2 is maintained at 0 unchanged.

[0069] In the case of a large duty cycle, a duty cycle greater than 0.5, for example, a duty cycle close to 100%, the second slope compensation signal RAMP2 is pulled down to 0 and maintained for a period of time, the duty cycle is large, the discharge time is long, the larger the duty cycle, the longer the upper power tube is turned on, the longer the discharge time, the second capacitor is completely discharged to 0, and the voltage value is maintained at 0 for a period of time;

[0070] Figure 7 An exemplary waveform diagram of the second slope compensation signal at a large duty cycle is provided for an embodiment of the present disclosure, wherein ON is a driving signal or a control signal of the upper power tube, which controls the turning on and off of the upper power tube; when the upper power tube is turned on, the second slope compensation signal RAMP2 will be gradually discharged to 0 and then maintained at 0 until the upper power tube is turned off and the lower power tube is turned on, and the second slope compensation signal RAMP2 will become the same as the value of the first slope compensation signal RAMP1.

[0071] The second slope compensation signal RAMP2 does not have a fast pull-down process, which can solve the problem of instability caused by fast pull-down under a large duty cycle; and, since the ripple voltage RIPPLE and the first slope compensation signal RAMP1 are both rising when the upper power tube is turned on, there may be a close slope that causes circuit instability. The second slope compensation signal RAMP2 provided in the embodiment of the present disclosure is in a state of remaining unchanged or decreasing when the ripple voltage RIPPLE rises, which can also avoid instability caused by close slopes and solve the problem of circuit instability;

[0072] In addition, for applications with a duty cycle close to 100%, when the upper power tube is turned on, the input voltage Vin and the output voltage Vout are close, resulting in a very slow charging speed. However, when the upper power tube is turned off and the lower power tube is turned on, the output voltage Vout is very high and the discharge is very fast. This may cause a large output ripple without control. Since the second slope compensation signal RAMP2 is quickly pulled up to the first slope compensation signal RAMP1 when the upper power tube is turned off and the lower power tube is turned on, CLK can be generated faster, which is equivalent to shortening the fast discharge time and reducing the output ripple voltage.

[0073] In an optional implementation of the present disclosure, in the second time period of the clock signal, the upper power tube is turned off, the lower power tube is turned on, the first switch S1 is closed, the second capacitor C2 and the first capacitor C1 are short-circuited, the first capacitor C1 charges the second capacitor C2, and the voltage of the second capacitor C2 is instantly pulled up to the same as the first capacitor C1, wherein the capacitance value of the first capacitor C1 is much greater than the capacitance value of the second capacitor C2. The second time period is when the upper power tube is turned off and the lower power tube is turned on; when the lower power tube is turned on, the first switch S1 is closed, the second capacitor C2 and the first capacitor C1 are short-circuited together, and the second capacitor C2 completes the sampling of the waveform of the first capacitor C1 by the second capacitor C2.

[0074] Figure 5 In the slope compensation circuit, the slope compensation circuit further includes a third transistor M3;

[0075] The control end of the third transistor M3 is coupled to the control end and the first end of the second transistor M2 respectively, the first end of the third transistor M3 is coupled to the working voltage end Vdd, and the second end of the third transistor M3 is coupled to the voltage dividing resistor;

[0076] The second transistor M2 and the third transistor M3 form a current mirror, which is configured to proportionally reduce the voltage value of the second slope compensation signal RAMP2 and generate a third slope compensation signal RAMP3 through a voltage-dividing resistor. The third slope compensation signal RAMP3 proportionally reduced compared to the second slope compensation signal RAMP2 can be generated through the current mirror and the voltage-dividing resistor.

[0077] Figure 5 In the embodiment, the slope compensation circuit further includes a second switch S2, and the voltage dividing resistor includes a first resistor r1 and a second resistor r2;

[0078] The first end of the second switch S2 is coupled to the second end of the first current source I1, and the second end of the second switch S2 is coupled to the second end of the second current source I2; the second switch S2 is generally in an open state; optionally, the first switch S1 and the second switch S2 may be closed, and the second current source I2 and the third current source I3 may be removed to restore the existing first slope compensation signal RAMP1;

[0079] A first end of the first resistor r1 is coupled to the second electrode of the third transistor M3, a second end of the first resistor r1 is coupled to the first end of the second resistor r2 via a third node N3, a second end of the second resistor r2 is respectively coupled to the second electrode of the second capacitor C2, a second end of the third current source I3 and the ground, and a third slope compensation signal RAMP3 is generated at the third node N3.

[0080] The present disclosure also provides a DC-DC converter 100, such as Figure 8As shown, a slope compensation circuit 107 for a DC-DC converter includes any one of the above items, and the DC-DC converter also includes a ripple generating circuit 102, a PWM comparator 103, an on-time control circuit 104, a logic circuit 105, a driver 106, an upper power tube Q1, a lower power tube Q2, an inductor Lx and an output circuit; wherein the ripple generating circuit 102, the PWM comparator 103, the on-time control circuit 104, the logic circuit 105, the driver 106 and the slope compensation circuit 107 constitute a control circuit 110;

[0081] The output end of the slope compensation circuit 107 outputs a slope compensation signal Vramp, and the slope compensation signal Vramp is superimposed on the reference voltage VREF to obtain an output signal Veao;

[0082] The output terminal of the ripple generating circuit 102 outputs a ripple voltage Vripple, and the ripple voltage Vripple and the feedback voltage VFB are superimposed to obtain a comparison signal Vcomp; wherein the output voltage Vout is divided by the resistors R1 and R2 to obtain the feedback voltage VFB;

[0083] The output signal Veao is input to the non-inverting input terminal of the PWM comparator 103, the comparison signal Vcomp is input to the inverting input terminal of the PWM comparator 103, and the output terminal of the PWM comparator 103 outputs a control signal CTRL to the logic circuit 105;

[0084] The on-time control circuit 104 is used to set the on-time Ton of the upper power tube Q1, the logic circuit 105 is used to output a PWM signal to the driver 106 according to the on-time Ton and the control signal CTRL, and the driver 106 is used to drive the upper power tube Q1 and the lower power tube Q2 according to the PWM signal;

[0085] The first end of the inductor Lx is respectively coupled to the first electrode of the upper power tube Q1 and the first electrode of the lower power tube Q2, and the second end of the inductor Lx is respectively coupled to the ripple generating circuit 102 and the output circuit. The output circuit includes an output capacitor Cout, a parasitic series resistor Resr of the output capacitor Cout, a load resistor RL, and feedback resistors R1 and R2.

[0086] Figure 8In the embodiment, the output voltage Vout is divided by the resistors R1 and R2 to obtain the feedback voltage VFB, and the feedback voltage VFB is sent to the non-inverting input terminal of the PWM comparator 103 through the adder; the ripple generating circuit 102 is used to obtain the ripple signal Vripple which is synchronized with and in phase with the inductor current of the DC-DC converter 100; the slope compensation circuit 107 is used to generate the slope compensation signal Vramp; the on-time control circuit 104 is used to set the on-time Ton of the upper power tube Q1; the non-inverting input terminal of the PWM comparator 103 is used to receive the superimposed signal Veao of the reference voltage VREF and the slope compensation signal Vramp, and the inverting input terminal of the PWM comparator 103 is used to receive the ripple signal Vrip The PWM comparator 103 is used to compare the signal Veao with the signal Vcomp to generate a conduction control signal CTRL, wherein Vcomp=Vripple+VFB, Veao=Vramp+VREF; the conduction time control circuit 104 is used to set the turn-on time Ton of the upper power tube Q1, the logic circuit 105 is used to output a PWM signal to the driver 106 according to the turn-on time Ton and the control signal CTRL, and the driver 106 is used to generate a drive signal (MAIN_ON signal) for driving the upper power tube Q1 and a drive signal for driving the switch tube Q2 according to the pulse width modulation signal PWM. When the COT-controlled DC-DC converter 100 detects that the output voltage Vout is low, it gives a trigger signal to turn on the main switch tube (i.e., the upper power tube Q1) of the DC-DC converter, and turns off the upper power tube Q1 again after the set on-time Ton. Then, after the set minimum off-time Toff-min, if the PWM comparator 103 detects that the output voltage Vout is low again, it triggers the upper power tube Q1 to turn on again, and the cycle repeats.

[0087] From the above description, it can be seen that the present disclosure achieves the following technical effects:

[0088] The first transistor in the present disclosure generates a first slope compensation signal by first instantaneously short-circuiting the first capacitor and then disconnecting the short-circuit. The first slope compensation signal is used for compensation, thereby improving the stability of the DC-DC converter circuit and solving the problem that the circuit stability cannot be guaranteed in the related art.

[0089] The second slope compensation signal provided by the present invention does not have a fast pull-down process, which can solve the instability problem caused by fast pull-down under a large duty cycle; the second slope compensation signal is in a constant or downward state when the ripple voltage rises, which can avoid instability caused by close slopes and solve the problem of circuit instability.

[0090] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the device and method according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, a program segment or an instruction, and a part of the module, a program segment or an instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0091] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0092] Further aspects and scopes become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present disclosure.

[0093] Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A slope compensation circuit for a DC-DC converter, characterized in that: The slope compensation circuit is arranged in a DC-DC converter, and the slope compensation circuit comprises a first current source, a first transistor, a first switch, a first capacitor and a second capacitor; A first terminal of the first current source is coupled to a working voltage terminal, a second terminal of the first current source is respectively coupled to a first electrode of the first transistor, a first electrode of the first capacitor and a first terminal of the first switch via a first node, and the first current source is configured to charge the first capacitor; The second end of the first switch is coupled to the first electrode of the second capacitor; A clock signal is input to the control electrode of the first transistor, and a second electrode of the first transistor is respectively coupled to a second electrode of the first capacitor, a second electrode of the second capacitor and a ground terminal. The first transistor is configured such that in a first time period of the clock signal, an upper power tube in the DC-DC converter is turned on and a lower power tube is turned off, and the first switch is disconnected, and the first capacitor is firstly short-circuited instantaneously, and the first capacitor is completely discharged instantaneously, and then the short-circuit of the first capacitor is disconnected, so as to generate a first slope compensation signal at the first node.

2. The slope compensation circuit for a DC-DC converter according to claim 1, characterized in that: The slope compensation circuit also includes a second current source, a second transistor and a third current source; A first terminal of the second current source is respectively coupled to the working voltage terminal and the first terminal of the first current source, a second terminal of the second current source is respectively coupled to the control electrode and the first electrode of the second transistor, and the second current source is configured to charge the second capacitor via the second transistor and the second node; The second electrode of the second transistor is respectively coupled to the second end of the first switch, the first electrode of the second capacitor and the first end of the third current source via the second node; The second end of the third current source is respectively coupled to the second electrode of the second capacitor, the second electrode of the first capacitor, the second electrode of the first transistor and the ground end, and the third current source is configured to discharge the second capacitor.

3. The slope compensation circuit for a DC-DC converter according to claim 2, characterized in that: In a first time period of the clock signal, the upper power tube is turned on, the lower power tube is turned off, the first switch is disconnected, and a second slope compensation signal is generated at the second node.

4. The slope compensation circuit for a DC-DC converter according to claim 3, characterized in that: In the first time period of the clock signal, the upper power tube is turned on, the lower power tube is turned off, the first switch is disconnected, and the charging current of the second capacitor by the second current source is controlled to be equal to the discharging current of the second capacitor by the third current source, so that the second slope compensation signal maintains the voltage value of the first slope compensation signal before the upper power tube is turned on.

5. The slope compensation circuit for a DC-DC converter according to claim 3, characterized in that: In the first time period of the clock signal, the upper power tube is turned on, the lower power tube is turned off, the first switch is disconnected, and the charging current of the second capacitor by the second current source is controlled to be smaller than the discharging current of the second capacitor by the third current source, so that the second capacitor is discharged, so that the second slope compensation signal decreases linearly from the voltage value of the first slope compensation signal before the upper power tube is turned on.

6. The slope compensation circuit for a DC-DC converter according to claim 3, characterized in that: When the duty cycle of the clock signal is greater than 0.5, in the first time period of the clock signal, the upper power tube is turned on, the lower power tube is turned off, the first switch is turned off, and the charging current of the second capacitor by the second current source is controlled to be less than the discharging current of the second capacitor by the third current source, so that the second capacitor is discharged, so that the second slope compensation signal linearly decreases from the voltage value of the first slope compensation signal before the upper power tube is turned on to 0, and the voltage value of the second slope compensation signal is maintained at 0 unchanged.

7. The slope compensation circuit for a DC-DC converter according to claim 2, characterized in that: In the second time period of the clock signal, the upper power tube is turned off, the lower power tube is turned on, the first switch is closed, the second capacitor and the first capacitor are short-circuited, the first capacitor charges the second capacitor, and the voltage of the second capacitor is instantaneously pulled up to the same as that of the first capacitor, wherein the capacitance value of the first capacitor is much larger than the capacitance value of the second capacitor.

8. The slope compensation circuit for a DC-DC converter according to claim 2, characterized in that: The slope compensation circuit further includes a third transistor; The control terminal of the third transistor is respectively coupled to the control terminal and the first terminal of the second transistor, the first terminal of the third transistor is coupled to the working voltage terminal, and the second terminal of the third transistor is coupled to a voltage dividing resistor; The second transistor and the third transistor form a current mirror, and the current mirror is configured to proportionally reduce the voltage value of the second slope compensation signal and generate a third slope compensation signal through the voltage dividing resistor.

9. The slope compensation circuit for a DC-DC converter according to claim 8, characterized in that: The slope compensation circuit further includes a second switch, and the voltage dividing resistor includes a first resistor and a second resistor; A first terminal of the second switch is coupled to a second terminal of the first current source, and a second terminal of the second switch is coupled to a second terminal of the second current source; The first end of the first resistor is coupled to the second electrode of the third transistor, the second end of the first resistor is coupled to the first end of the second resistor via a third node, the second end of the second resistor is respectively coupled to the second electrode of the second capacitor, the second end of the third current source and the ground terminal, and the third slope compensation signal is generated at the third node.

10. A DC-DC converter, characterized in that: A slope compensation circuit for a DC-DC converter comprising any one of claims 1 to 9, wherein the DC-DC converter further comprises a ripple generating circuit, a PWM comparator, an on-time control circuit, a logic circuit, a driver, an upper power tube, a lower power tube, an inductor and an output circuit; The output end of the slope compensation circuit outputs a slope compensation signal, and the slope compensation signal is superimposed on a reference voltage to obtain an output signal; The output end of the ripple generating circuit outputs a ripple voltage, and the ripple voltage is superimposed on the feedback voltage to obtain a comparison signal; The output signal is input to the non-inverting input terminal of the PWM comparator, the comparison signal is input to the inverting non-inverting input terminal of the PWM comparator, and the output terminal of the PWM comparator outputs a control signal to the logic circuit; The on-time control circuit is used to set the on-time of the upper power tube, the logic circuit is used to output a PWM signal to the driver according to the on-time and the control signal, and the driver is used to drive the upper power tube and the lower power tube according to the PWM signal; The first end of the inductor is respectively coupled to the first pole of the upper power tube and the first pole of the lower power tube, and the second end of the inductor is respectively coupled to the ripple generating circuit and the output circuit.

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