Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board includes: a substrate having a cavity; a semiconductor device including a first metal pad and a second metal pad, and disposed at least partially in the cavity, where the first metal pad is disposed on a lower side of the semiconductor device and the second metal pad is disposed on an upper side of the semiconductor device; a metal block at least partially disposed in the cavity, the metal block connected to the second metal pad; and a first insulating layer covering at least a portion of each of the substrate, the semiconductor device, and the metal block, and filling at least a portion of the cavity.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0140049 filed on October 19, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] According to the increase of input / output (I / O) terminals, there is a recent trend that electronic components applied to electronic devices become light, thin, short and small. For this reason, there is a demand to embed semiconductor devices (eg, power devices) in printed circuit boards. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board having a semiconductor device, such as a power device, embedded therein.

[0005] Another aspect of the present disclosure is to provide a printed circuit board capable of reducing power loss by reducing parasitic resistance of a power device.

[0006] Another aspect of the present disclosure is to provide a printed circuit board having improved heat dissipation characteristics by smoothly dissipating heat from a power device.

[0007] One of several solutions proposed in the present disclosure is that a semiconductor device, such as a power device, is disposed and embedded in a cavity of a substrate, and a metal block is connected to the semiconductor device.

[0008] According to one aspect of the present disclosure, a printed circuit board includes: a substrate having a cavity; a semiconductor device including a first metal pad and a second metal pad, and at least a portion of the semiconductor device is disposed in the cavity, wherein the first metal pad is disposed on a lower side of the semiconductor device and the second metal pad is disposed on an upper side of the semiconductor device; a metal block, at least a portion of the metal block is disposed in the cavity, the metal block is connected to the second metal pad; and a first insulating layer covering at least a portion of each of the substrate, the semiconductor device, and the metal block, and filling at least a portion of the cavity.

[0009] According to another aspect of the present disclosure, a printed circuit board includes: a substrate having a through cavity; a laminate, at least a portion of which is disposed in the through cavity, the laminate including a power device and a metal block, the power device having a first metal pad and a gate disposed on one side of the power device and a second metal pad disposed on the other side of the power device, the metal block being disposed on the power device and contacting the second metal pad; and an insulating layer covering at least a portion of each of the substrate and the laminate and filling at least a portion of the through cavity.

[0010] According to another aspect of the present disclosure, a printed circuit board includes: a substrate having a first cavity disposed in a first surface of the substrate and a second cavity disposed in a second surface of the substrate, the first cavity and the second cavity being at least partially overlapped in a thickness direction of the printed circuit board; a semiconductor device being at least partially disposed in the first cavity and having a first metal pad disposed on a first side of the semiconductor device and a second metal pad disposed on a second side of the semiconductor device; a metal block being at least partially disposed in the second cavity and directly contacting the second metal pad of the semiconductor device; and a first insulating layer being disposed on the first surface and the second surface of the substrate, at least partially covering each of the substrate, the semiconductor device and the metal block, and at least partially filling the first cavity and the second cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a schematic block diagram illustrating an example of an electronic device system; Figure 2 is a schematic perspective view showing an example of an electronic device; Figure 3 is a schematic cross-sectional view showing an example of a printed circuit board; FIG. 4A to FIG. 4E is shown for manufacturing Figure 3 A schematic cross-sectional view of an example of a process for producing a printed circuit board; Figure 5 is a schematic cross-sectional view showing a printed circuit board according to another example; 6A to 6H is shown for manufacturing Figure 5 A schematic cross-sectional view of an example of a process for producing a printed circuit board; Figure 7 is a schematic cross-sectional view showing a printed circuit board according to another example; FIG. 8A to FIG. 8H is shown for manufacturing Figure 7 A schematic cross-sectional view of an example of a process for producing a printed circuit board; Fig. 9 is a schematic cross-sectional view showing a printed circuit board according to another example; FIG. 10A to FIG. 10I is shown for manufacturing Fig. 9 A schematic cross-sectional view of an example of a process for producing a printed circuit board; Fig.11 is a schematic cross-sectional view showing a printed circuit board according to another example; and FIG. 12A to FIG. 12I is shown for manufacturing Fig.11 Schematic cross-sectional view of an example of a process for producing a printed circuit board. DETAILED DESCRIPTION

[0012] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer explanation, the shapes and sizes of elements in the drawings may be exaggerated or reduced.

[0013] Electronic Devices Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0014] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the mainboard 1010. These electronic components may be connected to other electronic components to be described below through various signal lines 1090.

[0015] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM) or flash memory); application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors or microcontrollers; and logic chips, such as analog-to-digital converters or application-specific integrated circuits (ASICs), etc. The chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips.

[0016] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols, and fifth generation mobile communication technology (5G) protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include components compatible with or operating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020.

[0017] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include chip component type passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the chip-related components 1020 and / or the network-related components 1030.

[0018] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. Examples of other electronic components may include a camera 1050, an antenna 1060, a display 1070, a battery 1080, and the like. The other electronic components are not limited thereto, but may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes, and the like.

[0019] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto but may be any other electronic device capable of processing data.

[0020] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0021] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is embedded. In addition, the electronic device need not be limited to the smart phone 1100, but may be any other electronic device as described above.

[0022] Printed Circuit Board Figure 3 is a schematic cross-sectional view showing an example of a printed circuit board.

[0023] Reference Figure 3, a printed circuit board 100A according to an example may include: a substrate 111 having a cavity H; a semiconductor device 150, at least a portion of which is disposed in the cavity H; a metal block 160, at least a portion of which is disposed in the cavity H, the metal block 160 being connected to the semiconductor device 150; and a first insulating layer 112 covering at least a portion of each of the substrate 111, the semiconductor device 150, and the metal block 160 and filling at least a portion of the cavity H. The semiconductor device 150 and the metal block 160 may be at least partially disposed in the cavity H penetrating a region between the upper surface and the lower surface of the substrate 111 in the form of a laminate, and buried in the first insulating layer 112. The first metal pad P1 and the second metal pad P2 may be disposed at the lower side (ie, the first side) and the upper side (ie, the second side) of the semiconductor device 150, respectively. The metal block 160 may be attached to or contact the second metal pad P2 of the semiconductor device 150. For example, the metal block 160 may be directly connected to the second metal pad P2 of the semiconductor device 150. Semiconductor device 150 may be a power device and may include, for example, at least one of a power metal-oxide semiconductor field effect transistor (MOSFET), a power insulated gate bipolar transistor (IGBT), and a junction field effect transistor (JFET). A gate G may be further provided at the lower side of semiconductor device 150. At this time, first metal pad P1 and second metal pad P2 may include a source pad and a drain pad, respectively.

[0024] In addition, a power device (e.g., a power MOSFET) may have a vertical structure in which a source pad and a gate are arranged on one side and a drain pad is arranged on the other side. At this time, even a small parasitic resistance in the path where a large current flows between the drain pad and the source pad may reduce efficiency and may generate a large amount of heat. Therefore, shortening the path can effectively improve the performance of the power MOSFET. In addition, when trying to embed the power MOSFET structure into the cavity of the substrate, it may be necessary to ensure that the thickness of the substrate is at a certain level or higher, because if the thickness of the substrate is too thin, problems may occur during the substrate manufacturing process. In this case, if the power MOSFET is only manufactured thinly, various problems such as insufficient filling and undulations may occur during the process of embedding the power MOSFET into the substrate. Therefore, it may be necessary to manufacture a power MOSFET with considerable thickness and embed the power MOSFET into the substrate, but in this case, the parasitic resistance may be increased, the power loss may be increased, and a large amount of heat may be generated.

[0025] In contrast, in the printed circuit board 100A according to the example, even if the substrate 111 is formed thick, the semiconductor device 150, for example, a power device such as a power MOSFET, which is processed thinly to reduce parasitic resistance, can be easily embedded. Specifically, in the example, the semiconductor device 150 can be disposed in the cavity H of the substrate 111, and the metal block 160 is attached to the semiconductor device 150. More specifically, the metal block 160 can be attached to the upper side of the semiconductor device 150, and at least a portion of the metal block 160 can be disposed in the cavity H together with the semiconductor device 150. In this case, even if the semiconductor device 150 is thin, the metal block 160 can be formed relatively thick to correspond to the thickness of the substrate 111. For example, the metal block 160 can be thicker than the semiconductor device 150. Therefore, in the case of embedding a power device such as a power MOSFET, the size of the system can be reduced, and power loss can also be reduced by reducing parasitic resistance, thereby improving system efficiency. In addition, heat can be smoothly dissipated from the power device, thereby improving heat dissipation characteristics. In addition, problems such as insufficient filling or undulation can be improved.

[0026] In addition, the semiconductor device 150 and the metal block 160 may be arranged in the cavity H of the substrate 111 in the form of a laminate. For example, the size of the semiconductor device 150 and the size of the metal block 160 may be similarly formed, and then the semiconductor device 150 and the metal block 160 may be joined to form a laminate. Alternatively, the laminate may be formed by joining a semiconductor wafer and a metal plate to each other, and then performing a cutting process. At this time, the metal block 160 may be directly connected to the second metal pad P2 of the semiconductor device 150. For example, each of the second metal pad P2 and the metal block 160 may include copper (Cu). For example, the second metal pad P2 may be a drain pad made of copper (Cu), and the metal block 160 may be a copper block (Cu block). Therefore, the second metal pad P2 and the metal block 160 may be directly connected to each other through a copper (Cu)-copper (Cu) junction. In this case, a separate adhesive may not be required, and the reliability of the junction may be better.

[0027] Reference Figure 3According to the example, the printed circuit board 100A may further include: a first wiring layer 121, which is disposed on the lower surface of the substrate 111 (i.e., the first surface of the substrate 111); a second wiring layer 122, which is disposed on the upper surface of the substrate 111 (i.e., the second surface of the substrate 111); a first via layer 131, which penetrates the substrate 111 and connects the first wiring layer 121 and the second wiring layer 122 to each other; a third wiring layer 123, which is disposed on the lower surface of the first insulating layer 112 (i.e., the first side of the first insulating layer 112); a second via layer 132, which penetrates at least a portion of the lower side of the first insulating layer 112 and connects the third wiring layer 123 to the first wiring layer 121, the first metal pad P1 and the gate G; a fourth wiring layer 124, which is disposed on the upper surface of the first insulating layer 112 (i.e., the first insulating layer 112); The second via layer 132 may include a first metal via connected to the first metal pad P1 and a second metal via connected to the gate G. The third via layer 133 may include a third metal via connected to the metal block 160. The second via layer 132 may include a first metal via connected to the first metal pad P1 and a second metal via connected to the gate G. The third via layer 133 may include a third metal via connected to the metal block 160.

[0028] For example, the printed circuit board 100A according to the example may have a multilayer wiring structure. At this time, the first metal pad P1 and the gate G of the semiconductor device 150 may be electrically connected to the wiring through the first metal via and the second metal via, respectively. In addition, the second metal pad P2 of the semiconductor device 150 may be electrically connected to the wiring through the third metal via and the metal block 160, thereby having an excellent heat dissipation effect. In addition, the third metal via may be deeper than the second metal via, but is not limited thereto.

[0029] Hereinafter, components of a printed circuit board 100A according to an example will be described in more detail with reference to the accompanying drawings.

[0030] The substrate 111 may be a core layer. For example, the substrate 111 may include an organic core layer or an inorganic core layer (e.g., a glass core layer, a metal core layer, a silicon core layer, or a ceramic core layer). The organic core layer may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material containing an inorganic filler, an organic filler and / or glass fiber (e.g., glass fabric with glass cloth as an example) and a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as a copper clad laminate (CCL), an Ajinomoto deposited film (ABF), or a prepreg (PPG), but is not limited thereto, and other polymer materials may be used. The glass core layer may include glass. The glass may include, for example, pure silicon dioxide (approximately 100% SiO 2 ), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, the glass core layer is not limited thereto, and optional glass materials (such as fluorine glass, phosphate glass, or chalcogenide glass, etc.) may also be used as materials for the glass layer. In addition, the glass core layer may further include other additives to form glass with specific physical properties. These additives may include magnesium, sodium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates (such as calcium carbonate (such as limestone) and sodium carbonate (such as soda)) and / or oxides of these and other elements. Glass may be distinguished from the aforementioned material containing glass fiber (such as glass fabric with glass cloth as an example). The metal core layer may include a metal. The metal may include, for example, copper (Cu), Invar, etc., but is not limited thereto. The silicon core layer may include pure silicon (Si). If necessary, the silicon core layer may include an oxide layer formed on the silicon (Si). In addition, the silicon core layer may also include a nitride layer formed on the oxide layer. The oxide layer may include a silicon oxide film, and the nitride layer may include a silicon nitride film, but the oxide layer and the nitride layer are not limited thereto. The ceramic core layer may include a ceramic material. The ceramic material may include, for example, aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (Si 3 N 4 ), etc., but not limited to.

[0031] The first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may include an organic insulating material. As described above, the organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including an inorganic filler, an organic filler, and / or glass fiber (for example, glass fabric using glass cloth as an example) and a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as a copper clad laminate (CCL), an Ajinomoto built-up film (ABF), or a prepreg (PPG), but is not limited thereto, and other polymer materials may be used. The first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may include the same organic insulating material or different organic insulating materials. If desired, each of the first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may include a plurality of layers.

[0032] Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 may include a metal material. That is, each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 may be a metal pattern layer. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. The first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 may perform various functions according to their respective designs. For example, the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 may include a signal pattern, a power pattern, a ground pattern, etc. These patterns may have various forms such as lines, planes, and pads, respectively. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 may include a seed layer and a plating layer formed on the seed layer. The seed layer may be an electroless plating layer (e.g., a chemical copper plating layer) and / or a sputtering layer, and the plating layer may be an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the seed layer and the plating layer are not limited thereto.

[0033] Each of the first via layer 131, the second via layer 132, the third via layer 133, the fourth via layer 134, and the fifth via layer 135 may include a metal material. Each of the first via layer 131, the second via layer 132, the third via layer 133, the fourth via layer 134, and the fifth via layer 135 may be a metal via. As described above, the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. The first via layer 131 may include a through metal via. The through metal via may be formed by providing a metal layer including the above-mentioned metal material on the inner wall of the through hole and filling the inside of the through hole with a filler. The filler may be an insulating ink containing an insulating resin (such as an epoxy resin), but is not limited thereto, and if necessary, the filler may include a conductive ink. Each of the second via layer 132, the third via layer 133, the fourth via layer 134, and the fifth via layer 135 may include a micro-metal via. Each of the micro-metal vias may include not only a filled via that fills the via hole, but also a conformal via disposed along the wall surface of the via hole. The second via layer 132 and the third via layer 133 may taper in opposite directions. The fourth via layer 134 and the fifth via layer 135 may taper in opposite directions. The second via layer 132 and the fourth via layer 134 may taper in the same direction. The third via layer 133 and the fifth via layer 135 may taper in the same direction. The first via layer 131, the second via layer 132, the third via layer 133, the fourth via layer 134, and the fifth via layer 135 may perform various functions according to their respective designs. For example, the first via layer 131, the second via layer 132, the third via layer 133, the fourth via layer 134, and the fifth via layer 135 may include a ground via, a power via, a signal via, etc. Each of the first via layer 131, the second via layer 132, the third via layer 133, the fourth via layer 134, and the fifth via layer 135 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Each of the first via layer 131, the second via layer 132, the third via layer 133, the fourth via layer 134, and the fifth via layer 135 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), or may include both an electroless plating layer (e.g., a chemical copper plating layer) and a sputtering layer.

[0034] The semiconductor device 150 may be an integrated circuit (IC) die in which hundreds to millions of devices are integrated into one chip. The IC die may be formed based on an effective wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the base material of the body of the IC die. Various circuits may be formed on the body. The first metal pad P1 and the second metal pad P2 and the gate G may be formed on the body to connect to external circuits such as signal circuits, power circuits, and ground circuits. Each of the first metal pad P1 and the second metal pad P2 may include a conductive material such as aluminum (Al) or copper (Cu). The first metal pad P1 and the second metal pad P2 may be pads for connecting the source and the drain, respectively. For example, the semiconductor device 150 may preferably be a power device, and more preferably a power MOSFET, but is not limited thereto.

[0035] The metal block 160 may include a metal material. As described above, the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal material may include copper (Cu), for example, the metal block 160 may be a copper block, but is not limited thereto. In the cross-sectional view, the metal block 160 may be a block having a polygonal (e.g., square) shape, but is not limited thereto.

[0036] FIG. 4A to FIG. 4E is shown for manufacturing Figure 3 Schematic cross-sectional view of an example of a process for producing a printed circuit board.

[0037] Reference Figure 4A , a substrate 111 may be prepared, and a first wiring layer 121 and a second wiring layer 122 may be formed on the substrate 111, and a first via layer 131 may be formed in the substrate 111. The substrate 111 may have various types of materials as described above, and the type of material may be selected as needed. A through-hole for forming the first via layer 131 may be formed by any of various processes such as a laser drilling process, a mechanical drilling process, a chemical etching process, and a sandblasting process according to the material of the substrate 111. The first wiring layer 121 and the second wiring layer 122 may be formed by a plating process. The first via layer 131 may be formed by a plating process, and if necessary, the first via layer 131 may be formed by a plugging process.

[0038] Reference Figure 4B , a cavity H may be formed in the substrate 111. The cavity H may be a through cavity penetrating a region between an upper surface and a lower surface of the substrate 111. The cavity H may be formed by any of various processes such as a laser drilling process, a mechanical drilling process, a chemical etching process, and a sandblasting process according to the material of the substrate 111.

[0039] Reference Figure 4C After forming a laminate by stacking the metal block 160 on the semiconductor device 150, the laminate may be disposed in the cavity H. To dispose the laminate, an adhesive such as a die attach film (DAF) may be used. For example, the laminate may be disposed in the cavity H by attaching the adhesive to the lower surface of the substrate 111 and then attaching the laminate to a portion of the adhesive exposed through the cavity H.

[0040] Reference Figure 4D , the first insulating layer 112 may be provided to bury the substrate 111 and the laminate. For example, the upper portion of the laminate and the upper portion of the substrate 111 may be covered by stacking a first layer of the first insulating layer 112 on the above-mentioned adhesive, and thereafter, the lower portion of the laminate and the lower portion of the substrate 111 may be covered by removing the adhesive and then stacking a second layer of the first insulating layer 112 on the area where the adhesive is removed.

[0041] Reference Figure 4E , a third wiring layer 123 and a fourth wiring layer 124 may be formed on the first insulating layer 112, and a second via layer 132 and a third via layer 133 may be formed in the first insulating layer 112. Via holes for forming the second via layer 132 and the third via layer 133 may be formed by a laser drilling process, a mechanical drilling process, or the like. The third wiring layer 123 and the fourth wiring layer 124 and the second via layer 132 and the third via layer 133 may be formed by a plating process. In addition, if necessary, a deposition process may be performed to form the second insulating layer 113 and the third insulating layer 114, the fifth wiring layer 125 and the sixth wiring layer 126, and the fourth via layer 134 and the fifth via layer 135.

[0042] The printed circuit board 100A according to the above-described example may be manufactured through a series of processes, and other redundant descriptions will be omitted.

[0043] Figure 5 is a schematic cross-sectional view showing a printed circuit board according to another example.

[0044] Reference Figure 5, when compared with the printed circuit board 100A according to the example described above, in a printed circuit board 100B according to another example, the cavity H may include: a first cavity H1 that penetrates at least a portion of the substrate 111 from the lower surface of the substrate 111 in the thickness direction; and a second cavity H2 that penetrates at least another portion of the substrate 111 from the upper surface of the substrate 111 in the thickness direction. That is, the first cavity H1 may be disposed in the lower surface of the substrate 111, and the second cavity H2 may be disposed in the upper surface of the substrate 111. The first cavity H1 and the second cavity H2 may at least partially overlap in the thickness direction. At least a portion of the first cavity H1 and at least a portion of the second cavity H2 may be connected to each other in the thickness direction to form at least one through hole penetrating the substrate 111. At least a portion of the semiconductor device 150 may be disposed in the first cavity H1. At least a portion of the metal block 160 may be disposed in the second cavity H2. If necessary, in a cross-sectional view, the first cavity H1 and the second cavity H2 may have different widths W1 and W2. Here, the width may refer to the size of an element (e.g., the first cavity H1, the second cavity H2) in the horizontal direction. For example, in the cross-sectional view, the width W2 of the second cavity H2 may be greater than the width W1 of the first cavity H1. Accordingly, in the cross-sectional view, the semiconductor device 150 and the metal block 160 may also have different widths W3 and W4. For example, in the cross-sectional view, the width W4 of the metal block 160 may be greater than the width W3 of the semiconductor device 150. The metal block 160 may be directly connected to the second metal pad P2 of the semiconductor device 150, but is not limited thereto. If necessary, an adhesive such as DAF may be provided between the semiconductor device 150 and the metal block 160. In this way, after the first cavity H1 and the second cavity H2 are separately formed, the semiconductor device 150 and the metal block 160 may be separately provided and then connected to each other. In this case, all of the above effects may also be achieved. Other redundant descriptions will be omitted. In the present disclosure, the thickness direction may refer to the thickness direction of the printed circuit board 100A, 100B, 100C, 100D, or 100E, that is, the direction along which the insulating layers in the printed circuit board 100A, 100B, 100C, 100D, or 100E are stacked. The horizontal direction may be perpendicular to the thickness direction of the printed circuit board 100A, 100B, 100C, 100D, or 100E.

[0045] 6A to 6H is shown for manufacturing Figure 5 Schematic cross-sectional view of an example of a process for producing a printed circuit board.

[0046] Reference Fig. 6A, a substrate 111 may be prepared, and a first wiring layer 121 and a second wiring layer 122 may be formed on the substrate 111, and a first via layer 131 may be formed in the substrate 111. The substrate 111 may have various types of materials as described above, and the type of material may be selected as needed. A through-hole for forming the first via layer 131 may be formed by any of various processes such as a laser drilling process, a mechanical drilling process, a chemical etching process, and a sandblasting process according to the material of the substrate 111. The first wiring layer 121 and the second wiring layer 122 may be formed by a plating process. The first via layer 131 may be formed by a plating process, and if necessary, the first via layer 131 may be formed by a plugging process.

[0047] Reference Figure 6B , a second cavity H2 may be formed in the substrate 111. The second cavity H2 may be a blind cavity penetrating a portion of the substrate 111 from the upper surface of the substrate 111. The second cavity H2 may be formed by any of various processes such as a laser drilling process, a mechanical drilling process, a chemical etching process, and a sandblasting process according to the material of the substrate 111.

[0048] Reference Figure 6C , a metal block 160 may be disposed in the second cavity H2. For example, the metal block 160 may be attached to the bottom surface of the second cavity H2 using an adhesive 165 such as DAF.

[0049] Reference Fig.6D , the first layer of the first insulating layer 112 may be provided to bury the substrate 111 and the metal block 160. For example, the substrate 111 and the metal block 160 may be covered by stacking the first layer of the first insulating layer 112 on the substrate 111.

[0050] Reference Fig. 6E , a first cavity H1 may be formed in the substrate 111. The first cavity H1 may be a blind cavity penetrating another portion of the substrate 111 from the lower surface of the substrate 111 in the thickness direction. The adhesive 165 may be removed if necessary. The first cavity H1 may be connected to the second cavity H2. The first cavity H1 may be formed by any of various processes such as a laser drilling process, a mechanical drilling process, a chemical etching process, and a sandblasting process according to the material of the substrate 111.

[0051] Reference Fig. 6F , the semiconductor device 150 may be disposed in the first cavity H1. For example, the semiconductor device 150 may be disposed in the first cavity H1 in such a manner that the second metal pad P2 of the semiconductor device 150 is connected to the metal block 160.

[0052] Reference Figure 6G, the second layer of the first insulating layer 112 may be provided to bury the substrate 111 and the semiconductor device 150. For example, the substrate 111 and the semiconductor device 150 may be covered by stacking the second layer of the first insulating layer 112 on the substrate 111.

[0053] Reference Figure 6H , a third wiring layer 123 and a fourth wiring layer 124 may be formed on the first insulating layer 112, and a second via layer 132 and a third via layer 133 may be formed in the first insulating layer 112. Via holes for forming the second via layer 132 and the third via layer 133 may be formed by a laser drilling process, a mechanical drilling process, or the like. The third wiring layer 123 and the fourth wiring layer 124 and the second via layer 132 and the third via layer 133 may be formed by a plating process. In addition, if necessary, a deposition process may be performed to form the second insulating layer 113 and the third insulating layer 114, the fifth wiring layer 125 and the sixth wiring layer 126, and the fourth via layer 134 and the fifth via layer 135.

[0054] The printed circuit board 100B according to another example described above may be manufactured through a series of processes, and other redundant descriptions will be omitted.

[0055] Figure 7 is a schematic cross-sectional view showing a printed circuit board according to another example.

[0056] Reference Figure 7 , when compared with the printed circuit board 100B according to another example described above, in the printed circuit board 100C according to another example, in the cross-sectional view, the width W1 of the first cavity H1 may be greater than the width W2 of the second cavity H2. Accordingly, in the cross-sectional view, the width W3 of the semiconductor device 150 may be greater than the width W4 of the metal block 160. For example, the size of the first cavity H1 and the size of the second cavity H2 may be changed according to the size of the semiconductor device 150 and the size of the metal block 160. In this case, all the above effects can also be achieved. Other redundant descriptions will be omitted.

[0057] FIG. 8A to FIG. 8H is shown for manufacturing Figure 7 Schematic cross-sectional view of an example of a process for producing a printed circuit board.

[0058] Reference FIG. 8A to FIG. 8H , except that the size of the first cavity H1 and the size of the second cavity H2 and the size of the semiconductor device 150 disposed in the first cavity H1 and the size of the metal block 160 disposed in the second cavity H2 are different, the above reference 6A to 6H A printed circuit board 100C according to another example is manufactured by substantially the same process.

[0059] The printed circuit board 100C according to another example described above may be manufactured through a series of processes, and other redundant descriptions will be omitted.

[0060] Fig. 9 is a schematic cross-sectional view showing a printed circuit board according to another example.

[0061] Reference Fig. 9 , when compared with the printed circuit board 100A according to the above-described example, in a printed circuit board 100D according to another example, the cavity H may include: a first cavity H1 penetrating at least a portion of the substrate 111 in the thickness direction from the lower surface of the substrate 111; and a second cavity H2 penetrating at least another portion of the substrate 111 in the thickness direction from the upper surface of the substrate 111. The substrate 111 may include a portion disposed between the first cavity H1 and the second cavity H2, thereby separating the first cavity H1 and the second cavity H2 from each other. The metal block 160 may include: a first metal block 161, at least a portion of which is disposed in the first cavity H1, the first metal block 161 being connected to the second metal pad P2; a second metal block 162, at least a portion of which is disposed in the second cavity H2, the second metal block 162 being attached to a portion of the substrate 111 disposed between the first cavity H1 and the second cavity H2 through an adhesive 165; and a metal via 163 penetrating the adhesive 165 and a portion of the substrate 111 disposed between the first cavity H1 and the second cavity H2 and connecting the first metal block 161 and the second metal block 162 to each other. The first metal block 161 and the second metal pad P2 may be directly connected to each other through a copper (Cu)-copper (Cu) junction, and may also be connected to each other through a solder junction if necessary. Here, the second metal block 162 may also be directly attached to a portion of the substrate 111 disposed between the first cavity H1 and the second cavity H2. If necessary, the first cavity H1 and the second cavity H2 may have different widths in a cross-sectional view. For example, in the cross-sectional view, the width W2 of the second cavity H2 may be greater than the width W1 of the first cavity H1. Accordingly, the semiconductor device 150 and the metal block 160 (e.g., the second metal block 162) may also have different widths W3 and W4 in the cross-sectional view. For example, in the cross-sectional view, the width W4 of the metal block 160 (e.g., the second metal block 162) may be greater than the width W3 of the semiconductor device 150. In this way, after the first cavity H1 and the second cavity H2 are separately formed, the semiconductor device 150 and the metal block 160 may be separately provided and then connected to each other using metal vias. In this case, all the above effects can also be achieved. Other redundant descriptions will be omitted.

[0062] FIG. 10A to FIG. 10I is shown for manufacturing Fig. 9 Schematic cross-sectional view of an example of a process for producing a printed circuit board.

[0063] Reference Fig. 10A , a substrate 111 may be prepared, and a first wiring layer 121 and a second wiring layer 122 may be formed on the substrate 111, and a first via layer 131 may be formed in the substrate 111. The substrate 111 may have various types of materials as described above, and the type of material may be selected as needed. A through-hole for forming the first via layer 131 may be formed by any of various processes such as a laser drilling process, a mechanical drilling process, a chemical etching process, and a sandblasting process according to the material of the substrate 111. The first wiring layer 121 and the second wiring layer 122 may be formed by a plating process. The first via layer 131 may be formed by a plating process, and if necessary, the first via layer 131 may be formed by a plugging process.

[0064] Reference Fig. 10B , a second cavity H2 may be formed in the substrate 111. The second cavity H2 may be a blind cavity penetrating a portion of the substrate 111 from the upper surface of the substrate 111 in the thickness direction. The second cavity H2 may be formed by any of various processes such as a laser drilling process, a mechanical drilling process, a chemical etching process, and a sandblasting process according to the material of the substrate 111.

[0065] Reference Fig. 10C , a second metal block 162 may be disposed in the second cavity H2. For example, the second metal block 162 may be attached to the bottom surface of the second cavity H2 using an adhesive 165 such as DAF.

[0066] Reference Fig. 10D , the first layer of the first insulating layer 112 may be provided to bury the substrate 111 and the second metal block 162. For example, the substrate 111 and the second metal block 162 may be covered by stacking the first layer of the first insulating layer 112 on the substrate 111.

[0067] Reference Fig.10E , a first cavity H1 may be formed in the substrate 111. The first cavity H1 may be a blind cavity penetrating another portion of the substrate 111 from the lower surface of the substrate 111 in the thickness direction. The first cavity H1 and the second cavity H2 may be separated from each other by the substrate 111. The first cavity H1 may be formed by any of various processes such as a laser drilling process, a mechanical drilling process, a chemical etching process, and a sandblasting process according to the material of the substrate 111.

[0068] Reference Fig.10F, a first metal block 161 may be disposed in the first cavity H1, and a metal via 163 may be formed in a portion of the substrate 111 disposed between the first cavity H1 and the second cavity H2 to connect the first metal block 161 and the second metal block 162. The metal via 163 may penetrate the substrate 111 and the adhesive 165 at the same time. A via hole for forming the metal via 163 may be formed by any of various processes such as a laser drilling process and a mechanical drilling process. The first metal block 161 and the metal via 163 may be formed by a plating process. For example, each of the first metal block 161 and the metal via 163 may include a seed metal layer and a plated metal layer formed on the seed metal layer.

[0069] Reference Figure 10G , the semiconductor device 150 may be disposed in the first cavity H1. For example, the semiconductor device 150 may be disposed in the first cavity H1 in such a manner that the second metal pad P2 of the semiconductor device 150 is connected to the first metal block 161.

[0070] Reference Fig. 10H , a second layer of the first insulating layer 112 may be provided to bury the substrate 111, the first metal block 161, and the semiconductor device 150. For example, the substrate 111, the first metal block 161, and the semiconductor device 150 may be covered by stacking the second layer of the first insulating layer 112 on the substrate 111.

[0071] Reference Fig.10I , a third wiring layer 123 and a fourth wiring layer 124 may be formed on the first insulating layer 112, and a second via layer 132 and a third via layer 133 may be formed in the first insulating layer 112. Via holes for forming the second via layer 132 and the third via layer 133 may be formed by a laser drilling process, a mechanical drilling process, or the like. The third wiring layer 123 and the fourth wiring layer 124 and the second via layer 132 and the third via layer 133 may be formed by a plating process. In addition, if necessary, a deposition process may be performed to form the second insulating layer 113 and the third insulating layer 114, the fifth wiring layer 125 and the sixth wiring layer 126, and the fourth via layer 134 and the fifth via layer 135.

[0072] The printed circuit board 100D according to another example described above may be manufactured through a series of processes, and other redundant descriptions will be omitted.

[0073] Fig.11 is a schematic cross-sectional view showing a printed circuit board according to another example.

[0074] Reference Fig.11, when compared with the printed circuit board 100D according to another example described above, in the printed circuit board 100E according to another example, in the cross-sectional view, the width W1 of the first cavity H1 may be greater than the width W2 of the second cavity H2. Accordingly, in the cross-sectional view, the width W3 of the semiconductor device 150 may be greater than the width W4 of the metal block 160 (e.g., the second metal block 162). For example, the size of the first cavity H1 and the size of the second cavity H2 may be changed according to the size of the semiconductor device 150 and the size of the metal block 160. In this case, all the above-mentioned effects can also be achieved. Other redundant descriptions will be omitted.

[0075] FIG. 12A to FIG. 12I is shown for manufacturing Fig.11 Schematic cross-sectional view of an example of a process for producing a printed circuit board.

[0076] Reference FIG. 12A to FIG. 12I , except that the size of the first cavity H1 and the size of the second cavity H2, the size of the semiconductor device 150 disposed in the first cavity H1, the size of the first metal block 161, and the size of the second metal block 162 disposed in the second cavity H2 are different, the above reference FIG. 10A to FIG. 10I A printed circuit board 100E according to another example is manufactured by substantially the same process.

[0077] The printed circuit board 100E according to another example described above may be manufactured through a series of processes, and other redundant descriptions will be omitted.

[0078] As described above, as one of several effects of the present disclosure, a printed circuit board in which a semiconductor device such as a power device is embedded can be provided.

[0079] As another one of several effects of the present disclosure, a printed circuit board capable of reducing power loss by reducing parasitic resistance of a power device may be provided.

[0080] As another one of several effects of the present disclosure, a printed circuit board having improved heat dissipation characteristics by smoothly dissipating heat from a power device may be provided.

[0081] In the present disclosure, the expression "covering" may refer not only to "completely covering" but also to "at least partially covering", and may refer not only to "directly covering" but also to "indirectly covering". Furthermore, the expression "filling" may refer not only to "completely filling" but also to "at least partially filling", and may also refer to "substantially filling". For example, the expression "filling" may be interpreted to include the case where there are some holes or gaps therein. Furthermore, the expression "surrounding" may refer not only to "completely surrounding" but also to "partially surrounding", and may also refer to "substantially surrounding".

[0082] In the present disclosure, an object "set in a cavity" may refer not only to a case where the object is completely set in the cavity, but also to a case where the object partially protrudes upward or partially downward in a cross-sectional view. For example, in a cross-sectional view, if the object is set in the cavity, this may be interpreted in a broader sense as described above.

[0083] In the present disclosure, the term “substantially” may be a concept including a process error, a position deviation, a measurement error, etc., which occur in a manufacturing process.

[0084] In the present disclosure, the same insulating material may refer not only to the completely same material, but also to the same type of insulating material. Therefore, the insulating materials may be slightly different in their specific composition ratios, but have basically the same composition.

[0085] In the present disclosure, a cross-sectional view may indicate a view of the cross-sectional shape of an object when the object is cut vertically, or a view showing the cross-sectional shape of an object when the object is observed from a side view. In addition, a plan view may indicate a view of the plane shape of an object when the object is cut horizontally, or a view showing the plane shape of an object when the object is observed from a top view or from a bottom view.

[0086] In the present disclosure, for the sake of convenience, "lower" in "lower side", "lower part", "lower surface", etc. is used to refer to the downward direction based on the cross section of the drawings, and "upper" in "upper side", "upper part", "upper surface", etc. is used to refer to the direction opposite to the above-mentioned downward direction. However, these directions are defined for the convenience of explanation, and the scope of the claims is not particularly limited by the definition of the directions. The concepts of "upper" and "lower" can be changed at any time.

[0087] In the present disclosure, "connection" is a concept including not only "direct connection" but also "indirect connection through an adhesive layer or the like". In addition, "electrical connection" is a concept including both "physical connection" and "non-physical connection". In addition, expressions such as "first", "second", etc. are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the claims.

[0088] The expression "example" used in this disclosure does not refer to the same example, but is used to emphasize and explain different unique features. However, the examples presented above can be implemented in combination with features of other examples. For example, even if a matter explained in a specific example is not explained in another example, the matter explained in the specific example can also be understood to be related to the other example, as long as there is no opposite or contradictory explanation to the matter in the other example.

[0089] In the present disclosure, each of the thickness, width, length, depth, etc. can be measured using a scanning electron microscope or an optical microscope based on a cross section obtained by polishing or cutting a printed circuit board. The cut section can be a vertical section or a horizontal section, and each value can be measured based on the desired cut section. If the value is not constant, the value can be determined as the average of the values ​​measured at five random points. When the substrate is cut in the thickness direction along the central axis of the via, the width of the upper and / or lower ends of the via can be measured in the cross-sectional view. The depth of the via can be measured as the distance from the upper end to the lower end of each object in the cross-sectional view when the substrate is cut in the thickness direction along the central axis of each object.

[0090] The average thickness, average diameter, average depth, etc. can be calculated as the average of the values ​​measured at five random points. In the case where each opening has a tapered shape, the diameter of each opening can be calculated as the average of the diameters measured on the uppermost and lowermost sides of each opening.

[0091] The terms used in the present disclosure are only for describing examples and are not intended to limit the present disclosure.At this time, unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0092] While exemplary embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a substrate having a cavity; a semiconductor device comprising a first metal pad and a second metal pad and at least partially disposed in the cavity, wherein the first metal pad is disposed at a lower side of the semiconductor device and the second metal pad is disposed at an upper side of the semiconductor device; a metal block at least partially disposed in the cavity, the metal block being connected to the second metal pad; and A first insulating layer covers at least a portion of each of the substrate, the semiconductor device, and the metal block, and fills at least a portion of the cavity.

2. The printed circuit board according to claim 1, wherein: The semiconductor device includes at least one of a power metal-oxide semiconductor field effect transistor, a power insulated gate bipolar transistor and a junction field effect transistor, The first metal pad comprises a source pad, The second metal pad includes a drain pad, and A gate is further disposed on the lower side of the semiconductor device.

3. The printed circuit board according to claim 1, wherein: The metal block is directly connected to the second metal pad.

4. The printed circuit board according to claim 3, wherein: Each of the second metal pad and the metal block includes copper, and the second metal pad and the metal block are directly connected to each other through a copper-copper junction.

5. The printed circuit board according to claim 1, wherein The cavity penetrates the area between the upper surface and the lower surface of the substrate along the thickness direction of the printed circuit board, and The metal block is attached to the upper side of the semiconductor device, and at least a portion of the metal block is disposed in the cavity together with the semiconductor device.

6. The printed circuit board according to claim 1, wherein The cavity comprises: a first cavity penetrating at least a portion of the substrate from a lower surface of the substrate in a thickness direction of the printed circuit board; and a second cavity penetrating at least another portion of the substrate from an upper surface of the substrate in the thickness direction. At least a portion of the semiconductor device is disposed in the first cavity, and At least a portion of the metal block is disposed in the second cavity.

7. The printed circuit board according to claim 6, wherein: In a cross-sectional view of the printed circuit board, the first cavity and the second cavity have different widths, and In the cross-sectional view, the semiconductor device and the metal block have different widths.

8. The printed circuit board according to claim 6, wherein: The first cavity and the second cavity are connected to each other in the thickness direction.

9. The printed circuit board according to claim 6, wherein: The substrate includes a portion disposed between the first cavity and the second cavity to separate the first cavity and the second cavity from each other.

10. The printed circuit board according to claim 9, wherein: The metal block includes: a first metal block at least partially disposed in the first cavity, the first metal block being connected to the second metal pad; a second metal block at least partially disposed in the second cavity, the second metal block being attached to the portion of the substrate disposed between the first cavity and the second cavity; and a metal via penetrating the portion of the substrate disposed between the first cavity and the second cavity and connecting the first metal block and the second metal block to each other.

11. The printed circuit board according to claim 1, further comprising: A first wiring layer is disposed on the lower surface of the substrate; A second wiring layer is disposed on the upper surface of the substrate; as well as The first via layer penetrates the substrate and connects the first wiring layer and the second wiring layer to each other.

12. The printed circuit board according to claim 11, further comprising: A third wiring layer is arranged on the lower surface of the first insulating layer; a second via layer penetrating at least a portion of a lower side of the first insulating layer and connecting the third wiring layer to each of the first wiring layer and the first metal pad; A fourth wiring layer is arranged on the upper surface of the first insulating layer; as well as A third via layer penetrates at least a portion of an upper side of the first insulating layer and connects the fourth wiring layer to each of the second wiring layer and the second metal pad.

13. The printed circuit board according to claim 1, wherein: The substrate includes an organic core layer or an inorganic core layer, and the inorganic core layer includes a glass core layer, a metal core layer, a silicon core layer or a ceramic core layer.

14. A printed circuit board, comprising: a substrate having a through cavity; a laminated body at least partially disposed in the through cavity, the laminated body comprising: a power device having a first metal pad and a gate disposed on a first side of the power device and a second metal pad disposed on a second side of the power device; and a metal block disposed on the power device and contacting the second metal pad; and An insulating layer covers at least a portion of each of the substrate and the laminate and fills at least a portion of the through cavity.

15. The printed circuit board according to claim 14, further comprising: A first metal pattern layer and a second metal pattern layer are respectively disposed on a first side and a second side of the insulating layer; a first metal via penetrating at least a portion of the first side of the insulating layer and connecting at least a portion of the first metal pattern layer to the first metal pad; a second metal via penetrating at least another portion of the first side of the insulating layer and connecting at least another portion of the first metal pattern layer to the gate; as well as A third metal via penetrates at least a portion of the second side of the insulating layer and connects at least a portion of the second metal pattern layer to the metal block.

16. The printed circuit board according to claim 14, wherein: In a cross-sectional view of the printed circuit board, the metal block is thicker than the power device.

17. A printed circuit board comprising: a substrate having a first cavity disposed in a first surface of the substrate and a second cavity disposed in a second surface of the substrate, the first cavity and the second cavity at least partially overlapping in a thickness direction of the printed circuit board; a semiconductor device at least partially disposed in the first cavity and having a first metal pad disposed on a first side of the semiconductor device and a second metal pad disposed on a second side of the semiconductor device; a metal block at least partially disposed in the second cavity and directly contacting the second metal pad of the semiconductor device; as well as A first insulating layer is disposed on the first surface and the second surface of the substrate, at least partially covers each of the substrate, the semiconductor device, and the metal block, and at least partially fills the first cavity and the second cavity.

18. The printed circuit board according to claim 17, wherein: In a cross-sectional view of the printed circuit board, at least a portion of the first cavity and at least a portion of the second cavity are connected to form at least one through hole penetrating the substrate.

19. The printed circuit board according to claim 17, wherein: In a cross-sectional view of the printed circuit board, the first cavity and the second cavity have different widths, and In the cross-sectional view, the semiconductor device and the metal block have different widths.

20. The printed circuit board according to any one of claims 17 to 19, further comprising: A first wiring layer is disposed on the first surface of the substrate; A second wiring layer is disposed on the second surface of the substrate; as well as The first via layer penetrates the substrate and connects the first wiring layer and the second wiring layer to each other.

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