CMOS device and preparation method thereof
By avoiding the formation of a barrier layer and a P-type work function layer in the NMOS region of the CMOS device, the problem of increasing the threshold voltage at low temperatures is solved, and the device can work normally at low temperatures is achieved, and the leakage current is reduced.
Patent Information
- Application Number
- CN202311333741.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-16
- Publication Date
- 2025-04-22
AI Technical Summary
At low temperature, CMOS devices have an increase in on-resistance and an increase in threshold voltage, which makes it difficult for them to work normally.
Avoid forming a barrier layer and a P-type work function layer in the NMOS region of the CMOS device. This method reduces the threshold voltage of the NMOS region so that the CMOS device can operate normally at low temperatures.
The threshold voltage in the NMOS region is reduced to ensure that the CMOS device can operate normally at low temperatures, and due to the low leakage current, the normal operation of the device can be ensured even if there is no barrier layer and P-type work function layer between the metal gate and the high K dielectric layer.
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Figure CN119866054A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a CMOS device and a preparation method thereof. Background Art
[0002] Complementary Metal Oxide Semiconductor (CMOS) transistors are one of the most important components in integrated circuits. CMOS devices at low temperatures can exhibit superior performance, such as low leakage current and low power consumption.
[0003] However, CMOS devices will experience carrier freeze-out effect at low temperatures. The so-called carrier freeze-out effect means that at room temperature, impurities are completely ionized to form carriers, and donor or acceptor impurity atoms ionize electrons or holes. However, at low temperatures, electrons or hole impurity atoms cannot ionize electrons or holes, and cannot form carriers. The mobility of carriers slows down, resulting in an increase in the on-resistance of the CMOS device and an increase in the threshold voltage of the CMOS device.
[0004] Due to the relatively large threshold voltage, CMOS devices designed to operate at room temperature will have difficulty operating at low temperatures. Summary of the invention
[0005] The object of the present invention is to provide a CMOS device and a method for manufacturing the same, so as to reduce the threshold voltage of the NMOS region of the CMOS device.
[0006] To solve the above technical problems, the present invention provides a CMOS device and a preparation method thereof, wherein the CMOS device comprises: a semiconductor substrate, the semiconductor substrate comprises an NMOS region and a PMOS region, a dielectric layer is formed on the surface of the semiconductor substrate, a first gate trench is formed in the dielectric layer on the NMOS region, and a second gate trench is formed in the dielectric layer on the PMOS region, the first gate trench and the second gate trench expose part of the surface of the semiconductor substrate; a barrier layer, the barrier layer covers the bottom of the second gate trench; a P-type work function layer, the P-type work function layer covers the surface of the barrier layer and extends along the sidewall of the second gate trench to the surface of the dielectric layer covering the PMOS region; an N-type work function layer, the N-type work function layer covers the bottom of the first gate trench and extends along the sidewall of the first gate trench to the surface of the dielectric layer covering the NMOS region and the surface of the P-type work function layer; and a metal gate, the metal gate fills the first gate trench and the second gate trench.
[0007] Preferably, in the CMOS device, the material of the barrier layer includes titanium nitride.
[0008] Preferably, in the CMOS device, the material of the P-type work function layer includes tantalum nitride.
[0009] The present invention also provides a method for preparing a CMOS device, comprising: providing a semiconductor substrate, the semiconductor substrate comprising an NMOS region and a PMOS region, a dielectric layer being formed on the surface of the semiconductor substrate, a first gate trench being formed in the dielectric layer on the NMOS region, and a second gate trench being formed in the dielectric layer on the PMOS region, the first gate trench and the second gate trench exposing a portion of the surface of the semiconductor substrate; forming a barrier layer and a P-type work function layer, the barrier layer covering the bottom of the second gate trench, the P-type work function layer covering the surface of the barrier layer and extending along the bottom of the second gate trench to the surface of the dielectric layer covering the PMOS region; forming an N-type work function layer, the N-type work function layer covering the bottom of the first gate trench and extending along the bottom of the first gate trench to the surface of the dielectric layer covering the NMOS region and the surface of the P-type work function layer; and forming a metal gate, the metal gate filling the first gate trench and the second gate trench.
[0010] Preferably, in the preparation method of the CMOS device, the method of forming the barrier layer and the P-type work function layer includes: forming the barrier layer, the barrier layer covering the bottom of the first gate trench and the bottom of the second gate trench; forming the P-type work function layer, the P-type work function layer covering the barrier layer and extending to cover the surface of the dielectric layer; forming a protective layer, the protective layer covering the surface of the P-type work function layer located in the PMOS region; and removing the barrier layer located at the bottom of the first gate trench and removing the barrier layer located in the NMOS region and the P-type work function layer on the surface of the dielectric layer.
[0011] Preferably, in the method for preparing the CMOS device, before forming the N-type work function layer, the method further comprises: removing the protective layer on the surface of the P-type work function layer in the PMOS region.
[0012] Preferably, in the method for preparing the CMOS device, a dry etching process is used to remove the barrier layer and the P-type work function layer.
[0013] Preferably, in the method for preparing the CMOS device, the dry etching process uses tungsten chloride gas, and the process temperature is 300 degrees Celsius to 400 degrees Celsius.
[0014] Preferably, the method for preparing the CMOS device further includes: forming a high-K dielectric layer, wherein the high-K dielectric layer is formed between the bottom of the first gate trench and the barrier layer, and between the bottom of the second gate trench and the barrier layer.
[0015] Preferably, in the method for preparing the CMOS device, the method for forming the metal gate includes: forming a metal gate material, the metal gate material filling the first gate trench and the second gate trench, and extending to cover the top surface of the N-type work function layer; and performing a chemical mechanical polishing process on the metal gate material to remove the P-type work function layer and the N-type work function layer located on the surface of the dielectric layer, and stopping at the surface of the dielectric layer.
[0016] In summary, the present invention provides a CMOS device and a method for preparing the same. Compared with the prior art, the present invention can reduce the threshold voltage of the NMOS region by avoiding forming a barrier layer and a P-type work function layer on the NMOS region, thereby enabling the CMOS device to work normally at low temperatures. Moreover, since the CMOS device has a lower leakage current at low temperatures, even if there is no barrier layer and a P-type work function layer between a metal gate subsequently formed in the NMOS region and a high-K dielectric layer, metal diffusion in the metal gate may cause leakage current, and the normal operation of the CMOS device can be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is a flow chart of a method for preparing a low-temperature CMOS device according to an embodiment of the present invention;
[0018] Figure 2 A schematic diagram of a device structure corresponding to step 1 of preparing a low-temperature CMOS device according to an embodiment of the present invention;
[0019] Figure 3 to Figure 9 A schematic diagram of a device structure corresponding to step 2 of preparing a low-temperature CMOS device according to an embodiment of the present invention;
[0020] Fig.10 A schematic diagram of a device structure corresponding to step 3 of preparing a low-temperature CMOS device according to an embodiment of the present invention;
[0021] Figure 11-12 A schematic diagram of a device structure corresponding to step 4 of preparing a low-temperature CMOS device according to an embodiment of the present invention;
[0022] The reference numerals are as follows:
[0023] 10- semiconductor substrate;
[0024] 11-NMOS region;
[0025] 12-PMOS region;
[0026] 110 a first gate trench;
[0027] 120- a second gate trench;
[0028] 111-N type work function layer;
[0029] 121-P type work function layer;
[0030] 13- dielectric layer;
[0031] 20- barrier layer;
[0032] 30-protective layer;
[0033] 40-photoresist layer;
[0034] 50-metal gate;
[0035] 51-Metal gate material. DETAILED DESCRIPTION
[0036] As described in the background technology, the threshold voltage is one of the important parameters of CMOS devices. Generally, in order to adjust the threshold voltage of CMOS devices, a work function layer is formed on the surface of the high-K gate dielectric layer. In the process of forming PMOS devices and NMOS devices, the work function layer can adjust the respective work function adjustment requirements of PMOS devices and NMOS devices.
[0037] CMOS devices working at low temperatures can exhibit superior performance, but due to their relatively large threshold voltage, CMOS devices designed to work at room temperature are difficult to adapt to low temperature environments. Therefore, it is necessary to reduce the threshold voltage of NMOS devices or PMOS devices to enable CMOS devices to work normally in low temperature environments.
[0038] In order to solve the above technical problems, the present invention proposes a CMOS device and a method for manufacturing the same, which are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.
[0039] It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layer and the zone may be exaggerated, and the same reference numerals represent the same elements from beginning to end. It should be understood that although the terms first, second, etc. can be used to describe various elements, components, zones, layers and / or parts, these elements, components, zones, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, zone, layer or part from another element, component, zone, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, zone, layer or part discussed below can be represented as a second element, component, zone, layer or part.
[0040] See also Figure 1 , an embodiment of the present invention provides a method for preparing a CMOS device, comprising:
[0041] S1, providing a semiconductor substrate, the semiconductor substrate comprising an NMOS region and a PMOS region, a dielectric layer being formed on the surface of the semiconductor substrate, a first gate trench being formed in the dielectric layer on the NMOS region, and a second gate trench being formed in the dielectric layer on the PMOS region, the first gate trench and the second gate trench exposing a portion of the surface of the semiconductor substrate;
[0042] S2, forming a barrier layer and a P-type work function layer, wherein the barrier layer covers the bottom of the second gate trench, and the P-type work function layer covers the surface of the barrier layer and extends along the sidewall of the second gate trench to the surface of the dielectric layer covering the PMOS region;
[0043] S3, forming an N-type work function layer, wherein the N-type work function layer covers the bottom of the first gate trench and extends along the sidewall of the first gate trench to the surface of the dielectric layer covering the NMOS region and the surface of the P-type work function layer; and,
[0044] S4, forming a metal gate, wherein the metal gate fills the first gate trench and the second gate trench.
[0045] The embodiment of the present invention reduces the threshold voltage of the NMOS region by avoiding the formation of the barrier layer and the P-type work function layer in the NMOS region, so that the CMOS device can work normally at low temperatures; and because the CMOS device has a lower leakage current at low temperatures, even if the barrier layer and the P-type work function layer do not exist between the metal gate and the high-K dielectric layer subsequently formed in the NMOS region, metal diffusion in the metal gate may occur to cause leakage current, the normal operation of the CMOS device can be guaranteed.
[0046] The following combination Figure 2 to Figure 12 Steps S1 to S4 are described in further detail.
[0047] First, execute step S1, see Figure 2 A semiconductor substrate 10 is provided, the semiconductor substrate 10 includes an NMOS region 11 and a PMOS region 12, a dielectric layer 13 is formed on the surface of the semiconductor substrate 10, a first gate trench 110 is formed in the dielectric layer 13 on the NMOS region 11, and a second gate trench 120 is formed in the dielectric layer 13 on the PMOS region 12, the first gate trench 110 and the second gate trench 120 expose a portion of the surface of the semiconductor substrate 10.
[0048] The semiconductor substrate 10 includes an NMOS region 11 and a PMOS region 12. As an implementation method, a method for forming a first gate trench 110 and a second gate trench 120 in the NMOS region 11 and the PMOS region 12, respectively, includes: first, forming an NMOS virtual gate (not shown) on the semiconductor substrate 10 in the NMOS region 11, and forming a PMOS virtual gate (not shown) on the semiconductor substrate 10 in the PMOS region 12, and then forming a dielectric layer 13, the dielectric layer 13 being located on both sides of the NMOS virtual gate and the PMOS virtual gate; then, forming a source region and a drain region on both sides of the NMOS virtual gate and the PMOS virtual gate by using a source-drain ion implantation process; finally, removing the NMOS virtual gate and the PMOS virtual gate to form a first gate trench 110 and a second gate trench 120. In this embodiment, the first gate trench 110 is obtained by removing the NMOS virtual gate, and the second gate trench 120 is obtained by removing the PMOS virtual gate.
[0049] Furthermore, the material of the dielectric layer 13 may be silicon oxide. Optionally, the dielectric layer 13 is formed by chemical vapor deposition, such as plasma chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition or high density plasma deposition.
[0050] Next, execute step S2, see Figure 3 to Figure 9, forming a barrier layer 20 and a P-type work function layer 121, the barrier layer 20 covers the bottom of the second gate trench 120, the P-type work function layer 121 covers the surface of the barrier layer 20, and extends along the sidewall of the second gate trench 120 to the surface of the dielectric layer 13 covering the PMOS region.
[0051] Before forming the barrier layer 20, a high-K dielectric layer (not shown) is formed at the bottom of the first gate trench 110 and the bottom of the second gate trench 120. The barrier layer 20 covers the surface of the high-K dielectric layer, which can prevent the diffusion of the polysilicon material in the PMOS virtual gate or the NMOS virtual gate in step S1 to stabilize the performance state of the high-K dielectric layer. The material of the high-K dielectric layer includes materials such as HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials or combinations of the above materials. In this embodiment, the material of the high-K dielectric layer includes hafnium oxide.
[0052] Optionally, the material of the barrier layer 20 may be La2O3, Al2O3, Ga2O3, In2O3, TiSiN, TaN or other suitable thin film layers. In this embodiment, the material of the barrier layer 20 is titanium nitride.
[0053] In this embodiment, in order to facilitate the process, the method of forming the barrier layer 20 and the P-type work function layer 121 includes: first, forming the barrier layer 20 and the P-type work function layer 121, see Figure 3 The barrier layer 20 covers the bottom of the first gate trench 110 and the second gate trench 120, and the P-type work function layer 121 covers the barrier layer 20 and extends to the surface of the dielectric layer 13; then, a protective layer 30 is formed, such as Figure 4 , the protective layer 30 covers the surface of the P-type work function layer 121; then remove the protective layer 30 located in the NMOS region 11, and stop at the surface of the P-type work function layer 121, and obtain Figure 7 The structural diagram shown; finally, see Figure 8 , the barrier layer 20 at the bottom of the first gate trench 110 is removed, and the P-type work function layer 121 covering the barrier layer 20 and the surface of the dielectric layer 13 in the NMOS region 11 is removed. In this way, only the barrier layer 20 remains at the bottom of the second gate trench 120, and the P-type work function layer 121 is formed only on the surface of the barrier layer 20 and the surface of the dielectric layer 13 in the PMOS region 12.
[0054] Optionally, the method of removing the protective layer 30 includes: Figure 5As shown, a photoresist layer 40 is formed. Optionally, the photoresist layer 40 can be a positive photoresist or a negative photoresist. In this embodiment, the photoresist contained in the photoresist layer 40 is a positive photoresist. The photoresist layer 40 masks the PMOS region 12 and exposes the NMOS region 11. The protective layer 30 located in the NMOS region 11 is removed using the photoresist layer 40 as a mask, and stops at the surface of the P-type work function layer 121 to obtain Figure 6 ; Then remove the photoresist layer 40.
[0055] The protective layer 30 is formed to protect the P-type work function layer 121 located in the PMOS region 12 from being stripped off during the process of removing the barrier layer 20 and the P-type work function layer 121 located in the NMOS region 11 after the photoresist layer 40 is subsequently removed.
[0056] In the present embodiment, a dry etching process is used to remove the barrier layer 20 and the P-type work function layer 121, and the etching gas used in the dry etching process includes tungsten chloride. Considering that chloride ions may affect the photoresist, for example, chloride ions may react with the chemical substances in the photoresist, thereby changing its chemical properties, or chloride ions may also interfere with the structure of the optical polymer in the photoresist, causing its refractive index to change, thereby affecting the optical properties of the photoresist, therefore, the present embodiment adopts a two-step removal method to prevent the photoresist layer 40 from entering the working machine of the tungsten chloride removal process, that is, the photoresist layer 40 is removed first, and then the barrier layer 20 and the P-type work function layer 121 are removed.
[0057] like Figure 5 and Figure 6 As shown, the protective layer 30 formed on the P-type work function layer 121 and located in the NMOS region 11 is first removed using the photoresist layer 40 as a mask. At this time, the P-type work function layer 121 located below the protective layer 30 serves as an etching barrier layer, and the dry etching process stops at the surface of the P-type work function layer 121; see Figure 7 After the protective layer 30 is removed, the photoresist layer 40 is removed; then the barrier layer 20 and the P-type work function layer 121 located in the NMOS region 11 are removed; Figure 8 As shown, after step S2 , only a high-K dielectric layer is formed at the bottom of the first gate trench 110 of the NMOS region 11 , while a barrier layer 20 , a P-type work function layer 121 and a protection layer 30 are formed at the bottom of the second gate trench 120 of the PMOS region 12 .
[0058] In this embodiment, since the material of the barrier layer 20 is titanium nitride, tungsten chloride can be used to remove the barrier layer 20 and the P-type work function layer 121. In order to ensure a high etching selectivity ratio of the tungsten chloride etching process, the material selected for the protective layer 30 includes tungsten or titanium silicon nitrogen. In this embodiment, the protective layer 30 is a tungsten layer.
[0059] Specifically, in order to achieve a better effect of removing the barrier layer 20 and the P-type work function layer 121, preferably, the process temperature of the dry etching is 300 degrees Celsius to 400 degrees Celsius, for example, the process temperature is 350 degrees Celsius.
[0060] like Fig. 9 As shown, before forming the N-type work function layer 111, the protection layer 30 located in the PMOS region 12 is removed. Optionally, the protection layer 30 is removed by wet cleaning.
[0061] Optionally, the photoresist layer 40 is removed by using an ashing process combined with a wet cleaning process.
[0062] In this embodiment, the material of the P-type work function layer 121 is tantalum nitride.
[0063] Then, execute step S3, see Fig.10 , forming an N-type work function layer 111, the N-type work function layer 111 covers the bottom of the first gate trench 110, and extends along the sidewall of the first gate trench 110 to the surface of the dielectric layer 13 covering the NMOS region and the surface of the P-type work function layer 121. In this embodiment, the material of the N-type work function layer 111 is titanium aluminum alloy.
[0064] Optionally, a titanium nitride layer is formed on the surface of the N-type work function layer 111 , and the titanium nitride layer can prevent the diffusion of metal elements in the subsequently formed metal gate 50 .
[0065] Finally, execute step S4, see Figure 11-12 , a metal gate 50 is formed, and the metal gate 50 fills the first gate trench 110 and the second gate trench 120 .
[0066] Specifically, the method of forming the metal gate 50 in the first gate trench 110 and the second gate trench 120 includes: Fig.11 As shown in FIG. 1 , a metal gate material 51 is formed, the metal gate material 51 fills the first gate trench 110 and the second gate trench 120, and extends to cover the top surface of the N-type work function layer 111; and a chemical mechanical polishing process is performed on the metal gate material 51 to remove the P-type work function layer 121 and the N-type work function layer 111 located on the surface of the dielectric layer 13 and stop at the surface of the dielectric layer 13, so as to obtain the Fig.12 A metal gate 50 is shown.
[0067] Optionally, the metal gate 50 is made of aluminum.
[0068] This embodiment is different from the prior art in which a barrier layer 20 and a P-type work function layer 121 are retained in the first gate trench 110. The embodiment of the present invention can reduce the threshold voltage of the NMOS region 11 by removing the barrier layer 20 and the P-type work function layer 121 of the NMOS region 11, thereby allowing the CMOS device to meet the conditions for normal operation at low temperatures.
[0069] The embodiment of the present invention further provides a CMOS device, such as Fig.12 As shown, it includes: a semiconductor substrate 10, the semiconductor substrate 10 includes an NMOS region 11 and a PMOS region 12, a dielectric layer 13 is formed on the surface of the semiconductor substrate 10, a first gate trench 110 is formed in the dielectric layer 13 on the NMOS region 11, and a second gate trench 120 is formed in the dielectric layer 13 on the PMOS region 12, the first gate trench 110 and the second gate trench 120 expose a portion of the surface of the semiconductor substrate 10; a barrier layer 20 and a P-type work function layer 121, the barrier layer 20 covers the bottom of the second gate trench 120, the P-type work function layer 121 covers the surface of the barrier layer 20 and extends to the surface of the dielectric layer covering the PMOS region 12; an N-type work function layer 111, the N-type work function layer 111 covers the bottom of the first gate trench 110 and extends to the surface of the dielectric layer 13 covering the NMOS region 11 and the surface of the P-type work function layer 121; and a metal gate 20, the metal gate 20 fills the first gate trench 110 and the second gate trench 120.
[0070] Furthermore, since the NMOS region 11 does not have the barrier layer 20 and the P-type work function layer 121 , the threshold voltage of the NMOS region 11 can be reduced compared with the prior art, so that the CMOS device can work normally at low temperatures.
[0071] In summary, an embodiment of the present invention provides a CMOS device and a method for preparing the same, wherein the method for preparing the CMOS device comprises: providing a semiconductor substrate, wherein the semiconductor substrate comprises an NMOS region and a PMOS region, wherein a dielectric layer is formed on the surface of the semiconductor substrate, wherein a first gate trench is formed in the dielectric layer on the NMOS region, and a second gate trench is formed in the dielectric layer on the PMOS region, wherein the first gate trench and the second gate trench expose a portion of the surface of the semiconductor substrate; forming a barrier layer and a P-type work function layer, wherein the barrier layer covers the bottom of the second gate trench, the P-type work function layer covers the surface of the barrier layer, and extends along the sidewall of the second trench to the surface of the dielectric layer covering the PMOS region; forming an N-type work function layer, wherein the N-type work function layer covers the bottom of the first gate trench, and extends along the sidewall of the first gate trench to the surface of the dielectric layer covering the NMOS region and the surface of the stop layer; and forming a metal gate, wherein the metal gate fills the first gate trench and the second gate trench. The embodiment of the present invention reduces the threshold voltage of the NMOS region by avoiding the formation of the barrier layer and the P-type work function layer in the NMOS region, so that the CMOS device can work normally at low temperatures; and because the CMOS device has a lower leakage current at low temperatures, even if the barrier layer and the P-type work function layer do not exist between the metal gate and the high-K dielectric layer subsequently formed in the NMOS region, metal diffusion in the metal gate may occur to cause leakage current, the normal operation of the CMOS device can be guaranteed.
[0072] In addition, it should be recognized that although the present invention application has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.
Claims
1. A CMOS device, characterized in that: include: A semiconductor substrate, the semiconductor substrate comprising an NMOS region and a PMOS region, a dielectric layer formed on the surface of the semiconductor substrate, a first gate trench formed in the dielectric layer on the NMOS region, a second gate trench formed in the dielectric layer on the PMOS region, the first gate trench and the second gate trench exposing a portion of the surface of the semiconductor substrate; a barrier layer, wherein the barrier layer covers the bottom of the second gate trench; A P-type work function layer, the P-type work function layer covers a surface of the barrier layer and extends along a sidewall of the second gate trench to a surface of the dielectric layer covering the PMOS region; An N-type work function layer, the N-type work function layer covers the bottom of the first gate trench and extends along the sidewall of the first gate trench to the surface of the dielectric layer covering the NMOS region and the surface of the P-type work function layer; as well as, A metal gate fills the first gate trench and the second gate trench.
2. The CMOS device according to claim 1, characterized in that The material of the barrier layer includes titanium nitride.
3. The CMOS device according to claim 1, characterized in that: The material of the P-type work function layer includes tantalum nitride.
4. A method for preparing a CMOS device, characterized in that: include: A semiconductor substrate is provided, the semiconductor substrate comprising an NMOS region and a PMOS region, a dielectric layer is formed on the surface of the semiconductor substrate, a first gate trench is formed in the dielectric layer on the NMOS region, a second gate trench is formed in the dielectric layer on the PMOS region, the first gate trench and the second gate trench expose a portion of the surface of the semiconductor substrate; forming a barrier layer and a P-type work function layer, wherein the barrier layer covers the bottom of the second gate trench, and the P-type work function layer covers the surface of the barrier layer and extends along the sidewall of the second trench to the surface of the dielectric layer covering the PMOS region; forming an N-type work function layer, wherein the N-type work function layer covers the bottom of the first gate trench and extends along the sidewall of the first gate trench to the surface of the dielectric layer covering the NMOS region and the surface of the P-type work function layer; and, A metal gate is formed, the metal gate filling the first gate trench and the second gate trench.
5. The method for preparing a CMOS device according to claim 4, wherein: The method of forming the barrier layer and the P-type work function layer includes: forming the barrier layer and the P-type work function layer, wherein the barrier layer covers the bottom of the first gate trench and the bottom of the second gate trench, and the P-type work function layer covers the barrier layer and extends to cover the surface of the dielectric layer; forming a protection layer, the protection layer covering the surface of the P-type work function layer located in the PMOS region; and, The barrier layer at the bottom of the first gate trench is removed, and the P-type work function layer covering the surface of the barrier layer and the dielectric layer in the NMOS region is removed.
6. The method for preparing a CMOS device according to claim 5, wherein: Before forming the N-type work function layer, the method further includes: removing the protection layer on the surface of the P-type work function layer located in the PMOS region.
7. The method for preparing a CMOS device according to claim 5, wherein: The barrier layer and the P-type work function layer are removed by a dry etching process.
8. The method for preparing a CMOS device according to claim 7, wherein: The dry etching process uses tungsten chloride gas, and the process temperature is 300 degrees Celsius to 400 degrees Celsius.
9. The method for preparing a CMOS device according to claim 4, wherein: Also includes: A high-K dielectric layer is formed between the bottom of the first gate trench and the barrier layer, and between the bottom of the second gate trench and the barrier layer.
10. The method for preparing a CMOS device according to claim 4, characterized in that: The method of forming the metal gate includes: forming a metal gate material, wherein the metal gate material fills the first gate trench and the second gate trench and extends to cover the top surface of the N-type work function layer; and, A chemical mechanical polishing process is performed on the metal gate material to remove the P-type work function layer and the N-type work function layer located on the surface of the dielectric layer, and the process stops at the surface of the dielectric layer.