Preparation method of TBC battery and battery
By using patterned local hollow plate CVD process for selective doping of polycrystalline silicon in TBC battery preparation, the problems of complex and high cost of traditional processes are solved, and process simplification and production efficiency are achieved.
Patent Information
- Application Number
- CN202510020539.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-04-22
AI Technical Summary
TBC batteries face complex process flow and high equipment investment costs during the preparation process, which limits their large-scale commercial applications.
Selective doping of polysilicon by using a patterned locally hollowed-out plate CVD process simplifies the process flow and avoids mask preparation and multiple etching and deposition operations.
It effectively simplifies process steps, reduces production costs, improves preparation efficiency, reduces development and mass production difficulties, and shortens production cycles.
Smart Images
Figure CN119866094A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solar cell technology, and in particular to a method for preparing a TBC cell and the cell itself. Background Technology
[0002] With the continuous growth of global demand for clean energy, solar cell technology has developed rapidly. Currently, mainstream TOPCon solar cells are gradually approaching their theoretical limits. Against this backdrop, back-contact battery technology has emerged as a highly promising technological approach and is widely considered an important development direction for the next generation of mainstream battery technology.
[0003] TBC solar cells are a novel cell structure that combines TOPCon and IBC technologies, offering unique structural advantages. The absence of metal grid lines on the front side allows the cell to absorb sunlight to the maximum extent, generating more electron-hole pairs and thus achieving higher photoelectric conversion efficiency. However, TBC cells face numerous challenges in their fabrication.
[0004] To achieve high performance, TBC (Transient Carbon Cell) batteries require the fabrication of mutually isolated P+-doped and N+-doped polysilicon passivation regions on the back side. Currently, the industry commonly uses two main fabrication methods: one is to fabricate a mask to achieve selective doping of polysilicon; the other is to use laser etching and chemical etching techniques to first remove the doped polysilicon layer in the boron / phosphorus-doped polysilicon region, and then perform secondary deposition of the polysilicon layer and boron or phosphorus doping to form the desired back-side structure of the battery. However, these traditional methods have significant drawbacks. The mask fabrication and multiple etching and deposition operations of polysilicon not only increase equipment investment costs but also make the entire process extremely complex, limiting the large-scale commercial application of TBC batteries. Summary of the Invention
[0005] This application addresses the aforementioned problems and overcomes the shortcomings of existing technologies by providing a method for preparing a TBC battery and the battery itself. It employs a patterned, locally hollowed-out plate CVD process for selective doping of polycrystalline silicon, avoiding mask preparation and multiple etching and deposition of polycrystalline silicon, reducing equipment investment, simplifying the process flow, and lowering production costs.
[0006] The technical solution of this application is as follows:
[0007] A method for preparing a TBC battery includes the following steps:
[0008] S1: Alkali polishing treatment of N-type silicon wafers;
[0009] S2: An oxide layer and a polycrystalline silicon layer are prepared on the back side of a silicon wafer using a plate CVD process;
[0010] S3: A patterned partial cutout plate CVD process is used to selectively dope boron on the back side of the silicon wafer to form a boron-doped polycrystalline silicon layer and a BSG layer.
[0011] S4: A patterned, partially hollowed-out plate CVD process is used to selectively dope phosphorus on the back side of the silicon wafer to form a phosphorus-doped polycrystalline silicon layer and a PSG layer.
[0012] S5: Laser film opening process is performed at the junction of the boron-doped region and the phosphorus-doped region on the back of the silicon wafer to remove the BSG layer and PSG layer in the corresponding area and form an isolation region of doped polycrystalline silicon layer.
[0013] S6: Perform a post-texturing process on the silicon wafer to form a textured surface on the front side of the silicon wafer and the isolation area of the doped polysilicon layer, while removing the BSG and PSG layers in the boron-doped and phosphorus-doped regions of the silicon wafer.
[0014] S7: Deposit passivation film on both sides of the silicon wafer, and prepare anti-reflection film on the silicon wafer using PECVD process;
[0015] S8: Screen printing, sintering, and photoinjection of silicon wafers.
[0016] Furthermore, in S1, the temperature for alkaline polishing is 60℃~80℃.
[0017] Furthermore, in S2, the thickness of the oxide layer is 1nm to 3nm, and the thickness of the polycrystalline silicon layer is 80nm to 300nm.
[0018] Furthermore, in S3, the boron doping temperature is 800℃~1100℃, the boron source flow rate is 200sccm~1100sccm, the BSG layer thickness is 40nm~120nm, and the boron doping concentration of the polycrystalline silicon is 1E19cm⁻¹. -3 ~1E20cm -3 .
[0019] Furthermore, in step S4, the phosphorus doping temperature is 600℃~800℃, the phosphorus source flow rate is 100sccm~1100sccm, the PSG layer thickness is 40nm~120nm, and the phosphorus doping concentration of the polycrystalline silicon is 1.5E20cm⁻¹. -3 ~3E20cm -3 .
[0020] Furthermore, in S5, the laser power of the laser film-opening process is 30W to 80W, the spot diameter is 100μm to 150μm, the frequency is 100KHz to 500KHz, and the spot overlap rate is 40% to 80%.
[0021] Furthermore, in S6, the post-flocking process includes flocking and pickling, wherein the flocking temperature is 60℃~80℃, and the pickling is performed using an aqueous solution of HF with a volume concentration of 10%~35%.
[0022] Furthermore, in step S7, the passivation film is AlO₂. x The membrane has a thickness of 5 nm to 30 nm.
[0023] Furthermore, in S7, the antireflective film is SiN. x The membrane has a thickness of 50 nm to 150 nm.
[0024] This application also provides a TBC battery, which is prepared using the aforementioned preparation method.
[0025] Compared with the prior art, the present invention has the following beneficial effects:
[0026] (1) Simplified process flow: This application uses a plate CVD process with patterned local hollowing to selectively dope polycrystalline silicon. There is no need to prepare a mask or perform multiple etching and deposition of polycrystalline silicon. Therefore, the process steps in the production process can be effectively simplified, and the production efficiency can be further improved while ensuring the yield. This reduces the difficulty of developing and mass-producing TBC cells, shortens the production cycle, increases production capacity, and reduces production costs.
[0027] (2) The TBC battery provided in this application is prepared by the preparation method of this application and has higher preparation efficiency and lower production cost. Attached Figure Description
[0028] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a process flow diagram of the fabrication process of a TBC battery provided in Embodiments 1-3 of the present invention. Detailed Implementation
[0030] The technical solution of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.
[0031] Example 1
[0032] This embodiment provides a method for preparing a TBC battery, such as... Figure 1 As shown, the preparation method includes the following steps:
[0033] S1: Perform alkaline polishing on N-type silicon wafers at 60℃ to optimize the surface condition of the silicon wafers, remove the surface damage layer, and provide a good foundation for subsequent processes.
[0034] S2: A 1nm thick oxide layer and an 80nm thick polycrystalline silicon layer are prepared on the back of a silicon wafer using a plate CVD process. The oxide layer can passivate and protect the silicon wafer, while the intrinsic polycrystalline silicon layer provides the basic structure for subsequent doping.
[0035] S3: A patterned, partially hollowed-out plate CVD process is used to perform region-selective boron doping on the back side of a silicon wafer at 800°C with a boron source flux of 200 sccm, forming a 40 nm thick BSG layer and a boron doping concentration of 1E19cm⁻¹. -3 A polycrystalline silicon layer; enabling doping control in specific regions.
[0036] S4: A patterned, partially perforated plate-type CVD process was used to perform region-selective phosphorus doping on the back side of a silicon wafer at 600°C. The phosphorus source flow rate was 100 sccm, forming a 40 nm thick PSG layer with a phosphorus doping concentration of 1.5E20cm. -3 The polycrystalline silicon layer, together with the boron-doped region, constitutes the doped structure on the back of the battery.
[0037] S5: Laser film removal is performed at the junction of the boron-doped and phosphorus-doped regions on the back of the silicon wafer to remove the corresponding BSG and PSG layers. The laser power is 30W, the spot diameter is 100μm, the frequency is 100KHz, and the spot overlap rate is 40%. By precisely controlling these laser parameters, the thin film in the junction region is accurately removed, and the laser-acted area forms an isolation region of doped polycrystalline silicon.
[0038] S6: Post-texturing process for silicon wafers, including texturing and acid pickling. The texturing temperature is 60℃, and the acid pickling uses a 10% (v / v) HF aqueous solution to form a textured surface on the front side of the silicon wafer and the isolation area of the doped polysilicon layer. At the same time, the BSG and PSG layers in the boron-doped and phosphorus-doped regions of the silicon wafer are removed. The textured surface structure can increase light absorption and further optimize the performance of the cell.
[0039] S7: Depositing 5nm thick AlO2 on both sides of a silicon wafer. x A passivation film is applied to reduce surface recombination and improve battery stability; subsequently, a 30nm thick SiN film is fabricated on the silicon wafer using PECVD technology. x Anti-reflective coatings reduce light reflection loss and improve the battery's light utilization rate.
[0040] S8: Screen printing, sintering, and light injection are performed on silicon wafers to form TBC cells; the electrical connection and performance optimization of the cells are achieved.
[0041] Example 2
[0042] This embodiment provides a method for preparing a TBC battery, such as... Figure 1 As shown, the preparation method includes the following steps:
[0043] S1: Perform alkaline polishing on N-type silicon wafers at 80℃ to optimize the surface condition of the silicon wafers, remove the surface damage layer, and provide a good foundation for subsequent processes.
[0044] S2: A 3nm thick oxide layer and a 300nm thick polycrystalline silicon layer are prepared on the back of a silicon wafer using a plate CVD process. The oxide layer can passivate and protect the silicon wafer, while the intrinsic polycrystalline silicon layer provides the basic structure for subsequent doping.
[0045] S3: A patterned, partially hollowed-out plate CVD process is used to perform region-selective boron doping on the back side of a silicon wafer at 1100℃, with a boron source flux of 1100 sccm, forming a 120 nm thick BSG layer and a boron doping concentration of 1E20cm⁻¹. -3 A polycrystalline silicon layer; enabling doping control in specific regions.
[0046] S4: A patterned, partially perforated plate-type CVD process is used to perform region-selective phosphorus doping on the back side of a silicon wafer at 800°C. The phosphorus source flow rate is 1100 sccm, forming a 120 nm thick PSG layer with a phosphorus doping concentration of 3E20cm⁻¹. -3 The polycrystalline silicon layer, together with the boron-doped region, constitutes the doped structure on the back of the battery.
[0047] S5: Laser film removal is performed at the junction of the boron-doped and phosphorus-doped regions on the back of the silicon wafer to remove the corresponding BSG and PSG layers. The laser power is 80W, the spot diameter is 150μm, the frequency is 500KHz, and the spot overlap rate is 80%. By precisely controlling these laser parameters, the thin film in the junction region is accurately removed, and the laser-acted area forms an isolation region of doped polycrystalline silicon.
[0048] S6: Post-texturing process for silicon wafers, including texturing and acid pickling. The texturing temperature is 80℃, and the acid pickling uses a 35% (v / v) HF aqueous solution to form a textured surface on the front side of the silicon wafer and the isolation region of the doped polysilicon layer. At the same time, the BSG and PSG layers in the boron-doped and phosphorus-doped regions of the silicon wafer are removed. The textured surface structure can increase light absorption and further optimize the performance of the battery.
[0049] S7: Depositing a 30nm thick AlO layer on both sides of a silicon wafer.x A passivation film is applied to reduce surface recombination and improve battery stability; subsequently, a 150nm thick SiN film is fabricated on the silicon wafer using PECVD technology. x Anti-reflective coatings reduce light reflection loss and improve the battery's light utilization rate.
[0050] S8: Screen printing, sintering, and light injection are performed on silicon wafers to form TBC cells; the electrical connection and performance optimization of the cells are achieved.
[0051] Example 3
[0052] This embodiment provides a method for preparing a TBC battery, such as... Figure 1 As shown, the preparation method includes the following steps:
[0053] S1: Perform alkaline polishing on N-type silicon wafers at 70℃ to optimize the surface condition of the silicon wafers, remove the surface damage layer, and provide a good foundation for subsequent processes.
[0054] S2: A 2nm thick oxide layer and a 190nm thick polycrystalline silicon layer are prepared on the back of a silicon wafer using a plate CVD process. The oxide layer can passivate and protect the silicon wafer, while the intrinsic polycrystalline silicon layer provides the basic structure for subsequent doping.
[0055] S3: A patterned, partially hollowed-out plate CVD process is used to perform region-selective boron doping on the back side of a silicon wafer at 950°C with a boron source flux of 550 sccm, forming an 80 nm thick BSG layer and a boron doping concentration of 5E19cm. -3 A polycrystalline silicon layer; enabling doping control in specific regions.
[0056] S4: A patterned, partially perforated plate-type CVD process was used to perform region-selective phosphorus doping on the back side of a silicon wafer at 700°C. The phosphorus source flow rate was 900 sccm, forming an 80 nm thick PSG layer with a phosphorus doping concentration of 2.2E20cm. -3 The polycrystalline silicon layer, together with the boron-doped region, constitutes the doped structure on the back of the battery.
[0057] S5: Laser film removal is performed at the junction of the boron-doped and phosphorus-doped regions on the back of the silicon wafer to remove the corresponding BSG and PSG layers. The laser power is 55W, the spot diameter is 125μm, the frequency is 125KHz, and the spot overlap rate is 60%. By precisely controlling these laser parameters, the thin film in the junction region is accurately removed, and the laser-acted area forms an isolation region of doped polycrystalline silicon.
[0058] S6: Post-texturing process for silicon wafers, including texturing and acid pickling. The texturing temperature is 70℃, and the acid pickling uses a 22% (v / v) HF aqueous solution to create a textured surface on the front side of the silicon wafer and the isolation region of the doped polysilicon layer. At the same time, the BSG and PSG layers in the boron-doped and phosphorus-doped regions of the silicon wafer are removed. The textured surface structure can increase light absorption and further optimize the performance of the battery.
[0059] S7: Depositing a 17nm thick AlO layer on both sides of a silicon wafer. x A passivation film is applied to reduce surface recombination and improve battery stability; subsequently, a 100nm thick SiN film is fabricated on the silicon wafer using PECVD technology. x Anti-reflective coatings reduce light reflection loss and improve the battery's light utilization rate.
[0060] S8: Screen printing, sintering, and light injection are performed on silicon wafers to form TBC cells; the electrical connection and performance optimization of the cells are achieved.
[0061] Comparative Example 1
[0062] The difference between this comparative example and Example 1 is that: in Comparative example 1, selective doping of polycrystalline silicon is achieved by preparing a mask to form P+-doped polycrystalline silicon and N+-doped polycrystalline silicon passivation regions that are isolated from each other on the back of the TBC cell; the rest of the preparation methods and parameters are the same as in Example 1.
[0063] Comparative Example 2
[0064] The difference between this comparative example and Example 1 is that: Comparative example 2 uses laser film opening and chemical etching technology to first remove the doped polysilicon layer in the boron / phosphorus doped polysilicon region, and then performs a secondary deposition of the polysilicon layer and boron or phosphorus doping to prepare the P+ doped polysilicon and N+ doped polysilicon passivation regions that are isolated from each other on the back of the TBC cell. The rest of the preparation methods and parameters are the same as those in Example 1.
[0065] Performance testing
[0066] The electrical performance of the TBC batteries prepared in Examples 1-3 and Comparative Examples 1-2 was tested.
[0067] The test method was as follows: the parameters of the solar cell were measured using an IV tester, and the results are shown in Table 1.
[0068] Table 1. Battery test results for the examples and comparative examples.
[0069]
[0070] Performance test data conclusions and analysis:
[0071] As can be seen from the table above, the TBC battery prepared by the preparation method provided by the present invention has excellent conversion efficiency.
[0072] The conversion efficiencies of Examples 1-3 are not significantly different from those of Comparative Examples 1-2, but are all at a high level. This indicates that the simplified process of selective doping of polycrystalline silicon using patterned plate CVD can produce TBC cells with relatively high conversion efficiencies, and the conversion efficiency, a key performance indicator, is not reduced due to the simplification of the process. In addition, the fill factor is slightly higher, and the reverse current is significantly lower than that of the comparative examples using a complex preparation process. This shows that the preparation method provided by this invention can obtain high-performance TBC cells while simplifying the process.
[0073] Therefore, this application achieves the preparation of P+-doped and N+-doped polycrystalline silicon passivation layers on the back of TBC cells by selectively doping polycrystalline silicon using a patterned plate CVD process, without the need for mask fabrication or etching of the doped layer and secondary deposition of the polycrystalline silicon layer. This effectively simplifies the process steps and reduces production costs, thereby reducing the difficulty of developing and mass-producing TBC cells and improving the market competitiveness of the products.
[0074] The present invention has been further described above with reference to specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the nature and scope of the present invention. Various modifications made to the above embodiments by those skilled in the art after reading this specification are all within the scope of protection of the present invention.
Claims
1. A method for preparing a TBC battery, characterized in that: The steps include: S1: alkaline polishing treatment is performed on the N-type silicon wafer; S2: using plate-type CVD process to prepare oxide layer and polysilicon layer on the back of silicon wafer; S3: using a patterned local hollow plate CVD process to perform regional selective boron doping on the back side of the silicon wafer to form a boron-doped polysilicon layer and a BSG layer; S4: using a plate-type CVD process with a pattern and a local hollowing-out to perform regional selective phosphorus doping on the back side of the silicon wafer to form a phosphorus-doped polysilicon layer and a PSG layer; S5: performing laser film opening treatment at the junction of the boron-doped area and the phosphorus-doped area on the back of the silicon wafer to remove the BSG layer and the PSG layer in the corresponding area to form an isolation area of the doped polysilicon layer; S6: performing a post-texturing process on the silicon wafer to form a velvet surface on the front side of the silicon wafer and the isolation area of the doped polysilicon layer, and removing the BSG layer and the PSG layer in the boron doped area and the phosphorus doped area of the silicon wafer; S7: depositing a passivation film on both sides of the silicon wafer, and preparing an anti-reflection film on the silicon wafer using a PECVD process; S8: Screen printing, sintering and light injection of silicon wafers.
2. The method for preparing a TBC battery according to claim 1, characterized in that: In the above S1, the polishing temperature is 60°C to 80°C.
3. The method for preparing a TBC battery according to claim 1, characterized in that: In the S2, the thickness of the oxide layer is 1 nm to 3 nm, and the thickness of the polysilicon layer is 80 nm to 300 nm.
4. The method for preparing a TBC battery according to claim 1, characterized in that: In S3, the boron doping temperature is 800°C to 1100°C, the flow rate of the boron source is 200sccm to 1100sccm, the thickness of the BSG layer is 40nm to 120nm, and the boron doping concentration of the polysilicon is 1E19 cm -3 ~1E20cm -3 .
5. The method for preparing a TBC battery according to claim 1, characterized in that: In S4, the phosphorus doping temperature is 600°C to 800°C, the flow rate of the phosphorus source is 100 sccm to 1100 sccm, the thickness of the PSG layer is 40nm to 120nm, and the phosphorus doping concentration of the polysilicon is 1.5E20 cm -3 ~3E20cm -3 .
6. The method for preparing a TBC battery according to claim 1, characterized in that: In the above S5, the laser power of the laser film opening process is 30W-80W, the spot diameter is 100μm-150μm, the frequency is 100KHz-500KHz, and the spot overlap rate is 40%-80%.
7. The method for preparing a TBC battery according to claim 1, characterized in that: In S6, the post-texturing process includes texturing and pickling treatment, wherein the texturing temperature is 60°C to 80°C, and the pickling treatment is performed using an aqueous solution of HF, and the volume concentration of HF is 10% to 35%.
8. The method for preparing a TBC battery according to claim 1, characterized in that: In S7, the passivation film is AlO x The film has a thickness of 5nm to 30nm.
9. The method for preparing a TBC battery according to claim 1, characterized in that: In S7, the anti-reflection film is SiN x The film has a thickness of 50nm to 150nm.
10. A TBC battery, characterized in that: The TBC battery is prepared by the preparation method according to any one of claims 1 to 9.