Method for producing semiconductor body, semiconductor body and power semiconductor device

Abstract

According to one embodiment, the method for manufacturing a semiconductor body (10) comprises a step of providing a first semiconductor layer (1) of SiC, a further step of introducing carbon into the first semiconductor layer such that at least a portion of the first semiconductor layer becomes at least one C-rich region (11), and a step of growing a second semiconductor layer (2) of SiC on the first semiconductor layer comprising the at least one C-rich region.

Description

Technical Field

[0001] The present disclosure relates to a method for producing a semiconductor body, a semiconductor body and a power semiconductor device. Summary of the invention

[0002] An improved method for manufacturing a semiconductor body is needed, for example a method allowing the manufacturing of a semiconductor body with a high charge carrier mobility. Another object to be achieved is to provide an improved semiconductor body, for example a semiconductor body with a high charge carrier mobility. A further object to be achieved is to provide a power semiconductor device with such a semiconductor body.

[0003] Embodiments of the present disclosure relate to an improved method for manufacturing a semiconductor body, an improved semiconductor body, and an improved power semiconductor device.

[0004] According to one embodiment, a method for manufacturing a semiconductor body includes a step of providing a first semiconductor layer of silicon carbide (SiC for short), another step of introducing carbon (C for short) into the first semiconductor layer so that at least a portion of the first semiconductor layer becomes at least one carbon-rich region (C-rich region for short), and a step of growing a second semiconductor layer of SiC on the first semiconductor layer including the at least one C-rich region.

[0005] The present invention is based on the recognition that carbon vacancies are the most important point defects in SiC (e.g., n-type 4H-SiC). Carbon vacancies create two electrically active levels in the band gap, labeled Z 1 / 2 and EH 6 / 7 , which are located at 0.65 eV and 1.6 eV below the conduction band edge, respectively. In particular, Z 1 / 2 It is considered to be a recombination center, which affects the life of bipolar devices.

[0006] The inventors of the present invention have conceived of forming at least one C-rich region within a semiconductor layer sequence. This C-rich region will eventually release carbon from interstitials, which will subsequently anneal out carbon vacancies. Since at least one C-rich region is formed during the process of forming the semiconductor layer sequence (i.e., after providing the first semiconductor layer and before growing the second semiconductor layer), a C-rich region can be formed within the semiconductor layer sequence, so that the C-rich region can more efficiently provide carbon from carbon interstitials to all regions of the semiconductor layer sequence.

[0007] Furthermore, forming at least one C-rich region during the formation of the semiconductor layer sequence as described herein is beneficial compared to forming the C-rich region after the semiconductor layer sequence has been fully grown. This is because, in the second case, the C-rich region must be formed within the semiconductor layer sequence by deep C ion implantation, which requires high implantation energy. This makes the process costly and also amorphizes the crystals, thereby creating more electrically active energy levels. The method proposed herein is cheaper and gentler, i.e., produces far fewer active energy levels than deep ion implantation.

[0008] The first semiconductor layer may be provided as a continuous layer, e.g. without interruption. Providing the first semiconductor layer may include the step of growing (e.g. epitaxially growing) the first semiconductor layer on a substrate. The first semiconductor layer may be grown by chemical vapor deposition (CVD for short). For example, the substrate is made of SiC. The substrate may be doped, e.g. n-type doped. The doping concentration in the substrate may be at least 10 18 cm -3 .

[0009] The thickness of the first semiconductor layer is, for example, at least 1 μm, at least 2 μm, or at least 5 μm. Additionally or alternatively, the thickness of the first semiconductor layer may be at most 30 μm or at most 20 μm. The thickness of the substrate may be greater than the thickness of the first semiconductor layer. For example, the thickness of the substrate is at least 100 μm or at least 300 μm and / or at most 600 μm or at most 400 μm.

[0010] Here, the thickness of a layer, region or substrate refers to its extension in the vertical direction (i.e. in a direction perpendicular to the main extension plane of the first semiconductor layer). The SiC of the different semiconductor layers and / or substrates described herein is, for example, 4H-SiC, in particular n-doped 4H-SiC.

[0011] The first semiconductor layer may be doped, for example, n-type doped. For example, the average and / or maximum doping concentration in the first semiconductor layer is less than the average and / or minimum doping concentration in the substrate, for example, less than at least one, at least two, or at least three orders of magnitude. For example, the average doping concentration in the first semiconductor layer is about 10 14 cm -3 and 10 17 cm -3 The first semiconductor layer may have been doped with n-type when provided. For example, the first semiconductor layer is doped during its growth process.

[0012] The step of introducing carbon into the first semiconductor layer is accomplished such that at least a portion of the first semiconductor layer becomes at least one C-rich region. A C-rich region is understood herein as a region in which the carbon concentration is greater than that in an ideal SiC crystal. For example, in a C-rich region, additional carbon atoms (C atoms) or carbon ions (C ions) are located at interstitial sites.

[0013] For example, a C-rich region is defined herein as a region in which the minimum and / or average concentration of C atoms or C ions at interstitial sites is at least 100 times, or at least 1000 times, or at least 10,000 times greater than the maximum and / or average concentration in the remainder of the first semiconductor layer or in the first semiconductor layer before the step of introducing carbon is performed, respectively. Carbon at interstitial sites is typically charged, so interstitial sites are primarily C ions.

[0014] Here, the minimum concentration in a region, layer, etc. refers to the lowest concentration that can be found in the aforementioned region, layer, etc. Thus, the maximum concentration in a region, layer, etc. refers to the highest concentration that can be found in the aforementioned region, layer. The average concentration in a region, layer, etc. is the concentration averaged over the entire volume of the aforementioned region, layer, etc.

[0015] For example, only a portion, not the entire first semiconductor layer, becomes a C-rich region. For example, only the region at the exposed surface (through which carbon enters the first semiconductor layer) becomes C-rich. For example, at most 10%, at most 5%, or at most 1% of the volume of the first semiconductor layer becomes at least one C-rich region.

[0016] "At least one C-rich region" means that only one continuous region of the first semiconductor layer becomes a C-rich region, or that multiple spatially separated regions of the first semiconductor layer all become C-rich regions. All features disclosed herein for one C-rich region are also disclosed for all other C-rich regions.

[0017] The introduction of carbon into the first semiconductor layer can be done by C ion implantation or by annealing in a C-rich environment (eg, CO2, CH4, etc.) or by PIII. Once the carbon is introduced, it can be diffused by thermal annealing.

[0018] The second semiconductor layer is also made of SiC and is grown on the first semiconductor layer after forming at least one C-rich region. That is, the second semiconductor layer is grown on the first semiconductor layer that already includes at least one C-rich region. In particular, the second semiconductor layer is grown so that it partially or completely covers at least one C-rich region. The main extension plane of the second semiconductor layer can be parallel to the main extension plane of the first semiconductor layer.

[0019] The second semiconductor layer may be epitaxially grown on the first semiconductor layer. For example, the second semiconductor layer is grown directly on the first semiconductor layer, ie adjacent to the first semiconductor layer (particularly at at least one C-rich region). The growth technique may be the same as that used for the first semiconductor layer.

[0020] After growth, the second semiconductor layer may have a thickness of at least 2 μm or at least 5 μm. Additionally or alternatively, the thickness of the second semiconductor layer may be at most 30 μm or at most 20 μm. The second semiconductor layer may, for example, be grown uninterruptedly as a continuous layer. It may extend over the entire lateral extension of the first semiconductor layer. Here, lateral is a direction parallel to the main extension plane of the first semiconductor layer.

[0021] During the growth process, the second semiconductor layer may be doped, for example n-type doped, with a doping concentration, for example, the same as the concentration specified in connection with the first semiconductor layer.

[0022] According to another embodiment, the C-rich region is formed on the exposed side of the first semiconductor layer. That is, the C-rich region is formed so that it is adjacent to the top side of the first semiconductor layer, carbon is introduced through the top side, and then the second semiconductor layer is grown thereon.

[0023] According to another embodiment, the C-rich region is formed so that after the second semiconductor layer is grown, the C-rich region is located between the remaining portion of the first semiconductor layer that has not become C-rich and the second semiconductor layer. In other words, the C-rich region is formed so that it does not extend over the entire thickness of the first semiconductor layer. For example, the depth (thickness) of the C-rich region is at most 10% or at most 5% or at most 1% of the thickness of the first semiconductor layer.

[0024] According to another embodiment, carbon is introduced into the first semiconductor layer using plasma ion immersion implantation (PIII for short). PIII is a particularly mild implantation method that can produce very shallow implantation regions, i.e. implantation regions of small depth (thickness). Due to the special implantation shape generated by PIII and the presence of additional species from one or more precursors used, SIMS can detect the use of PIII in the final semiconductor body.

[0025] According to another embodiment, the method comprises a further step of implanting a first type dopant into the semiconductor layer sequence, the aforementioned semiconductor layer sequence comprising a first semiconductor layer and a second semiconductor layer. That is, the first type dopant is implanted after the second semiconductor layer is grown. In addition to the first semiconductor layer and the second semiconductor layer, the semiconductor layer sequence implanted with the first type dopant may also include one or more additional semiconductor layers. For example, before growing the first semiconductor layer and / or after growing the second semiconductor layer, at least one further semiconductor layer is grown.

[0026] For example, after the growth of the semiconductor layer sequence is completed, that is, after all growth steps for manufacturing the semiconductor body have been performed, the implantation of the first type dopant is performed. For example, the first type dopant is injected into the semiconductor layer sequence via a side of the semiconductor layer sequence that is closer to the second semiconductor layer than the first semiconductor layer. For example, the first type dopant is implanted at such a depth that it does not reach the C-rich region and / or the first semiconductor layer. For example, the first type dopant is implanted into the second semiconductor layer. The first type dopant can be a p-type dopant, such as boron. For example, a p-well is formed in the step of implanting the first type dopant.

[0027] According to another embodiment, the first type dopant is activated at a temperature of at least 1000° C. or at least 1500° C. Additionally or alternatively, the temperature for activating the first type dopant may be at most 1800° C. or at most 1700° C.

[0028] Heating the semiconductor layer sequence to such a temperature will also release carbon at interstitial sites of the C-rich region. The released carbon will then recombine with carbon vacancies created during implantation of the first type of dopant and / or with pre-existing carbon vacancies.

[0029] Additionally or alternatively, the semiconductor layer sequence can be heated to the above temperatures independently of the implantation of the first type dopant. For example, the semiconductor layer sequence can be heated to these temperatures before implanting the first type dopant, or even without performing a dopant implantation at all. Such heating has the same effect as carbon being released from interstitial sites and eventually combining with carbon vacancies.

[0030] According to another embodiment, the implantation is performed with a C ion energy in the range of 0.5 keV (inclusive) to 100 keV (inclusive), for example, 1 keV (inclusive) to 50 keV (inclusive). With such an implantation energy, the damage caused by the implantation can be kept small.

[0031] According to another embodiment, in the C-rich region, the minimum and / or average concentration of C atoms or C ions at interstitial sites is at least 10 14 cm -3 or at least 10 16 cm -3 , at least 10 17 cm-3 or at least 10 18 cm -3 Additionally or alternatively, in the C-rich region, the maximum concentration of C atoms or C ions at interstitial sites is at most 10 21 cm -3In particular, the C-rich region may be defined as a region where this minimum concentration exists everywhere, or as a region having this average concentration.

[0032] According to another embodiment, at least one buffer region of the second semiconductor layer is adjacent to the C-rich region and is doped with a second type dopant. The second type dopant is, for example, an n-type dopant. In particular, the second type dopant is different from the first type dopant, ie, has an opposite conductivity type.

[0033] According to another embodiment, the minimum and / or average concentration of the second type dopant in at least one buffer region of the second semiconductor layer is greater than the maximum and / or average concentration of the second type dopant in the first semiconductor layer. For example, the minimum and / or average concentration of the second type dopant in the buffer region is at least 10 times or at least 100 times or at least 1000 times greater than the maximum and / or uniform concentration of the second type dopant in the first semiconductor layer. The minimum and / or average concentration of the second type dopant in the buffer region is, for example, at least 10 16 cm -3 or at least 10 17 cm -3 Additionally or alternatively, the maximum and / or average concentration of the second type dopant in the buffer region may be at most 10 19 cm -3 or up to 10 18 cm -3 Also in this case, the buffer region can be defined by a region that satisfies the minimum doping concentration condition everywhere or satisfies the average concentration condition.

[0034] The buffer region may be a buffer layer extending continuously over the entire lateral extent of the second semiconductor layer, eg without interruption.

[0035] The C-rich region may cause strains in the crystal lattice. The buffer region may compensate for these strains, for example, and may improve the growth conditions for the rest of the second semiconductor layer.

[0036] According to another embodiment, a plurality of C-rich regions are formed in the first semiconductor layer, which are laterally spaced apart from each other. In the step of introducing carbon into the first semiconductor layer, for example by C ion implantation, a plurality of C-rich regions are formed. The C-rich regions of the first semiconductor layer may all be arranged at the same height relative to the main extension plane of the first semiconductor layer. That is, a plane parallel to the main extension plane of the first semiconductor layer intersects each C-rich region in the first semiconductor layer.

[0037] For example, the lateral extension of each C-rich region is at most 2 μm or at most 1 μm and / or at least 0.5 μm. For example, the distance between each two adjacent C-rich regions measured in the lateral direction is at most 5 μm or at most 2 μm and / or at least 0.5 μm. The C-rich regions can be arranged on the grid points of a regular grid. For example, when viewed in a plan view of the side of the first semiconductor layer on which the second semiconductor layer is grown, each C-rich region is a rectangular region or a circular region. Alternatively, the C-rich regions of the first semiconductor layer can be formed as strips, for example, the strips extend parallel to each other.

[0038] Forming the plurality of C-rich regions may be accomplished by using a mask, for example, during a C ion implantation process.

[0039] According to another embodiment, the method includes the step of introducing carbon into the second semiconductor layer so that at least a portion of the second semiconductor layer becomes at least one C-rich region. All features disclosed in connection with at least one C-rich region of the first semiconductor layer are also disclosed for at least one C-rich region of the second semiconductor layer. For example, the (one or more) C-rich regions in the second semiconductor layer can be formed using the same method as used to form the C-rich region in the first semiconductor layer, such as PIII.

[0040] According to another embodiment, the method comprises the step of growing a third semiconductor layer of SiC on the second semiconductor layer. For example, the third semiconductor layer is epitaxially grown. All features disclosed in relation to the second semiconductor layer are also disclosed for the third semiconductor layer, in particular with regard to doping and thickness.

[0041] According to another embodiment, a plurality of C-rich regions laterally spaced apart from each other are formed in the second semiconductor layer. Features disclosed in relation to the plurality of C-rich regions in the first semiconductor layer are also disclosed for the plurality of C-rich regions of the second semiconductor layer.

[0042] According to a further embodiment, the C-rich regions in the first semiconductor layer and the C-rich regions in the second semiconductor layer are arranged in a staggered configuration. This means in particular that the C-rich regions of the first semiconductor layer at most partially overlap with the C-rich regions of the second semiconductor layer in at least one lateral direction. For example, the C-rich regions of the first semiconductor layer do not overlap with the C-rich regions of the second semiconductor layer in at least one lateral direction. The C-rich regions of the first semiconductor layer are arranged at a different height than the C-rich regions of the first semiconductor layer relative to a main extension plane of the first semiconductor layer and do not overlap each other, for example, in a vertical direction.

[0043] Next, a semiconductor body is described. In particular, the semiconductor body can be manufactured using a method according to any of the embodiments described herein. Therefore, all features disclosed in relation to the method are also disclosed for the semiconductor body, and vice versa.

[0044] According to one embodiment, the semiconductor body comprises a first semiconductor layer of SiC, a second semiconductor layer of SiC on the first semiconductor layer, and at least one C-rich region in the first semiconductor layer. The C-rich region is adjacent to the second semiconductor layer. In the C-rich region, the minimum and / or average concentration of C atoms or C ions at interstitial sites is at least 10 17 cm -3 The thickness of the C-rich region is at most 100 nm or at most 50 nm or at most 30 nm and / or at least 10 nm or at least 15 nm. Thereby, the thickness is measured along a main extension plane perpendicular to the first semiconductor layer.

[0045] According to another embodiment, the C-rich region has its maximum concentration of C atoms or C ions at interstitial sites located at the interface of the second semiconductor layer. For example, the concentration distribution in the vertical direction perpendicular to the main extension plane of the first semiconductor layer is asymmetric with respect to the interface between the first and second semiconductor layers. For example, in the first semiconductor layer, along the vertical direction, the distance measured from the interface where the concentration drops to less than 0.01 times the maximum concentration is at least two orders of magnitude or at least three orders of magnitude greater than in the second semiconductor layer. For example, the aforementioned distance in the first semiconductor layer is at least 5nm or at least 10nm and / or at most 30nm or at most 25nm. The maximum concentration of C atoms / C ions at interstitial sites in the C-rich region can be at least 10 19 cm -3 and / or up to 10 21 cm -3 .

[0046] The minimum and / or average concentration of C atoms / C ions at interstitial sites in the C-rich region is at least 10 18 cm -3 The thickness of the portion may be at most 30 nm or at most 25 nm and / or at least 5 nm or at least 10 nm. The minimum and / or average concentration of C atoms / C ions at interstitial sites in the C-rich region is at least 10 19 cm -3 The thickness of the portion may be at most 20 nm and at least 10 nm.

[0047] According to another embodiment, the maximum and / or average concentration of carbon vacancies (C vacancies for short) in the second semiconductor layer is at most 10 12 cm -3 or up to 10 11 cm -3 This refers especially to Z 1 / 2 Vacant seat.

[0048] According to another embodiment, at room temperature, the average mobility of the charge carriers and the second semiconductor layer is at least 100 cm 2 / Vs or at least 120cm 2 / Vs or at least 150cm 2 / Vs.

[0049] The specified C vacancy concentration and the specified mobility in the second semiconductor layer apply equally to the first semiconductor layer. In case a third semiconductor layer is grown on the second semiconductor layer, these values ​​may additionally or alternatively hold for the third semiconductor layer.

[0050] Next, a power semiconductor device will be described.

[0051] The power semiconductor device comprises a semiconductor body according to any one of the embodiments described herein. In addition, the power semiconductor device comprises an electrode in electrical contact with the semiconductor body. The electrode can be metal and / or highly doped polysilicon. For example, the power semiconductor device is a transistor, such as a MOSFET or an IGBT, or a thyristor.

[0052] In the following, a method for manufacturing a semiconductor body, a semiconductor body, and a power semiconductor device will be explained in more detail with reference to the accompanying drawings based on exemplary embodiments. The accompanying drawings are included to provide further understanding. In the accompanying drawings, elements of the same structure and / or function may be represented by the same reference numerals. It should be understood that the embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale. As long as the functions of the elements or components in different figures correspond to each other, their descriptions are not repeated for each of the following figures. For clarity, the elements may not appear with corresponding reference numerals in all figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figures 1 to 8 shows different locations in a first exemplary embodiment of a method, different exemplary embodiments of a semiconductor body, and exemplary embodiments of a power semiconductor device,

[0054] Fig. 9 shows the DLTS measurement curve,

[0055] Fig.10 shows the concentration profile of C atoms or C ions at interstitial sites in the C-rich region generated with PIII,

[0056] Fig.11 shows the concentration profile of C atoms at interstitial sites in a C-rich region created with deep ion implantation,

[0057] Figure 12 to Figure 14 shows different locations in a second exemplary embodiment of a method, as well as an exemplary embodiment of a semiconductor body and an exemplary embodiment of a power semiconductor device,

[0058] Figures 15 to 18shows different locations in a third exemplary embodiment of a method and further exemplary embodiments of a semiconductor body,

[0059] Fig.19 A further exemplary embodiment of a semiconductor body is shown. DETAILED DESCRIPTION

[0060] exist Figure 1 A substrate 4 is provided at a position, for example, an n-type doped 4H-SiC substrate 4. The substrate 4 may be a standard 4° off substrate.

[0061] exist Figure 2 A first semiconductor layer of SiC, such as 4H-SiC, is epitaxially grown on the substrate 4 at a position. The growth can be performed by chemical vapor deposition (CVD), such as hot wall chemical vapor deposition (HWCVD). For example, the first semiconductor layer 1 grows to a thickness of about 10 μm. During the growth process, the first semiconductor layer 1 can be doped with a second type dopant, in which case the second type dopant is an n-type dopant.

[0062] exist Figure 3 The growth process is interrupted at the position of the first semiconductor layer 1, and carbon is introduced into the first semiconductor layer 1, whereby a portion of the first semiconductor layer becomes a C-rich region 11. In the C-rich region 11, C atoms or C ions are gathered at interstitial sites. The C-rich region 11 is formed only in the region of the exposed surface of the first semiconductor layer 1, i.e., at a very low depth, so that the C-rich region 11 does not extend over the entire thickness of the first semiconductor layer 1. For example, this is achieved by implanting C ions using plasma ion immersion implantation (PIII). This implantation technique does allow the formation of very shallow and well-defined implantation regions.

[0063] exist Figure 3 In the embodiment, the C-rich region 11 extends continuously over the entire exposed surface of the first semiconductor layer 1 .

[0064] exist Figure 4 The second semiconductor layer 2 is grown on the first semiconductor layer 1 (i.e., directly on the C-rich region 11) until a semiconductor layer sequence of the desired thickness is obtained. The second semiconductor layer 2 is also SiC, for example 4H-SiC. The growth of the second semiconductor layer 2 can be carried out in the same way as the first semiconductor layer 1. In addition, during the growth process, the second semiconductor layer 2 can be doped with n-type.

[0065] exist Figure 5An implantation process is performed at a position where a second type dopant, i.e., an n-type dopant, is implanted into the second semiconductor layer 2, thereby forming a buffer region 20 adjacent to the C-rich region 11. The average doping concentration of the buffer region 20 is higher than that of the rest of the first semiconductor layer 1 or the second semiconductor layer 2. This buffer region 20 compensates for the strain caused by carbon in the C-rich region 11.

[0066] and Figure 5 In contrast, the buffer region 20 can be produced during the growth of the second semiconductor layer 2 .

[0067] exist Figure 6 At the position of , a further implantation process is performed, in which a first type of dopant (in this case a p-type dopant) is implanted. Here, a so-called p-well is formed in the second semiconductor layer 2.

[0068] exist Figure 7 The semiconductor body 10 is heated to a temperature in the range of 1500° C. to 1700° C. to activate the first type dopant previously implanted. During this period, the C atoms or C ions in the C-rich region 11 at the interstitial site are partially released and fill the carbon vacancies in the semiconductor body 10.

[0069] exist Figure 8 , the final power semiconductor device 100 in the form of a MOSFET is shown. This device 100 has been produced by further implanting second type dopants into the p-well to produce contact regions, and applying main electrodes 5, 6 and a gate electrode 7 to the semiconductor body 10.

[0070] exist Fig. 9 The position of the deep level transient spectrum (DLTS) signal of different semiconductor bodies varies with temperature. Curve S9_1 shows the case of a SiC semiconductor body without applying measures to reduce carbon vacancies. Curve S9_1 shows the indication Z 1 / 2 The prominent peak of vacancies. Curve S9_2 shows the situation of the semiconductor body after oxidation treatment. The carbon vacancies disappear. Curve S9_3 shows the result obtained when the semiconductor body 10 is manufactured as described above (i.e., the C-rich region 11 is formed by PIII). In this case as well, the carbon vacancies also disappear.

[0071] Fig.10The concentration of C atoms / C ions at interstitial sites in the C-rich region 11 produced in the SiC layer by using PIII is shown as a function of depth, i.e., a function of the distance from the surface of the SiC layer into which carbon is implanted. Curve S10_1 shows the concentration of C atoms / C ions at interstitial sites before heating to a temperature between 1500°C and 1700°C, and curve S10_2 shows the concentration after heating. Due to heating, some C atoms / C ions at interstitial sites recombine with C vacancies, thereby reducing the concentration of C atoms / C ions at interstitial sites. It can be seen that the PIII technology produces a very shallow and sharply decreasing concentration profile, with the maximum concentration occurring at the surface of the SiC layer where the carbon of the SiC layer enters the SiC layer.

[0072] As a comparison, Fig.11 shows the concentration of C atoms / C ions at interstitial sites when a C-rich region is formed by deep ion implantation using much higher ion energy than PIII. In this case, the maximum value of the concentration is within the SiC layer. This region is larger than Fig.10 Thicker and less steeply distributed.

[0073] Fig.12 The position in a second exemplary embodiment of the method is shown. In this position, several laterally spaced apart C-rich regions 11 are formed at the exposed surface of the first semiconductor layer 1. For example, such a pattern of C-rich regions 11 can be obtained by using a mask on the first semiconductor layer 1 during carbon implantation. Fig.12 The mask is not shown.

[0074] exist Fig.13 position, and then the second semiconductor layer 2 is grown again on the first semiconductor layer 1.

[0075] Fig.14 Shows the use of Fig.12 and 13 The described method relates to an exemplary embodiment of manufacturing a final power semiconductor device 100. Also in this case, the power semiconductor device 100 is a power MOSFET.

[0076] Fig.15 The position in a third exemplary embodiment of the method is shown, which is similar to Fig.12 The same position.

[0077] exist Fig.16 In the embodiment, the second semiconductor layer 2 is grown on the first semiconductor layer 1 .

[0078] exist Fig.17In the process, carbon is introduced into the second semiconductor layer 2, for example again by PIII, so that laterally spaced apart C-rich regions 22 are formed in the second semiconductor layer 2. Here too, a mask not shown can be used to obtain such a C-rich region pattern.

[0079] like Fig.17 As shown, the C-rich regions 22 of the second semiconductor layer 2 and the C-rich regions 11 of the first semiconductor layer 1 are in a staggered arrangement, wherein the regions 11 do not overlap with the regions 22 in the lateral direction.

[0080] Fig.18 The position where the third semiconductor layer 3 is grown on the second semiconductor layer 2 is shown. The third semiconductor layer 3 is also made of SiC and can be grown in the same way as the first and second semiconductor layers 2.

[0081] Fig.19 Another exemplary embodiment of a semiconductor body 10 is shown, which is similar to Fig.18 However, in this case, the region 22 of the second semiconductor layer 2 and the region 11 of the first semiconductor layer 1 are closer to each other in the vertical direction.

[0082] like Figures 1 to 19 The embodiments shown represent exemplary embodiments; therefore, they do not constitute a complete list of all embodiments according to the improved method, the improved semiconductor body, and the improved power semiconductor device. For example, the actual method, the semiconductor body, and the power semiconductor device may differ from the embodiments shown in terms of arrangement, components, and layer thickness.

[0083] Reference mark

[0084] 1First semiconductor layer

[0085] 2 Second semiconductor layer

[0086] 3Third semiconductor layer

[0087] 4 Substrate

[0088] 5 Main electrode

[0089] 6 Main electrode

[0090] 7 Gate electrode

[0091] 10Semiconductor body

[0092] 11 C-rich region

[0093] 20 Buffer area

[0094] 21 C-rich area

[0095] 100 Power semiconductor devices

[0096] S9_1 to S9_3 curves

[0097] S10_1, S10_2 curves

Claims

1. A method for manufacturing a semiconductor body (10), comprising: Providing a first semiconductor layer (1) of SiC; Introducing carbon into the first semiconductor layer (1) so that at least a portion of the first semiconductor layer becomes at least one C-rich region (11); A second semiconductor layer (2) of SiC is grown on the first semiconductor layer (1) including the at least one C-rich region (11).

2. The method according to claim 1, wherein: The C-rich region (11) is formed on the exposed side of the first semiconductor layer (1), so that after the second semiconductor layer (2) is grown, the C-rich region (11) is located between the remaining portion of the first semiconductor layer (1) that has not become C-rich and the second semiconductor layer (2).

3. The method according to claim 1 or 2, wherein: Carbon is introduced into the first semiconductor layer using plasma ion immersion implantation.

4. The method according to any one of the preceding claims, further comprising: A first type dopant is implanted into a semiconductor layer sequence, the semiconductor layer sequence comprising the first semiconductor layer (1) and the second semiconductor layer (2).

5. The method according to claim 4, further comprising: The first type dopant is activated at a temperature of at least 1500°C.

6. A method according to claim 3 or any one of claims 4 and 5 as appended to claim 3, wherein: The implantation is performed using a C ion energy in the range of 1 KeV to 50 KeV, including 1 KeV and 50 KeV, wherein the average concentration of C atoms or C ions at interstitial sites in the C-rich region (11) is at least 10 14 cm -3 .

7. A method according to any one of the preceding claims, wherein: At least one buffer region (20) of the second semiconductor layer (2) is adjacent to the C-rich region (11) and is doped with a second type dopant, wherein an average concentration of the second type dopant in the buffer region (20) is greater than an average concentration of the second type dopant in the first semiconductor layer (1).

8. A method according to any one of the preceding claims, wherein: A plurality of C-rich regions (11) are formed in the first semiconductor layer (1) and are laterally spaced apart from each other.

9. The method according to any one of the preceding claims, further comprising: Introducing carbon into the second semiconductor layer (2) so that at least a portion of the second semiconductor layer (2) becomes at least one C-rich region (21); A third semiconductor layer (3) of SiC is grown on the second semiconductor layer (2).

10. A method according to claim 9 as appended to claim 8, wherein: forming a plurality of C-rich regions (21) laterally spaced apart from each other in the second semiconductor layer (2); The C-rich regions (11) in the first semiconductor layer (1) and the C-rich regions (21) in the second semiconductor layer (2) are arranged in a staggered configuration.

11. A semiconductor body (10), comprising: A first semiconductor layer (1) of SiC; A second semiconductor layer (2) of SiC on the first semiconductor layer (1); At least one C-rich region (11) in the first semiconductor layer (1), wherein The at least one C-rich region (11) is adjacent to the second semiconductor layer (2), In the C-rich region (11), the average concentration of C atoms or C ions at interstitial sites is at least 10 17 cm -3 , The thickness of the C-rich region (11) is at most 100 nm.

12. The semiconductor body (10) as claimed in claim 11, wherein: The at least one C-rich region (11) has its maximum concentration of C atoms or C ions at interstitial sites at the interface with the second semiconductor layer (2).

13. The semiconductor body (10) as claimed in claim 11 or 12, wherein: The average concentration of C vacancies in the second semiconductor layer (2) is at most 10 12 cm -3 .

14. The semiconductor body (10) according to any one of claims 11 to 13, wherein: At room temperature, the average mobility of charge carriers in the second semiconductor layer (2) is at least 100 cm 2 / Vs.

15. A power semiconductor device (100), comprising: A semiconductor body (10) according to any one of claims 11 to 14, and an electrode (5, 6, 7) which is in electrical contact with the semiconductor body (10).

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