Reducing parasitic capacitance in differential cascode amplifiers

Abstract

An apparatus for reducing parasitic capacitance is disclosed. In an example aspect, an apparatus includes an amplifier having a differential cascode configuration. Each stack of the amplifiers includes a first transistor configured to operate as an input stage and a second transistor configured to operate as a cascode stage. The first transistor and the second transistor each include two channel terminal regions having a uniform doping type across the two channel terminal regions. The surfaces of the first channel terminal regions of the first and second transistors abut a first number of electrical contacts and a second number of electrical contacts, respectively. Second channel terminal regions of the first transistor and the second transistor form a floating region at a floating node. Each of the first number of electrical contacts and the second number of electrical contacts is larger than a third number of electrical contacts adjoining a surface of the floating region.

Description

Technical Field

[0001] The present disclosure relates generally to wireless transceivers and other components that employ amplifiers, and more particularly to reducing parasitic capacitance within amplifiers. Background Art

[0002] In order to increase transmission rates and throughput, cellular networks and other wireless networks are using signals with higher frequencies and smaller wavelengths. For example, devices with 5th generation (5G) capabilities or devices with next-generation wireless local area network (WLAN) capabilities use frequencies including frequencies at or near the extremely high frequency (EHF) spectrum (e.g., frequencies greater than 24 gigahertz (GHz)) to communicate with the network at wavelengths at or near millimeter wavelengths (mmW). However, these signals bring various technical challenges, such as higher path losses than signals used for earlier generations of wireless communications. In some scenarios, mmW wireless signals may have difficulty traveling far enough to make cellular communications or WLAN communications feasible at these higher frequencies. Summary of the invention

[0003] A device for reducing parasitic capacitance is disclosed. In an example aspect, an amplifier with a differential cascode configuration has an input stage and a cascode stage coupled together at a floating node. Channel terminal regions of the input stage and the cascode stage form a floating region at the floating node. In order to manage the parasitic capacitance between the gate terminal of the input stage and the floating region, a small amount (if any) of electrical contacts are deposited on the surface of the floating region. In this way, a smaller amount of electrical contacts are adjacent to the floating region than other channel terminal regions of the input stage and the cascode stage. By having fewer electrical contacts in the floating region, the parasitic capacitance of the amplifier can be less than other amplifier designs having a larger amount of electrical contacts in the floating region. In addition, the amplifier can occupy a smaller area than other amplifier designs using capacitors.

[0004] In an example aspect, a device for amplification is disclosed. The device includes an amplifier having a differential cascode configuration. The amplifier includes at least two stacks. Each of the at least two stacks includes a first transistor and a second transistor. The first transistor is configured to operate as an input stage of the amplifier. The second transistor is coupled to the first transistor at a floating node and is configured to operate as a cascode stage of the amplifier. The first transistor and the second transistor each include two channel terminal regions, and the two channel terminal regions have a uniform doping type across the two channel terminal regions. The two channel terminal regions include a first channel terminal region and a second channel terminal region. The surface of the first channel terminal region of the first transistor is adjacent to a first number of electrical contacts. The surface of the first channel terminal region of the second transistor is adjacent to a second number of electrical contacts. The second channel terminal regions of the first transistor and the second transistor form a floating region at a floating node. Each of the first number of electrical contacts and the second number of electrical contacts is greater than a third number of electrical contacts adjacent to the surface of the floating region.

[0005] In an example aspect, a device for amplification is disclosed. The device includes a component for amplifying a differential signal using a differential cascode configuration. The component for amplification includes an input stage and a cascode stage, which is coupled to the input stage at a floating node. The input stage and the cascode stage each include two channel terminal regions, and the two channel terminal regions have a uniform doping type across the two channel terminal regions. One of the two channel terminal regions of the input stage and one of the two channel terminal regions of the cascode stage form a floating region at a floating node. The device also includes a component for setting a parasitic capacitance between a gate terminal of the input stage and the one of the two channel terminal regions of the input stage based on the number of electrical contacts adjacent to the surface of the floating region.

[0006] In an example aspect, a device for amplification is disclosed. The device includes an amplifier having a differential cascode configuration. The amplifier includes at least two stacks. Each of the at least two stacks includes a first transistor and a second transistor. The first transistor is configured to operate as an input stage of the amplifier. The second transistor is coupled to the first transistor at a floating node and is configured to operate as a cascode stage of the amplifier. The first transistor and the second transistor each include two channel terminal regions, and the two channel terminal regions have a uniform doping type across the two channel terminal regions. The two channel terminal regions include a first channel terminal region and a second channel terminal region. The second channel terminal regions of the first transistor and the second transistor form a floating region at a floating node. The floating region includes a region without electrical contacts.

[0007] In an example aspect, a device is disclosed. The device includes an amplifier having a differential cascode configuration. The amplifier includes at least two stacks. Each stack of the at least two stacks includes a first transistor and a second transistor. The first transistor is configured to operate as an input stage of the amplifier. The second transistor is coupled to the first transistor at a floating node and is configured to operate as a cascode stage of the amplifier. The amplifier also includes a first capacitor and a second capacitor. The first capacitor is coupled between the gate of the first transistor of the first stack of the at least two stacks and the floating node of the second stack of the at least two stacks. The second capacitor is coupled between the gate of the first transistor of the second stack and the floating region of the first stack. The first transistor and the second transistor each include two channel terminal regions, and the two channel terminal regions have a uniform doping type across the two channel terminal regions. The two channel terminal regions include a first channel terminal region and a second channel terminal region. The surface of the second channel terminal region of the first transistor and the second transistor forms a floating region at the floating node. Each of the number of electrical contacts adjacent to the first channel terminal region of the first transistor and the number of electrical contacts adjacent to the first channel terminal region of the second transistor is greater than the number of electrical contacts adjacent to the surface of the floating region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An example operating environment for reducing parasitic capacitance is illustrated.

[0009] Figure 2 An example wireless transceiver including at least one amplifier that reduces parasitic capacitance is illustrated.

[0010] Figure 3 Example components of an amplifier that reduces parasitic capacitance are illustrated.

[0011] Figure 4 An example assembly of a transistor is illustrated.

[0012] Figure 5 Example implementations of amplifiers that reduce parasitic capacitance are illustrated.

[0013] Figure 6 Another example implementation of an amplifier that reduces parasitic capacitance is illustrated.

[0014] Figure 7 An example layout of a stack in a stack of amplifiers that reduces parasitic capacitance is illustrated.

[0015] Figure 8 Yet another example implementation of an amplifier that reduces parasitic capacitance is illustrated.

[0016] Fig. 9 An example layout of an amplifier that reduces parasitic capacitance is illustrated.

[0017] Fig.10 An example vertical layout of an amplifier to reduce parasitic capacitance is illustrated. DETAILED DESCRIPTION

[0018] Cellular networks and other wireless networks can use signals with higher frequencies and smaller wavelengths to increase transmission rates and throughput. However, signals within the extremely high frequency (EHF) spectrum (e.g., frequencies greater than 24 gigahertz (GHz)) with wavelengths at or near millimeter wavelengths experience higher path losses than signals at lower frequency ranges. As a result, mmW wireless signals may have difficulty traveling far enough to make cellular or WLAN communications feasible at these higher frequencies.

[0019] Electronic devices may employ amplifiers to amplify transmitted or received signals. The performance of an amplifier depends on several factors, including the amount of parasitic capacitance present within the amplifier. Parasitic capacitance refers to the unwanted capacitive effect that forms between two parts that are close to each other and have different voltages. Within an amplifier, parasitic capacitance can degrade output power, gain, efficiency, linearity, and / or stability, especially at frequencies within the very high frequency spectrum.

[0020] Some techniques connect a neutralizing capacitor to the transistors within the amplifier to reduce the amount of parasitic capacitance associated with the transistors. However, the neutralizing capacitor may increase the footprint of the amplifier. Reducing parasitic capacitance while keeping the amplifier footprint small enough to fit within a space-constrained device, such as a portable electronic device like a smartphone or wearable device, may be challenging. Furthermore, amplifiers with larger footprints result in larger integrated circuits that are more expensive.

[0021] To address this challenge, an example technique for reducing parasitic capacitance is described. In an example aspect, an amplifier with a differential cascode configuration has an input stage and a cascode stage coupled together at a floating node. The channel terminal regions of the input stage and the cascode stage form a floating region at the floating node. In order to manage the parasitic capacitance between the gate terminal of the input stage and the floating region, a small amount (if any) of electrical contacts are deposited on the surface of the floating region. In this way, a smaller amount of electrical contacts adjoins the floating region compared to other channel terminal regions of the input stage and the cascode stage. By having fewer electrical contacts in the floating region, the parasitic capacitance of the amplifier can be less than other amplifier designs having a larger amount of electrical contacts in the floating region. In addition, the amplifier can occupy a smaller area than other amplifier designs using capacitors.

[0022] Figure 1An example environment 100 for operating an amplifier with reduced parasitic capacitance is illustrated. In the environment 100, a computing device 102 communicates with a base station 104 via a wireless communication link 106 (wireless link 106). In this example, the computing device 102 is depicted as a smart phone. However, the computing device 102 can be implemented as any suitable computing or electronic device, such as a modem, a cellular base station, a broadband router, an access point, a cellular phone, a gaming device, a navigation device, a media device, a laptop computer, a desktop computer, a tablet computer, a wearable computer, a server, a network attached storage (NAS) device, a smart appliance or other Internet of Things (IoT) device, a medical device, a vehicle-based communication system, a radar, a radio, and the like.

[0023] Base station 104 communicates with computing device 102 via wireless link 106, which may be implemented as any suitable type of wireless link. Although depicted as a cellular network tower, base station 104 may represent or be implemented as another device, such as a satellite, a server device, a terrestrial television broadcast tower, an access point, a peer device, a mesh network node, etc. Thus, computing device 102 may communicate with base station 104 or another device via a wireless connection.

[0024] Wireless link 106 may include a downlink of data or control information communicated from base station 104 to computing device 102, an uplink of other data or control information communicated from computing device 102 to base station 104, or both. Wireless link 106 may be implemented using any suitable communication protocol or standard, such as 2nd generation (2G), 3rd generation (3G), 4th generation (4G), or 5th generation (5G) cellular; IEEE 802.11 (e.g., ); IEEE 802.15 (e.g., ); IEEE 802.16 (e.g., ); and so on. In some implementations, wireless link 106 can provide power wirelessly, and base station 104 or computing device 102 can include a power source.

[0025] As shown, computing device 102 includes an application processor 108 and a computer-readable storage medium 110 (CRM 110). Application processor 108 may include any type of processor, such as a multi-core processor, that executes processor executable code stored by CRM 110. CRM 110 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media, magnetic media (e.g., disk), etc. In the context of the present disclosure, CRM 110 is implemented to store instructions 112, data 114, and other information for computing device 102, and therefore does not include transient propagating signals or carrier waves.

[0026] The computing device 102 may also include input / output ports 116 (I / O ports 116) and a display 118. The I / O ports 116 enable data exchange or interaction with other devices, networks, or users. The I / O ports 116 may include serial ports (e.g., universal serial bus (USB) ports), parallel ports, audio ports, infrared (IR) ports, user interface ports such as a touch screen, and the like. The display 118 presents graphics of the computing device 102, such as a user interface associated with an operating system, program, or application. Alternatively or additionally, the display 118 may be implemented as a display port or a virtual interface through which the graphical content of the computing device 102 is presented.

[0027] The wireless transceiver 120 of the computing device 102 provides connectivity to a corresponding network and other electronic devices connected thereto. The wireless transceiver 120 may facilitate communication over any suitable type of wireless network, such as a wireless local area network (WLAN), a peer-to-peer (P2P) network, a mesh network, a cellular network, an ultra-wideband (UWB) network, a wireless wide area network (WWAN), and / or a wireless personal area network (WPAN). In the context of the example environment 100, the wireless transceiver 120 enables the computing device 102 to communicate with the base station 104 and the network connected thereto. However, the wireless transceiver 120 may also enable the computing device 102 to communicate "directly" with other devices or networks.

[0028] The wireless transceiver 120 includes circuits and logic for sending and receiving communication signals via the antenna 122. The components of the wireless transceiver 120 may include amplifiers, switches, mixers, analog-to-digital converters, filters, etc. for conditioning communication signals (e.g., for generating or processing signals). The wireless transceiver 120 may also include logic for performing in-phase / quadrature (I / Q) operations such as synthesis, encoding, modulation, decoding, demodulation, etc. In some cases, the components of the wireless transceiver 120 are implemented as separate transmitter and receiver entities. Additionally or alternatively, the wireless transceiver 120 may be implemented using multiple or different parts to implement corresponding transmission and reception operations (e.g., separate transmission chains and reception chains). In general, the wireless transceiver 120 processes data and / or signals associated with data communicated to the computing device 102 via the antenna 122.

[0029] exist Figure 1 In the example shown, the wireless transceiver 120 includes at least one amplifier 124. The amplifier 124 can implement various aspects of reducing parasitic capacitance, which refers to the action, condition / state, or configuration of reducing and / or canceling parasitic capacitance to a measurable level (such as a sufficient amount) so that target performance is achieved. For example, by reducing parasitic capacitance, the amplifier 124 can achieve a target output power, target gain, target efficiency, target linearity, and / or target stability for wireless applications, including wireless applications that utilize frequencies within the very high frequency spectrum. Figure 2 Amplifier 124 is further described.

[0030] Figure 2 An example wireless transceiver 120 is illustrated. In the depicted configuration, the wireless transceiver 120 includes a transmitter 202 and a receiver 204, which are coupled to a first antenna 122-1 and a second antenna 122-2, respectively. In other specific implementations, the transmitter 202 and the receiver 204 can be connected to the same antenna through a duplexer (not shown) or some other interface (e.g., a time division duplex (TDD) system such as many millimeter wave systems). The transmitter 202 is shown as including at least one digital-to-analog converter 206 (DAC 206), at least one first mixer 208-1, and at least one amplifier 124 (e.g., a power amplifier). The receiver 204 includes at least one amplifier 210 (e.g., a low noise amplifier), at least one second mixer 208-2, and at least one analog-to-digital converter 212 (ADC 212). The first mixer 208-1 and the second mixer 208-2 are coupled to a local oscillator 214. Although not explicitly shown, the digital-to-analog converter 206 of the transmitter 202 and the analog-to-digital converter 212 of the receiver 204 may be coupled to ( Figure 1 ) application processor 108 or another processor associated with the wireless transceiver 120 (e.g., a modem).

[0031] In some implementations, wireless transceiver 120 is implemented using multiple circuits (e.g., multiple integrated circuits) such as transceiver circuit 216 and radio frequency front end (RFFE) circuit 218. Thus, the components that form transmitter 202 and receiver 204 are distributed across these circuits. Figure 2 As shown, the transceiver circuit 216 includes the digital-to-analog converter 206 of the transmitter 202, the mixer 208-1 of the transmitter 202, the mixer 208-2 of the receiver 204, and the analog-to-digital converter 212 of the receiver 204. In other specific implementations, the digital-to-analog converter 206 and the analog-to-digital converter 212 can be implemented on another separate circuit including the application processor 108 or the modem. The RF front-end circuit 218 includes the amplifier 124 of the transmitter 202 and the amplifier 210 of the receiver 204.

[0032] During transmission, the transmitter 202 generates a radio frequency transmit signal 220 that is transmitted using the antenna 122-1. To generate the radio frequency transmit signal 220, the digital-to-analog converter 206 provides the transmit signal 222 to the first mixer 208-1. The transmit signal 222 may be a baseband signal or an intermediate frequency signal. The first mixer 208-1 uses a local oscillator (LO) signal 224 provided by the local oscillator 214 to up-convert the transmit signal 222. The first mixer 208-1 generates an up-converted version of the transmit signal 222, which may be a radio frequency signal. The amplifier 124 amplifies the up-converted transmit signal 222 and passes the amplified transmit signal 226 to the antenna 122-1 for transmission. The transmitted amplified transmit signal 226 is represented by the radio frequency transmit signal 220.

[0033] During reception, the antenna 122-2 receives the RF receive signal 228 and passes the RF receive signal 228 to the receiver 204. The amplifier 210 of the receiver 204 amplifies the RF receive signal 228 and passes the amplified receive signal 230 to the second mixer 208-2. The second mixer 208-2 down-converts the amplified receive signal 230 using the local oscillator signal 224. The analog-to-digital converter 212 converts the down-converted amplified receive signal 230 into a digital signal that can be processed by the application processor 108 or another processor associated with the wireless transceiver 120 (e.g., a modem).

[0034] In the depicted configuration, amplifier 124 implements a power amplifier within transmitter 202. However, amplifier 124 is not limited to a specific implementation associated with a power amplifier. In general, amplifier 124 may implement other types of amplifiers within RF front end circuitry 218 and / or transceiver circuitry 216. For example, amplifier 124 may implement a low noise amplifier within receiver 204. Additionally or alternatively, amplifier 124 may implement another amplifier within transmitter 202 or receiver 204, such as a variable gain amplifier.

[0035] Figure 2 One example configuration of the wireless transceiver 120 is illustrated. Other configurations of the wireless transceiver 120 may support multiple frequency bands and share the antenna 122 across multiple transceivers. A person of ordinary skill in the art may appreciate various other configurations that may include the amplifier 124. For example, the amplifier 124 may be implemented within a wireless transceiver 120 having a superheterodyne architecture or a direct conversion architecture (or a zero intermediate frequency architecture). In some aspects, the amplifier 124 may be integrated within an active phase shifter of the wireless transceiver 120. The amplifier 124 may have a differential cascode configuration that is about Figure 3 Further description.

[0036] Figure 3 An example assembly of an amplifier 124 having a differential cascode configuration 302 is illustrated. Specifically, the amplifier 124 includes at least two stacks (or at least a pair of stacks), which are represented by a first stack 304 and a second stack 306. Each stack 304 and 306 represents an amplification branch of the amplifier 124. The two stacks 304 and 306 enable the amplifier 124 to accept a differential input signal (e.g., two complementary input signals or two input signals with opposite polarities) and generate a differential output signal (e.g., two complementary output signals or two output signals with opposite polarities). The differential output signal is amplified relative to the differential input signal.

[0037] Each stack 304 and 306 includes an input stage 308 and a cascode stage 310, which are coupled together at a floating node 312. The floating node 312 has a floating potential (e.g., a floating voltage) because the floating node 312 is not directly connected to ground or a fixed voltage (such as a supply voltage). Therefore, the voltage at the floating node 312 can change during operation of the amplifier 124. The floating node 312 can also be referred to as an internal node. As an internal node, the floating node 312 is not connected to any component of the wireless transceiver 120 or a voltage source external to the amplifier 124. In this way, the floating node 312 is different from the input node 502 and the output node 506 connected to other components of the wireless transceiver 120.

[0038] For each stack 304 or 306, the input stage 308 may be implemented using at least one transistor 314, and the cascode stage 310 may be implemented using at least one other transistor 316. In an example implementation, the transistor 314 is configured as a common source amplifier 318 (CS amplifier 318), and the transistor 316 is configured as a common gate amplifier 320 (CG amplifier 320). The transistors 314 and 316 may be implemented using an n-channel metal oxide semiconductor field effect transistor (NMOSFET), a p-channel metal oxide semiconductor field effect transistor (PMOSFET), an extended drain NMOSFET (ED-NMOSFET), a super low threshold voltage NMOSFET (SLVT-NMOSFET), a bipolar junction transistor (BJT), another type of transistor, or a combination thereof.

[0039] In an example implementation, transistors 314 and 316 within each stack 304 and 306 are symmetrical 322. This means that transistor 314 of input stage 308 and transistor 316 of cascode stage 310 are transistors of the same type. For example, both transistors 314 and 316 can be implemented using NMOSFETs. In another example implementation, transistors 314 and 316 within each stack 304 and 306 are asymmetrical 324. This means that transistor 314 of input stage 308 and transistor 316 of cascode stage 310 are transistors of different types (e.g., different types of NMOSFETs). For example, transistor 314 can be implemented using SLVT-NMOSFETs, and transistor 316 can be implemented using ED-NMOSFETs.

[0040] The transistor 314 of the input stage 308 has a parasitic capacitance 326. To at least partially reduce this parasitic capacitance 326, a small number (if any) of electrical contacts may be provided at the surface of the floating region associated with the floating node 312, as described with respect to FIG. Figure 4 and Figure 5 In some implementations, significantly reducing or eliminating electrical contacts disposed on the surface of the floating region can reduce parasitic capacitance 326 by as much as 60%.

[0041] Optionally, amplifier 124 may include two or more capacitors 328 (or neutralizing capacitors) to further reduce at least a portion of parasitic capacitance 326. Capacitor 328 is coupled between stacks 304 and 306, as described with respect to FIG. Figure 8 and Fig. 9As further described herein. The capacitance of capacitor 328 may be appropriately set to at least partially reduce parasitic capacitance 326. To avoid increasing the footprint of amplifier 124, capacitor 328 may be integrated within the layout of stacks 304 and 306. In other words, capacitor 328 may be formed using metal interconnect layers associated with stacks 304 and 306. By not using a different external capacitor, capacitor 328 may provide additional parasitic capacitance reduction capability without significantly increasing the footprint of amplifier 124. Figure 4 Capacitors 314 and 316 are further described.

[0042] Figure 4 An example component of a capacitor 314 or 316 is illustrated. In the depicted configuration, the transistor 314 or 316 is implemented as a metal oxide semiconductor field effect transistor (MOSFET). Other specific implementations of the transistors 314 and 316 are also possible. The transistor 314 or 316 includes at least one substrate 402 (or body) having at least two channel terminal regions 404-1 and 404-2 arranged or positioned along the axis 400. The substrate 402 can be a single crystal silicon wafer. Generally speaking, the substrate 402 provides physical support for the components of the amplifier 124. Sometimes, the substrate 402 represents the substrate of an integrated circuit including the amplifier 124. The example integrated circuit may include a radio frequency front end circuit 218 and / or a transceiver circuit 216. The substrate 402 has a first doping type 406-1.

[0043] The two channel terminal regions 404-1 and 404-2 have a second doping type 406-2 that is different from the first doping type 406-1 of the substrate 402. Consider an example in which the transistor 314 or 316 represents an NMOSFET. In this case, the doping type 402-1 of the substrate 406 represents p-type doping, and the doping type 404-2 of the two channel terminal regions 406-1 and 404-2 represents n-type doping. The doping type (e.g., n-type doping or p-type doping) within each of the two channel terminal regions 404-1 and 404-2 is uniform. Here, the term "uniform" means that the two channel terminal regions 404-1 and 404-2 have a single doping type, such as an n+ doping type, and the profiles of the channel terminal regions 404-1 and 404-2 are roughly similar.

[0044] The transistor 314 or 316 also includes at least one insulator 408, which can be grown or disposed on the surface of the substrate 402. The insulator 408 covers a portion of the surface of the substrate 402 located between the two channel terminal regions 404-1 and 404-2. In an example implementation, an oxide such as silicon dioxide (SiO2) is used to form the insulator 408. A conductive material such as a metal is deposited on the surface of the insulator 408 to form a gate electrode 410.

[0045] At least one electrical contact 412 is deposited in the trench terminal region 404 (such as Figure 4 The electrical contacts 412 are deposited on the surface of at least one of the channel terminal regions 404-1 in the embodiment of the present invention. Generally, any number of electrical contacts 412 may be deposited on the surface of the channel terminal region 404-1. For example, the number of electrical contacts 412 may be 1, 2, 4, 10, 20, 100, etc. The electrical contacts 412 may or may not be deposited on the surface of another channel terminal region 404-2, as further described below.

[0046] Transistor 314 or 316 can be viewed as a three-terminal device, where the terminals include a gate 414 (e.g., a gate terminal) and two channel terminals 416-1 and 416-2. Channel terminals 416-1 and 416-2 can each represent a source 418 (e.g., a source terminal) or a drain 420 (e.g., a drain terminal). In an example implementation in which transistor 314 implements a common-source amplifier 318 and transistor 316 implements a common-gate amplifier 320, channel terminal 416-1 represents the source 418 of transistor 314, and channel terminal 416-2 represents the drain 420 of transistor 314. For transistor 316, channel terminal 416-1 represents the drain 420, and channel terminal 416-2 represents the source 418.

[0047] The transistor 314 may have a parasitic capacitance 326 between the gate 414 and the channel terminal 416-2 (e.g., the drain 420). This parasitic capacitance 326 is based at least in part on parasitic capacitances of the back end of line (BEOL) of the amplifier 124 and parasitic capacitances between the gate 414 and any electrical contacts 412 disposed on the surface of the channel terminal region 404-2.

[0048] One aspect of reducing parasitic capacitance 326 is reducing the number of electrical contacts 412 deposited in channel terminal region 404-2 so that this number is less than the number of electrical contacts 412 deposited in channel terminal region 404-1. For example, the number of electrical contacts 412 deposited in channel terminal region 404-2 can be between 0% and 50% of the number of electrical contacts 412 deposited in channel terminal region 404-1. In some implementations, channel terminal region 404-2 represents a "no electrical contact region" where no electrical contacts are deposited on the surface of channel terminal region 404-2. In other implementations, one or more electrical contacts 412 are deposited in channel terminal region 404-2. Generally speaking, the total surface area of ​​channel terminal region 404-2 adjacent to electrical contacts 412 is less than the total surface area of ​​channel terminal region 404-1 adjacent to electrical contacts 412. The channel terminal region 404-2 of transistors 314 and 316 forms a floating region that is about Figure 5 Further description.

[0049] Figure 5 An example implementation of amplifier 124 is illustrated. In the depicted configuration, amplifier 124 includes stacks 304 and 306. Each stack 304 and 306 includes transistors 314 and 316 that are configured as a common-source amplifier 318 and a common-gate amplifier 320, respectively. Figure 5 , transistors 314 and 316 are shown as being implemented as NMOSFETs. However, other specific implementations are possible. For example, transistor 314 may be a SLVT-NMOSFET, and transistor 316 may be an ED-NMOSFET.

[0050] Transistors 314 and 316 are coupled together within each stack 304 and 306 at a floating node 312. Specifically, a drain 420 of transistor 314 is coupled to a source 418 of transistor 316 at a floating node 312. The drain 420 of transistor 314 and the source 418 of transistor 316 are associated with a channel terminal region 404-2. The channel terminal regions 404-2 of transistors 314 and 316 may form a floating region 514. In some cases, the floating region 514 represents a shared region that represents both the drain 420 of transistor 314 and the source 418 of transistor 316. Implementing the floating region 514 as a shared region may save space within the amplifier 124. The floating region 514 represents a conductive metal silicide diffusion region. Specifically, a thin layer of silicide, such as nickel silicide, may be present on the surface of the floating region 514.

[0051] Each stack 304 and 306 also includes an input node 502, a bias node 504, an output node 506, and a ground node 508. The input node 502 is coupled to the gate 414 of the transistor 314. The bias node 504 is coupled to the gate 414 of the transistor 316. The stacks 304 and 306 may include at least one capacitor coupled between the gate 414 of the transistor 316 and the bias node 504. The output node 506 is coupled to the drain 420 of the transistor 316. Although not explicitly shown, the output node 506 may also be coupled to a load and a power source node. The ground node 508 is coupled to the source 418 of the transistor 314.

[0052] During operation, input node 502 accepts a differential input signal (e.g., transmit signal 222). Output node 506 provides a differential output signal (e.g., amplified transmit signal 226) that is amplified relative to the differential input signal. Bias node 504 is coupled to supply voltage 510 and provides a bias voltage to gate 414 of transistor 316. Ground node 508 couples source 418 of transistor 314 to ground 512. Although Figure 5 1 and 2 as including a pair of stacks, but some implementations of amplifier 124 may have additional pairs of stacks, such as with respect to FIG. Figure 6 as further described.

[0053] Figure 6 Another example implementation of amplifier 124 is illustrated. In the depicted configuration, amplifier 124 includes multiple pairs of stacks. In the depicted configuration, amplifier 124 includes stacks 304-1, 304-2 ... 304-N, where N represents a positive integer. Amplification unit 124 also includes stacks 306-1, 306-2 ... 306-N. Each pair of stacks includes one of stacks 304-1 to 304-N and one of stacks 306-1 to 306-N. For example, the first pair of stacks includes stacks 304-1 and 306-1, the second pair of stacks includes stacks 304-2 and 306-2, and the Nth pair of stacks includes stacks 304-N and 306-N.

[0054] The stacks 304-1 through 304-N are coupled together in parallel, and the stacks 306-1 through 306-N are coupled together in parallel. Specifically, the stacks 304-1 through 304-N are coupled together at the input node 502 (not shown), the bias node 504, the output node 506, and the ground node 508. Also, the stacks 306-1 through 306-N are coupled together at the input node 502 (not shown), the bias node 504, the output node 506, and the ground node 508. To reduce parasitic capacitance 326, the number of electrical contacts 412 associated with the floating region 514 of the amplifier 124 is limited, as described with respect to FIG. Figure 7as further described.

[0055] Figure 7 An example layout of stack 304 or 306 is illustrated. In the depicted configuration, transistors 314 and 316 are implemented as multi-finger transistors. With this multi-finger design, multiple pairs of parallel stacks can be implemented in a space-efficient manner. Channel terminals 416-1 and 416-2 and gates 414 of transistors 314 and 316 are arranged or positioned along axis 400. Figure 7 Starting on the left side of and moving rightward along axis 400, stack 304 or 306 includes a first region 702, which is a channel terminal region 404-1. Disposed on the surface of first region 702 is an electrical contact 412, which connects first region 702 to at least one metal layer of transistor 314. First region 702 and electrical contact 412 at least partially form source 418 of transistor 314.

[0056] The gate 414 of transistor 314 is to the right of the source 418 of transistor 314. A second region 704 to the right of the gate 414 of transistor 316 represents a floating region 514 (e.g., the drain 420 of transistor 314 and the source 418 of transistor 314). The floating region 514 is positioned between the gate 414 of transistor 314 and the gate 414 of transistor 316. The floating region 514 may be formed with a single type of doping, such as an n+ doping type.

[0057] The third region 706 represents another channel terminal region 404-1. Specifically, the third region 706 corresponds to the drain 420 of the transistor 316. Disposed on the surface of the third region 706 is an electrical contact 412, which connects the third region 706 to at least one metal layer of the transistor 316. The third region 706 and the electrical contact 412 at least partially form the source 420 of the transistor 316.

[0058] In some implementations, the width of gate 414 is different between transistors 314 and 316. Consider axis 708, which is substantially perpendicular to axis 400. Along axis 708, the finger associated with gate 414 of transistor 314 has width 710. Also, the finger associated with gate 414 of transistor 316 has width 712. Figure 7 As shown, width 712 is greater than width 710. Larger width 712 may enhance the stability performance of amplifier 124 by effectively adding resistance between gate 414 of transistor 316 and bias node 504.

[0059] Consider Figure 7The case of stack 304 is illustrated. Although not explicitly shown, the layout of stack 306 can be positioned to the right or left of stack 304 along axis 400. In some implementations, sources 418 of transistors 314 of stack 306 can extend along axis 400 and connect to corresponding sources 418 of transistors 314 of stack 304.

[0060] In order to reduce parasitic capacitance 326, fewer electrical contacts 412 are disposed on floating region 514 relative to other channel terminal regions 404-1. For example, the number of electrical contacts 412 disposed on floating region 514 may be 0, 1, 2, 4, 6, or 10, while the number of electrical contacts 412 disposed on one of the other channel terminal regions 404-1 is larger. Therefore, the total surface area of ​​floating region 514 adjacent to electrical contacts 412 is less than the total surface area of ​​one of the channel terminal regions 404-1 adjacent to electrical contacts 412. In this example, floating region 514 (e.g., second region 704) is an electrical contact-free region, wherein no electrical contacts are disposed on the surface of floating region 514. In other words, floating region 514 lacks or has no electrical contacts 412. Sometimes, this aspect of reducing parasitic capacitance may be sufficient to enable amplifier 124 to achieve a desired level of performance without the need for a neutralizing capacitor. If additional parasitic capacitance reduction is required to achieve the desired performance level, at least one electrical contact 412 may be deposited on each of the floating regions 514 to enable the use of capacitor 328, as described with respect to FIG. Figure 8 and Fig. 9 as further described.

[0061] Figure 8 Yet another example implementation of amplifier 124 is illustrated. Figure 8 The amplifier 124 is similar to Figure 5 1 and 328-2. The amplifier 124 of FIG. 1 is similar to the amplifier 124 of FIG. 1 , but with the addition of two capacitors 328-1 and 328-2. In this case, at least one electrical contact is disposed on the surface of each of the floating regions 514 of the stacks 304 and 306. In the depicted configuration, capacitor 328-1 is coupled between at least one electrical contact disposed on the surface of the floating region 514 of the stack 306 and the gate 414 of the common-source amplifier 318 of the stack 304. Similarly, capacitor 328-2 is coupled between at least one electrical contact disposed on the surface of the floating region 514 of the stack 304 and the gate 414 of the common-source amplifier 318 of the stack 306. In this way, capacitors 328-1 and 328-2 may further reduce parasitic capacitance 326 within the common-source amplifier 318. To avoid increasing the footprint of amplifier 124, capacitors 328-1 and 328-2 may be integrated within the layout of the stacks 304 and 306, as described with respect to FIG. 1 . Fig. 9 and Fig.10 as further described.

[0062] Fig. 9 An example layout of amplifier 124 is illustrated, with stack 304 shown on the left and stack 306 shown on the right. Fig. 9 The layout of each stack 304 and 306 is similar to Figure 7 The layout shown, however, is for simplicity. Fig. 9 The stacks 304 and 306 in are shown as having fewer fingers. Capacitors 328-1 and 328-2 can be integrated within the footprint of amplifier 124. In this case, capacitors 328-1 and 328-2 are implemented at least in part using existing back-end processes for amplifier 124. In this way, capacitors 328-1 and 328-2 do not measurably increase the footprint of amplifier 124. Moreover, because the floating region 514 (e.g., region 704) has fewer electrical contacts 412 than other channel terminal regions 404-1 (e.g., regions 702 and 706), the capacitance of capacitors 328-1 and 328-2 can also be smaller than the capacitance of neutralizing capacitors of other amplifiers having a larger number of electrical contacts 412 disposed on the floating region 514. Using the described techniques, parasitic capacitance 326 within amplifier 124 can be meaningfully reduced without substantially increasing the footprint of amplifier 124. About Fig.10 Capacitors 328 - 1 and 328 - 2 are further described.

[0063] Fig.10 Portions of stacks 304 and 306 are illustrated as being implemented using multiple metal layers 1002 and at least one polysilicon layer 1004 disposed “above” substrate 402 along axis 1006. Axis 1006 is orthogonal to axes 400 and 708. Vias 1008 connect metal layers 1002 and polysilicon layers 1004 together. For example, a first set of vias 1008 connects polysilicon layer 1004 and a first set of metal layers 1002 together to form gate 414. A second set of vias 1008 connects a second set of metal layers 1002 together to form floating node 312. Although Fig.10 Five metal layers 1002 are explicitly shown in FIG. 3 , but stacks 304 and 306 may be implemented with any number of metal layers 1002 .

[0064] In the depicted configuration, capacitors 328-1 and 328-2 are formed by overlapping one of the metal layers 1002 associated with the appropriate floating node 312 and one of the metal layers 1002 associated with the appropriate gate 414 along axis 1006. Specifically, capacitor 328-1 is formed by overlapping metal layer 1002 associated with floating node 312 of stack 306 and metal layer 1002 associated with gate 414 of stack 304. Also, capacitor 328-2 is formed by overlapping metal layer 1002 associated with floating node 312 of stack 304 and metal layer 1002 associated with gate 414 of stack 306. In this manner, capacitors 328-1 and 328-2 are integrated within the layout of first stack 304 and second stack 306 using metal layer 1002. Other possible implementations of capacitors 328-1 and 328-2 using metal layer 1002 are also possible. By using a back-end process for amplifier 124 , capacitors 328 - 1 and 328 - 2 may be integrated without increasing the footprint of amplifier 124 along axes 400 and 708 .

[0065] Some aspects are described below.

[0066] Aspect 1: A device, comprising:

[0067] An amplifier having a differential cascode configuration, the amplifier comprising at least two stacks, each of the at least two stacks comprising:

[0068] a first transistor configured to operate as an input stage of the amplifier; and

[0069] a second transistor coupled to the first transistor at a floating node, the second transistor being configured to operate as a cascode stage of the amplifier, wherein:

[0070] The first transistor and the second transistor each include two channel terminal regions,

[0071] the two channel terminal regions having a doping type that is uniform across the two channel terminal regions,

[0072] The two channel terminal regions include a first channel terminal region and a second channel terminal region;

[0073] A surface of the first channel terminal region of the first transistor abuts a first number of electrical contacts;

[0074] a surface of the first channel terminal region of the second transistor abutting a second number of electrical contacts;

[0075] the second channel terminal regions of the first transistor and the second transistor form a floating region at the floating node; and

[0076] Each of the first number of electrical contacts and the second number of electrical contacts is greater than a third number of electrical contacts adjacent to a surface of the floating region.

[0077] Aspect 2: The device according to aspect 1, wherein:

[0078] a total surface area of ​​the floating region adjacent to the third number of electrical contacts is less than a total surface area of ​​the first channel terminal region of the first transistor adjacent to the first number of electrical contacts; and

[0079] The total surface area of ​​the floating region adjoining the third number of electrical contacts is less than a total surface area of ​​the first channel terminal region of the second transistor adjoining the second number of electrical contacts.

[0080] Aspect 3: The apparatus of aspect 1 or 2, wherein the third number of contacts is equal to zero.

[0081] Aspect 4: The apparatus according to aspect 3, wherein:

[0082] Each surface of the first channel terminal region of the first transistor and the second transistor adjoins at least one electrical contact; and

[0083] The surface of the floating region does not abut electrical contacts.

[0084] Aspect 5: The apparatus according to any of the preceding aspects, wherein:

[0085] said third number of electrical contacts being greater than zero;

[0086] The at least two stacks include a first stack and a second stack;

[0087] said surface of said floating region of said first stack abuts at least one first electrical contact;

[0088] The surface of the floating region of the second stack abuts at least one second electrical contact; and

[0089] The amplifier comprises:

[0090] a first capacitor coupled between the at least one first electrical contact and a gate terminal of the first transistor of the second stack; and

[0091] A second capacitor is coupled between the at least one second electrical contact and a gate terminal of the first transistor of the first stack.

[0092] Aspect 6: The apparatus of aspect 5, wherein the first capacitor and the second capacitor are integrated within a layout of the first stack and the second stack.

[0093] Aspect 7: The apparatus according to any of the preceding aspects, wherein:

[0094] The first transistor comprises a common-source amplifier; and

[0095] The second transistor comprises a common-gate amplifier.

[0096] Aspect 8: The apparatus of any preceding aspect, wherein the first transistor and the second transistor are symmetric for each of the at least two stacks.

[0097] Aspect 9: The apparatus of any one of aspects 1 to 7, wherein the first transistor and the second transistor are asymmetric for each of the at least two stacks.

[0098] Aspect 10: The apparatus according to aspect 9, wherein:

[0099] The first transistor comprises an extended drain n-channel metal oxide semiconductor field effect transistor; and

[0100] The second transistor comprises an ultra-low threshold voltage n-channel metal oxide semiconductor field effect transistor.

[0101] Aspect 11: The apparatus according to any of the preceding aspects, wherein:

[0102] The amplifier includes a substrate;

[0103] The two channel terminal regions of the first transistor and the second transistor are positioned within the substrate along a first axis;

[0104] The first transistor and the second transistor each include at least one metal layer forming one or more fingers associated with a gate terminal, the one or more fingers having a width along a second axis substantially perpendicular to the first axis; and

[0105] and

[0106] The width of the one or more fingers of the second transistor is greater than the width of the one or more fingers of the first transistor.

[0107] Aspect 12: The apparatus of any preceding aspect, wherein the floating region comprises a silicided diffusion region positioned between the gate of the first transistor and the gate of the second transistor.

[0108] Aspect 13: The apparatus of any preceding aspect, wherein the at least two stacks comprise a plurality of pairs of stacks coupled together in parallel.

[0109] Aspect 14: The apparatus according to any of the preceding aspects, further comprising:

[0110] A wireless transceiver coupled to at least one antenna, the wireless transceiver including the amplifier and configured to use the amplifier to amplify wireless signals communicated via the at least one antenna.

[0111] Aspect 15: The apparatus of aspect 14, wherein the amplifier comprises a power amplifier.

[0112] Aspect 16: A device, comprising:

[0113] A means for amplifying a differential signal using a differential cascode configuration, the means for amplifying comprising:

[0114] input stage; and

[0115] a cascode stage coupled to the input stage at a floating node, the input stage and the cascode stage each comprising two channel terminal regions having a doping type that is uniform across the two channel terminal regions, one of the two channel terminal regions of the input stage and one of the two channel terminal regions of the cascode stage forming a floating region at the floating node; and

[0116] Means for setting a parasitic capacitance between a gate terminal of the input stage and the one of the two channel terminal regions of the input stage based on a number of electrical contacts adjoining a surface of the floating region.

[0117] Aspect 17: The apparatus according to Aspect 16, wherein:

[0118] Another of the two trench terminal regions of the input stage adjoins a first number of electrical contacts;

[0119] Another of the two channel terminal regions of the cascode stage adjoins a second number of electrical contacts; and

[0120] Each of the first number of electrical contacts and the second number of electrical contacts is greater than a third number of electrical contacts adjacent the surface of the floating region.

[0121] Aspect 18: The apparatus of aspect 17, wherein the number of electrical contacts adjoining the surface of the floating region is equal to zero.

[0122] Aspect 19: The apparatus according to aspect 17, wherein:

[0123] The number of electrical contacts adjacent the surface of the floating region is greater than zero; and

[0124] and

[0125] The means for setting comprises a capacitive means for reducing at least a portion of the parasitic capacitance, the capacitive means being coupled to the floating region via an electrical contact.

[0126] Aspect 20: The apparatus according to any one of aspects 16 to 19, wherein:

[0127] The input stage and the cascode stage form a stack of components for amplification; and

[0128] The input stage and the cascode stage of the stack are symmetrical.

[0129] Aspect 21: The apparatus according to any one of aspects 16 to 19, wherein:

[0130] The input stage and the cascode stage form a stack of components for amplification; and

[0131] The input stage and the cascode stage of the stack are asymmetric.

[0132] Aspect 22: A device, comprising:

[0133] An amplifier having a differential cascode configuration, the amplifier comprising at least two stacks, each of the at least two stacks comprising:

[0134] a first transistor configured to operate as an input stage of the amplifier; and

[0135] a second transistor coupled to the first transistor at a floating node, the second transistor being configured to operate as a cascode stage of the amplifier, wherein:

[0136] The first transistor and the second transistor each include two channel terminal regions,

[0137] the two channel terminal regions having a doping type that is uniform across the two channel terminal regions,

[0138] The two channel terminal regions include a first channel terminal region and a second channel terminal region;

[0139] the second channel terminal regions of the first transistor and the second transistor form a floating region at the floating node; and

[0140] The floating region includes an electrical contact-free area.

[0141] Aspect 23: The apparatus according to Aspect 22, wherein:

[0142] Each surface of the first channel terminal region of the first transistor and the second transistor adjoins at least one electrical contact; and

[0143] The surface of the floating region does not abut electrical contacts.

[0144] Aspect 24: The apparatus according to Aspect 22 or 23, wherein:

[0145] The first transistor comprises a common-source amplifier; and

[0146] The second transistor comprises a common-gate amplifier.

[0147] Aspect 25: The apparatus of any one of aspects 22 to 24, wherein the first transistor and the second transistor are symmetric for each of the at least two stacks.

[0148] Aspect 26: The apparatus of any one of aspects 22 to 24, wherein the first transistor and the second transistor are asymmetric for each of the at least two stacks.

[0149] Aspect 27: The device according to any one of aspects 22 to 26, wherein:

[0150] The amplifier includes a substrate;

[0151] The two channel terminal regions of the first transistor and the second transistor are positioned within the substrate along a first axis;

[0152] The first transistor and the second transistor each include at least one metal layer forming one or more fingers associated with a gate terminal, the one or more fingers having a width along a second axis substantially perpendicular to the first axis; and

[0153] and

[0154] The width of the one or more fingers of the second transistor is greater than the width of the one or more fingers of the first transistor.

[0155] Aspect 28: A device, comprising:

[0156] An amplifier having a differential cascode configuration, the amplifier comprising at least two stacks, each of the at least two stacks comprising:

[0157] a first transistor configured to operate as an input stage of the amplifier; and

[0158] a second transistor coupled to the first transistor at a floating node, the second transistor configured to operate as a cascode stage of the amplifier;

[0159] a first capacitor coupled between a gate of the first transistor of a first stack of the at least two stacks and the floating node of a second stack of the at least two stacks; and

[0160] a second capacitor coupled between a gate of the first transistor of the second stack and the floating node of the first stack, wherein:

[0161] The first transistor and the second transistor each include two channel terminal regions,

[0162] the two channel terminal regions having a doping type that is uniform across the two channel terminal regions,

[0163] The two channel terminal regions include a first channel terminal region and a second channel terminal region;

[0164] surfaces of the second channel terminal regions of the first transistor and the second transistor form a floating region at the floating node; and

[0165] Each of a number of electrical contacts adjoining the first channel terminal region of the first transistor and a number of electrical contacts adjoining the first channel terminal region of the second transistor is greater than a number of electrical contacts adjoining a surface of the floating region.

[0166] Aspect 29: The apparatus of aspect 28, wherein the first capacitor and the second capacitor are integrated within a layout of the first stack and the second stack using metal interconnect layers associated with the first stack and the second stack.

[0167] Aspect 30: The apparatus according to aspect 28 or 29, wherein:

[0168] The amplifier includes a substrate;

[0169] The two channel terminal regions of the first transistor and the second transistor are positioned within the substrate along a first axis;

[0170] The first transistor and the second transistor each include at least one metal layer forming one or more fingers associated with a gate terminal, the one or more fingers having a width along a second axis substantially perpendicular to the first axis; and

[0171] and

[0172] The width of the one or more fingers of the second transistor is greater than the width of the one or more fingers of the first transistor.

[0173] Unless the context dictates otherwise, the use of the word "or" herein may be considered an "inclusive or" or use of a term that permits inclusion or application of one or more items linked by the word "or" (e.g., the phrase "A or B" may be interpreted as permitting only "A," only "B," or both "A" and "B"). As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including a single member). As an example, "at least one of a, b, or c" is intended to encompass: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c). In addition, the items represented in the drawings and the terms discussed herein may indicate one or more items or terms, and thus the singular or plural forms of those items and terms may be referred to interchangeably in this written description. Finally, although the subject matter has been described in language specific to structural features or methodological operations, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations described above, including not necessarily being limited to the organization in which the features are arranged or the order in which the operations are performed.

Claims

1. A device, comprising: An amplifier having a differential cascode configuration, the amplifier comprising at least two stacks, each of the at least two stacks comprising: a first transistor configured to operate as an input stage of the amplifier; and a second transistor coupled to the first transistor at a floating node, the second transistor being configured to operate as a cascode stage of the amplifier, wherein: the first transistor and the second transistor each comprising two channel terminal regions having a doping type that is uniform across the two channel terminal regions, the two channel terminal regions comprising a first channel terminal region and a second channel terminal region; A surface of the first channel terminal region of the first transistor abuts a first number of electrical contacts; a surface of the first channel terminal region of the second transistor abutting a second number of electrical contacts; the second channel terminal regions of the first transistor and the second transistor form a floating region at the floating node; and Each of the first number of electrical contacts and the second number of electrical contacts is greater than a third number of electrical contacts adjacent to a surface of the floating region.

2. The device according to claim 1, wherein: a total surface area of ​​the floating region adjacent to the third number of electrical contacts is less than a total surface area of ​​the first channel terminal region of the first transistor adjacent to the first number of electrical contacts; and The total surface area of ​​the floating region adjoining the third number of electrical contacts is less than a total surface area of ​​the first channel terminal region of the second transistor adjoining the second number of electrical contacts. The device of claim 1 , wherein the third number of contacts is equal to zero.

4. The device according to claim 3, wherein: Each surface of the first channel terminal region of the first transistor and the second transistor adjoins at least one electrical contact; and The surface of the floating region does not abut electrical contacts.

5. The device according to claim 1, wherein: said third number of electrical contacts being greater than zero; The at least two stacks include a first stack and a second stack; said surface of said floating region of said first stack abuts at least one first electrical contact; said surface of said floating region of said second stack abuts at least one second electrical contact; and The amplifier comprises: a first capacitor coupled between the at least one first electrical contact and a gate terminal of the first transistor of the second stack; and A second capacitor is coupled between the at least one second electrical contact and a gate terminal of the first transistor of the first stack. 6 . The device of claim 5 , wherein the first capacitor and the second capacitor are integrated within a layout of the first stack and the second stack.

7. The device according to claim 1, wherein: The first transistor comprises a common-source amplifier; and The second transistor comprises a common-gate amplifier. 8 . The device of claim 1 , wherein the first transistor and the second transistor are symmetric for each of the at least two stacks. 9 . The device of claim 1 , wherein the first transistor and the second transistor are asymmetric for each of the at least two stacks.

10. The device according to claim 9, wherein: The first transistor comprises an extended drain n-channel metal oxide semiconductor field effect transistor; and The second transistor comprises an ultra-low threshold voltage n-channel metal oxide semiconductor field effect transistor.

11. The device according to claim 1, wherein: The amplifier includes a substrate; The two channel terminal regions of the first transistor and the second transistor are positioned within the substrate along a first axis; The first transistor and the second transistor each include at least one metal layer forming one or more fingers associated with a gate terminal, the one or more fingers having a width along a second axis substantially perpendicular to the first axis; and The width of the one or more fingers of the second transistor is greater than the width of the one or more fingers of the first transistor. 12 . The apparatus of claim 1 , wherein the floating region comprises a silicided diffusion region positioned between a gate of the first transistor and a gate of the second transistor.

13. The apparatus of claim 1, wherein the at least two stacks comprise a plurality of pairs of stacks coupled together in parallel.

14. The apparatus according to claim 1, further comprising: A wireless transceiver coupled to at least one antenna, the wireless transceiver including the amplifier and configured to use the amplifier to amplify wireless signals communicated via the at least one antenna.

15. The apparatus of claim 14, wherein the amplifier comprises a power amplifier.

16. A device, comprising: A means for amplifying a differential signal using a differential cascode configuration, the means for amplifying comprising: input stage; and a cascode stage coupled to the input stage at a floating node, the input stage and the cascode stage each comprising two channel terminal regions having a doping type that is uniform across the two channel terminal regions, one of the two channel terminal regions of the input stage and one of the two channel terminal regions of the cascode stage forming a floating region at the floating node; and Means for setting a parasitic capacitance between a gate terminal of the input stage and the one of the two channel terminal regions of the input stage based on a number of electrical contacts adjoining a surface of the floating region.

17. The device according to claim 16, wherein: Another of the two trench terminal regions of the input stage adjoins a first number of electrical contacts; Another of the two channel terminal regions of the cascode stage adjoins a second number of electrical contacts; and Each of the first number of electrical contacts and the second number of electrical contacts is greater than the number of electrical contacts adjacent the surface of the floating region.

18. The apparatus of claim 17, wherein the number of electrical contacts adjacent the surface of the floating region is equal to zero.

19. The apparatus of claim 17, wherein: The number of electrical contacts adjacent the surface of the floating region is greater than zero; and The means for setting comprises a capacitive means for reducing at least a portion of the parasitic capacitance, the capacitive means being coupled to the floating region via an electrical contact.

20. The apparatus of claim 16, wherein: The input stage and the cascode stage form a stack of components for amplification; and The input stage and the cascode stage of the stack are symmetrical.

21. The apparatus of claim 16, wherein: The input stage and the cascode stage form a stack of components for amplification; and The input stage and the cascode stage of the stack are asymmetric.

22. A device, comprising: An amplifier having a differential cascode configuration, the amplifier comprising at least two stacks, each of the at least two stacks comprising: a first transistor configured to operate as an input stage of the amplifier; and a second transistor coupled to the first transistor at a floating node, the second transistor being configured to operate as a cascode stage of the amplifier, wherein: the first transistor and the second transistor each comprising two channel terminal regions having a doping type that is uniform across the two channel terminal regions, the two channel terminal regions comprising a first channel terminal region and a second channel terminal region; the second channel terminal regions of the first transistor and the second transistor form a floating region at the floating node; and The floating region includes an electrical contact-free area.

23. The apparatus of claim 22, wherein: Each surface of the first channel terminal region of the first transistor and the second transistor adjoins at least one electrical contact; and The surface of the floating region does not abut electrical contacts.

24. The apparatus of claim 22, wherein: The first transistor comprises a common-source amplifier; and The second transistor comprises a common-gate amplifier.

25. The device of claim 22, wherein the first transistor and the second transistor are symmetric for each of the at least two stacks.

26. The device of claim 22, wherein the first transistor and the second transistor are asymmetric for each of the at least two stacks.

27. The apparatus of claim 22, wherein: The amplifier includes a substrate; The two channel terminal regions of the first transistor and the second transistor are positioned within the substrate along a first axis; The first transistor and the second transistor each include at least one metal layer forming one or more fingers associated with a gate terminal, the one or more fingers having a width along a second axis substantially perpendicular to the first axis; and The width of the one or more fingers of the second transistor is greater than the width of the one or more fingers of the first transistor.

28. An apparatus, comprising: An amplifier having a differential cascode configuration, the amplifier comprising at least two stacks, each of the at least two stacks comprising: a first transistor configured to operate as an input stage of the amplifier; and a second transistor coupled to the first transistor at a floating node, the second transistor configured to operate as a cascode stage of the amplifier; a first capacitor coupled between a gate of the first transistor of a first stack of the at least two stacks and the floating node of a second stack of the at least two stacks; and a second capacitor coupled between a gate of the first transistor of the second stack and the floating node of the first stack, wherein: the first transistor and the second transistor each comprising two channel terminal regions having a doping type that is uniform across the two channel terminal regions, the two channel terminal regions comprising a first channel terminal region and a second channel terminal region; surfaces of the second channel terminal regions of the first transistor and the second transistor form a floating region at the floating node; and Each of a number of electrical contacts adjoining the first channel terminal region of the first transistor and a number of electrical contacts adjoining the first channel terminal region of the second transistor is greater than a number of electrical contacts adjoining a surface of the floating region.

29. The apparatus of claim 28, wherein the first capacitor and the second capacitor are integrated within a layout of the first stack and the second stack using metal interconnect layers associated with the first stack and the second stack.

30. The apparatus of claim 28, wherein: The amplifier includes a substrate; The two channel terminal regions of the first transistor and the second transistor are positioned within the substrate along a first axis; The first transistor and the second transistor each include at least one metal layer forming one or more fingers associated with a gate terminal, the one or more fingers having a width along a second axis substantially perpendicular to the first axis; and The width of the one or more fingers of the second transistor is greater than the width of the one or more fingers of the first transistor.

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