Manufacturing method for semiconductor structure

Abstract

The invention provides a manufacturing method for a semiconductor structure. The manufacturing method comprises the following steps: carrying out annealing treatment on a substrate in a reaction chamber; forming an oxide film layer with a predetermined thickness on the surface of the annealed substrate; and forming a first polycrystalline silicon layer on the oxide film layer of the substrate through vapor deposition so as to manufacture the semiconductor structure.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor processing technology, and more particularly to a method for manufacturing a semiconductor structure. Background Art

[0002] Chemical Vapor Deposition (CVD) technology is a thin film deposition method widely used in semiconductor manufacturing, which can form functional thin films, such as polysilicon layers, on the surface of substrates. Common CVD technologies include atmospheric pressure chemical vapor deposition (APCVD) and low pressure chemical vapor deposition (LPCVD). These technologies are widely used in the manufacture of semiconductor devices due to their advantages such as high deposition rate and good film thickness uniformity.

[0003] It is a common process to deposit a polysilicon layer on the surface of a single-crystal silicon wafer using CVD technology. The specific steps include: placing a single-crystal silicon wafer in a CVD reaction chamber heated to a high temperature, and mixing a reaction gas (such as trichlorosilane or silane) with a carrier gas (such as hydrogen) to deposit polysilicon on the surface of the silicon wafer to form a thin film. After the deposition is completed, the silicon wafer is cooled and used for subsequent processing.

[0004] However, the process has problems of uneven internal stress in practical applications, especially the thermal stress caused by the different thermal expansion coefficients of polysilicon and monocrystalline silicon, as well as the imbalance of front and back stress caused by single-sided deposition. These stress problems may cause defects such as warping or cracking of the silicon wafer, thus affecting the stability of the process and the quality of the polysilicon layer. Summary of the invention

[0005] In view of the above problems, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. Before forming a polysilicon layer by vapor deposition, the method for manufacturing a semiconductor structure anneals a substrate and forms an oxide film layer on its surface, thereby releasing the mechanical stress remaining in the substrate in advance and ensuring that the subsequent deposition of the polysilicon layer can proceed smoothly, thereby manufacturing a desired semiconductor structure.

[0006] The technical solution of the present disclosure is achieved as follows: The present disclosure provides a method for manufacturing a semiconductor structure, the method comprising: performing an annealing process on the substrate in a reaction chamber; forming an oxide film layer of a predetermined thickness on the surface of the substrate after the annealing treatment; A first polysilicon layer is formed by vapor deposition on the oxide film layer of the substrate to manufacture a semiconductor structure.

[0007] In some optional examples, the forming a first polysilicon layer by vapor deposition on the oxide film layer of the substrate includes: Etching the oxide film layer of the substrate using a reducing gas; The first polysilicon layer is formed by vapor deposition on the etched oxide film layer.

[0008] In some optional examples, the thickness of the oxide film layer is greater than the etching amount of the reducing gas.

[0009] In some optional examples, forming an oxide film layer of a predetermined thickness on the surface of the substrate after the annealing treatment includes: The annealed substrate is unloaded from the reaction chamber into a substrate container and left to stand for more than 6 hours.

[0010] In some optional examples, the thickness of the oxide film layer is greater than 5Å and less than 400nm.

[0011] In some optional examples, the thickness of the oxide film layer is greater than 15Å and less than 50Å.

[0012] In some optional examples, the temperature of vapor deposition corresponding to forming the first polysilicon layer is above 700° C.

[0013] In some optional examples, after forming a first polysilicon layer by vapor deposition on the oxide film layer of the substrate, the manufacturing method further includes: forming a second polysilicon layer by vapor deposition on the first polysilicon layer.

[0014] In some optional examples, a vapor deposition temperature corresponding to forming the second polysilicon layer is above 1000° C.

[0015] In some optional examples, the thickness of the first polysilicon layer is greater than 200 nm and less than 10 μm.

[0016] In some optional examples, the thickness of the first polysilicon layer is greater than 200 nm and less than 1 μm, and the thickness of the second polysilicon layer is greater than 200 nm and less than 10 μm.

[0017] In some optional examples, the temperature corresponding to the annealing treatment performed on the substrate is above 950°C.

[0018] The present disclosure provides a method for manufacturing a semiconductor structure. In the manufacturing method, after annealing the substrate and forming an oxide film layer of a predetermined thickness on the surface thereof, a polysilicon layer is generated on the oxide film layer using a vapor deposition technique to manufacture a semiconductor structure. The annealing treatment can effectively reduce the crystal defects and residual stress inside the substrate, and provide a stable foundation for the subsequent deposition process. As a key intermediate isolation layer, the oxide film layer not only helps the uniform film formation of the polysilicon layer during the deposition process, but also isolates the influence of the characteristics of the substrate surface on the quality of the polysilicon layer, and blocks the diffusion of impurities during the deposition process, thereby ensuring the high purity and uniformity of the polysilicon layer. The manufacturing method significantly improves the quality of the polysilicon layer of the semiconductor structure, not only improves the uniformity of the deposited film, but also reduces the interface defects or chemical contamination problems that may occur between the polysilicon layer and the substrate, thereby providing an effective solution for achieving high-quality polysilicon deposition. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.

[0020] Figure 2 To use Figure 1 A stress distribution cloud diagram of a semiconductor structure obtained by a method for manufacturing a semiconductor structure is shown.

[0021] Figure 3 A flowchart of a method for manufacturing a semiconductor structure is provided according to another embodiment of the present disclosure.

[0022] Figure 4 A stress distribution cloud diagram of a semiconductor structure obtained by using a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.

[0023] Figure 5 A stress distribution cloud diagram of a semiconductor structure obtained by using a method for manufacturing a semiconductor structure provided by yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The technical solutions in the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings in the present disclosure.

[0025] See also Figure 1 Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, the method for manufacturing a semiconductor structure is used to deposit a polycrystalline silicon layer on a single crystal silicon substrate to obtain a semiconductor structure with a polycrystalline silicon thin film deposited on the surface. The manufacturing method may include the following steps: S01, placing a single crystal silicon substrate into a reaction chamber.

[0026] The single crystal silicon substrate is precisely placed on the designated pedestal in the reaction chamber to ensure its correct position. The reaction chamber is vacuum treated to reduce the pressure inside the chamber to a high vacuum environment to remove impurity gases. This step is to ensure the purity of the gas during the deposition process and the deposition effect of the polysilicon film.

[0027] S02, heating the reaction chamber and delivering reaction gas to the reaction chamber to form a polycrystalline silicon film on the single crystal silicon substrate by a vapor deposition method, thereby manufacturing a semiconductor structure.

[0028] Start the heating device in the reaction chamber to uniformly heat the single crystal silicon substrate to the target temperature. The setting of the target temperature depends on the specific deposition requirements. The reaction gas, such as silane (SiH4) or trichlorosilane (SiHCl3), is transported into the reaction chamber through the gas pipeline, and the carrier gas, such as hydrogen (H2), is introduced at the same time to form a stable mixed gas flow and establish a suitable reaction atmosphere in the chamber. The reaction gas decomposes at high temperature, and the silicon atoms are deposited on the surface of the single crystal silicon substrate through chemical reaction to form a uniform polycrystalline silicon film.

[0029] The inventors have found in actual production that when the polysilicon layer is deposited on the surface of a single crystal silicon substrate using the above-mentioned manufacturing method, significant stress problems and uneven quality are likely to occur. After research and experiments, the inventors believe that the main reason for the above-mentioned problems and phenomena is the difference in thermal expansion coefficients between polysilicon and single crystal silicon. During the high-temperature deposition process, this difference causes thermal stress to be generated at the interface. Especially when the deposition only acts on the front side of the substrate, the uneven force on the front and back sides of the substrate further aggravates the accumulation of internal mechanical stress. For example, see Figure 2 , which shows a mechanical stress distribution cloud diagram of a semiconductor structure obtained by the above manufacturing method. Figure 2 As shown, thermal stress is often concentrated in specific areas of the semiconductor structure, forming a "butterfly-shaped" stress distribution, which not only weakens the shape stability of the semiconductor structure but also poses a threat to the reliability of subsequent processes.

[0030] In view of this, the present disclosure provides a method for manufacturing a semiconductor structure. The method anneals a substrate and forms an oxide film layer on its surface before forming a polysilicon layer by vapor deposition, thereby releasing the residual mechanical stress in the substrate in advance and ensuring that the subsequent deposition of the polysilicon layer can proceed smoothly, thereby manufacturing a desired semiconductor structure.

[0031] See also Figure 3 Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The manufacturing method may include: S101, performing annealing treatment on the substrate in a reaction chamber; S102, forming an oxide film layer of a predetermined thickness on the surface of the substrate after the annealing treatment; S103, forming a first polysilicon layer by vapor deposition on the oxide film layer of the substrate to manufacture a semiconductor structure.

[0032] The above method is further described below by taking a single crystal silicon substrate as an example.

[0033] During the processing and use of single-crystal silicon substrates, mechanical stress is mainly generated from a variety of process links. For example, during mechanical processing such as cutting, grinding and polishing, external forces can cause partial deformation of the single-crystal silicon substrate lattice, and the atomic arrangement in the lattice is slightly offset or dislocated. This offset usually manifests itself in the form of dislocations and microcracks, and accumulates inside the lattice to form residual mechanical stress. In addition, when single-crystal silicon substrates are used in deposition processes (such as chemical vapor deposition), due to the difference in thermal expansion coefficients between polycrystalline silicon and single-crystal silicon, the mismatch in dimensional changes in high-temperature environments will also generate additional thermal stress. If the above stresses are not effectively released, it may cause the substrate to warp, crack, or even scrap the semiconductor structure, seriously affecting the quality of subsequent processes.

[0034] To solve the mechanical stress problem, the substrate can be heat treated in step S101. This process heats the single crystal silicon substrate to a predetermined temperature and maintains it for a period of time, so that the atoms in the lattice are rearranged under the action of thermal diffusion, getting rid of the original dislocation state, and thus reaching a lower energy and more stable equilibrium position. This process significantly reduces the dislocation density in the lattice and effectively releases the residual mechanical stress.

[0035] As an example, the annealing temperature can be set above 950°C. Under this high temperature condition, the atomic migration ability within the silicon substrate is significantly improved, allowing tiny defects (such as dislocations, vacancies, and stress concentration areas) to be repaired, thereby improving the integrity and quality of the crystal. At the same time, high-temperature annealing can effectively release the residual stress generated by the processing or growth process, avoiding the problem of cracks or device performance degradation that may occur in subsequent processes. In addition, the thermal expansion effect in a high temperature environment allows the internal stress of the substrate to be redistributed. When the substrate reaches thermal equilibrium under uniform heating conditions, the local stress is diffused and homogenized, further reducing the risk of cracks or defects caused by stress concentration.

[0036] After heat treatment, the internal stress level of the single-crystal silicon substrate is significantly reduced, and its mechanical stability is enhanced, providing a more stable physical platform for subsequent high-temperature deposition processes. Therefore, by rationally designing the temperature and time of heat treatment, not only can the accumulation of mechanical stress during processing and deposition be effectively alleviated, but the flatness and reliability of the single-crystal silicon substrate and its adaptability to subsequent processes can also be significantly improved.

[0037] In step S102 after step S101, a silicon oxide film of a predetermined thickness may be formed on the surface of the single crystal silicon substrate. The formation of this silicon oxide film not only supplements the substrate state after annealing, but also is an important guarantee for the subsequent polysilicon layer deposition quality.

[0038] Specifically, the silicon oxide film layer plays multiple key roles in the polysilicon deposition process, from nucleation support to stress buffering to structural stability, and its importance runs through the entire process. First, the silicon oxide film provides an ideal basis for the uniform nucleation of polysilicon, while isolating the direct contact between the silicon source gas and the silicon substrate, effectively preventing the substrate surface from being etched due to gas reactions. Secondly, during the deposition process, the silicon oxide film can absorb and alleviate the stress caused by differences in thermal expansion coefficients and changes in deposition temperature, thereby significantly reducing the risk of stress-related defects such as warping and cracking of the semiconductor structure.

[0039] In the low-temperature deposition stage, the silicon oxide film provides uniform nucleation points for polysilicon nuclei, ensuring uniform growth of grains in the expected direction and reducing structural defects that may be caused by uneven nucleation. In the high-temperature deposition stage, the silicon oxide film further plays a supporting and stabilizing role, not only preventing grains from desorbing due to temperature increases, but also inhibiting abnormal growth, ensuring the overall quality and uniformity of the film layer.

[0040] In addition, the silicon oxide film also plays an important isolation role, effectively preventing the polysilicon layer from being embedded too deeply into the single-crystal silicon substrate, avoiding the local area from being converted into single-crystal silicon characteristics, thereby ensuring that the entire film layer maintains the expected polysilicon structure. In short, the silicon oxide film plays an indispensable role in the deposition process from nucleation uniformity to stress regulation to structural integrity, laying a solid foundation for the high-quality deposition of the polysilicon layer.

[0041] Next, in step S103 , a polysilicon layer is formed on the silicon oxide film of the silicon substrate by vapor deposition technology to manufacture a desired semiconductor structure.

[0042] Specifically, after a single crystal silicon substrate with a silicon oxide film formed on the surface is placed in a reaction chamber, the temperature and atmosphere conditions in the reaction chamber can be precisely controlled to ensure the stability of the reaction and the uniformity of the film. When the reaction gas is introduced into the chamber, the silicon source gas decomposes under high temperature conditions to produce silicon atoms and byproducts. These silicon atoms adsorb on the surface of the silicon oxide film and begin to nucleate. Unlike single crystal silicon, the surface of the silicon oxide film has a high lattice mismatch, which prevents silicon atoms from arranging in the direction of a single crystal, but randomly oriented to form polycrystalline silicon grains. As the reaction proceeds, these grains gradually grow and cover the entire substrate surface, eventually forming a continuous polycrystalline silicon film.

[0043] like Figure 4As shown, it shows the stress distribution cloud diagram of the semiconductor structure obtained by the above-mentioned manufacturing method for the semiconductor structure provided by the embodiment of the present disclosure. Figure 2 and Figure 4 It can be clearly seen that the semiconductor structure obtained by the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure has significantly smaller mechanical stress.

[0044] For the semiconductor structure obtained by the manufacturing method for a semiconductor structure described above, the mechanical stress of the semiconductor structure measured by Scanning Infrared Depolarization Measurement (SIRD) 40 DU% is below 45%.

[0045] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. In the manufacturing method, after annealing the substrate and forming an oxide film layer of a predetermined thickness on its surface, a polysilicon layer is generated on the oxide film layer using a vapor deposition technique to manufacture the desired semiconductor structure. The annealing treatment can effectively reduce the crystal defects and residual stress inside the substrate, providing a stable foundation for the subsequent deposition process. As a key intermediate isolation layer, the oxide film layer not only helps the uniform film formation of the polysilicon layer during the deposition process, but also isolates the influence of the characteristics of the substrate surface on the quality of the polysilicon layer, while blocking the diffusion of impurities during the deposition process, thereby ensuring the high purity and uniformity of the polysilicon layer. The manufacturing method significantly improves the quality of the polysilicon layer, not only improves the uniformity of the deposited film, but also reduces the interface defects or chemical contamination problems that may occur between the polysilicon layer and the substrate, thereby providing an effective solution for achieving high-quality polysilicon deposition.

[0046] In some embodiments of the present disclosure, forming a first polysilicon layer by vapor deposition on an oxide film layer of a substrate may include: Using reducing gas to etch the oxide film layer of the substrate; A first polysilicon layer is formed by vapor deposition on the etched oxide film layer.

[0047] Specifically, a reducing gas, such as hydrogen, ammonia or a mixture thereof, can be used to etch the oxide film layer. Through chemical reactions, part of the material in the oxide film layer is removed, thereby significantly reducing the roughness of the surface of the oxide film layer and improving its uniformity. This smooth and uniform surface state is crucial for the subsequent vapor deposition process, which helps to improve the nucleation efficiency of the polysilicon layer and form a dense and uniformly thick polysilicon layer. Next, a first polysilicon layer can be formed on the etched oxide film layer using a vapor deposition process. The smooth surface of the oxide film layer provides ideal interface conditions for the deposition of polysilicon, thereby improving the quality of the film.

[0048] In order to prevent the oxide film from being completely etched, in some embodiments, the thickness of the oxide film is designed to be greater than the etching amount of the reducing gas, so as to ensure that the oxide film still covers the substrate surface after the etching step.

[0049] In addition, the silicon oxide film not only helps to flatten the surface, but also provides effective protection during the subsequent thin film epitaxial growth process. Reducing gases such as hydrogen easily react with the exposed surface of the single crystal silicon substrate during the epitaxial growth process, causing etching and destroying the surface smoothness and structural integrity. The silicon oxide film covering the surface of the substrate acts as a protective barrier to isolate the direct contact between the reducing gas and the silicon-based surface, avoid surface etching, and maintain the flatness and integrity of the substrate.

[0050] It can be seen that by rationally designing the thickness of the oxide film layer so that it remains on the substrate surface after the etching step, effective protection of the single-crystalline silicon substrate can be achieved, while providing superior surface conditions for subsequent polysilicon deposition, thereby ensuring the stability of the entire process and the high quality of the finished product.

[0051] In some embodiments of the present disclosure, forming an oxide film layer of a predetermined thickness on the surface of the annealed substrate includes: unloading the annealed substrate from the reaction chamber into a substrate container and leaving it to stand for more than 6 hours.

[0052] Specifically, after the annealing process is completed, the substrate can be unloaded from the reaction chamber into a dedicated substrate container to avoid direct impact of the external environment on the substrate surface. The substrate container can be, for example, a wafer box, which can provide a relatively controlled environment and reduce film defects caused by impurities or particle contamination.

[0053] By keeping the annealed substrate in the substrate container for more than 6 hours, the thickness of the oxide film layer can be fully developed during the natural oxidation process, meeting the technical requirements of the subsequent deposition process. This method of forming an oxide film layer by standing still does not require an additional oxidation treatment process, simplifying the overall process. The uniform and high-purity oxide film layer obtained in this way optimizes the film formation conditions of polysilicon deposition and further improves the uniformity and stability of the thin film layer.

[0054] It should be noted that the formation method of the oxide film layer is not limited to the above-mentioned static method, and other suitable oxidation treatment methods may be selected according to specific process requirements, such as thermal oxidation method, chemical solution oxygen method, etc. This disclosure does not limit this.

[0055] In order to ensure the stability of the deposition process and the deposition quality of the polysilicon layer, in some embodiments of the present disclosure, the thickness of the oxide film layer may be greater than or equal to 5Å and less than or equal to 400nm. In further embodiments, the thickness of the oxide film layer may be greater than or equal to 15Å and less than or equal to 50Å.

[0056] Specifically, on the one hand, controlling the thickness of the oxide film layer to more than 5Å can provide effective surface protection for the silicon substrate, preventing the reducing gas from directly etching the substrate surface, thereby ensuring the integrity of the silicon substrate during the subsequent deposition process. On the other hand, limiting the thickness to less than 400nm can avoid affecting the uniformity and efficiency of the vapor deposition reaction due to the excessive thickness of the oxide film layer.

[0057] Furthermore, the thickness of the oxide film layer is controlled within the range of 15Å to 50Å. The oxide film layer can ensure the uniform deposition of silicon atoms on the surface of the oxide film layer, and can also avoid the uneven growth or stratification of polysilicon grains caused by the excessive thickness of the oxide film layer. In addition, this thickness range can also effectively isolate impurities that may diffuse during the deposition process, provide a uniform reaction interface for the polysilicon layer, improve the interlayer bonding strength, and reduce the risk of stratification or peeling.

[0058] In summary, by controlling the thickness of the oxide film layer, the manufacturing method for semiconductor structures not only meets the requirements of different deposition equipment and process parameters, but also can improve the uniformity and bonding strength of the polysilicon layer deposition by optimizing the film thickness, thereby providing important support for achieving high quality of the thin film layer and process stability.

[0059] In some embodiments of the present disclosure, a polysilicon layer may be formed by two depositions. Specifically, after vapor deposition forms a first polysilicon layer on the oxide film layer of the substrate, the manufacturing method may further include: A second polysilicon layer is formed by vapor deposition on the first polysilicon layer.

[0060] By vapor-depositing a second polysilicon layer on the basis of the first polysilicon layer, the overall performance of the film can be significantly improved. On the one hand, this process conceals the microscopic defects on the surface of the first polysilicon layer through the newly formed growth interface, improving the flatness of the film; on the other hand, it compensates for the uneven thickness problem that may exist during the deposition of the first layer, thereby forming an overall film with higher uniformity. In addition, the addition of the second polysilicon layer significantly enhances the mechanical strength and thermal stability of the film, while effectively inhibiting the expansion of defects during the deposition process, ensuring the consistency of film quality.

[0061] In addition, the advantage of the two-step deposition process is that the deposition of the second polysilicon layer forms a uniform transition interface with the first layer, which not only enhances the interlayer bonding strength and avoids delamination or peeling caused by insufficient bonding force, but also further improves the overall performance of the polysilicon film. The flexibility of this step-by-step deposition method enables it to adjust the total thickness of the polysilicon layer as needed, thereby adapting to different application scenarios. In addition, the combination of high-temperature deposition process and stress release mechanism optimizes the internal structure of the polysilicon layer, significantly reduces the residual stress in the semiconductor structure, and ensures that the deposited film layer has higher flatness and mechanical stability.

[0062] In summary, the two-step deposition process not only solves the problems of uneven thickness and interface defects that may exist in a single deposition, but also improves the physical properties and film quality of the polysilicon layer through step-by-step optimization and high-temperature treatment, providing a more stable technical guarantee for the high-precision manufacturing of semiconductor structures. Figure 5 As shown, it shows the stress distribution cloud diagram of the semiconductor structure obtained by the manufacturing method for the semiconductor structure including two deposition processes provided by the embodiment of the present disclosure. Figure 2 , Figure 4 and Figure 5 It can be clearly seen that, among the three methods, the semiconductor structure obtained by the method for manufacturing a semiconductor structure including two deposition processes obviously has the smallest mechanical stress.

[0063] According to some embodiments of the present disclosure, the vapor deposition temperature corresponding to forming the first polysilicon layer is greater than or equal to 700° C. According to some other embodiments of the present disclosure, the vapor deposition temperature corresponding to forming the second polysilicon layer is greater than or equal to 1000° C.

[0064] Controlling the temperature above 700°C can provide sufficient thermal energy to promote uniform reaction between the silicon source in the reaction gas and the oxide film layer, thereby ensuring stable deposition of the polysilicon layer.

[0065] Deposition at high temperatures above 1000°C can not only significantly promote the rapid diffusion of silicon atoms and make the grain structure of polysilicon more uniform, but also effectively improve the mechanical stability and mechanical properties of the material. In addition, this high-temperature process is equivalent to an "in-situ annealing" treatment of the polysilicon layer, which helps to further release the mechanical stress generated during the deposition process and reduce the residual stress inside the semiconductor structure, thereby reducing the risk of potential defects such as warping and cracking of the semiconductor structure caused by stress concentration.

[0066] As explained above, the polysilicon layer may be formed by a single vapor deposition, in which case the semiconductor structure includes only the first polysilicon layer, and the thickness of the first polysilicon layer is greater than or equal to 200 nm and less than or equal to 10 μm.

[0067] Alternatively, the polysilicon layer can also be formed by two vapor deposition processes, in which case the semiconductor structure includes a first polysilicon layer formed on the oxide film layer and a second polysilicon layer formed on the first polysilicon layer, wherein the thickness of the first polysilicon layer is greater than or equal to 200nm and less than or equal to 1μm, and the thickness of the second polysilicon layer is greater than or equal to 200nm and less than or equal to 10μm.

[0068] In the case where the semiconductor structure only includes the first polysilicon layer, the thickness of the first polysilicon layer is limited to more than 200nm and less than 10μm, which can ensure the controllability of the deposition process while taking into account the process adaptability and mechanical properties of the polysilicon layer. At the same time, this thickness range can form a stable polysilicon grain structure during the deposition process and improve the overall quality of the polysilicon layer.

[0069] In the case where the semiconductor structure includes a first polysilicon layer formed on an oxide film layer and a second polysilicon layer formed on the first polysilicon layer, the thickness of the first polysilicon layer is controlled to be greater than or equal to 200nm and less than or equal to 1μm, so that a uniform seed layer can be formed to provide a stable grain growth basis for the deposition of the second polysilicon layer. Setting the thickness of the second polysilicon layer to be greater than or equal to 200nm and less than or equal to 10μm can further meet the requirements of the thickness of the thin film layer, thereby enhancing the overall mechanical properties and interlayer bonding strength. The thickness division of this double-layer polysilicon design not only optimizes the deposition process, but also improves the performance and reliability of the thin film layer.

[0070] For the semiconductor structure including two polysilicon layers obtained by the manufacturing method for a semiconductor structure provided in the above embodiment, the mechanical stress of the semiconductor structure measured by SIRD 40 DU% is less than 40%.

[0071] Embodiment 1 Step S1, performing annealing treatment on the substrate at a temperature above 950° C. in a reaction chamber; Step S2, taking the annealed substrate out of the reaction chamber, and leaving the substrate to stand for more than 6 hours to form an oxide film layer of a predetermined thickness on the surface of the substrate; Step S3, when the temperature in the reaction chamber is above 700° C., forming a first polysilicon layer on the oxide film layer to manufacture a semiconductor structure, wherein the thickness of the first polysilicon layer is above 200 nm and below 10 μm.

[0072] See also Figure 4 , which shows a stress distribution cloud diagram of a semiconductor structure obtained by using the method provided in Example 1. Figure 2 and Figure 4It can be clearly seen that the semiconductor structure obtained by the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure has significantly smaller mechanical stress.

[0073] For the semiconductor structure obtained by the method for manufacturing a semiconductor structure provided in the first embodiment, the mechanical stress of the semiconductor structure measured by SIRD40 DU% is below 45%.

[0074] Embodiment 2 Step S1, performing annealing treatment on the substrate at a temperature above 950° C. in a reaction chamber; Step S2, taking the annealed substrate out of the reaction chamber, and leaving the substrate to stand for more than 6 hours to form an oxide film layer of a predetermined thickness on the surface of the substrate; Step S3, when the temperature in the reaction chamber is greater than 700° C. and less than 1050° C., vapor-depositing a first polysilicon layer on the oxide film layer, wherein the thickness of the first polysilicon layer is greater than 200 nm and less than 1 μm; Step S4, when the temperature in the reaction chamber is above 950° C. and below 1200° C., vapor depositing a first polysilicon layer on the first polysilicon layer to manufacture a semiconductor structure, wherein the thickness of the second polysilicon layer is above 200 nm and below 10 μm.

[0075] like Figure 5 As shown, it shows the stress distribution cloud diagram of the semiconductor structure obtained by the manufacturing method for the semiconductor structure including two deposition processes provided by the second embodiment. Figure 2 , Figure 4 and Figure 5 It can be clearly seen that, among the three methods, the semiconductor structure obtained by the method for manufacturing a semiconductor structure including two deposition processes obviously has the smallest mechanical stress.

[0076] For the semiconductor structure obtained by the method for manufacturing a semiconductor structure provided in the second embodiment, the mechanical stress of the semiconductor structure measured by SIRD40 DU% is below 40%.

[0077] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0078] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: performing an annealing process on the substrate in a reaction chamber; forming an oxide film layer of a predetermined thickness on the surface of the substrate after the annealing treatment; A first polysilicon layer is formed by vapor deposition on the oxide film layer of the substrate to manufacture a semiconductor structure.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The vapor deposition forming a first polysilicon layer on the oxide film layer of the substrate comprises: Etching the oxide film layer of the substrate using a reducing gas; The first polysilicon layer is formed by vapor deposition on the etched oxide film layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The thickness of the oxide film layer is greater than the etching amount of the reducing gas.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of forming an oxide film layer of a predetermined thickness on the surface of the substrate after the annealing treatment comprises: The annealed substrate is unloaded from the reaction chamber into a substrate container and left to stand for more than 6 hours.

5. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The thickness of the oxide film layer is greater than 5Å and less than 400nm.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The thickness of the oxide film layer is greater than 15Å and less than 50Å.

7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The temperature of vapor deposition corresponding to forming the first polysilicon layer is above 700° C.

8. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: After forming a first polysilicon layer by vapor deposition on the oxide film layer of the substrate, the manufacturing method further comprises: A second polysilicon layer is formed on the first polysilicon layer by vapor deposition.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The vapor deposition temperature corresponding to forming the second polysilicon layer is above 1000° C.

10. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The thickness of the first polysilicon layer is greater than 200 nm and less than 10 μm.

11. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The thickness of the first polysilicon layer is greater than or equal to 200 nm and less than or equal to 1 μm, and the thickness of the second polysilicon layer is greater than or equal to 200 nm and less than or equal to 10 μm.

12. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The temperature corresponding to the annealing treatment performed on the substrate is above 950°C.

Images