Low-noise optical fiber acquisition card based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a low-noise optical fiber acquisition card based on an FPGA (Field Programmable Gate Array). The low-noise optical fiber acquisition card comprises a power supply control protection circuit, a temperature monitoring protection circuit, an amplification filtering unit, an ADC (Analog to Digital Converter) data acquisition unit and an FPGA unit, one end of the power supply control protection circuit is connected with the power supply, and the other end is connected with the CPU; the CPU firstly controls the digital power supply to supply power to the FPGA unit, and then controls the analog power supply to supply power to the amplification filtering unit and the ADC data acquisition unit; the temperature monitoring protection circuit monitors the operating temperature of the FPGA and the power supply in real time; and the amplifying and filtering unit and the ADC data acquisition unit are used for processing the optical fiber sensing signal and sending the processed optical fiber sensing signal to the FPGA unit. According to the technical scheme in the embodiment of the invention, high-quality signal transmission and system safety protection are realized through cooperative work of all module units.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of optical fiber signal acquisition, and in particular to a low-noise optical fiber acquisition card based on FPGA. Background Art

[0002] Fiber optic sensing technology has been widely used in many fields such as the oil and gas industry, smart grid, structural health monitoring, and military security due to its advantages such as high sensitivity, anti-electromagnetic interference, high temperature resistance, and long-distance transmission. With the development of fiber optic sensing technology and the expansion of its fields, fiber optic sensing technology has increasingly higher requirements for signal quality, data acquisition speed, and real-time signal processing. FPGA has highly parallel processing capabilities and reconfigurability, and is suitable for high-speed data processing and real-time signal processing, becoming an indispensable part of fiber optic sensing.

[0003] However, in actual tasks, the longer the optical fiber distance, the weaker the signal. When processing signals of different strengths, the signal is often drowned by noise; in addition, in harsh environments, power failures or temperature anomalies often cause equipment damage, resulting in significant economic losses.

[0004] Therefore, how to ensure the security of the system while ensuring signal quality is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The embodiment of the present invention provides a low-noise optical fiber acquisition card based on FPGA, which realizes high-quality signal transmission and system safety protection.

[0006] In order to achieve the purpose of this application, the present application provides a low-noise fiber optic acquisition card based on FPGA, including a power control protection circuit, a temperature monitoring protection circuit, an amplification and filtering unit, an ADC data acquisition unit, and an FPGA unit; one end of the power control and protection circuit is connected to the power supply, and the other end is connected to the CPU; the CPU controls the digital power supply to power the FPGA unit, and the CPU controls the analog power supply to power the amplification and filtering unit and the ADC data acquisition unit;

[0007] The temperature monitoring protection circuit monitors the operating temperature of the FPGA and the power supply in real time;

[0008] The amplifying and filtering unit and the ADC data acquisition unit process the optical fiber sensing signal and send the processing result to the FPGA unit.

[0009] Furthermore, the digital power supply and the analog power supply are converted by an input power supply; the digital power supply and the analog power supply are isolated from each other by a common-mode filter circuit; the common-mode filter circuit is composed of a filter capacitor and a common-mode inductor.

[0010] Furthermore, an LDO unit and a filtering circuit are arranged after the common-mode filtering circuit; the CPU controls the analog power supply to supply power to the amplifying filtering unit and the ADC data acquisition unit after passing through the LDO unit and the filtering circuit.

[0011] Furthermore, the power startup process is as follows: after the power is connected, whether the power is normal is detected, and if the power is abnormal, the next level of power is not connected; if the power is normal, the next level of power is connected and the CPU is started, and the CPU controls the subsequent power to start step by step and detects the subsequent power; when the CPU detects that the subsequent power is abnormal, the CPU turns off the corresponding subsequent power;

[0012] The power supply anomaly includes: overvoltage and undervoltage.

[0013] Furthermore, the temperature monitoring protection circuit shuts down the power supply when the operating temperature of the power supply or FPGA exceeds a preset operating temperature range;

[0014] The preset operating temperature range includes: a preset maximum temperature and a preset minimum temperature.

[0015] Furthermore, the analog signal preprocessing circuit is composed of an ESD protection circuit, a voltage divider circuit, an impedance matching circuit and a follower circuit;

[0016] The voltage divider circuit adjusts the range of the optical fiber sensing signal through the voltage divider resistor; the impedance matching circuit provides selectable low-frequency impedance and high-frequency impedance.

[0017] Furthermore, the low noise amplifier circuit is composed of a configurable filter, a differential amplifier circuit and a differential filter circuit;

[0018] The configurable filter provides a selectable high-pass filter and a low-pass filter;

[0019] The differential amplifier circuit provides adjustable 1-20 times differential amplification;

[0020] The differential filter circuit is composed of a fourth-order differential filter.

[0021] Furthermore, the fourth-order differential filter is composed of a fourth-order improved LRC differential filter and an RC differential filter; wherein the fourth-order improved LRC differential filter is composed of two second-order LRC differential filters.

[0022] Furthermore, the optical fiber sensing signal is processed by the amplifying and filtering unit and then enters the ADC data acquisition unit. The ADC data acquisition unit and the AD9642 acquisition unit inside the FPGA unit acquire the data to the inside of the FPGA unit through an acquisition channel.

[0023] Furthermore, the sampling rate of the AD9642 acquisition unit inside the FPGA unit is 250Mhz.

[0024] Compared with the prior art, the FPGA-based low-noise fiber optic acquisition card provided by the present invention controls the power supply of the digital power supply and the analog power supply through the CPU to reduce the interference between the power supplies; further, the digital power supply and the analog power supply are isolated through the common-mode filtering circuit to ensure that the analog power supply is not affected by the fluctuation of the digital power supply; at the same time, the circuit is protected by monitoring the power supply and temperature of the system to ensure that the circuit and the equipment are not damaged; finally, the power supply noise is reduced and the signal quality is improved by the amplification and filtering unit.

[0025] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0027] Figure 1 It is a structural schematic diagram of a low-noise optical fiber acquisition card based on FPGA provided by the present invention;

[0028] Figure 2 It is a schematic diagram of a power supply circuit provided by the present invention;

[0029] Figure 3 This is a schematic diagram of a power supply startup monitoring protection structure provided by the present invention;

[0030] Figure 4 This is a schematic diagram of a temperature monitoring protection structure provided by the present invention;

[0031] Figure 5 It is a schematic diagram of the structure of an analog signal preprocessing and low-noise amplification circuit provided by the present invention;

[0032] Figure 6 It is a schematic diagram of the structure of an optimized fourth-order differential filter provided by the present invention;

[0033] Figure 7 It is a schematic diagram of an amplitude-frequency characteristic curve of a fourth-order differential filter provided by the present invention;

[0034] Figure 8 This is a schematic diagram of the internal structure of an FPGA provided by the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0036] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0037] The following describes the FPGA-based low-noise fiber optic acquisition card described in some embodiments of the present invention in conjunction with the accompanying drawings. For the convenience of description, the "FPGA-based low-noise fiber optic acquisition card" is referred to as the "fiber optic acquisition card" below.

[0038] Before the introduction of the embodiments of the present invention, the related technology has at least the following problems when performing low-noise signal acquisition:

[0039] 1. Depending on the fiber distance, the longer the fiber distance, the weaker the signal, and the higher the noise requirement for the acquisition card.

[0040] 2. Due to different fiber distances and laser powers, signal strengths are inconsistent. To process different signal strengths so that the signal is not submerged by noise, the ADC needs to be able to collect the maximum signal.

[0041] 3. Power supply and temperature monitoring are important parts of the system. It is necessary to ensure that the acquisition unit is not damaged in harsh environments to avoid major economic losses.

[0042] To this end, an embodiment of the present invention proposes a low-noise fiber optic acquisition card based on FPGA, which aims to at least solve the above-mentioned known problems.

[0043] Figure 1 A schematic diagram of the structure of a low-noise fiber optic acquisition card based on FPGA provided by the present invention, combined with Figure 1 An embodiment of the present invention provides a low-noise fiber optic acquisition card based on FPGA, including a power control protection circuit, a temperature monitoring protection circuit, an amplification and filtering unit, an ADC data acquisition unit, and an FPGA unit; one end of the power control protection circuit is connected to the power supply, and the other end is connected to the CPU.

[0044] Furthermore, the CPU controls the digital power supply to supply power to the FPGA unit, and the CPU controls the analog power supply to supply power to the amplifying and filtering unit and the ADC data acquisition unit; the temperature monitoring and protection circuit monitors the operating temperature of the FPGA and the power supply in real time; the amplifying and filtering unit and the ADC data acquisition unit process the optical fiber sensing signal and send the processing result to the FPGA unit.

[0045] The amplifying and filtering unit includes: an analog signal preprocessing circuit and a low-noise amplifying circuit.

[0046] Combination Figure 1 , Figure 2 and Figure 3 The power control protection circuit unit mainly controls the power startup sequence to ensure that the FPGA power-on timing requirements and signal acquisition are correct, and monitors the power supply. When the power supply is abnormal (overvoltage or undervoltage), it protects other onboard circuits to ensure that other circuits are not damaged.

[0047] Figure 2 A schematic diagram of a power supply circuit provided by the present invention, combined with Figure 2 The embodiment of the present invention provides a power supply solution, the power supply can support hot plugging, and the power supply is protected against reverse connection and overvoltage and undervoltage. When the power supply is connected to the positive and negative reverse connection, the subsequent circuit will be powered off through the anti-reverse connection circuit to protect the subsequent circuit. At the same time, if the connected voltage is greater than 13V or less than 10V, the over-voltage and undervoltage protection circuit will take effect. When the voltage is higher than 13V or lower than 10V, the over-voltage and undervoltage circuit considers that the power supply is abnormal, and will cut off the input main power supply to power off the subsequent circuit to protect the subsequent circuit.

[0048] Furthermore, the digital power supply and the analog power supply are converted by the input power supply; the digital power supply and the analog power supply are isolated from each other by using a common mode filter circuit; the common mode filter circuit is composed of a filter capacitor and a common mode inductor.

[0049] Combination Figure 2 , the embodiment of the present invention also provides a control scheme for digital power supply and analog power supply, the scheme is as follows: first, for the digital power supply part controlled by the chip STM32, first control the power supply from 1.0V to 1.2V to 1.8V to 1.5V to 2.5V to 3.3V to 5.0V to power on in sequence to ensure the normal startup of FPGA. After all the digital power supplies are normal, start the analog 3V power supply to enable the subsequent analog ±2.5V and analog 1.8V power supplies to start normally. At the same time, the analog power supply and the digital power supply are isolated from each other by using a common-mode filter circuit composed of a filter capacitor and a common-mode inductor to ensure that the analog power supply is not affected by the fluctuation of the digital power supply. The analog power supply uses an LDO linear power supply output, and the power ripple output by the LDO linear power supply is lower, which can be as low as 8mV, and the performance is more excellent.

[0050] Combination Figure 2The power control protection circuit unit in the embodiment of the present invention also provides power detection and protection functions. Figure 3 The implementation process of power supply detection and protection functions is described in detail.

[0051] Figure 3 This is a schematic diagram of a power supply startup monitoring protection structure provided by the present invention, combined with Figure 3 The implementation process of the power detection and protection function mentioned in the embodiment of the present invention is as follows: when the system (fiber optic acquisition card) is connected to the power supply, it is first detected whether the input power is normal. If the power supply is abnormal, the voltage will not be connected to the next level of power supply. Only when the power input is normal can the 12V power supply be sent to the next level, and then the CPU (STM32) is started. The CPU controls the subsequent power supplies to start step by step, and detects the output voltage until all the power supplies are turned on and the system works normally. When the CPU detects that the power supply of the subsequent stage is abnormal, the CPU will turn off the power supply of that stage, and the power supply status can be checked through the serial port. If there is a power supply abnormality, the location of the power supply abnormality can be accurately checked, which is convenient for maintenance.

[0052] Further, Figure 4 A schematic diagram of a temperature monitoring protection structure provided by the present invention, combined with Figure 4 The temperature monitoring protection circuit in the embodiment of the present invention is mainly used to monitor the power supply temperature and the FPGA temperature. When the power supply or FPGA temperature exceeds the normal operating temperature range, the power supply is shut down. The temperature monitoring protection circuit can protect the fiber optic acquisition card device from damage.

[0053] Figure 4 A schematic diagram of a temperature monitoring protection structure provided by the present invention, and specifically provides a temperature detection and protection scheme, the scheme is as follows: the temperature monitoring protection circuit can detect the operating temperature of the FPGA and the power supply in real time. When the ambient temperature is too high or there is a major problem with heat dissipation, the modules can be effectively protected from damage according to the configured maximum and minimum temperatures, especially after the fiber optic acquisition card is integrated into the system, it is avoided that after the system heat dissipation system is damaged, the fiber optic acquisition card is damaged due to excessive temperature, thereby causing high economic losses; at the same time, the temperature monitoring protection circuit can also output the temperature information of the FPGA and the power supply in real time by the CPU (STM32). After the system is integrated, the operating status of the fiber optic acquisition card can be observed at any time, and a quick response can be made when an abnormality of the fiber optic acquisition card is found.

[0054] Figure 5 A schematic diagram of an analog signal preprocessing and low noise amplification circuit structure provided by an embodiment of the present invention. Figure 5In the analog front-end preprocessing circuit, according to the strength of the input signal, an ESD protection circuit, a voltage divider circuit, an impedance matching circuit and a follower circuit are added to the input front end to form an analog front-end preprocessing circuit. The analog front-end preprocessing circuit can protect the back-end circuit from overvoltage damage and has a certain ability to resist electromagnetic interference (EMI).

[0055] Figure 5 In the process, the fiber optic sensing signal enters the fiber optic acquisition card through the SMA interface, is processed by the analog signal preprocessing circuit and the low-noise amplification circuit, and then is collected in high-speed parallel by the ADC data acquisition unit. The ADC data acquisition unit is connected to the AD9642 acquisition unit in the FPGA unit through a channel, and finally the fiber optic sensing signal is processed and stored inside the FPGA unit.

[0056] Further, combined with Figure 5 ,The analog signal preprocessing circuit is composed of an ESD protection circuit, a voltage divider circuit, an impedance matching circuit and a follower circuit.

[0057] ESD protection is "electrostatic discharge", which prevents electrostatic discharge from causing current heat (spark) effects (such as fire and explosion caused by static electricity) and electromagnetic effects (such as electromagnetic interference) on electronic equipment. There are two mechanisms for ESD to interfere with circuits: one is that the electrostatic discharge current directly passes through the circuit and causes damage to the circuit; the other is that the electromagnetic field generated by the electrostatic discharge current interferes with the circuit through capacitive coupling, inductive coupling or spatial radiation coupling.

[0058] The ESD protection circuit can effectively protect the analog front end from damage by electrostatic discharge, and has an effective protective effect against external crosstalk and pulse interference caused by the integrated system, thus avoiding damage to electronic equipment.

[0059] Furthermore, the voltage divider circuit adjusts the range of the optical fiber sensing signal through the voltage divider resistor.

[0060] A voltage divider circuit is set after the ESD protection unit. The voltage divider circuit processes the range of the front-end optical fiber sensor signal through the voltage divider resistor. The normal range of the front-end optical fiber sensor signal is -2.0V~+2.0V. If a wider range is required, it is adjusted to any range under -12V~+12V through the voltage divider resistor, such as -3.0V~+3.0V, -4.096V~+4.096V, -5.0V~+5.0V, etc., to ensure the access of optical fiber sensor signals of different ranges and have stronger system compatibility.

[0061] Furthermore, an impedance matching circuit is arranged after the voltage divider circuit, and the impedance matching circuit provides selectable low-frequency impedance and high-frequency impedance.

[0062] Impedance matching refers to a suitable matching method between a signal source or transmission line and a load. Impedance matching is divided into two cases: low frequency and high frequency. The impedance matching circuit in the embodiment of the present invention can provide 50Ω impedance matching or 1MΩ impedance matching. Impedance matching is mainly used to adjust load power and suppress signal reflection.

[0063] A follower circuit is set after the impedance matching circuit. The follower circuit can ensure the impedance matching between the front-end signal source and the load. The follower circuit is realized by a voltage follower. The bandwidth limitation of the voltage follower has a filtering effect on high-frequency out-of-band signals, thereby ensuring the quality of the signal.

[0064] The voltage follower is a common-collector circuit composed of triodes with a voltage gain of one. The common-collector circuit has a high input impedance and a low output impedance, which enables it to play an impedance matching role in the circuit and enable the subsequent amplifier circuit to work better.

[0065] Figure 5 A schematic diagram of the structure of an analog signal preprocessing and low noise amplification circuit provided by the present invention, combined with Figure 2 and Figure 5 In the low-noise amplifier circuit, the digital power supply is isolated through the common-mode filter circuit to reduce the power supply noise, and the power supply is supplied by the LDO power supply to further reduce the power supply noise, and then the signal quality is improved by signal amplification and filtering.

[0066] Furthermore, an LDO unit and a filtering circuit are arranged after the common-mode filtering circuit; the CPU controls the analog power supply to supply power to the amplifying filtering unit and the ADC data acquisition unit after passing through the LDO unit and the filtering circuit.

[0067] Combination Figure 2 After the analog power passes through the LDO and filter circuit, it provides ±2.5V voltage for the 1st, 2nd, 3rd, and 4th amplifiers and +1.8V voltage for the ADC. Figure 1 The four amplification and filtering modules in the ADC refer to Figure 1 The four ADC data acquisition units in the.

[0068] It should be noted that LDO (Low Dropout Regulator) is a low voltage dropout linear regulator. The structure of LDO low voltage dropout linear regulator mainly includes startup circuit, constant current source bias unit, enable circuit, adjustment element, reference source, etc. It has extremely low self-noise and high power supply rejection ratio.

[0069] Further, combined with Figure 5 , the low noise amplifier circuit is composed of a configurable filter, a differential amplifier circuit and a differential filter circuit.

[0070] The follower circuit in the analog signal preprocessing circuit is connected to the configurable filter in the low-noise amplifier circuit. The voltage follower can select a high-pass or low-pass configurable filter, so that the fiber optic acquisition card has stronger system adaptability.

[0071] A differential amplifier circuit is added after the high-pass or low-pass configurable filter to make the fiber optic acquisition card have stronger small signal detection capability. The differential amplifier circuit provides 1-20 times differential amplification capability and can be flexibly configured as needed. A fourth-order differential filter is provided after the differential amplifier circuit to ensure the signal quality within the passband.

[0072] A traditional fourth-order differential filter is a filter circuit consisting of four inductors L and four capacitors C. This filter can be used in a variety of applications, including RF communications, audio processing, and power supply filtering. A fourth-order differential filter can be realized by cascading two second-order LC filters. Each second-order LC filter consists of two inductors and two capacitors. By cascading two second-order filters, the selectivity and attenuation characteristics of the filter can be improved.

[0073] Furthermore, Figure 6 The present invention provides an optimized fourth-order differential filter structure schematic diagram, which can optimize the quality factor Q value of the filter, and its structure is composed of a fourth-order improved LRC differential filter and an RC differential filter. Among them, the fourth-order improved LRC differential filter is composed of two second-order LRC differential filters.

[0074] Combination Figure 6 In the fourth-order improved LRC differential filter, L1, L2, R1, R2, C1 and C2 together constitute the first second-order LRC differential filter, L3, L4, R3, R4, C3 and C4 constitute the second second-order LRC differential filter, and L1=L2, L3=L4, R1=R2, R3=R4, C1=C2, C3=C4.

[0075] In the RC differential filter, R5 and C5 form a low-pass filter, R6 and C5 also form a low-pass filter, and R5 and R6 form a matching resistor. The size of R5 and R6 directly affects the quality factor of the entire filter. R7, R8 and C6 form a second-order RC differential low-pass filter, and R5=R6, R7=R8.

[0076] At the same time, after many tests, the present invention provides a highly high-performance and feasible parameter data for the optimized fourth-order differential filter, so that the fourth-order differential filter has higher performance. Specifically, L1 = L2 = 56nH, R1 = R2 = 4.99Ω, C1 = C2 = 62pF, L3 = L4 = 120nH, R3 = R4 = 4.99Ω, C3 = C4 = 13pF, R5 = R6 = 49.9Ω, C3 = 0.1μF, R7 = R8 = 4.99Ω, C3 = 3.5pF. The amplitude-frequency characteristic curve of the optimized fourth-order differential filter is shown in Figure 7 Solid line.

[0077] Figure 7 is a schematic diagram of an amplitude-frequency characteristic curve of a fourth-order differential filter provided by an embodiment of the present invention, wherein the amplitude-frequency characteristic curve of the optimized fourth-order differential filter is as follows: Figure 7 As shown by the solid line in , the amplitude-frequency characteristic curve of the traditional fourth-order differential filter is as follows Figure 7 As shown by the dotted line in .

[0078] From the amplitude-frequency characteristic curve, it can be seen that the amplitude-frequency characteristic curve of the improved filter is relatively flat, which not only meets the performance of the low-pass filter, but also does not affect the signal amplitude near the cutoff frequency. It can also be seen that after exceeding the cutoff frequency, as the frequency increases, the amplitude-frequency characteristic decreases rapidly, which shows that the optimized filter has a high ability to suppress high-frequency noise. The quality factor of the traditional fourth-order differential filter is too high. Although the filtering performance is very good, it has a great impact on the signal amplitude near the cutoff frequency, which will cause serious distortion of the signal collected later.

[0079] Figure 8 This is a schematic diagram of the internal structure of an FPGA provided by the present invention, combined with Figure 5 and Figure 8 , the optical fiber sensing signal enters the ADC data acquisition unit after being processed by the analog signal preprocessing circuit and the low-noise amplifier circuit. The FPGA unit collects the data into the FPGA through the internal AD9642 acquisition unit. The sampling rate of the ADC data acquisition unit is 250Mhz. The ADC data acquisition unit uses the optical fiber sensing algorithm to parse the original signal into phase information and amplitude information. The AD9642 acquisition unit sends the data to the data processing unit, which processes the data and sends it to the data buffer unit. The data buffer unit sends the data to the DDR buffer and waits for the host to read the data into the host through the PCIE port for subsequent processing.

[0080] Combination Figure 1 and Figure 8, the FPGA unit uses a 250Mhz sampling rate high-speed AD9642 acquisition unit for data acquisition. The FPGA unit uses the xilinx@XC7Z045 platform, with 350K Logic Cells and 900 DSP Slices, which can perform a large amount of real-time parallel data processing. At the same time, it has 2 groups of DDR3, one group of DDR3 is 64-bit wide 1600Mhz, and one group of DDR3 is 32-bit wide 1333Mhz, which has the memory requirements for a large amount of real-time processing. The AD9642 acquisition unit processes the data according to the optical fiber sensing algorithm and sends it to the high-speed transmission channel. The FPGA unit has 1 PCIE x 8gen2 host interface, with a theoretical data transmission rate of up to 5GB / s, 1 10Gbps SFP+ external optical fiber serial network port, backward compatible with 2.5Gbps and 1Gbps optical network ports, 2 1GbpsRJ45 network ports, and has a fairly rich external interface.

[0081] In summary, the fiber optic acquisition card provided by the present invention, based on the FPGA with high-speed data processing, sets power protection and temperature protection to protect the system safety, ensure that the acquisition unit is not damaged in harsh environments, and isolates the analog power supply from the digital power supply through a common-mode filtering circuit to reduce interference between circuits, and then performs analog front-end preprocessing and low-noise amplification and filtering processing on the fiber optic sensor signal to eliminate pulse interference and ensure signal quality.

[0082] In the description of the embodiments of the present invention, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0083] In the description of this specification, the description of the terms "one embodiment", "some embodiments", "specific embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0084] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A low-noise fiber optic acquisition card based on FPGA, characterized in that: It includes a power control protection circuit, a temperature monitoring protection circuit, an amplifying and filtering unit, an ADC data acquisition unit, and an FPGA unit; one end of the power control protection circuit is connected to the power supply, and the other end is connected to the CPU; the CPU controls the digital power supply to supply power to the FPGA unit, and the CPU controls the analog power supply to supply power to the amplifying and filtering unit and the ADC data acquisition unit; The temperature monitoring protection circuit monitors the operating temperature of the FPGA and the power supply in real time; The amplifying and filtering unit and the ADC data acquisition unit process the optical fiber sensing signal and send the processing result to the FPGA unit.

2. The FPGA-based low-noise fiber acquisition card according to claim 1, characterized in that: The digital power supply and the analog power supply are converted by input power supply; the digital power supply and the analog power supply are isolated from each other by a common mode filter circuit; the common mode filter circuit is composed of a filter capacitor and a common mode inductor.

3. The FPGA-based low-noise fiber acquisition card according to claim 2, characterized in that: An LDO unit and a filter circuit are arranged after the common mode filter circuit; the CPU controls the analog power supply to supply power to the amplifying filter unit and the ADC data acquisition unit after the analog power supply passes through the LDO unit and the filter circuit.

4. The FPGA-based low-noise fiber acquisition card according to claim 1, characterized in that: The power startup process is as follows: after the power is connected, check whether the power is normal. If the power is abnormal, do not connect the next level of power; if the power is normal, connect the next level of power and start the CPU. The CPU controls the subsequent power to start step by step and detect the subsequent power; when the CPU detects that the subsequent power is abnormal, the CPU turns off the corresponding subsequent power; The power supply anomaly includes: overvoltage and undervoltage.

5. The FPGA-based low-noise fiber acquisition card according to claim 1, characterized in that: The temperature monitoring protection circuit shuts down the power supply when the operating temperature of the power supply or the FPGA exceeds a preset operating temperature range; The preset operating temperature range includes: a preset maximum temperature and a preset minimum temperature.

6. The FPGA-based low-noise fiber acquisition card according to claim 1, characterized in that: The amplification and filtering unit includes: an analog signal preprocessing circuit and a low-noise amplification circuit; wherein the analog signal preprocessing circuit is composed of an ESD protection circuit, a voltage divider circuit, an impedance matching circuit and a follower circuit; The voltage divider circuit adjusts the range of the optical fiber sensing signal through the voltage divider resistor; the impedance matching circuit provides selectable low-frequency impedance and high-frequency impedance.

7. The FPGA-based low-noise fiber acquisition card according to claim 1, characterized in that: The amplification and filtering unit comprises: an analog signal preprocessing circuit and a low-noise amplification circuit; wherein the low-noise amplification circuit is composed of a configurable filter, a differential amplification circuit and a differential filtering circuit; The configurable filter provides a selectable high-pass filter and a low-pass filter; The differential amplifier circuit provides adjustable 1-20 times differential amplification; The differential filter circuit is composed of a fourth-order differential filter.

8. The FPGA-based low-noise fiber acquisition card according to claim 7, characterized in that: The fourth-order differential filter is composed of a fourth-order improved LRC differential filter and an RC differential filter; wherein the fourth-order improved LRC differential filter is composed of two second-order LRC differential filters.

9. The FPGA-based low-noise fiber acquisition card according to claim 1, characterized in that: The optical fiber sensing signal is processed by the amplifying and filtering unit and then enters the ADC data acquisition unit. The ADC data acquisition unit and the AD9642 acquisition unit inside the FPGA unit collect data into the inside of the FPGA unit through an acquisition channel.

10. The FPGA-based low-noise fiber acquisition card according to claim 9, characterized in that: The sampling rate of the AD9642 acquisition unit inside the FPGA unit is 250Mhz.

Images