Encoder speed monitoring device

Abstract

A rotational speed monitoring apparatus includes a second MCU (4b) that outputs a second count value (C2) of which the counter is reset by a Z-phase signal. The second MCU (4b) includes: a phase count counter (6b) that counts an A-phase signal and a B-phase signal and outputs a counting result as a basic count value (Cb); a first capture circuit (7b) that latches the basic count value (Cb) in a capture period (Ts) and outputs the latched value as a position count value (Cp); a second capture circuit (7c) that latches the basic count value (Cb) at the active edge of the Z-phase signal and outputs the latched value as a reference count value (Cz); and a second counter calculation unit (9) that calculates a second count value (C2) on the basis of the position count value (Cp) and the reference count value (Cz).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Japanese Patent Application No. 2023-182433 filed on October 24, 2023, the entire contents of which (including specification, claims, drawings, and abstract) are incorporated herein by reference. Technical Field

[0003] This specification discloses a speed monitoring device using an encoder that outputs a signal having a phase difference according to a rotation angle. Background Art

[0004] Regarding the spindle of a machine tool, international standards require speed limit monitoring functions. For example, regarding the spindle of a lathe, ISO23125 requires speed limit monitoring to be implemented in safety category 3.

[0005] Generally, the speed detector for the machine tool spindle is classified into a type such as a magnetic encoder (hereinafter referred to as "encoder"), which can output cosine and sine signals with a wave number N per revolution and a phase difference of 90 degrees according to the rotation angle. Generally, these signals are called A-phase signal and B-phase signal.

[0006] When the encoder is used to perform speed monitoring, the count value of the phase difference counter that performs quadruple pulse counting based on the phase difference between the A-phase signal and the B-phase signal is usually referenced, and the difference in the value between the speed monitoring cycles is used. That is, the safety controller that performs speed monitoring samples the count value of the phase difference counter in each monitoring cycle T and calculates the monitoring speed V, which is defined as V = (P(n)-P(n-1)) / (T×4×N), where P(n) represents the current count value and P(n-1) represents the previous count value. Therefore, in order to ensure the accuracy of speed monitoring using the phase difference counter, the single-turn wave number N set for the phase difference counter needs to be equal to the actual single-turn wave number N of the encoder. For example, in safety communications that ensure the reliability of communication data through a protocol, sampling of the phase difference counter by the safety controller can be performed.

[0007] Furthermore, in order to implement speed monitoring using the encoder in safety category 3, two phase difference counters with different components are required to compare the respectively calculated speeds (i.e., the difference in pulse counts) and perform cross monitoring. Furthermore, the encoder is usually accompanied by a marker signal that outputs one pulse per revolution, which is called a Z-phase signal, to identify the position within one revolution. Furthermore, one of the phase difference counters may be a single-turn counter cleared by the Z-phase signal, and the other may be a multi-turn counter that counts up and down the Z-phase signal.

[0008] Further, calculation is performed to obtain the speed of the phase difference counter based on the combination of the single-turn counter and the multi-turn counter using the Z phase signal, and the speed of the phase difference counter based on the phase difference counter not using the Z phase signal. Then, the two obtained speeds are compared to confirm whether the single-turn wave number of the encoder is correct.

[0009] Non-patent document 1 discloses an exemplary counter using a Z-phase signal. The counter disclosed in non-patent document 1 is a microcontroller unit (hereinafter referred to as "MCU"), which has the function of clearing a single-turn counter at a rising edge of a Z-phase signal and counting up and down a multi-turn counter according to an instantaneous up- or down-counting direction of the single-turn counter.

[0010] Furthermore, Patent Document 1 discloses a method for realizing counter clearing of a single-turn counter and incrementing and decrementing of a multi-turn counter based on the logic level of the Z-phase signal rather than on the edge of the Z-phase signal and the rising or falling edge of the A-phase signal and the B-phase signal.

[0011] Reference List

[0012] Patent Literature

[0013] Patent Document 1: JP2009-153335A

[0014] Non-patent literature

[0015] Non-patent literature 1: “32-Bit Microcontroller FM0+Family Peripheral Manual Timer Part”, Cypress Semiconductor Corporation, September 9, 2020

[0016] According to the counter implemented in the general MCU disclosed in Non-Patent Document 1, when only the Z-phase signal vibrates without accompanying changes in the A-phase signal and the B-phase signal, for example, when the Z-phase signal vibrates at an angle where the edge changes, it is not feasible to accurately perform speed monitoring because the multi-turn counter repeatedly counts up or down. Figure 3 For example, if vibrations of less than 1 count continue around the edge of the Z-phase signal after forward rotation, the multi-turn counter will repeatedly count up at each rising edge of the Z-phase signal.

[0017] Furthermore, when the pulse width of the Z-phase signal is wide, an error is generated in speed monitoring when switching the rotation direction, and its amount corresponds to the pulse width count. Figure 4 An exemplary timing diagram of the Z-phase signal after switching from forward to reverse rotation is illustrated. Figure 4In the example, during the forward rotation, the rising edge of the Z phase (see Figure 4 (a) in the figure) and the rising edge of phase Z during the inversion period (see Figure 4 There is a deviation corresponding to 6 counts between (b) in FIG. 1 and (c) in FIG. 1. Therefore, at the first Z-phase rising edge after the rotation direction changes, a deviation corresponding to 6 counts may occur between the phase difference counter using the Z-phase signal and the phase difference counter not using the Z-phase signal. These factors lead to inconsistency in the count value difference with the phase difference counter not using the Z-phase signal, so the safety controller may erroneously detect an abnormality in the speed monitoring interface.

[0018] In addition, according to the counter circuit described in Patent Document 1, the multi-turn counter and the single-turn counter can be accurately configured using the Z-phase signal. However, this counter circuit is not installed in a general-purpose MCU. Therefore, in order to implement a counter equivalent to the counter disclosed in Patent Document 1 using a general-purpose MCU, a complex logic circuit must be added outside the MCU, which leads to increased costs and an increased probability of dangerous failure per hour (PFHD). Note that the frequency of the A-phase signal and the B-phase signal may exceed 100kHz, and it is difficult to simply replace the processing equivalent to the processing of the counter circuit disclosed in Patent Document 1 with the software processing of the MCU. Summary of the invention

[0019] The rotation speed monitoring device disclosed in the present specification is a rotation speed monitoring device for monitoring the rotation speed of an object, characterized in that it includes: an encoder, which outputs an A-phase signal of N pulses per revolution, a B-phase signal that is 90 degrees out of phase with the A-phase signal, and a Z-phase signal of 1 pulse per revolution; a first unit, which is configured to output a first count value by quadruple phase counting based on the A-phase signal and the B-phase signal; a second unit, which is configured to calculate a second count value, which is composed of a single-turn count value obtained by clearing a counter to a count value obtained by quadruple phase counting based on the A-phase signal and the B-phase signal according to the Z-phase signal, and a multi-turn count value obtained by counting the Z-phase signal incrementally or incrementally according to the rotation direction; and a safety controller, which calculates a first monitoring speed based on a change in the first count value, calculates a second monitoring speed based on a change in the second count value, and determines whether there is a speed abnormality based on a comparison result between the first monitoring speed and the second monitoring speed. The second unit includes: a phase count counter that performs quadruple phase counting of the A-phase signal and the B-phase signal and outputs the counting result as a basic count value; a first capture circuit that latches the basic count value in a capture period and outputs the latched value as a position count value, the capture period being a value obtained by dividing the speed monitoring period by a positive integer; a second capture circuit that latches the basic count value at a valid edge of the Z-phase signal and outputs the latched value as a reference count value; and a second counter calculation unit that is configured to calculate a second count value based on the position count value and the reference count value. The second counter calculation unit calculates a reference count correction value corresponding to a difference between the basic count value and the reference count value at a reference position of the Z-phase signal based on a current value of the reference count value, a previous value of the reference count value, and a previous value of the reference count correction value, calculates a reference count estimate value by adding the reference count correction value to the reference count value, counts up or down the multi-turn count value based on a magnitude relationship between the current value of the position count value, the previous value of the position count value, and the reference count estimate value, and calculates a difference between the position count value and the reference count estimate value as a single-turn count.

[0020] According to the technology disclosed in this specification, a phase difference counter based on a Z-phase signal can be constructed by using a general-purpose MCU, and speed monitoring can be configured inexpensively, which includes confirming the consistency between the single-turn wave number set value in the speed monitoring and the actual single-turn wave number of the encoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments of the present invention will be described based on the following drawings, in which:

[0022] Figure 1 is a block diagram illustrating a speed monitoring device;

[0023] Figure 2is a flow chart illustrating an exemplary calculation method for a multi-turn counter and a single-turn counter;

[0024] Figure 3 is a timing diagram illustrating the problems of a conventional multi-turn counter;

[0025] Figure 4 is a timing diagram illustrating the problem of a conventional phase difference counter; and

[0026] Figure 5 It is an example Figure 1 Timing diagram of the counter operation in the illustrated speed monitoring device. DETAILED DESCRIPTION

[0027] In the case of a duplex phase difference counter using different elements, the inconsistency of the change timing may occur between the count values ​​due to the difference in signal delay time, etc. Therefore, it is necessary to allow the inconsistency of the difference between the count values ​​of the duplex counter within the range where the speed monitoring is not adversely affected. When the counting method of the phase difference counter is 1x, the allowable inconsistency is 1 count or less, which is the minimum resolution; that is, 1 wave number or less. Even in the case where the counting method of the phase difference counter is 4x, if the allowable inconsistency is set to a value equivalent to that in the counting method of 1x in terms of resolution, the inconsistency of the difference between the count values ​​of 1 wave number or less (that is, 4 counts or less) in the duplex counter will be allowed. Therefore, the phase difference counter mounted on the general MCU is configured to perform calculations as a phase difference counter combining a multi-turn counter and a single-turn counter using the Z-phase signal based on the position count value sampled in each speed monitoring cycle and the reference count value sampled at the valid edge of the Z-phase signal, and the error of the phase difference counter that does not use the Z-phase signal due to software processing is less than 4 counts (less than 1 wave number) in the difference corresponding to the speed monitoring cycle.

[0028] Will refer to Figure 1 and Figure 2 To describe the speed monitoring equipment. Figure 1 is a block diagram illustrating an exemplary configuration of a speed monitoring device. Figure 2 is a flow chart illustrating an exemplary calculation method for a multi-turn counter and a single-turn counter performed by a speed monitoring device.

[0029] Figure 1The encoder 1 outputs an A-phase signal with a wave number of N per revolution, a B-phase signal with a phase difference of 90 degrees relative to the A-phase signal, and a Z-phase signal with one pulse per revolution according to the rotation angle of the object (not illustrated). The Z-phase signal is a signal with an effective level at a predetermined reference position, which is determined to be a unique position per revolution. The A-phase signal is level-converted and pulsated by the pulsation circuit 2a, and is input to the first MCU 4a and the second MCU 4b as an A-phase pulse signal. Similarly, the B-phase signal is level-converted and pulsated by the pulsation circuit 2b, and is input to the first MCU 4a and the second MCU 4b as a B-phase pulse signal. Further, the Z-phase signal is level-converted and pulsated by the pulsation circuit 2c, and is input to the second MCU 4b as a Z-phase pulse signal. The first MCU 4a is a microcontroller unit, which includes a phase counting counter 6a, a capture circuit 7a, and a first counter calculation unit 8 used as a peripheral device. Similarly, the second MCU 4b is a microcontroller unit, which includes a phase count counter 6b, first and second capture circuits 7b and 7c, and a second counter calculation unit 9. Each of the phase count counters 6a and 6b has the ability of phase counting. Each of the capture circuits 7a, 7b and 7c captures the count value of the counter based on at least two external signals. These microcontroller units are available from various products on the market. The first MCU 4a generates a first count value C1 that is not cleared by the Z-phase pulse signal for the count value obtained by phase counting the A-phase pulse signal and the B-phase pulse signal, and outputs the generated first count value C1 to the safety controller 10 in each speed monitoring cycle. The second MCU 4b obtains the single-turn count value Cs cleared by the Z-phase pulse signal and the multi-turn count value Cm for counting the Z-phase pulse signal from the count value (hereinafter referred to as "basic count value Cb") obtained by phase counting the A-phase pulse signal and the B-phase pulse signal. Further, the second MCU 4b outputs the single-turn count value Cs and the multi-turn count value Cm to the safety controller 10 as the second count value C2 in each speed monitoring cycle. By using the number of waves per revolution N, the second count value C2 can be converted into a count value in the same format as the first count value C1. The number of waves per revolution N is set and stored in the safety controller 10. For example, safety communication for taking measures against transmission errors will be used to output the first count value C1 and the second count value C2 from the first MCU 4a and the second MCU 4b to the safety controller 10.

[0030] The first speed monitoring unit 11 of the safety controller 10 performs speed monitoring using the change amount ΔC1 of the first count value C1 per speed monitoring cycle T and the single-turn count setting value N' of the encoder 1 pre-set in the safety controller 10, wherein the first monitoring speed V1 is calculated as V1=ΔC1 / N'. The single-turn count setting value N' is the count value of the phase count when the encoder 1 makes one full rotation. In the case of 4x phase counting, using the number of waves per revolution N, the single-turn count setting value N' is given as N'=4×N.

[0031] Similarly, the second speed monitoring unit 12 of the safety controller 10 uses the change ΔC2 of the second count value C2 per speed monitoring cycle T and the preset single-turn count setting value N' of the encoder 1 to perform speed monitoring, wherein the second monitoring speed V2 is calculated as V2 = ΔC2 / N'. The second count value C2 is converted into a count value of the same format as that in the case where the counter is cleared by the Z-phase signal, and is used for the calculation of ΔC2. This conversion is performed by applying the multi-turn count value Cm and the single-turn count value Cs to the following equation (1).

[0032] C2=(Cm+F)×N'+Cs (1)

[0033] Here, F takes the value 0 when the single-turn count value Cs is 0 or positive, and takes the value 1 when it is negative. The first speed monitoring unit 11 and the second speed monitoring unit 12 exchange the change amount ΔC1 of the first count value C1 and the change amount ΔC2 of the second count value C2, and if |ΔC1-ΔC2| is equal to or greater than the predetermined abnormality detection threshold, the abnormality of the speed monitoring interface is detected. The abnormality detection threshold can be set to, for example, 4 counts; that is, a count value corresponding to 1 wave number. This makes it possible to detect an abnormality when the single-turn wave number N of the encoder 1 is inconsistent with the single-turn wave number setting value N'.

[0034] The phase count counter 6a of the first MCU 4a is a counting circuit that performs quadruple phase counting using an A-phase pulse signal and a B-phase pulse signal. The A-phase pulse signal and the B-phase pulse signal can be de-noised by noise filters 5a and 5b before being input to the phase count counter 6a. The capture circuit 7a detects the valid edge of the capture timing signal output by the capture timing generation unit 3 described below, and latches the count value of the phase count counter 6a. The capture timing signal can be de-noised by a noise filter 5c before being input to the capture circuit 7a.

[0035] The first counter calculation unit 8 performs a predetermined interrupt processing each time the capture circuit 7a latches a count value. As an interrupt processing, the first counter calculation unit 8 makes the count value latched by the capture circuit 7a consistent with the bit width M' of the first count value C1 required by the safety control device 10, and outputs the consistent value as the first count value C1 to the safety controller 10 in each speed monitoring cycle.

[0036] The consistency of the bit width is performed by software processing. If M≥M', the first counter calculation unit 8 extracts the lower M' bits from the bit width M of the phase count counter 6a. Further, in the case of M<M', the first counter calculation unit 8 detects overflow or underflow according to the change of the count value latched by the capture circuit 7a, and increments the (M'-M)-bit extension counter by +1 when overflowing, and decrements it by -1 when underflowing. Although not illustrated, the first counter calculation unit 8 is a microcomputer including various memories, computing devices (i.e., processors), etc. required to perform software processing.

[0037] The phase count counter 6b of the second MCU 4b is a counting circuit that performs quadruple phase counting using an A-phase pulse signal and a B-phase pulse signal. The A-phase pulse signal and the B-phase pulse signal can be de-noised by noise filters 5d and 5e before being input to the phase count counter 6b. The first capture circuit 7b detects the effective edge of the capture timing signal output by the capture timing generation unit 3, and latches the count value of the phase count counter 6b. The capture timing signal can be de-noised by a noise filter 5f before being input to the first capture circuit 7b. The second capture circuit 7c detects the effective edge of the Z-phase pulse signal, and latches the count value of the phase count counter 6b. The Z-phase pulse signal can be de-noised by a noise filter 5g before being input to the second capture circuit 7c.

[0038] The second counter calculation unit 9 performs interrupt processing every time the first capture circuit 7b latches a count value. As an interrupt processing, the second counter calculation unit 9 performs the software processing described below based on the position count value Cp latched by the first capture circuit 7b and the reference count value Cz latched by the second capture circuit 7c to calculate the single-turn count value Cs and the multi-turn count value Cm. Then, the second counter calculation unit 9 outputs the single-turn count value Cs and the multi-turn count value Cm to the safety controller 10 as the second count value C2 in each speed monitoring cycle. Although not illustrated, the second counter calculation unit 9 is a microcomputer including various memories, computing devices (i.e., processors), etc. required to perform software processing.

[0039] The capture timing generation unit 3 is a circuit that generates and outputs a capture timing signal indicating a capture period Ts. The capture period Ts is a value that satisfies Ts=T / INT (where INT is a positive integer) for the speed monitoring period T. Further, the capture period Ts is a value that is pre-set to be shorter than the period of the Z-phase signal when the encoder 1 rotates at the maximum speed. Figure 1 The capture timing generation unit 3 is illustrated as a component independent of the first MCU 4a and the second MCU 4b, but it does not have to be an independent component. For example, the first MCU 4a or the second MCU 4b may be configured to output a capture timing signal.

[0040] In the following, reference will be made to Figure 2 The flowchart of FIG. 1 describes an exemplary process performed by the second counter calculation unit 9. As described above, Figure 2 The processing of the flowchart illustrated in is started at each count latch of the first capture circuit 7b (i.e., at each capture cycle Ts). In the following description, Cp(n) represents the current value of the position count value Cp obtained by latching, and Cp(n-1) represents the previous value. Other parameters will be expressed in the same way.

[0041] In step S901, the position count value Cp(n) is acquired from the first capture circuit 7b by 0 extension, and the reference count value Cz(n) is acquired from the second capture circuit 7c. In addition, the previous values ​​of the position count value Cp(n) and the reference count value Cz(n) are acquired from the memory by 0 extension as the previous position count value Cp(n-1) and the previous reference count value Cz(n-1). Then, the process proceeds to step S902.

[0042] Step S902 is a correction process for eliminating the discontinuity of Cp(n), Cz(n), Cp(n-1), and Cz(n-1) caused by overflow or underflow of the phase count counter 6b in step S903 and subsequent processes. Specifically, the corrected position count value Cp'(n), the corrected previous position count value Cp'(n-1), the corrected reference count value Cz'(n), and the corrected previous reference count value Cz'(n-1) are calculated using the following equations. Then, the process proceeds to step S903.

[0043] Cp'(n)=Cp(n)+f×f1×2 M

[0044] Cp'(n-1)=Cp(n-1)+f×f2×2 M

[0045] Cz'(n)=Cz(n)+f×f3×2 M

[0046] Cz'(n-1)=Cz(n-1)+f×f4×2 M

[0047] Here, M represents the bit width of the phase count counter 6b, and f is a flag indicating the implementation of the correction process. At least one of the above count values ​​Cp(n), Cz(n), Cp(n-1), and Cz(n-1) is used in the determination. If the count value used in the determination is not greater than the lower threshold or not less than the upper threshold, f is 1, otherwise it is 0. Regarding the threshold, the bit width M can be used to set the lower threshold to 2 M / 4, and set the upper threshold to 2 M ×3 / 4. If Cp(n) is equal to or less than the determined value, f1 is 1, and if it is greater than the determined value, it is 0. Similarly, if Cp(n-1) is equal to or less than the determined value, f2 is 1, and if it is greater than the determined value, it is 0. If Cz(n) is equal to or less than the determined value, f3 is 1, and if it is greater than the determined value, it is 0. If Cz(n-1) is equal to or less than the determined value, f4 is 1, and if it is greater than the determined value, it is 0. When the bit width M is used, the determined value can be set to, for example, 2 (M-1) The above-described method of setting the lower threshold value, the upper threshold value, and the determination value is merely an example and may be changed appropriately.

[0048] Step S903 is a process of using the Z-phase pass flag to determine whether the multi-turn count value Cm has been counted up or down once. If the Z-phase pass flag is OFF, the process proceeds to step S904. If it is ON, the process proceeds to step S911. The Z-phase pass flag is turned OFF in the initialization process (not illustrated).

[0049] Steps S904 to S910 are processes to be performed when the multi-turn count value Cm has never been counted up or down. Here, when it is considered that the Z-phase signal has passed the reference position, the multi-turn count value Cm is counted up or down. The reference position of the Z-phase signal is determined based on the logic levels of the A-phase pulse signal, the B-phase pulse signal, and the Z-phase pulse signal. For example, the reference position of the Z-phase signal is a position where the A-phase pulse signal is at an L level, the B-phase pulse signal is at an L level, and the Z-phase pulse signal is at an H level when the Z-phase pulse signal is a valid H signal.

[0050] Step S904 is for acquiring a state indicating whether the latch operation of the phase count counter 6b has been performed (even once) from the second capture circuit 7c in response to the valid edge of the Z-phase pulse signal. If the latch operation has been performed, the process proceeds to step S905. If not, the process proceeds to step S910.

[0051] Steps S905 and S907 are processes for determining whether the Z-phase signal has passed the reference position. In this example, when there is a large advance of more than two counts after the active edge of the Z-phase signal is detected, it is considered that the reference position has been passed. Therefore, when the relationship Cp’(n)>Cz’(n)+2≥Cp’(n - 1) is satisfied, it is determined that the reference position has been passed in the forward rotation direction. As described above, the reference count value Cz is a value obtained by latching the basic count value Cb when the active edge of the Z-phase signal has been detected. Therefore, Cz’(n) is the basic count value Cb when the active edge of the Z-phase signal was most recently detected.

[0052] If the result in step S905 is yes, the process proceeds to step S906, where the reference count correction value Zc(n) is set to +2, and the multi-turn count value Cm is set to +1. On the other hand, if the result in step S905 is no, the process proceeds to step S907, where when the relationship Cp’(n)<Cz’(n)-2≤Cp’(n - 1) is satisfied, it is determined that the reference position has been passed in the reverse rotation direction, and then the process proceeds to step S908. In step S908, the reference count correction value Zc(n) is set to -2, and the multi-turn count value Cm is set to -1. Step S909 is a common process to be executed after the processes of steps S906 and S907 when it is considered that the Z-phase signal has passed the reference position. In step S909, the Z-phase pass flag is turned ON, and the reference count estimated value Czc is set to the value obtained by adding the reference count value Cz’(n) and the reference count correction value Zc(n).

[0053] Here, the reference count correction value Zc(n) is a correction value for correcting the difference between the basic count value Cb (i.e., the reference count value Cz) at the active edge of the Z-phase pulse signal and the basic count value Cb at the true Z-phase reference position. Further, the reference count estimated value Czc is the basic count value Cb at the estimated Z-phase reference position. As described above, the true Z-phase reference position is determined based on the logic levels of the A-phase pulse signal, B-phase pulse signal, and Z-phase pulse signal. For example, when the Z-phase pulse signal is a valid H signal, the true Z-phase reference position is, for example, the position where the A-phase pulse signal is at the L level, the B-phase pulse signal is at the L level, and the Z-phase pulse signal is at the H level.

[0054] Step S910 is a process for clearing the reference count correction value Zc(n), the reference count estimated value Czc, and the Z-phase pass flag when it is considered that the Z-phase signal has never passed the reference position.

[0055] Steps S911 to S920 are processes to be executed after it is considered that the Z-phase signal has passed the reference position (even once). Steps S911 to S915 are processes for updating the reference count correction value Zc(n). Specifically, when the relation Cz’(n) - Cz’(n - 1) > 6 is satisfied, it is determined that the valid edge of the Z-phase signal has passed in the forward rotation direction, and Zc(n) = +2 is set. When the relation Cz’(n) - Cz’(n - 1) < -6 is satisfied, it is determined that the valid edge of the Z-phase signal has passed in the reverse rotation direction, and Zc(n) = -2 is set. In other cases, it is determined that the rotation direction has changed and the valid edge of the Z-phase signal has passed or not passed, and Zc(n) = Zc(n - 1) - Cz’(n) + Cz’(n - 1) is set.

[0056] Here, Zc(n - 1) is the previous value of the reference count correction value Zc(n), and the value stored in the memory is obtained. Further, the reference value "6" used in the determination is the maximum value of the difference between the basic count value Cb at the valid edge of the Z-phase pulse signal and the basic count value Cb at the non-valid edge of the Z-phase pulse signal. In other words, the reference value "6" is the count value corresponding to the maximum pulse width of the Z-phase pulse signal. If the maximum width of the Z-phase pulse signal exceeds the value corresponding to 6 counts, there will be multiple reference positions based on the logic levels of the A-phase pulse signal, B-phase pulse signal, and Z-phase pulse signal, regardless of the phase relationship between the A-phase pulse signal, B-phase pulse signal, and Z-phase pulse signal. Therefore, the maximum width of the Z-phase pulse signal always corresponds to a value of 6 counts or less.

[0057] Step S916 is for setting the reference count estimated value Czc to the value obtained by adding the reference count value Cz’(n) and the reference count correction value Zc(n), and then the process proceeds to S917.

[0058] Steps S917 to S920 are processes for incrementing or decrementing the multi-turn count value Cm. Specifically, when the relation Cp’(n) ≥ Czc > Cp’(n - 1) is satisfied, it is determined that the Z-phase signal has passed the reference position in the forward rotation direction, and the multi-turn count value Cm is incremented. When the relation Cp’(n) < Czc ≤ Cp’(n - 1) is satisfied, the multi-turn count value Cm is decremented.

[0059] Step S921 is a process for calculating the single-turn count value Cs, where the single-turn count value is set to the value obtained by subtracting Czc from Cp’(n).

[0060] Step S922 is for storing the position count value Cp(n), the reference count value Cz(n), and the reference count correction value Zc(n) as previous values ​​in the memory so that these values ​​can be referenced when the next process starts.

[0061] Here, as described above, the safety controller 10 determines whether there is a speed abnormality based on the difference between the change amount ΔC1 of the first count value C1 and the change amount ΔC2 of the second count value C2 (i.e., |ΔC1-ΔC2|). When the basic count value Cb of the real Z-phase reference position is the "real reference count value Cz*", the difference |ΔC1-ΔC2| is equal to the value obtained by adding the change amount of the error ΔCz=|Czc-Cz*| between the reference count estimate value Czc and the real reference count value Cz* and the difference ±1 between the count values ​​captured by the capture circuit 7a and the first capture circuit 7b. For example, the difference in the captured value occurs due to the difference in the delay time between the internal signals of the first MCU 4a and the second MCU 4b.

[0062] The error ΔCz is determined based on the reference count correction value Zc(n) and the pulse width of the Z-phase pulse signal. That is, the difference between the basic count value Cb (reference count value Cz) when the effective edge of the Z-phase pulse signal has passed in the forward direction and the basic count value Cb of the actual Z-phase reference position (i.e., the actual reference count value Cz*) is set to w1, and the difference between the reference count value Cz when it has passed in the reverse direction and the actual reference count value Cz* is set to -w2. In this case, the error ΔCz when the effective edge of the Z-phase pulse signal has passed in the forward direction is w1-2. In addition, the error ΔCz when the effective edge of the Z-phase pulse signal has passed in the reverse direction is -w2+2. Therefore, when w=w1+w2, the change in ΔCz is at most |w-4|, as shown in Equation 2.

[0063] |Change in ΔCz|=|(w1-2)-(-w2+2)|=|w-4|(2)

[0064] Here, w=w1+w2 is a value obtained by converting the pulse width at the effective level of the Z-phase pulse signal into the count value of the phase count counter 6b. As described above, the maximum value of w is 6. Under the condition that the logic level range of the A-phase pulse signal and the B-phase pulse signal is included in the case where the effective level of the Z-phase pulse signal is the true Z-phase reference position, the minimum value of w is 2. Therefore, according to equation (2), the change in ΔCz of the speed monitoring period Ts falls within the range of ±2. Therefore, the difference between ΔC1 as the change in the first count value C1 and ΔC2 as the change in the second count value C2 falls within the range of ±3.

[0065] Therefore, the second counter calculation unit 9 is configured to perform Figure 2 The above-mentioned processing illustrated in , makes it possible to suppress the difference between ΔC1 as the change amount of the first count value C1 and ΔC2 as the change amount of the second count value C2 to be equal to or less than 4 counts, which is less than the equivalent of one wave number, in the speed monitoring period Ts. Therefore, the safety controller 10 can perform speed monitoring without erroneously detecting an abnormality of the speed monitoring interface.

[0066] For example, Figure 5 is an exemplary timing diagram illustrating an exemplary passage of the Z-phase signal in the following order when the wave number N=25 and the Z-phase signal pulse width is equivalent to 6 counts:

[0067] [1] Forward direction, two or more times (not shown)

[0068] [2] Forward direction ( Figure 5 Between (a) and (b)

[0069] [3] Reverse direction ( Figure 5 (between (c) and (d))

[0070] [4] Reverse direction ( Figure 5 between (e) and (f)).

[0071] exist Figure 5 In order to make the timing diagram easier to understand, the Figure 2 The correction processing of overflow and underflow is considered in the flowchart (0 extension in step S901 and step S902). The Z-phase signal passing in [2] is the Z-phase signal passing when the forward rotation continues, and the reference count correction value Zc is passed Figure 2 The processing of step S912 in is maintained at +2. Therefore, no error occurs in the count value difference. The Z-phase signal passing in [3] is the first Z-phase signal passing after the transition from forward to reverse, and the reference count correction value Zc passes Figure 2 The pulse width of the Z-phase signal is corrected by the processing of step S915 in step S915. Therefore, the reference count estimate value Czc is the same value as when the Z-phase signal in the immediately previous forward direction passes ([2]). Therefore, no error occurs in the count value difference. The Z-phase signal passing in [4] is the second Z-phase signal passing after the transition from forward to reverse, and the reference count correction value passes Figure 2 The processing of step S914 in is set to -2. Figure 5 Between (e) and (f) in FIG. 1 , the difference of the phase count counter is -4. On the other hand, the count value difference after converting the single-turn count value Cs and the multi-turn count value Cm using equation (1) becomes -6. Therefore, an error of -2 occurs. Figure 5In the example, the pulse width of the Z-phase signal is equivalent to 6 counts, which is consistent with the calculation result using equation (2).

[0072] Reference numerals list

[0073] 1: Encoder

[0074] 2a, 2b, 2c: Pulsating circuit

[0075] 3: Capture timing generation unit

[0076] 4a: First MCU

[0077] 4b: Second MCU

[0078] 5a, 5b, 5c, 5d, 5e, 5f, 5g: Noise filter

[0079] 6a, 6b: Phase counting counter

[0080] 7a: Capture Circuit

[0081] 7b: First capture circuit

[0082] 7c: Second capture circuit

[0083] 8: First counter calculation unit

[0084] 9: Second counter calculation unit

[0085] 10: Safety Controller

[0086] 11: First speed monitoring unit

[0087] 12: Second speed monitoring unit

Claims

1. A rotation speed monitoring device for monitoring the rotation speed of an object, comprising: An encoder that outputs an A-phase signal of N pulses per revolution, a B-phase signal that is 90 degrees out of phase with the A-phase signal, and a Z-phase signal of 1 pulse per revolution; a first unit configured to output a first count value by quadruple phase counting based on the A-phase signal and the B-phase signal; a second unit configured to calculate a second count value composed of a single-turn count value obtained by counter-clearing the count value obtained by the quadruple phase counting based on the A-phase signal and the B-phase signal by the Z-phase signal, and a multi-turn count value obtained by counting up or down the Z-phase signal according to a rotation direction; and a safety controller that calculates a first monitoring speed based on a change in the first count value, calculates a second monitoring speed based on a change in the second count value, and determines whether there is a speed abnormality based on a comparison result between the first monitoring speed and the second monitoring speed, Wherein, the second unit comprises: a phase count counter that performs quadruple phase counting of the A-phase signal and the B-phase signal and outputs a counting result as a basic count value; a first capture circuit that latches the basic count value during a capture period, which is a value obtained by dividing the speed monitoring period by a positive integer, and outputs the latched value as a position count value; a second capture circuit that latches the basic count value at a valid edge of the Z-phase signal and outputs the latched value as a reference count value; and a second counter calculation unit configured to calculate the second count value based on the position count value and the reference count value, wherein the second counter calculation unit calculates a reference count correction value corresponding to a difference between the basic count value and the reference count value at a reference position of the Z-phase signal based on a current value of the reference count value, a previous value of the reference count value, and a previous value of the reference count correction value, calculating a reference count estimate by adding the reference count correction value to the reference count value, incrementing or decrementing the multi-turn count value based on a magnitude relationship among a current value of the position count value, a previous value of the position count value, and the reference count estimate value, and The difference between the position count value and the reference count estimate value is calculated as the single-turn count.

2. The speed monitoring device according to claim 1, characterized in that: The second counter calculation unit calculates a difference between the current value of the reference count value and the previous value of the reference count value while taking overflow and underflow into consideration, sets the reference count correction value to +2 when the difference exceeds a count value corresponding to a pulse width of the Z-phase signal, sets the reference count correction value to -2 when the difference falls below a reciprocal of the count value corresponding to the pulse width of the Z-phase signal, and otherwise sets the reference count correction value to a value obtained by subtracting the difference between the current value of the reference count value and the previous value of the reference count value from the previous value of the reference count correction value.

3. The speed monitoring device according to claim 1 or 2, characterized in that: After acquiring the initial value of the reference count value, the second counter calculation unit sets each of the reference count correction value and the multi-turn count value to 0 until the first condition or the second condition is satisfied, and when the first condition is satisfied, the reference count correction value is set to +2 and the multi-turn count value is set to +1, and when the second condition is satisfied, the reference count correction value is set to -2 and the multi-turn count value is set to -1, and further, when the reference count value is Cz( n), the current value of the position count value is Cp(n), the previous value of the position count value is Cp(n-1), and the values ​​after correction processing for eliminating the discontinuity of Cz(n), Cp(n) and Cp(n-1) are Cz'(n), Cp'(n) and Cp'(n-1) respectively, the first condition is Cp'(n)>Cz'(n)+2≥Cp'(n-1), and the second condition is Cp'(n)<Cz'(n)-2≤Cp'(n-1).

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