Semiconductor power device static test leakage current suppression method

Abstract

The invention discloses a semiconductor power device static test leakage current suppression method, which comprises the following operation steps: performing PCB design in cooperation with a three-coaxial interface, performing optimization design by adopting a Guard line technology in the PCB design stage, enclosing all high-voltage lines, namely a Hi line and a SENSE Hi line, by a Guard line, and meanwhile, avoiding contact with low-voltage lines, namely a Lo line and a SENSE Lo line, so that the leakage current suppression efficiency is improved. Equipotential surrounding protection of an input signal line is realized, and meanwhile, leakage current of a connecting line, a test fixture and auxiliary equipment is suppressed; the instrument is connected with the PCB through the double-end three-coaxial interface, and the three-coaxial interface of the instrument is connected with the three-coaxial interface on the PCB. According to the static test leakage current suppression method for the semiconductor power device, the Guard line with the three coaxial interfaces is utilized to suppress the leakage current on the connecting line, the test fixture and the auxiliary equipment, so that the accuracy of the leakage current test in the static test of the power device is effectively improved, and the reliability of the system is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of static testing of semiconductor power devices, and in particular to a method for suppressing leakage current during static testing of semiconductor power devices. Background Art

[0002] The leakage current suppression method for static testing of semiconductor power devices is a method for static testing of semiconductor power devices. The leakage current of semiconductor power devices usually refers to the unexpected small current generated inside the device due to material imperfections such as crystal defects, impurities, interface states, etc. in the absence of an external signal or in the cut-off state. The existence of leakage current may cause the power device to generate additional power consumption. In the static test of power devices, accurate measurement of leakage current is crucial to evaluating the insulation performance of the device. With the continuous development of science and technology, people's requirements for leakage current suppression methods for static testing of semiconductor power devices are also getting higher and higher.

[0003] The existing static test method for semiconductor power devices has certain drawbacks when used. Although the existing leakage current test method can suppress the leakage current to a certain extent, the non-target leakage current generated by other parts of the test circuit, such as connecting wires, test fixtures and auxiliary equipment, may interfere with the test results and cause measurement errors. Therefore, when conducting leakage current testing of semiconductor power devices, it is necessary to effectively suppress the leakage current generated by the circuit parts other than the power device under test. To this end, we propose a static test leakage current suppression method for semiconductor power devices. Summary of the invention

[0004] Technical problem to be solved: In view of the shortcomings of the prior art, the present invention provides a method for suppressing leakage current in static testing of semiconductor power devices. The Guard line of the three-coaxial interface is used to suppress leakage current on connecting wires, test fixtures and auxiliary equipment, effectively improving the accuracy of leakage current testing in static testing of power devices, enhancing the reliability of the system, and effectively solving the problems in the background technology.

[0005] Technical solution: To achieve the above purpose, the technical solution adopted by the present invention is: a method for suppressing leakage current in static testing of semiconductor power devices, comprising the following steps:

[0006] S1: PCB design is carried out in conjunction with the triaxial interface. During the PCB design stage, Guard line technology is used for optimization design. The Guard line completely surrounds the high-voltage line, namely the Hi line and the SENSE Hi line, and avoids contact with the low-voltage line, namely the Lo line and the SENSELo line, to achieve equipotential surround protection for the input signal line, and at the same time suppress the leakage current of the connecting line, test fixture and auxiliary equipment;

[0007] S2: The instrument is connected to the PCB via a double-ended triaxial interface. Connect the triaxial interface of the instrument to the triaxial interface on the PCB to avoid additional noise or error caused by poor contact.

[0008] S3: Insert the MOS tube to be tested into the socket, insert the MOS tube of the semiconductor power device to be tested into the dedicated test socket on the PCB board, ensure that the electrical connection between the MOS tube and the test system is correct, and prepare for the subsequent leakage current test;

[0009] S4: Start the static leakage current test. The experimental environment required for the leakage current test has been built, and the static leakage current test of the MOS tube can be started;

[0010] S5: The Hi end of the meter outputs a high level and the Lo end outputs a low level, which means that the Hi port and Lo port of the meter output the set high level and low level respectively. The voltage is transmitted from the dual-port triaxial connection line to the Hi end and Lo end of the PCB board, and is added to the D end and S end of the MOS tube of the semiconductor power device to be tested through a special test socket;

[0011] S6: The meter displays the leakage current of the MOS tube. Since the level of the Guard line on the PCB is consistent with the Hi end, the leakage current generated by the circuit part other than the power device under test is suppressed, so that the leakage current measured by the meter is the leakage current of the MOS tube itself.

[0012] S7: The static leakage current test is completed. The static leakage current test of the MOS tube has been completed, and the accuracy of the leakage current test has been improved through this method.

[0013] As a preferred technical solution of the present application, a three-coaxial interface, a leakage resistor and a leakage capacitor, a semiconductor power device DUT under test and a PCB board, a Hi line, a SENSE Hi line, a Guard line, a Lo line and a SENSE Lo line are set on the PCB board, the three-coaxial interface is used to provide high and low levels to the semiconductor power device DUT under test, and measure the leakage current of the semiconductor power device DUT under test, and the three-coaxial interface includes a center signal line, a Guard line and a GROUND line.

[0014] As a preferred technical solution of the present application, the center signal line is located at the center of the three-coaxial interface, with the purpose of providing high and low levels to the semiconductor power device DUT under test and measuring the leakage current of the semiconductor power device DUT under test. The high level is transmitted through the Hi line in the three-coaxial interface, and the low level is transmitted through the Lo line in the three-coaxial interface, which enhances the stability and anti-interference ability of the signal and improves the accuracy of the leakage current test.

[0015] As a preferred technical solution of the present application, the Guard line is in the middle layer of the three-coaxial interface, surrounding the Hi line and the Lo line of the central signal line respectively, wherein the potential of the Guard line is equal to the potential of the Hi line. This potential matching ensures that the current on the Hi line will not leak through the Guard line, thereby achieving equipotential surround protection for the input signal line.

[0016] As a preferred technical solution of the present application, the GROUND line is in the outermost layer of the three-coaxial interface, and the outermost GROUND line of the Hi line and the outermost GROUND line of the Lo line are connected together to provide a common reference potential for the central signal line in the three-coaxial interface to ensure the accuracy and stability of the signal.

[0017] As a preferred technical solution of the present application, the leakage resistance and leakage capacitance come from the connecting wires, test fixtures and auxiliary equipment in the leakage current test loop from the Hi line, Guard line to the Lo line, including the leakage resistance R and leakage capacitance C between the Hi line and the Guard line and the leakage resistance R and leakage capacitance C between the Lo line and the Guard line.

[0018] As a preferred technical solution of the present application, there is no leakage current in the leakage resistor R and the leakage capacitor C. Since the potential of the Hi line is equal to the potential of the Guard line, the current of the Hi line will not leak to the Guard line through the leakage resistor R and the leakage capacitor C.

[0019] As a preferred technical solution of the present application, there is leakage current in the leakage resistor R and the leakage capacitor C. Since the potential of the Guard line is equal to the potential of the Hi line, the leakage current of the Guard line will flow to the Lo line through the leakage resistor R and the leakage capacitor C, and will not pass through the semiconductor power device DUT under test. The leakage current from the Guard line to the Lo line is provided by the Guard line voltage, and the Guard line voltage is obtained after the Hi line passes through the voltage follower. Since the voltage follower is a high-impedance input, the current of the Guard line has no effect on the Hi line current. Therefore, the leakage current flowing through the semiconductor power device DUT under test is the current output by the instrument on the Hi line.

[0020] Beneficial effects: Compared with the prior art, the present invention provides a method for suppressing leakage current in static testing of semiconductor power devices, which has the following beneficial effects: This method for suppressing leakage current in static testing of semiconductor power devices utilizes the Guard line of the three-coaxial interface to suppress leakage current on connecting lines, test fixtures and auxiliary equipment, effectively improves the accuracy of leakage current testing in static testing of power devices, and enhances the reliability of the system; the method is simple and easy to implement, and can achieve high-precision leakage current testing in conjunction with PCB design, which reduces the difficulty of operation, reduces additional equipment investment and maintenance costs, and improves the economy of testing; the method is not only suitable for leakage current testing of semiconductor power devices, but can also be extended to other electronic testing and measurement fields to improve the performance and reliability of electronic systems. The entire method for suppressing leakage current in static testing of semiconductor power devices has a simple structure, is easy to operate, and has better results than traditional methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The present invention is a schematic structural diagram of a method for suppressing leakage current in static testing of a semiconductor power device.

[0022] Figure 2 The present invention is a schematic diagram of the structure of a PCB in a method for suppressing leakage current in a static test of a semiconductor power device.

[0023] Figure 3 The present invention is a schematic flow chart of a method for suppressing leakage current in static testing of a semiconductor power device.

[0024] In the figure: 1. triaxial interface; 2. leakage resistance and leakage capacitance; 3. semiconductor power device under test DUT; 4. Hi line; 5. SENSE Hi line; 6. Guard line; 7. Lo line; 8. SENSE Lo line. DETAILED DESCRIPTION

[0025] The technical scheme of the present invention will be clearly and completely described below in conjunction with the accompanying drawings and specific embodiments, but it will be understood by those skilled in the art that the following described embodiments are part of embodiments of the present invention, rather than all embodiments, and are only used to illustrate the present invention, and should not be considered as limiting the scope of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of the present invention. If specific conditions are not specified in the embodiments, they are carried out according to normal conditions or conditions recommended by the manufacturer. If the manufacturer is not specified in the reagents or instruments used, they are all conventional products that can be purchased commercially.

[0026] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0027] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] like Figure 1-3 As shown, a method for suppressing leakage current in static testing of a semiconductor power device comprises the following steps:

[0029] S1: PCB design is carried out in conjunction with the triaxial interface. During the PCB design stage, Guard line technology is used for optimization design. The Guard line completely surrounds the high-voltage line, namely the Hi line and the SENSE Hi line, and avoids contact with the low-voltage line, namely the Lo line and the SENSELo line, to achieve equipotential surround protection for the input signal line, and at the same time suppress the leakage current of the connecting line, test fixture and auxiliary equipment;

[0030] S2: The instrument is connected to the PCB via a double-ended triaxial interface. Connect the triaxial interface of the instrument to the triaxial interface on the PCB to avoid additional noise or error caused by poor contact.

[0031] S3: Insert the MOS tube to be tested into the socket, insert the MOS tube of the semiconductor power device to be tested into the dedicated test socket on the PCB board, ensure that the electrical connection between the MOS tube and the test system is correct, and prepare for the subsequent leakage current test;

[0032] S4: Start the static leakage current test. The experimental environment required for the leakage current test has been built, and the static leakage current test of the MOS tube can be started;

[0033] S5: The Hi end of the meter outputs a high level and the Lo end outputs a low level, which means that the Hi port and Lo port of the meter output the set high level and low level respectively. The voltage is transmitted from the dual-port triaxial connection line to the Hi end and Lo end of the PCB board, and is added to the D end and S end of the MOS tube of the semiconductor power device to be tested through a special test socket;

[0034] S6: The meter displays the leakage current of the MOS tube. Since the level of the Guard line on the PCB is consistent with the Hi end, the leakage current generated by the circuit part other than the power device under test is suppressed, so that the leakage current measured by the meter is the leakage current of the MOS tube itself.

[0035] S7: The static leakage current test is completed. The static leakage current test of the MOS tube has been completed, and the accuracy of the leakage current test has been improved through this method.

[0036] Furthermore, the three coaxial interface 1, the leakage resistor and the leakage capacitor 2, the semiconductor power device DUT3 under test and the PCB board, the Hi line 4, the SENSE Hi line 5, the Guard line 6, the Lo line 7 and the SENSE Lo line 8 are set on the PCB board, the three coaxial interface 1 is used to provide high and low levels to the semiconductor power device DUT3 under test, and measure the leakage current of the semiconductor power device DUT3 under test, and the three coaxial interface 1 includes a center signal line, a Guard line 6 and a GROUND line.

[0037] Furthermore, the center signal line is located at the center of the three-coaxial interface 1, with the purpose of providing high and low levels to the semiconductor power device DUT3 under test and measuring the leakage current of the semiconductor power device DUT3 under test. The high level is transmitted through the Hi line 4 in the three-coaxial interface 1, and the low level is transmitted through the Lo line 7 in the three-coaxial interface 1, which enhances the stability and anti-interference ability of the signal and improves the accuracy of the leakage current test.

[0038] Furthermore, the Guard line 6 is in the middle layer of the three-coaxial interface 1, surrounding the Hi line 4 and the Lo line 7 of the central signal line respectively, wherein the potential of the Guard line 6 is equal to the potential of the Hi line 4. This potential matching ensures that the current on the Hi line 4 will not leak through the Guard line 6, thereby achieving equipotential surround protection for the input signal line.

[0039] Furthermore, the GROUND line is at the outermost layer of the triaxial interface 1, the outermost GROUND line of the Hi line 4 and the outermost GROUND line of the Lo line 7 are connected together to provide a common reference potential for the central signal line in the triaxial interface 1, thereby ensuring the accuracy and stability of the signal.

[0040] Furthermore, the leakage resistance and leakage capacitance 2 come from the connecting wires, test fixtures and auxiliary equipment in the leakage current test loop from the Hi line 4, the Guard line 6 to the Lo line 7, including the leakage resistance R1 and the leakage capacitance C1 between the Hi line 4 and the Guard line 6 and the leakage resistance R2 and the leakage capacitance C2 between the Lo line 7 and the Guard line 6.

[0041] Furthermore, there is no leakage current in the leakage resistor R1 and the leakage capacitor C1 . Since the potential of the Hi line 4 is equal to the potential of the Guard line 6 , the current of the Hi line 4 will not leak to the Guard line 6 through the leakage resistor R1 and the leakage capacitor C1 .

[0042] Furthermore, there is leakage current in the leakage resistor R2 and the leakage capacitor C2. Since the potential of the Guard line 6 is equal to the potential of the Hi line 4, the leakage current of the Guard line 6 will flow to the Lo line 7 through the leakage resistor R2 and the leakage capacitor C2, and will not pass through the semiconductor power device DUT under test. The leakage current from the Guard line 6 to the Lo line 7 is provided by the Guard line 6 voltage, and the Guard line 6 voltage is obtained after the Hi line 4 passes through the voltage follower. Since the voltage follower is a high-impedance input, the current of the Guard line 6 has no effect on the current of the Hi line 4. Therefore, the leakage current flowing through the semiconductor power device DUT under test is the current output by the instrument on the Hi line 4.

[0043] Example:

[0044] Figure 1 The invention is a structural diagram of a leakage current suppression method for static testing of a conductor power device, comprising a triaxial interface 1, a leakage resistor and a leakage capacitor 2, and a semiconductor power device DUT 3 under test;

[0045] The triaxial interface is used to provide high and low levels to the semiconductor power device DUT under test and measure the leakage current of the semiconductor power device DUT under test. The triaxial interface includes the center signal line (Hi line and Lo line), the Guard line (shielding net) and the GROUND line (grounding line);

[0046] The center signal line is located in the center of the three-coaxial interface. The purpose is to provide high and low levels to the power device DUT under test and measure the leakage current of the DUT. The high level is transmitted through the Hi line in the three-coaxial interface, and the low level is transmitted through the Lo line in the three-coaxial interface. This separation design enhances the stability and anti-interference ability of the signal and improves the accuracy of the leakage current test.

[0047] The Guard line is in the middle layer of the triaxial interface, surrounding the Hi line and the Lo line of the central signal line respectively. The potential of the Guard line is equal to that of the Hi line. This potential matching ensures that the current on the Hi line will not leak through the Guard line, realizing equipotential surrounding protection for the input signal line, thereby protecting the integrity of the signal; the two Guard lines are connected together to form a continuous shielding path, further enhancing the anti-interference capability, preventing external leakage current from reaching the input port and affecting the output voltage of the port, and at the same time suppressing the leakage current of the connecting wire, test fixture and auxiliary equipment;

[0048] The GROUND line is at the outermost layer of the triaxial interface. The outermost GROUND line of the Hi line and the outermost GROUND line of the Lo line are connected together to provide a common reference potential for the central signal line in the triaxial interface to ensure the accuracy and stability of the signal.

[0049] The leakage resistance and leakage capacitance come from the connection wires, test fixtures and auxiliary equipment in the leakage current test loop from Hi line, Guard line to Lo line, including the leakage resistance R1 and leakage capacitance C1 between Hi line and Guard line, and the leakage resistance R2 and leakage capacitance C2 between Lo line and Guard line.

[0050] There is no leakage current in the leakage resistor R1 and the leakage capacitor C1. Since the potential of the Hi line is equal to the potential of the Guard line, the current of the Hi line will not leak to the Guard line through the leakage resistor R1 and the leakage capacitor C1.

[0051] There is leakage current in the leakage resistor R2 and the leakage capacitor C2. Since the potential of the Guard line is equal to the potential of the Hi line, the leakage current of the Guard line will flow to the Lo line through the leakage resistor R2 and the leakage capacitor C2, and will not pass through the semiconductor power device DUT under test. The leakage current from the Guard line to the Lo line is provided by the Guard line voltage, and the Guard line voltage is obtained after the Hi line passes through the voltage follower. Since the voltage follower is a high-impedance input, the current of the Guard line has no effect on the Hi line current. Therefore, the leakage current flowing through the semiconductor power device DUT under test is the current output by the instrument on the Hi line.

[0052] The semiconductor power device DUT under test supports the measurement of various types of semiconductor power devices, such as MOS tubes, IGBTs and other power devices.

[0053] Figure 2 It is a semiconductor power device static test leakage current suppression method and corresponding PCB design;

[0054] 4 is the Hi line, which provides high voltage for the power device under test DUT;

[0055] 5 is the SENSE Hi line, which has the same potential as the Hi line;

[0056] 6 is a Guard line, which has the same potential as the Hi line and surrounds the Hi line and the SENSE Hi line respectively, while avoiding contact with the low-voltage lines (Lo line and SENSE Lo line).

[0057] 7 is the Lo line, which provides a low level for the power device under test DUT;

[0058] 8 is the SENSE Lo line, which has the same potential as the Lo line.

[0059] The triaxial interface is used in conjunction with the Guard line to suppress leakage current on connecting wires, test fixtures and auxiliary equipment.

[0060] Figure 3 The present invention is a flow chart of a method for suppressing leakage current during static testing of a semiconductor power device;

[0061] S1 cooperates with triaxial interface for PCB design, which means that Guard line technology is used for optimization design in the PCB design stage. Guard line surrounds all high-voltage lines (Hi line and SENSE Hi line) and avoids contact with low-voltage lines (Lo line and SENSELo line), realizing equipotential surround protection for input signal lines and suppressing leakage current of connecting lines, test fixtures and auxiliary equipment.

[0062] The S2 instrument is connected to the PCB through a double-ended triaxial interface, which means connecting the triaxial interface of the instrument to the triaxial interface on the PCB board to avoid additional noise or error introduced by poor contact;

[0063] S3 inserts the MOS tube to be tested into the socket, which is to insert the MOS tube of the semiconductor power device to be tested into the special test socket on the PCB board to ensure that the electrical connection between the MOS tube and the test system is correct, so as to prepare for the subsequent leakage current test;

[0064] S4 starts the leakage current static test, which means that the experimental environment required for the leakage current test has been built, and the leakage current static test of the MOS tube can be started;

[0065] The Hi end of the S5 meter outputs a high level and the Lo end outputs a low level, which means that the Hi port and Lo port of the meter output the set high level and low level respectively. The voltage is transmitted from the dual-port triaxial connection line to the Hi end and Lo end of the PCB board, and is added to the D end and S end of the MOS tube of the semiconductor power device to be tested through a special test socket;

[0066] The leakage current of the MOS tube displayed by the S6 meter is that the level of the Guard line on the PCB board is consistent with the Hi end, which suppresses the leakage current generated by the circuit part other than the power device under test, so that the leakage current measured by the meter is the leakage current of the MOS tube itself;

[0067] S7 leakage current static test completion means that the MOS tube leakage current static test has been completed, and the accuracy of the leakage current test is improved through this method.

[0068] It should be noted that, in this article, relational terms such as first and second (number one, number two), etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0069] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited by the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements all fall within the scope of the present invention to be protected.

Claims

1. A method for suppressing leakage current in static testing of semiconductor power devices, characterized in that: The steps include: S1: PCB design is carried out in conjunction with the triaxial interface. During the PCB design stage, Guard line technology is used for optimization design. The Guard line completely surrounds the high-voltage line, namely the Hi line and the SENSE Hi line, and avoids contact with the low-voltage line, namely the Lo line and the SENSE Lo line, to achieve equipotential surround protection for the input signal line, and at the same time suppress the leakage current of the connecting line, test fixture and auxiliary equipment; S2: The instrument is connected to the PCB via a double-ended triaxial interface. Connect the triaxial interface of the instrument to the triaxial interface on the PCB to avoid additional noise or error caused by poor contact. S3: Insert the MOS tube to be tested into the socket, insert the MOS tube of the semiconductor power device to be tested into the dedicated test socket on the PCB board, ensure that the electrical connection between the MOS tube and the test system is correct, and prepare for the subsequent leakage current test; S4: Start the static leakage current test. The experimental environment required for the leakage current test has been built, and the static leakage current test of the MOS tube can be started; S5: The Hi end of the meter outputs a high level and the Lo end outputs a low level, which means that the Hi port and Lo port of the meter output the set high level and low level respectively. The voltage is transmitted from the dual-port triaxial connection line to the Hi end and Lo end of the PCB board, and is added to the D end and S end of the MOS tube of the semiconductor power device to be tested through a special test socket; S6: The meter displays the leakage current of the MOS tube. Since the level of the Guard line on the PCB is consistent with the Hi end, the leakage current generated by the circuit part other than the power device under test is suppressed, so that the leakage current measured by the meter is the leakage current of the MOS tube itself. S7: The static leakage current test is completed. The static leakage current test of the MOS tube has been completed, and the accuracy of the leakage current test has been improved through this method.

2. A method for suppressing leakage current in static testing of a semiconductor power device according to claim 1, characterized in that: A triaxial interface (1), a leakage resistor and a leakage capacitor (2), a semiconductor power device DUT (3) under test and a PCB board; a Hi line (4), a SENSE Hi line (5), a Guard line (6), a Lo line (7) and a SENSE Lo line (8) are arranged on the PCB board; the triaxial interface (1) is used to provide high and low levels to the semiconductor power device DUT (3) under test and to measure the leakage current of the semiconductor power device DUT (3) under test; the triaxial interface (1) comprises a central signal line, a Guard line (6) and a GROUND line.

3. A method for suppressing leakage current in static testing of a semiconductor power device according to claim 2, characterized in that: The central signal line is located at the center of the triaxial interface (1) and is intended to provide high and low levels to the semiconductor power device DUT (3) under test and measure the leakage current of the semiconductor power device DUT (3) under test. The high level is transmitted through the Hi line (4) in the triaxial interface (1) and the low level is transmitted through the Lo line (7) in the triaxial interface (1), thereby enhancing the stability and anti-interference ability of the signal and improving the accuracy of the leakage current test.

4. A method for suppressing leakage current in static testing of a semiconductor power device according to claim 2, characterized in that: The Guard line (6) is located in the middle layer of the triaxial interface (1), and surrounds the Hi line (4) and the Lo line (7) of the central signal line respectively, wherein the potential of the Guard line (6) is equal to the potential of the Hi line (4). This potential matching ensures that the current on the Hi line (4) will not leak through the Guard line (6), thereby achieving equipotential surround protection for the input signal line.

5. A method for suppressing leakage current in static testing of a semiconductor power device according to claim 2, characterized in that: The GROUND line is at the outermost layer of the triaxial interface (1), and the GROUND line at the outermost layer of the Hi line (4) and the GROUND line at the outermost layer of the Lo line (7) are connected together to provide a common reference potential for the central signal line in the triaxial interface (1), thereby ensuring the accuracy and stability of the signal.

6. A method for suppressing leakage current in static testing of a semiconductor power device according to claim 2, characterized in that: The leakage resistance and leakage capacitance (2) are derived from connection wires, test fixtures and auxiliary equipment in a leakage current test loop from the Hi line (4), the Guard line (6) to the Lo line (7), including a leakage resistance R1 and a leakage capacitance C1 between the Hi line (4) and the Guard line (6) and a leakage resistance R2 and a leakage capacitance C2 between the Lo line (7) and the Guard line (6).

7. A method for suppressing leakage current in static testing of a semiconductor power device according to claim 6, characterized in that: There is no leakage current in the leakage resistor R1 and the leakage capacitor C1. Since the potential of the Hi line (4) is equal to the potential of the Guard line (6), the current of the Hi line (4) will not leak to the Guard line (6) through the leakage resistor R1 and the leakage capacitor C1.

8. A method for suppressing leakage current in static testing of a semiconductor power device according to claim 6, characterized in that: The leakage resistor R2 and the leakage capacitor C2 have leakage current. Since the potential of the Guard line (6) is equal to the potential of the Hi line (4), the leakage current of the Guard line (6) will flow to the Lo line (7) through the leakage resistor R2 and the leakage capacitor C2, and will not pass through the semiconductor power device DUT under test. The leakage current from the Guard line (6) to the Lo line (7) is provided by the Guard line (6) voltage. The Guard line (6) voltage is obtained after the Hi line (4) passes through the voltage follower. Since the voltage follower is a high impedance input, the current of the Guard line (6) has no effect on the current of the Hi line (4). Therefore, the leakage current flowing through the semiconductor power device DUT under test is the current output by the instrument on the Hi line (4).

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