A high-speed current detection circuit and a power supply circuit

Abstract

The present application provides a high-speed current detection circuit and a power supply circuit. The high-speed current detection circuit includes a power switch tube to be measured, a current detection module, a switching module, and a replication module. The current detection module is connected to the power switch tube to be measured and is used to detect the power switch tube to be measured and generate a detection current. The switching module is connected to the current detection module and is used to control the output of the detection current. The replication module is connected to the current detection module and the switching module and is used to replicate the detection current output by the switching module and feedback it to the current detection module, so as to reduce the jump amplitude of the detection current when the power switch tube to be measured switches between the off state and the on state. The power supply circuit includes the high-speed current detection circuit. By setting the replication module to replicate the detection current and feedback it to the current detection module, the present application reduces the jump amplitude of the circuit, thereby reducing the time required for the circuit to reach stability, not only improving the detection efficiency of the circuit, but also helping to expand the application range of the current detection circuit.

Description

Background Art

[0002] Current detection circuits play a crucial role in power supply systems and can be used for functions such as loop control, over-current protection, and zero-crossing detection. Therefore, current detection circuits have become an essential part of most power circuit designs. There are various ways to detect current in power circuits, but directly detecting the voltage drop across a power switch in the conducting state is a low-cost and highly reliable detection scheme.

[0003] In related technologies, a current detection circuit includes an upper transistor and a lower transistor, where the lower transistor serves as the power switch to be detected. When this power switch conducts, it can be equivalent to a resistor R. When it conducts, the output voltage can be expressed as V = -IL * R. Therefore, as long as the V when the power switch conducts can be sampled, the current value I can be obtained. The current detection circuit needs to detect the voltage difference from the output terminal of the power switch to the ground terminal, so it is necessary to convert the current of the power switch into a voltage signal. And this voltage signal is output and sent to subsequent control loops and other comparator circuits for over-current protection. After the power switch turns off, the current flowing through the power switch is 0A. After the power switch turns on, the current of the power switch needs to quickly jump to a relatively high current value. At the same time, the detection current generated by the current detection circuit also needs to quickly jump to a higher current value. Due to this large jump amplitude, the current detection circuit requires a relatively long time to stabilize. And the minimum on-time of the power switch must be longer than the time required to stabilize, otherwise the subsequent control loop cannot detect an effective current. The time required to stabilize is usually much higher than 100ns, which limits the minimum on-time of the power switch. For example, in the application of a high-frequency buck converter, if the minimum on-time of the power switch exceeds 100ns, it will limit the application range of the buck converter, thus restricting the output voltage of the buck converter to a lower range. Summary of the Invention

[0004] This application provides a high-speed current detection circuit and a power supply circuit aimed at reducing the circuit jump amplitude, reducing the stabilization time, and expanding the application range.

[0005] In a first aspect, this application provides a high-speed current detection circuit, including:

[0006] A power switch tube M1 to be measured;

[0007] A current detection module, connected to the power switch tube M1 to be measured, for detecting the power switch tube M1 to be measured and generating a detection current;

[0008] A switch module, connected to the current detection module, for controlling the output of the detection current;

[0009] A replication module, connected to the current detection module and the switch module, is configured to replicate the detected current output by the switch module and feedback it to the current detection module, so as to reduce the jump amplitude of the detected current when the power switch to be measured, M1, switches between the off state and the on state.

[0010] In the above technical solution, by setting a replication module to replicate the detected current output by the switch module and feedback it to the current detection module, when the power switch to be measured switches between off and on, the jump amplitude of the current detection circuit is significantly reduced, thereby reducing the time required for the current detection circuit to reach stability. In this way, not only the detection efficiency of the circuit is improved, but also it helps to expand the application range of the current detection circuit.

[0011] Optionally, the high-speed current detection circuit includes a power supply terminal; the replication module includes a first MOS transistor M11, a first resistor R12, a second MOS transistor M12, and a third MOS transistor M13; wherein,

[0012] The gate of the first MOS transistor M11 is connected to the output terminal of the switch module, the drain is connected to the power supply terminal, and the source is connected to the drain of the second MOS transistor M12 through the first resistor R12; the gate of the second MOS transistor M12 is short-circuited to its drain, and the source is grounded; the gate of the third MOS transistor M13 is connected to the gate of the second MOS transistor M12, the drain is connected to the current detection module, and the source is grounded.

[0013] Optionally, the current detection module further includes a detection unit and an error amplification unit;

[0014] Wherein, the detection unit includes a fourth MOS transistor M2, a fifth MOS transistor M3, a sixth MOS transistor M4, a seventh MOS transistor M5, an eighth MOS transistor M6, and a ninth MOS transistor M7; wherein,

[0015] The drain of the fourth MOS transistor M2 is connected to the source of the power switch to be measured, M1, the gate is connected to the power supply terminal, and the source is connected to the drain of the fifth MOS transistor M3; the gate of the fifth MOS transistor M3 is connected to the power supply terminal, and the source is connected to the source of the sixth MOS transistor M4; the gate of the sixth MOS transistor M4 is connected to the power supply terminal, and the drain is connected to the error amplification unit; the drain of the seventh MOS transistor M5 is connected to the drain of the power switch to be measured, M1, the gate is connected to the gate of the power switch to be measured, M1, and the source is connected to the drain of the eighth MOS transistor M6; the gate of the eighth MOS transistor M6 is connected to the power supply terminal, and the source is connected to the source of the ninth MOS transistor M7; the gate of the ninth MOS transistor M7 is connected to the power supply terminal, and the drain is connected to the error amplification unit and the replication module.

[0016] Optionally, the error amplification unit includes an error amplifier Error Amp and a tenth MOS transistor M8; wherein,

[0017] The non-inverting input terminal of the error amplifier Error Amp is connected to the drain of the sixth MOS transistor M4, the inverting input terminal of the error amplifier Error Amp is connected to the drain of the ninth MOS transistor M7, and the output terminal of the error amplifier Error Amp is connected to the gate of the tenth MOS transistor M8; the source of the tenth MOS transistor M8 is connected to the drain of the ninth MOS transistor M7 and the replication module, and the drain is connected to the switch module.

[0018] Optionally, the switch module includes an eleventh MOS transistor M9, a twelfth MOS transistor M10, a capacitor C1, and a first switch switch1; wherein,

[0019] The drain of the eleventh MOS transistor M9 is connected to the drain of the tenth MOS transistor M8, the source is connected to the power supply terminal, the gate is shorted to its drain and connected to the gate of the twelfth MOS transistor M10 through the first switch switch1; the source of the twelfth MOS transistor M10 is connected to the power supply terminal, and the drain is connected to the gate of the first MOS transistor; one end of the capacitor C1 is connected between the first switch switch1 and the gate of the twelfth MOS transistor M10, and the other end is connected to the power supply terminal.

[0020] Optionally, the high-speed current detection circuit further includes a detection current output terminal; the current detection module further includes a current detection output unit, and the current detection output unit includes a first amplifier OP2, a second amplifier OP3, a third amplifier OP1, and a second resistor R1; wherein,

[0021] The non-inverting input terminal of the first amplifier OP2 is connected to a reference voltage, the inverting input terminal of the first amplifier OP2 is connected to the inverting input terminal of the second amplifier OP3, the output terminal of the first amplifier OP2 is shorted to its inverting input terminal and connected to the drain of the twelfth MOS transistor M10 through the second resistor; the non-inverting input terminal of the second amplifier OP3 is connected to the inverting input terminal of the third amplifier OP1, the inverting input terminal of the second amplifier OP3 is connected to the output terminal of the first amplifier OP2, and the output terminal of the second amplifier OP3 is used to output a zero-current clock detection signal ZC; the non-inverting input terminal of the third amplifier OP1 is connected between the drain of the twelfth MOS transistor M10 and the second resistor, the inverting input terminal and the output terminal of the third amplifier OP1 are shorted, and the output terminal of the third amplifier OP1 is connected to the detection current output terminal.

[0022] Optionally, the replication module further includes a second switch switch2. One end of the second switch switch2 is connected to the drain of the third MOS transistor M13, and the other end is connected to the source of the tenth MOS transistor M8 and the drain of the ninth MOS transistor M7.

[0023] Optionally, the detection unit further includes an inverter LSGATE and a thirteenth MOS transistor M15, where

[0024] The input end of the inverter LSGATE is connected to the gate of the power switch transistor M1 to be measured; the gate of the thirteenth MOS transistor M15 is connected to the output end of the inverter LSGATE, the drain is connected to the source of the seventh MOS transistor M5, and the source is connected to the drain of the fourth MOS transistor M2.

[0025] Optionally, it further includes a first current source Ib1. One end of the first current source Ib1 is connected to the power supply terminal, and the other end is connected to the positive-phase input terminal of the error amplifier Error Amp; and / or

[0026] It further includes a second current source Ib2. One end of the second current source Ib2 is connected to the drain of the twelfth MOS transistor M10, and the other end is grounded.

[0027] In a second aspect, the present application further provides a power supply circuit, including the high-speed current detection circuit described above. Description of the Drawings

[0028] Figure 1 The following shows a structural block diagram of a high-speed current detection circuit provided by an embodiment of the present application;

[0029] Figure 2 For Figure 1 The following shows a circuit diagram of a high-speed current detection circuit of an embodiment;

[0030] Figure 3 For Figure 2 The following shows a specific circuit diagram of the replication module in a high-speed current detection circuit of an embodiment connected to the resistor R1 and the first amplifier OP2;

[0031] Figure 4 The following shows a waveform schematic diagram of a high-speed current detection circuit before setting the replication module provided by an embodiment of the present application;

[0032] Figure 5 The following shows a waveform schematic diagram of a high-speed current detection circuit after setting the replication module provided by an embodiment of the present application;

[0033] Figure 6 The following shows a simulation schematic diagram of a high-speed current detection circuit provided by an embodiment of the present application. Detailed Embodiments

[0034] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. Through these descriptions, the features and advantages of the present application will become more clearly defined.

[0035] The special term "exemplary" here means "serving as an example, embodiment, or illustrative". Any embodiment described as "exemplary" here does not have to be construed as superior or better than other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0036] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0037] The embodiment of the present application provides a high-speed current detection circuit and a power supply circuit to improve the current detection speed. It will be described in detail below with reference to specific drawings by way of embodiments.

[0038] Referring to Figure 1 As shown, a high-speed current detection circuit provided by the present application includes a power switch tube M1 to be measured, a current detection module 1, a switch module 2, and a replication module 3. The current detection module 1 is connected to the power switch tube M1 to be measured, and is used to detect the power switch tube M1 to be measured and generate a detection current. The switch module 2 is connected to the current detection module 1 and is used to control the output of the detection current. The replication module 3 is connected to the current detection module 1 and the switch module 2, and is used to replicate the detection current output by the switch module 2 and feedback it to the current detection module 1, so that when the power switch tube M1 to be measured switches between the off state and the on state, the jump amplitude of the detection current is reduced.

[0039] The current detection circuit detects the current of the power switch tube M1 to be measured through the current detection module 1 to identify whether there are abnormal phenomena such as overcurrent or overvoltage in related application devices. In the related art, during the process of detecting the current, when the power switch tube M1 to be measured switches between the off state and the on state, a large voltage difference will be generated in the switch module 2, resulting in a large jump amplitude of the detection current. Therefore, the time required for the current detection circuit to reach a stable state is also increased. In this embodiment, in order to avoid the situation of a high jump amplitude of the detection current in the current detection circuit, the replication module 3 is set to replicate the detection current Ic output by the switch module 2 and feedback it to the current detection module 1, so that when the power switch tube M1 to be measured switches between off and on, the jump amplitude of the current detection circuit is significantly reduced, thereby reducing the time required for the current detection circuit to reach stability. In this way, not only the detection efficiency of the circuit is improved, but also it helps to expand the application range of the current detection circuit.

[0040] AsFigure 2 As shown, in a specific feasible embodiment, the high-speed current detection circuit includes a power supply terminal VDRV; the current detection module 1 further includes a detection unit 10 and an error amplification unit 11;

[0041] Among them, the detection unit 10 includes a fourth MOS transistor M2, a fifth MOS transistor M3, a sixth MOS transistor M4, a seventh MOS transistor M5, an eighth MOS transistor M6, and a ninth MOS transistor M7; among them,

[0042] The drain of the fourth MOS transistor M2 is connected to the source of the power switch transistor M1 to be measured, the gate is connected to the power supply terminal VDRV, and the source is connected to the drain of the fifth MOS transistor M3; the gate of the fifth MOS transistor M3 is connected to the power supply terminal VDRV, and the source is connected to the source of the sixth MOS transistor M4; the gate of the sixth MOS transistor M4 is connected to the power supply terminal VDRV, and the drain is connected to the error amplification unit 11; the drain of the seventh MOS transistor M5 is connected to the drain of the power switch transistor M1 to be measured, the gate is connected to the gate of the power switch transistor M1 to be measured, and the source is connected to the drain of the eighth MOS transistor M6; the gate of the eighth MOS transistor M6 is connected to the power supply terminal VDRV, and the source is connected to the source of the ninth MOS transistor M7; the gate of the ninth MOS transistor M7 is connected to the power supply terminal VDRV, and the drain is connected to the error amplification unit 11 and the replication module 3.

[0043] In this embodiment, the fourth MOS transistor M2, the fifth MOS transistor M3, the sixth MOS transistor M4, the seventh MOS transistor M5, the eighth MOS transistor M6, and the ninth MOS transistor M7 are current detection MOS transistors, and the current when the power switch transistor M1 to be measured is turned on can be accurately detected through these MOS transistors.

[0044] In a specific feasible embodiment, the error amplification unit 11 includes an error amplifier Error Amp and a tenth MOS transistor M8. The positive input terminal of the error amplifier Error Amp is connected to the drain of the sixth MOS transistor M4, the negative input terminal of the error amplifier Error Amp is connected to the drain of the ninth MOS transistor M7, and the output terminal of the error amplifier ErrorAmp is connected to the gate of the tenth MOS transistor M8; the source of the tenth MOS transistor M8 is connected to the drain of the ninth MOS transistor M7 and the replication module 3, and the drain is connected to the switch module 2. In this embodiment, the error amplification unit 11 amplifies the detected current through the error amplifier Error Amp and the tenth MOS transistor M8, so as to improve the detection accuracy of the current detection circuit.

[0045] The high-speed current detection circuit further includes a first current source Ib1, which provides a first current Ib1 to the branch where the positive input terminal of the error amplifier Error Amp is located. One end of the first current source Ib1 is connected to the power supply terminal VDRV, and the other end is connected to the positive input terminal of the error amplifier Error Amp.

[0046] In this application, by utilizing the characteristic of the large gain of the error amplifier Error Amp, when the error amplifier Error Amp is operating normally, the voltages of its positive input terminal PGNDSNS and negative input terminal SWSNS are forced to be the same, that is, U(PGNDSNS) = U(SWSNS), formula ①.

[0047] When the power switch tube M1 to be measured is turned on, it can be equivalent to a resistor R, and PGND is the reference ground. Then, when the power switch tube M1 to be measured is turned on, the voltage at the SW point is Vsw = -IL*R, which is also the voltage value of the branch where the fourth MOS tube M2, the fifth MOS tube M3, and the sixth MOS tube M4 are located, where I is the current flowing through the power switch tube M1 to be measured. Let the total resistance of the fourth MOS tube M2, the fifth MOS tube M3, and the sixth MOS tube M4 be RSNS1; the total resistance of the seventh MOS tube M5, the eighth MOS tube M6, and the ninth MOS tube M7 be RSNS2. Since the current detection MOS tubes are all the same, RSNS1 = RSNS2, formula ②.

[0048] In addition, a first current source Ib1 is also provided. Therefore, U(PGNDSNS) = IL*R + Ib1*RSNS1, formula ③. According to the above formulas ①, ②, and ③, Ia = Ib1 + IL*R / RSNS2 is obtained, where Ia is the current flowing through the seventh MOS tube M5, the eighth MOS tube M6, and the ninth MOS tube M7, and is also the current output by the tenth MOS tube M8.

[0049] Further, in a specific feasible implementation, the switch module 2 includes an eleventh MOS tube M9, a twelfth MOS tube M10, a capacitor C1, and a first switch switch1. Among them, the drain of the eleventh MOS tube M9 is connected to the drain of the tenth MOS tube M8, the source is connected to the power supply terminal, the gate is short-circuited to its drain and is connected to the gate of the twelfth MOS tube M10 through the first switch switch1; the source of the twelfth MOS tube M10 is connected to the power supply terminal, and the drain is connected to the gate of the first MOS tube; one end of the capacitor C1 is connected between the first switch switch1 and the gate of the twelfth MOS tube M10, and the other end is connected to the power supply terminal.

[0050] In this embodiment, in combination with the solution in the above embodiment, since the eleventh MOS transistor M9 and the twelfth MOS transistor M10 form a current mirror structure, the current flowing through the twelfth MOS transistor M10 is also Ia = Ib1 + IL * R / RSNS2, Equation ④. In this application, a second current source Ib2 is further provided. One end of the second current source Ib2 is connected to the drain of the twelfth MOS transistor M10, and the other end is grounded. Furthermore, the current output by the switch module 2, that is, the current Ic output by the twelfth MOS transistor M10, is Ic = Ia - Ib2, Equation ⑤. In this application, the first current source Ib1 is set to be the same as the second current source Ib2, that is, Ib1 = Ib2, Equation ⑥. According to Equations ④, ⑤, and ⑥, we get Ic = Ib1 + IL * R / RSNS2 - Ib2 = IL * R / RSNS2, Equation ⑦. It can be seen from Equation ⑦ that Ic is directly proportional to IL.

[0051] Further, in a specific feasible implementation, the high-speed current detection circuit further includes a detection current output terminal CSA_OUT_BUF; the current detection module 1 further includes a current detection output unit 12, and the current detection output unit 12 includes a first amplifier OP2, a second amplifier OP3, a third amplifier OP1, and a second resistor R1; wherein, the positive input terminal of the first amplifier OP2 is connected to a reference voltage VREF, the negative input terminal of the first amplifier OP2 is connected to the negative input terminal of the second amplifier OP3, the output terminal of the first amplifier OP2 is short-circuited to its negative input terminal and is connected to the drain of the twelfth MOS transistor M10 through the second resistor. The positive input terminal of the second amplifier OP3 is connected to the negative input terminal of the third amplifier OP1, the negative input terminal of the second amplifier OP3 is connected to the output terminal of the first amplifier OP2, and the output terminal of the second amplifier OP3 is used to output a zero-current clock detection signal ZC. The positive input terminal of the third amplifier OP1 is connected between the drain of the twelfth MOS transistor M10 and the second resistor R1, the negative input terminal and the output terminal of the third amplifier OP1 are short-circuited, and the output terminal of the third amplifier OP1 is connected to the detection current output terminal CSA_OUT_BUF. In this application, by setting the first amplifier OP2, the second amplifier OP3, the third amplifier OP1, and the second resistor R1, when Ic flows through the second resistor R1, CSA_OUT_BUF = VREF + Ic * R1, Equation ⑧; according to the above Equations ⑦ and ⑧, CSA_OUT_BUF = VREF + IL * R * R1 / RSNS2, Equation ⑨. Thus, the current value I of the power switch M1 to be measured, that is, the detection current, can be obtained through Equation ⑨. According to Equation ⑨, when the current value of the power switch M1 to be measured changes from 0A to I, the jump amplitude of CSA_OUT_BUF also increases accordingly, and thus the current Ia output by the tenth MOS transistor M8 also increases in jump amplitude. Therefore, before setting the replication module 3, when the first switch Switch1 is turned on, a relatively large pressure difference is generated between VGS_M9 of the eleventh MOS transistor M9 and VGS_M10 of the twelfth MOS transistor M10, so the current detection circuit requires a relatively long time to achieve stability. After setting the replication module 3 in this application, since the replication module 3 is connected in parallel with the switch module 2, the pressure difference between VGS_M9 of the eleventh MOS transistor M9 and VGS_M10 of the twelfth MOS transistor M10 becomes smaller, even reaching an optimal state where the pressure difference is almost zero. Therefore, the time required for the current detection circuit to stabilize can be significantly reduced, and the current detection speed is improved.

[0052] Combined with Figure 2 、 Figure 3As shown, in a specific feasible implementation, the replication module 3 includes a first MOS transistor M11, a first resistor R12, a second MOS transistor M12, and a third MOS transistor M13. Among them, the gate of the first MOS transistor M11 is connected to the output terminal CSA_OUT of the switch module 2, the drain is connected to the power supply terminal VDRV, and the source is connected to the drain of the second MOS transistor M12 through the first resistor R12; the gate of the second MOS transistor M12 is shorted to its drain, and the source is grounded; the gate of the third MOS transistor M13 is connected to the gate of the second MOS transistor M12, the drain is connected to the current detection module 1, and the source is grounded.

[0053] In this embodiment, the detection current Ic output by the switch module 2 is replicated by setting the first MOS transistor M11, the first resistor R12, the second MOS transistor M12, and the third MOS transistor M13. Specifically,

[0054] According to the first amplifier OP2 and the second resistor R1, and setting the voltage output by the first amplifier OP2 to 1V, Ic = (CSA_OUT - 1V) / R1 can be obtained, formula ⑩; at the same time, the current Im flowing through the first MOS transistor M11 and the second MOS transistor M12 is Im = (CSA_OUT - VGS_M12 - VGS_M11) / R12, formula ⑪, where VGS_M12 is the gate-source voltage of the second MOS transistor M12, and VGS_M11 is the gate-source voltage of the first MOS transistor M11.

[0055] Furthermore, in this application, the twelfth MOS transistor M12 is a conventional NMOS transistor, and its gate-source voltage VGS_M12 is 800mV; the eleventh MOS transistor M11 is a Native NMOS (intrinsic NMOS) transistor, and its gate-source voltage VGS_M11 is 200mV. Therefore, VGS_M12 + VGS_M11 = 1V, formula ⑫. According to the above formulas ⑩, ⑪, and ⑫, the current flowing through the twelfth MOS transistor M12 is obtained as (CSA_OUT - 1V) / R2; and by setting R1 = R12, the current Im flowing through the second MOS transistor M12 is obtained as Im = Ic.

[0056] Furthermore, the second MOS transistor M12 and the third MOS transistor M13 form a current mirror structure. Therefore, the current flowing through the third MOS transistor M13 is also equal to Ic. In this way, the purpose of replicating the current Ic is achieved. That is to say, the detection current Ic output by the switch module 2 is replicated through the first MOS transistor M11, the first resistor R12, the second MOS transistor M12, and the third MOS transistor M13, and then fed back to the current detection module 1.

[0057] Combined with Figure 4 、 Figure 5As shown, the simulation results show that after the copy module 3 feeds the copied detected current Ic back to the current detection module 1, compared with the traditional circuit, the jump amplitude of Ia in the circuit of the present application is significantly reduced, and it can reach stability quickly. Moreover, the voltage difference between VGS_M9 of the eleventh MOS transistor M9 and VGS_M10 of the twelfth MOS transistor M10 is also significantly reduced.

[0058] As Figure 6 shown, waveform A represents the voltage change of the output terminal CSA_OUT in the circuit of the present application over time, and waveform B represents the voltage change of the output terminal CSA_OUT in the traditional circuit over time. According to waveforms A and B, the voltage rise time in the circuit of the present application is significantly less than that of the traditional circuit, thereby significantly reducing the minimum on-time of the power switch tube M1 to be measured, and this minimum on-time can be reduced to less than 100 ns. In this way, for a high-frequency buck converter, if the operating frequency is 3 MHz, one cycle is only 333 ns. Thus, by reducing the minimum on-time of the power switch tube M1 to be measured, it helps to expand the application range (the range of VIN and VOUT) of the current detection circuit.

[0059] In a specific feasible implementation, as Figure 2 shown, the copy module further includes a second switch switch2. One end of the second switch switch2 is connected to the drain of the third MOS transistor M13, and the other end is connected to the source of the tenth MOS transistor M8 and the drain of the ninth MOS transistor M7. In this embodiment, by setting the second switch switch2, the switching control of the copy module is realized, with simple and reliable control and low cost.

[0060] In a specific feasible implementation, the detection unit further includes an inverter INV and a thirteenth MOS transistor M15. The input end of the inverter INV is connected to the gate of the power switch tube M1 to be measured; the gate of the thirteenth MOS transistor M15 is connected to the output end of the inverter LSGATE, the drain is connected to the source of the seventh MOS transistor M5, and the source is connected to the drain of the fourth MOS transistor M2.

[0061] The present application also provides a power supply circuit including the above-mentioned high-speed current detection circuit.

[0062] By setting the copy module 3 to copy the detected current Ic output by the switch module 2 and feed it back to the current detection module 1, the present application significantly reduces the jump amplitude of the current detection circuit when the power switch tube M1 to be measured switches between off and on, thereby reducing the time required for the current detection circuit to reach stability. In this way, not only the detection efficiency of the circuit is improved, but also it helps to expand the application range of the current detection circuit.

[0063] Those skilled in the art of the present application know that the present application can be implemented as a system, a method, or a computer program product.

[0064] Therefore, the present disclosure can be specifically implemented in the following forms, that is: it can be entirely hardware, or entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software, which is generally referred to as "circuit", "module" or "system" in this article. In addition, in some embodiments, the present application can also be implemented in the form of a computer program product in one or more computer-readable media, which contain computer-readable program code.

[0065] Any combination of one or more computer-readable media can be adopted. The computer-readable media can be computer-readable signal media or computer-readable storage media. The computer-readable storage media can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer-readable storage media can be any tangible medium that contains or stores a program, which can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0066] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application. On this basis, various substitutions and improvements can be made to the present application, and all of these fall within the protection scope of the present application.

Claims

1. A high-speed current detection circuit, characterized in that: include: The power switch tube M1 to be tested; A current detection module, connected to the power switch tube M1 to be tested, used to detect the power switch tube M1 to be tested and generate a detection current; A switch module, connected to the current detection module, and used to control the output of the detection current; A copy module, connected to the current detection module and the switch module, for copying the detection current output by the switch module and feeding it back to the current detection module, so that when the power switch tube M1 to be tested switches between the off state and the on state, the jump amplitude of the detection current is reduced; The high-speed current detection circuit includes a power supply terminal; the replication module includes a first MOS tube M11, a first resistor R12, a second MOS tube M12 and a third MOS tube M13; wherein, The gate of the first MOS tube M11 is connected to the output end of the switch module, the drain is connected to the power supply end, and the source is connected to the drain of the second MOS tube M12 through the first resistor R12; the gate of the second MOS tube M12 is short-circuited with its drain, and the source is grounded; the gate of the third MOS tube M13 is connected to the gate of the second MOS tube M12, the drain is connected to the current detection module, and the source is grounded; The current detection module also includes a detection unit and an error amplification unit; The detection unit includes a fourth MOS tube M2, a fifth MOS tube M3, a sixth MOS tube M4, a seventh MOS tube M5, an eighth MOS tube M6, and a ninth MOS tube M7; The drain of the fourth MOS tube M2 is connected to the source of the power switch tube M1 to be tested, the gate is connected to the power supply end, and the source is connected to the drain of the fifth MOS tube M3; the gate of the fifth MOS tube M3 is connected to the power supply end, and the source is connected to the source of the sixth MOS tube M4; the gate of the sixth MOS tube M4 is connected to the power supply end, and the drain is connected to the error amplification unit; the drain of the seventh MOS tube M5 is connected to the drain of the power switch tube M1 to be tested, the gate is connected to the gate of the power switch tube M1 to be tested, and the source is connected to the drain of the eighth MOS tube M6; the gate of the eighth MOS tube M6 is connected to the power supply end, and the source is connected to the source of the ninth MOS tube M7; the gate of the ninth MOS tube M7 is connected to the power supply end, and the drain is connected to the error amplification unit and the copy module.

2. The high-speed current detection circuit according to claim 1, characterized in that: The error amplification unit includes an error amplifier Error Amp and a tenth MOS tube M8; wherein, The non-inverting input terminal of the error amplifier Error Amp is connected to the drain of the sixth MOS tube M4, the inverting input terminal of the error amplifier Error Amp is connected to the drain of the ninth MOS tube M7, and the output terminal of the error amplifier Error Amp is connected to the gate of the tenth MOS tube M8; the source of the tenth MOS tube M8 is connected to the drain of the ninth MOS tube M7 and the replica module, and the drain is connected to the switch module.

3. The high-speed current detection circuit according to claim 2, characterized in that: The switch module includes an eleventh MOS transistor M9, a twelfth MOS transistor M10, a capacitor C1 and a first switch switch1; wherein, The drain of the eleventh MOS tube M9 is connected to the drain of the tenth MOS tube M8, the source is connected to the power supply end, the gate is short-circuited with its drain and connected to the gate of the twelfth MOS tube M10 through the first switch switch1; the source of the twelfth MOS tube M10 is connected to the power supply end, and the drain is connected to the gate of the first MOS tube; one end of the capacitor C1 is connected between the first switch switch1 and the gate of the twelfth MOS tube M10, and the other end is connected to the power supply end.

4. The high-speed current detection circuit according to claim 3, characterized in that: The high-speed current detection circuit also includes a detection current output terminal; the current detection module also includes a current detection output unit, and the current detection output unit includes a first amplifier OP2, a second amplifier OP3, a third amplifier OP1 and a second resistor R1; wherein, The positive phase input terminal of the first amplifier OP2 is connected to the reference voltage, the negative phase input terminal of the first amplifier OP2 is connected to the negative phase input terminal of the second amplifier OP3, the output terminal of the first amplifier OP2 is short-circuited with its negative phase input terminal and connected to the drain of the twelfth MOS tube M10 through the second resistor; the positive phase input terminal of the second amplifier OP3 is connected to the negative phase input terminal of the third amplifier OP1, the negative phase input terminal of the second amplifier OP3 is connected to the output terminal of the first amplifier OP2, and the output terminal of the second amplifier OP3 is used to output the zero current clock detection signal ZC; the positive phase input terminal of the third amplifier OP1 is connected between the drain of the twelfth MOS tube M10 and the second resistor, the negative phase input terminal of the third amplifier OP1 is short-circuited with the output terminal, and the output terminal of the third amplifier OP1 is connected to the detection current output terminal.

5. The high-speed current detection circuit according to claim 2, characterized in that: The copy module further includes a second switch switch2, one end of which is connected to the drain of the third MOS tube M13, and the other end of which is connected to the source of the tenth MOS tube M8 and the drain of the ninth MOS tube M7.

6. The high-speed current detection circuit according to claim 1, characterized in that: The detection unit further includes an inverter LSGATE and a thirteenth MOS tube M15, wherein: The input end of the inverter LSGATE is connected to the gate of the power switch tube M1 to be tested; the gate of the thirteenth MOS tube M15 is connected to the output end of the inverter LSGATE, the drain is connected to the source of the seventh MOS tube M5, and the source is connected to the drain of the fourth MOS tube M2.

7. The high-speed current detection circuit according to claim 3, characterized in that: It also includes a first current source Ib1, one end of the first current source Ib1 is connected to the power supply end, and the other end is connected to the non-inverting input end of the error amplifier Error Amp; and / or The second current source Ib2 is also included. One end of the second current source Ib2 is connected to the drain of the twelfth MOS transistor M10, and the other end is grounded.

8. A power supply circuit, characterized in that: The invention comprises a high-speed current detection circuit as described in any one of claims 1 to 7.

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