Dynamic stress evaluation and parameter detection method, system, device, storage medium and program product

Abstract

The application relates to a dynamic stress evaluation and parameter detection method, system, device, storage medium and program product, which is applied to a dynamic stress evaluation and parameter detection system, and the dynamic stress evaluation and parameter detection system comprises a host computer, a test circuit board and a signal collector, wherein the test circuit board is arranged with a measured power device on the upper part; the method comprises the following steps: in the case that stress application time corresponding to gate stress applied to the measured power device is exhausted, sending a test loop access instruction to the test circuit board by the host computer; controlling the measured power device to be in a corresponding first stress test loop based on the test loop access instruction by the test circuit board; collecting a gate test signal of the measured power device under the first stress test loop by the signal collector; and detecting an electrical performance parameter of the measured power device based on the gate test signal by the host computer. The method improves the detection accuracy of dynamic stress evaluation and parameter detection.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power device detection, in particular to a dynamic stress evaluation and parameter detection method, system, computer device, computer readable storage medium and computer program product. BACKGROUND

[0002] Compared with silicon-based power devices, gallium nitride and silicon carbide-based power devices have higher breakdown voltage, faster switching speed, lower on-resistance and better stability, etc. The above-mentioned characteristics make gallium nitride and silicon carbide power devices have broad application prospects in electric vehicles, renewable energy systems, efficient power converters and smart grids, etc. Since gallium nitride and silicon carbide power devices are subjected to long-term gate stress, it is necessary to detect the electrical performance parameters of power devices to accurately evaluate the performance and reliability of power devices under gate stress.

[0003] At present, in the process of detecting the electrical performance parameters of power devices, the traditional gate stress test equipment is usually used to apply fixed gate stress, for example, a constant gate voltage or current is applied as a stress source. However, since the gate stress of power devices under actual working conditions is real-time changing, the stress source given by the gate stress test equipment cannot simulate the dynamic gate stress of power devices under actual working conditions, which may lead to the situation that the detected electrical performance parameters are not the actual electrical performance parameters of power devices under working conditions. Therefore, the detection accuracy of the current dynamic stress evaluation and parameter detection is low. SUMMARY

[0004] Therefore, it is necessary to provide a dynamic stress evaluation and parameter detection method, system, computer device, computer readable storage medium and computer program product for improving the detection accuracy of dynamic stress evaluation and parameter detection.

[0005] In a first aspect, the present application provides a dynamic stress evaluation and parameter detection method applied to a dynamic stress evaluation and parameter detection system, wherein the dynamic stress evaluation and parameter detection system comprises an upper computer, a test circuit board and a signal collector, the test circuit board is disposed with a measured power device; the method comprises:

[0006] When the stress application time corresponding to the gate stress applied to the measured power device is exhausted, the upper computer sends a test loop access instruction to the test circuit board;

[0007] The test circuit board controls the measured power device to be in a corresponding first stress test loop based on the test loop access instruction;

[0008] acquire, by the signal collector, a gate test signal of the power device under test in the first stress test loop;

[0009] detect, by the host computer, an electrical performance parameter of the power device under test based on the gate test signal.

[0010] In one of the embodiments, the dynamic stress evaluation and parameter detection system comprises a source table and a program-controlled power supply, the test circuit board comprises a coaxial shunt and a clamping circuit, the gate test signal comprises a first gate test voltage and a second gate test voltage, and the electrical performance parameter comprises a threshold voltage and an on-resistance;

[0011] The detecting, by the host computer, an electrical performance parameter of the power device under test based on the gate test signal comprises one of the following:

[0012] Based on a voltage pulse signal sent by the program-controlled power supply to a power loop of the test circuit board, the host computer receives the first gate test voltage acquired by the signal collector, and takes the first gate test voltage as a trigger signal of the signal collector. After the signal collector is triggered by the first gate test voltage, the signal collector receives a shunt current on the coaxial shunt and a clamping voltage on the clamping circuit. According to the shunt current and the clamping voltage, the on-resistance of the power device under test is detected.

[0013] Based on a current pulse signal sent by the source table, the host computer receives the second gate test voltage acquired by the signal collector, and detects the threshold voltage of the power device under test based on the second gate test voltage.

[0014] In one of the embodiments, the test circuit board comprises a pulse generator and a gate drive.

[0015] In the case where the stress application time corresponding to the gate stress applied to the power device under test is exhausted, before the host computer sends a test loop access instruction to the test circuit board, the method further comprises:

[0016] Based on the signal adjustment instruction sent by the host computer, the initial pulse signal is adjusted by the pulse generator to obtain a target pulse control signal.

[0017] Based on the target pulse control signal, the gate drive applies a gate stress to the power device under test.

[0018] In one of the embodiments, the adjusting of the initial pulse signal to obtain the target pulse control signal at least comprises one of the following:

[0019] adjusting the amplitude of the initial pulse signal to obtain the target pulse control signal;

[0020] adjusting the frequency of the initial pulse signal to obtain the target pulse control signal;

[0021] adjusting the duty cycle of the initial pulse signal to obtain the target pulse control signal.

[0022] In one of the embodiments, after the detection of the electrical performance parameter of the power device under test by the host computer based on the gate test signal, the method further comprises:

[0023] if the electrical performance parameter is between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test is not failed;

[0024] if the electrical performance parameter is not between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test is failed, wherein the first preset electrical performance parameter threshold is less than the second preset electrical performance parameter threshold.

[0025] In one of the embodiments, the test circuit board comprises a recovery test loop and a second stress test loop;

[0026] After the detection of the electrical performance parameter of the power device under test by the host computer based on the gate test signal, the method further comprises at least one of the following:

[0027] performing recovery processing on the power device under test by connecting the power device under test to the recovery test loop;

[0028] detecting the electrical performance parameter of the power device under test by connecting the power device under test to the second stress test loop, wherein the gate stress of the first stress test loop and the second stress test loop is different.

[0029] In a second aspect, the application further provides a dynamic stress evaluation and parameter detection system, which comprises a host computer, a test circuit board and a signal collector, wherein the test circuit board is disposed with a power device under test;

[0030] The host computer is configured to send a test connection instruction to the test circuit board in the case that the stress application time corresponding to the gate stress applied to the power device under test is exhausted, and detect an electrical performance parameter of the power device under test based on a gate test signal transmitted by the signal collector.

[0031] The test circuit board is configured to control the power device under test to be in a corresponding first stress test loop based on the test loop access instruction.

[0032] The signal collector is configured to collect a gate test signal of the power device under test in the first stress test loop by the signal collector.

[0033] In a third aspect, the present application provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0034] In a case where a stress application time corresponding to the gate stress applied to the power device under test is exhausted, the host computer sends a test loop access instruction to the test circuit board; the test circuit board controls the power device under test to be in a corresponding first stress test loop based on the test loop access instruction; the signal collector collects a gate test signal of the power device under test in the first stress test loop; and the host computer detects an electrical performance parameter of the power device under test based on the gate test signal.

[0035] In a fourth aspect, the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the following steps:

[0036] In a case where a stress application time corresponding to the gate stress applied to the power device under test is exhausted, the host computer sends a test loop access instruction to the test circuit board; the test circuit board controls the power device under test to be in a corresponding first stress test loop based on the test loop access instruction; the signal collector collects a gate test signal of the power device under test in the first stress test loop; and the host computer detects an electrical performance parameter of the power device under test based on the gate test signal.

[0037] In a fifth aspect, the present application provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the following steps:

[0038] In a case where a stress application time corresponding to the gate stress applied to the power device under test is exhausted, the host computer sends a test loop access instruction to the test circuit board; the test circuit board controls the power device under test to be in a corresponding first stress test loop based on the test loop access instruction; the signal collector collects a gate test signal of the power device under test in the first stress test loop; and the host computer detects an electrical performance parameter of the power device under test based on the gate test signal.

[0039] The dynamic stress evaluation and parameter detection method, system, computer device, computer readable storage medium and computer program product are applied to a dynamic stress evaluation and parameter detection system, which comprises a host computer, a test circuit board and a signal collector. The test circuit board is disposed with a power device to be tested. First, the host computer sends a test loop access instruction to the test circuit board when the gate stress applied to the power device to be tested is exhausted at a stress application time. Then, the test circuit board controls the power device to be tested to be in a corresponding first stress test loop based on the test loop access instruction. The signal collector collects the gate test signal of the power device to be tested under the first stress test loop. Finally, the host computer detects the electrical performance parameters of the power device to be tested based on the gate test signal. Thus, the real simulation of the dynamic gate stress of the power device to be tested in the actual working condition is realized, and the accurate detection of the electrical performance parameters of the power device to be tested under the real simulated gate stress is completed. That is, the actual electrical performance parameters of the power device are detected by greatly reducing the stress interference in the measurement process and significantly shortening the measurement response time, rather than using the traditional gate stress test equipment to detect the actual electrical performance parameters of the power device by the fixed gate stress. Therefore, the technical defect that the electrical performance parameters detected are not the actual electrical performance parameters of the power device due to the real-time change of the gate stress of the power device in the actual working condition and the stress source given by the gate stress test equipment cannot simulate the dynamic gate stress of the power device in the actual working condition is overcome. Thus, the detection accuracy of the dynamic stress evaluation and parameter detection is improved. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0041] Figure 1 A flowchart of the dynamic stress evaluation and parameter detection method in an embodiment;

[0042] Figure 2 A schematic diagram of the test circuit board of the dynamic stress evaluation and parameter detection method in an embodiment;

[0043] Figure 3 A schematic diagram of the dynamic stress evaluation and parameter detection system of the dynamic stress evaluation and parameter detection method in an embodiment;

[0044] Figure 4 a structural block diagram of a dynamic stress evaluation and parameter detection system in an embodiment;

[0045] Figure 5 an internal structure diagram of a computer device in an embodiment. DETAILED DESCRIPTION

[0046] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0047] Firstly, it should be understood that power devices using gallium nitride and silicon carbide materials as substrates can exhibit threshold voltage (VTH) instability and accompanying dynamic changes in on-resistance under gate stress, thereby affecting the performance and long-term reliability of the power device. For example, threshold voltage drift of a gallium nitride high electron mobility transistor (GaN HEMT) during fast switching can affect the switching characteristics and efficiency of the power device. It can be understood that electron trapping and hole injection in a p-GaN gate HEMT device under positive gate stress cause a significant change in threshold voltage that is different from that of a silicon-based metal-oxide-semiconductor field-effect transistor (Si MOSFET). Similarly, a SiC MOSFET exhibits more significant VTH drift than a Si MOSFET. The instability of VTH is mainly affected by the trapping and emission of positive and negative electric charges in the gate oxide layer. In addition, the dynamic change in on-resistance (RON) is also an important indicator for evaluating the reliability of the device. The change in RON is not only closely related to the instability of VTH, but can also be coupled with drain stress, thereby exhibiting more complex change behavior. Based on the above, since the threshold voltage and on-resistance and other electrical performance parameters of power devices using silicon carbide and gallium nitride as substrates exhibit fast recovery characteristics, the threshold voltage obtained by using the traditional threshold voltage scanning method is severely underestimated. It has been proven that capturing the VTH change on the microsecond time scale through fast measurement technology is a more accurate and effective evaluation method. However, using a traditional gate stress test device with fixed gate stress leads to the fact that the stress source given by the gate stress test device cannot simulate the dynamic gate stress suffered by the power device in actual working conditions, thereby making it easy to occur that the electrical performance parameters detected are not the actual electrical performance parameters of the power device, that is, there is currently a lack of effective means for detecting the electrical performance parameters of the power device under dynamic gate stress. Therefore, how to comprehensively evaluate the reliability of the device in actual application and how to simulate the dynamic gate stress in actual working conditions while quickly and accurately measuring the threshold voltage and on-resistance are difficult problems to be solved in the field, that is, there is an urgent need for a dynamic stress evaluation and parameter detection method for improving the detection accuracy of dynamic stress evaluation and parameter detection.

[0048] In one embodiment, as shown in the figure, Figure 1 a dynamic stress evaluation and parameter detection method is provided. In this embodiment, the method is applied to a dynamic stress evaluation and parameter detection system, which includes a host computer, a test circuit board, and a signal collector. The test circuit board is disposed with a power device under test. It can be understood that the host computer includes, but is not limited to, a personal computer, a notebook computer, a smart phone, a tablet computer, and the like. The signal collector includes, but is not limited to, an oscilloscope, a digital signal collector, a general data collector, and the like. The test circuit board includes, but is not limited to, an aluminum substrate, a ceramic substrate, or a polyimide (PI) board, and the like. The host computer, the test circuit board, and the signal collector are electrically connected in pairs. The test circuit board is disposed with a power device under test. For example, in an implementable manner, the power device under test is soldered on an aluminum substrate with high thermal conductivity, and the gate, drain, and source pins are led out and connected to the dynamic stress evaluation and parameter detection system. The back of the aluminum substrate is tightly attached to a constant temperature heating sheet. The host computer is used to send a test loop connection instruction to the test circuit board when the stress application time corresponding to the gate stress applied to the power device under test is exhausted. Based on the gate test signal transmitted by the signal collector, the electrical performance parameters of the power device under test are detected. The test circuit board controls the gate test signal of the power device under test based on the test loop connection instruction. The signal collector collects the gate test signal of the power device under test under the first stress test loop. Through the signal interaction among the host computer, the test circuit board, and the signal collector, the dynamic gate stress suffered by the power device under test in the actual working condition is truly simulated, and the electrical performance parameters of the power device under test are accurately detected under the truly simulated gate stress applied to the power device under test. That is, by significantly reducing the stress interference in the measurement process and significantly shortening the measurement response time, the actual electrical performance parameters of the power device are detected, so that the detection accuracy of the dynamic stress evaluation and parameter detection is improved. In this embodiment, the method includes the following steps 202 to 208.

[0049] In step 202, a test loop connection instruction is sent to the test circuit board by the host computer when the stress application time corresponding to the gate stress applied to the power device under test is exhausted.

[0050] It should be noted that the measured power device deployed on the test circuit board is connected to the dynamic stress evaluation and parameter detection system through the lead-out pins. For example, in an implementable manner, the lead-out pins of the measured power device have a pitch of 2.54 mm, are compatible with TO220 packaging, and the pin sequence can be GDS. The measured power device refers to a power device waiting for electrical performance parameter detection, which can be a power device with silicon carbide as a substrate or a power device with gallium nitride as a substrate, etc. To evaluate the performance change of the measured power device after experiencing a certain period of gate stress, the stress type, stress size, and stress time can be set through the host computer control program. The stress type includes constant voltage mode (static stress mode) or dynamic stress mode stress. If the stress type is dynamic stress mode stress, the frequency and duty cycle need to be specified. For example, in an implementable manner, the gate stress is applied to the measured power device by short-circuiting the drain and source of the measured power device. The voltage of the gate stress applied to the measured power device can be controlled by a low-dropout linear regulator and a variable potentiometer.

[0051] It should be noted that the test loop access instruction is triggered by the host computer, that is, the test loop access instruction is issued by the host computer program logic control. For example, in an implementable manner, the stress application time can be set in the host computer program, and the stress application time is detected to be exhausted. At this time, the host computer sends a switching circuit instruction to the test circuit board, that is, the host computer sends a test loop access instruction to the test circuit board. After the MCU receives the instruction, a control signal is sent to the high-speed switch to open or close the high-speed switch of the test circuit board. Based on the different types of test loop access instructions, the test circuit board can be in the first stress test loop for detecting the threshold voltage, the first stress test loop for detecting the on-resistance, or end the electrical performance parameter detection process. It can be understood that the stress application time is obtained by pre-setting based on the recovery characteristics of the measured power device.

[0052] It should be noted that, in order to avoid the deviation of the detection result caused by temperature change, the dynamic stress evaluation and parameter detection system can also be provided with a temperature control device, the temperature control device is electrically connected with the test circuit board, and the temperature control device is used for temperature control of the power device under test. It should be noted that, in the process of temperature control of the power device under test, local heating of the test circuit board can be used, for example, in one of the implementable ways, the device is welded on an aluminum substrate with high thermal conductivity, the gate, drain and source pins are connected to the test system, and the back of the aluminum substrate is tightly attached to a constant temperature heating sheet. The constant temperature heating sheet contains a thermocouple feedback, and the temperature is controlled by a PID algorithm. The chip can be welded on the aluminum adapter circuit board, the pins can be extracted using the adapter board, and the socket can be deployed on the test circuit board. Thus, the adapter board can be inserted into the socket of the test circuit board to realize connection. It can be understood that the aluminum substrate has better thermal conductivity than other materials, which is convenient for temperature control, so that the temperature remains unchanged during the detection process.

[0053] As an example, step 202 includes applying gate stress to the power device under test, and sending a test loop access instruction to the test circuit board through the host computer when the actual time of applying the gate stress reaches the stress application time.

[0054] Step 204, based on the test loop access instruction, the test circuit board controls the power device under test to be in the corresponding first stress test loop.

[0055] It should be noted that, under the action of the test loop access instruction, the test circuit board rapidly switches to the first stress test loop through the high-speed switch, so that the subsequent signal collector can collect the gate test signal under the first stress test loop. The first stress test loop can be a threshold voltage test loop or a on-resistance test loop.

[0056] As an example, step 204 includes: based on the test loop access instruction, the test circuit board controls the power device under test to be in the corresponding first stress test loop.

[0057] Step 206, the signal collector collects the gate test signal of the power device under test in the first stress test loop.

[0058] As an example, step 206 includes: the oscilloscope collects the gate test signal of the power device under test in the first stress test loop.

[0059] Step 208, based on the gate test signal, the host computer detects the electrical performance parameters of the power device under test.

[0060] It should be noted that the conversion of the gate test signal to the electrical performance parameter of the power device under test can be completed by the host computer. For example, in an implementable manner, assuming that the signal collector is an oscilloscope, after extracting the test voltage signal, the oscilloscope analyzes the test voltage signal to obtain the electrical performance parameter of the power device under test.

[0061] Specifically, in the case of measuring the threshold voltage, since the clamping voltage and the coaxial shunt current are invalid waveforms at this time, and thus do not need to be collected, the signal collector only needs to collect the gate voltage signal waveform; in the case of measuring the on-resistance, the clamping voltage and the coaxial shunt current need to be collected, and at this time the gate signal is only used to trigger the oscilloscope (i.e., to inform the oscilloscope to collect data), and does not participate in the direct calculation of the on-resistance.

[0062] As an example, step 208 includes detecting, by the host computer, the electrical performance parameter of the power device under test according to the gate test signal.

[0063] The above dynamic stress evaluation and parameter detection method is applied to a dynamic stress evaluation and parameter detection system, which includes a host computer, a test circuit board, and a signal collector. The test circuit board is disposed with a power device under test. First, in the case that the gate stress applied to the power device under test is exhausted at the stress application time, the host computer sends a test loop access instruction to the test circuit board, and then the test circuit board controls the power device under test to be in a corresponding first stress test loop based on the test loop access instruction. The signal collector collects the gate test signal of the power device under test under the first stress test loop. Finally, the host computer detects the electrical performance parameter of the power device under test based on the gate test signal. Thus, the real simulation of the dynamic gate stress of the power device under test in the actual working condition is realized, and the accurate detection of the electrical performance parameter of the power device under test under the real simulation of the gate stress applied to the power device under test is completed. That is, by significantly reducing the stress interference in the measurement process and significantly shortening the measurement response time, the actual electrical performance parameter of the power device is detected. Unlike the conventional gate stress test equipment, the actual electrical performance parameter of the power device is detected by the fixed gate stress. Therefore, the technical defect that the electrical performance parameter detected is not the actual electrical performance parameter of the power device due to the real-time change of the gate stress of the power device in the actual working condition, which makes the stress source given by the gate stress test equipment unable to simulate the dynamic gate stress of the power device in the actual working condition, is overcome. Thus, the detection accuracy of the dynamic stress evaluation and parameter detection is improved.

[0064] In one embodiment, the dynamic stress evaluation and parameter detection system comprises a source table and a program-controlled power supply, the test circuit board comprises a coaxial shunt and a clamping circuit, the gate test signal comprises a first gate test voltage and a second gate test voltage, and the electrical performance parameter comprises a threshold voltage and an on-resistance;

[0065] The upper computer detects the electrical performance parameter of the power device under test based on the gate test signal, and the electrical performance parameter comprises one of the following:

[0066] In step 302, the first gate test voltage collected by the signal collector of the upper computer is received based on the voltage pulse signal emitted by the program-controlled power supply to the power loop of the test circuit board, and the first gate test voltage is used as the trigger signal of the signal collector. After the signal collector is triggered by the first gate test voltage, the shunt current on the coaxial shunt and the clamping voltage on the clamping circuit are received. The on-resistance of the power device under test is detected according to the shunt current and the clamping voltage.

[0067] It should be noted that the electrical performance parameter comprises a threshold voltage and an on-resistance. It can be understood that the threshold voltage and the on-resistance can be detected based on the same dynamic stress evaluation and parameter detection system, but there are differences in the specific detection logic. In the process of detecting the on-resistance of the power device under test, the first gate test voltage is measured by the probe of the first channel of the oscilloscope (GS means gate G to source S), and the first gate test voltage is used as the trigger signal of the oscilloscope. The clamping voltage on the clamping circuit is measured by the probe of the second channel of the oscilloscope (M means Measure, i.e. measurement), and the shunt current on the coaxial shunt is measured by the third channel of the oscilloscope (DS means drain D to source S), and the on-resistance can be solved based on the above. The expression for solving the on-resistance is as follows:

[0068]

[0069] wherein, is a constant related to the clamping circuit, is the contact resistance of K1 in the test circuit board, and is a constant, is the clamping voltage, is the shunt current.

[0070] As an example, step 302 comprises: the first gate test voltage collected by the oscilloscope is received by the upper computer through the voltage pulse signal emitted by the program-controlled power supply, and the first gate test voltage is used as the trigger signal of the oscilloscope. After the oscilloscope is triggered by the first gate test voltage, the shunt current on the coaxial shunt and the clamping voltage on the clamping circuit are received. The on-resistance of the power device under test is detected according to the shunt current and the clamping voltage.

[0071] In step 304, based on the current pulse signal emitted by the source table, the second gate test voltage collected by the signal collector of the host computer is acquired, and based on the second gate test voltage, the threshold voltage of the power device under test is detected.

[0072] It should be noted that the capture of the threshold voltage can also be completed by the signal collector. For example, in an implementable manner, when the first stress test loop is switched to the stress test loop for detecting the threshold voltage, the SMU emits a current pulse signal of a specified size, thereby triggering the oscilloscope to collect the second gate test voltage. Specifically, the stable segment of the second gate test voltage can be extracted as the second gate test voltage, and the current pulse signal can be 1 mA current pulse.

[0073] As an example, step 304 includes: according to the current pulse signal emitted by the source table, the second gate test voltage collected by the signal collector of the host computer is acquired, and the voltage in the stable segment is selected as the target gate test voltage; and the target gate test voltage is taken as the threshold voltage of the power device under test.

[0074] In the present embodiment, in the process of detecting the electrical performance parameters of the power device under test by the host computer based on the gate test signal, different detection methods are adopted for detection based on the different electrical performance parameters to be detected, that is, when detecting the on-resistance of the power device under test, the voltage pulse signal emitted by the program-controlled power source triggers the collection of the first gate test voltage, the shunt current and the clamping voltage, and finally the on-resistance of the power device under test is detected by fusing the first gate test voltage, the shunt current and the clamping voltage, while when detecting the threshold voltage of the power device under test, the current pulse signal emitted by the source table triggers the collection of the second gate test voltage, and finally the threshold voltage of the power device under test is detected by the second gate test voltage, thereby achieving the purpose of quickly capturing the threshold voltage and on-resistance of the power device under test by the host computer cooperating with the source table, the program-controlled power source and the oscilloscope, so as to improve the detection accuracy of the threshold voltage and on-resistance of the power device under test.

[0075] In one embodiment, the test circuit board includes a pulse generator and a gate driver;

[0076] In the case where the stress application time corresponding to the gate stress applied to the power device under test is exhausted, before the host computer sends the test loop access instruction to the test circuit board, the method further includes:

[0077] Adjust the initial pulse signal to obtain a target pulse control signal based on the signal adjustment instruction sent by the host computer; and apply gate stress to the power device under test through the gate drive based on the target pulse control signal.

[0078] It should be noted that the actual gate stress can be sent to the power device under test through the gate drive, that is, a correct control signal is provided for the gate drive, so that the gate drive correctly sends the waveform, and the frequency and duty cycle of the control signal also determine the frequency and duty cycle of the gate stress waveform sent by the gate drive. By regarding the gate drive as an amplifier, the low level (0V) of the control signal can be amplified to VGS(OFF), and the high level (>2V) of the control signal can be amplified to VGS(ON), wherein VGS(OFF) and VGS(ON) are the low level and high level of the dynamic stress, and their sizes are adjustable. It can be understood that the control signal for the gate drive can be any form of pulse generator, such as a micro control unit (MCU), a field programmable gate array (FPGA), and a function signal generator. By integrating the MCU on the test circuit board, the pulse waveform can be sent to the gate drive. At the same time, the MCU is connected to the host computer, and according to the test loop connection instruction sent by the host computer to the test circuit board, the target pulse control signal is obtained by adjusting the initial pulse signal based on the signal adjustment instruction sent by the host computer. Figure 3 , Figure 3 The test circuit board controls the MCU to open or close the five high-speed switches K1 to K5 according to the test loop connection instruction, so that the power device under test is in the first stress test loop in the corresponding mode. At the same time, the test circuit board can modify the control signal with different frequencies and duty cycles sent to the gate drive according to the instruction of the host computer, so as to realize the adjustment of the dynamic gate stress.

[0079] As an example, the initial pulse signal is adjusted to the target pulse control signal based on the signal adjustment instruction sent by the host computer; and the gate stress is applied to the power device under test through the gate drive under the action of the target pulse control signal. In this embodiment, the pulse generator and the gate drive are deployed on the test circuit board, so that before the test loop connection instruction is sent to the test circuit board by the host computer, the initial pulse signal is adjusted to the target pulse control signal by the pulse generator based on the signal adjustment instruction sent by the host computer, and then the gate stress is applied to the power device under test through the gate drive under the action of the target pulse control signal, so as to realize the purpose of dynamically adjusting the gate stress applied to the power device under test. Therefore, it lays a foundation for improving the detection accuracy of dynamic stress evaluation and parameter detection.

[0080] In one embodiment, the initial pulse signal is adjusted to obtain a target pulse control signal, including at least one of the following:

[0081] The amplitude of the initial pulse signal is adjusted to obtain a target pulse control signal; the frequency of the initial pulse signal is adjusted to obtain a target pulse control signal; and the duty cycle of the initial pulse signal is adjusted to obtain a target pulse control signal.

[0082] It should be noted that, in the process of adjusting the initial pulse signal by the pulse generator, different adjustment modes can be adopted to adjust the initial pulse signal based on different signal adjustment instructions. Specifically, the size (amplitude), frequency, and duty cycle of the initial pulse signal can be adjusted synchronously, or the size, frequency, and duty cycle of the initial pulse signal can be adjusted individually.

[0083] As an example, the amplitude of the initial pulse signal is adjusted to obtain a target pulse control signal; the frequency of the initial pulse signal is adjusted to obtain a target pulse control signal; and the duty cycle of the initial pulse signal is adjusted to obtain a target pulse control signal.

[0084] In this embodiment, the amplitude, frequency, and / or duty cycle of the initial pulse signal are adjusted to obtain a target pulse control signal for applying a gate stress to the power device under test, so that different types of dynamic gate stress can be flexibly provided for detecting the electrical performance parameters of the power device under test, thereby laying a foundation for improving the detection accuracy of dynamic stress evaluation and parameter detection.

[0085] In one embodiment, after the host computer detects the electrical performance parameters of the power device under test based on the gate test signal, the method further includes:

[0086] If the electrical performance parameter is between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test is not failed; and if the electrical performance parameter is not between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test is failed, wherein the first preset electrical performance parameter threshold is smaller than the second preset electrical performance parameter threshold.

[0087] It should be noted that, after the electrical performance parameters of the power device under test are detected, the performance of the power device under test can be further discriminated based on the detected electrical performance parameters. For example, in one implementable manner, assuming that the electrical performance parameter is the threshold voltage, the first preset voltage threshold and the second preset voltage threshold can be set synchronously, wherein the first preset voltage threshold is 1.6V and the second preset voltage threshold is 2.4V. When the threshold voltage of the power device under test before stress is detected to be 2V (between the first preset voltage threshold and the second preset voltage threshold), it is determined that the power device under test is not failed, and when the threshold voltage of the power device under test is detected to be 2.6V (>2.4V) or 1.2V (<1.6V), it is determined that the power device under test is failed.

[0088] As an example, the test circuit board comprises a recovery test loop and a second stress test loop;

[0089] After detecting the electrical performance parameter of the power device under test based on the gate test signal by the host computer, the method further comprises at least one of the following:

[0090] The recovery process of the power device under test is tracked by connecting the power device under test to the recovery test loop, and the influence of the cumulative stress on the power device under test is evaluated by connecting the power device under test to the second stress test loop, for example, in an implementable manner, assuming that the electrical performance parameter is the threshold voltage, to capture the curve of the threshold voltage drift over time, a first stress can be applied for a period of time, and then the threshold voltage is measured quickly, and then a second stress is applied for a period of time, and the influence of the cumulative stress is accumulated through the cycle until the stress application time is exhausted, that is, until the stress application time is exhausted, and then the recovery mode is entered, wherein the first stress and the second stress are different stresses, and the power device under test is also connected to the recovery test loop, and the process can be recovery-measurement-recovery-measurement, and so on, until the stress application time is exhausted, and the program exits.

[0091] It should be noted that after the detection of the electrical performance parameter of the power device under test is completed, the recovery process of the power device under test can be tracked by connecting the power device under test to the recovery test loop, and the influence of the cumulative stress on the power device under test can be evaluated by connecting the power device under test to the second stress test loop, for example, in an implementable manner, assuming that the electrical performance parameter is the threshold voltage, to capture the curve of the threshold voltage drift over time, a first stress can be applied for a period of time, and then the threshold voltage is measured quickly, and then a second stress is applied for a period of time, and the influence of the cumulative stress is accumulated through the cycle until the stress application time is exhausted, that is, until the stress application time is exhausted, and then the recovery mode is entered, wherein the first stress and the second stress are different stresses, and the power device under test is also connected to the recovery test loop, and the process can be recovery-measurement-recovery-measurement, and so on, until the stress application time is exhausted, and the program exits.

[0092] As an example, the recovery process of the power device under test is tracked by connecting the power device under test to the recovery test loop, and the influence of the cumulative stress on the power device under test is evaluated by connecting the power device under test to the second stress test loop, for example, in an implementable manner, assuming that the electrical performance parameter is the threshold voltage, to capture the curve of the threshold voltage drift over time, a first stress can be applied for a period of time, and then the threshold voltage is measured quickly, and then a second stress is applied for a period of time, and the influence of the cumulative stress is accumulated through the cycle until the stress application time is exhausted, that is, until the stress application time is exhausted, and then the recovery mode is entered, wherein the first stress and the second stress are different stresses, and the power device under test is also connected to the recovery test loop, and the process can be recovery-measurement-recovery-measurement, and so on, until the stress application time is exhausted, and the program exits.

[0093] In this embodiment, after the electrical performance parameter of the power device under test is detected, the loop of the power device under test can be switched, for example, the power device under test can be connected to the recovery test loop or the second stress test loop, so as to realize in-depth exploration of the mutual relationship between the electrical performance parameter and the on-resistance in the degradation process, and provide a new perspective and data support for reliability analysis and life prediction of the power device under test, so as to improve the detection accuracy of dynamic stress evaluation and parameter detection, and at the same time, the detection effect of dynamic stress evaluation and parameter detection is improved.

[0094] In an implementable manner, referring to Figure 3 , Figure 3The overall schematic diagram of the dynamic stress evaluation and parameter detection system, wherein the dynamic stress evaluation and parameter detection system comprises a programmable power supply, an oscilloscope, a source meter, a temperature control device, an upper computer and a test circuit board, and the connection relationship of the above-mentioned devices is shown in the figure. First, the dynamic stress evaluation and parameter detection system is switched to the first stress test loop, and the stress type, stress size and stress time are set through the upper computer control program. The stress size can be controlled by a low dropout linear regulator and an adjustable potentiometer. The stress is started to be applied. After the stress application time is consumed, the first stress test loop for detecting the threshold voltage and the first stress test loop for detecting the on-resistance are rapidly switched by using a high-speed switch. The data is measured and collected. The speed of the high-speed switch can be set in advance. The greater the switching delay of the high-speed switch, the longer the recovery time of the device (leaving the stress loop means removing the stress, and the device starts to recover). The measured threshold voltage of the device is low. Therefore, the smaller the switching delay, the better. The speed of the high-speed switch can be set to about 10 ms. Preferably, the speed of the high-speed switch is <1 ms. After the measurement and data collection are completed, the device failure condition can be judged according to the parameters. If it is failed, the process can be exited in advance. In the threshold voltage measurement loop and the on-resistance measurement loop (the first stress test loop), the oscilloscope and the source meter are connected to the device source electrode. In the threshold voltage measurement loop, the gate and the drain of the device are short-circuited, the source meter and the oscilloscope are connected to the gate. In the threshold voltage measurement loop, the source meter outputs a precise constant current, and the oscilloscope captures the gate voltage waveform and returns it to the upper computer to analyze the threshold voltage. In the on-resistance measurement loop, the gate of the device is connected to a double-pulse generation circuit, the drain of the device is connected to an inductive load and a clamping circuit, the other end of the inductive load is connected to the positive electrode of the programmable power supply, the source of the device is connected to a coaxial shunt, and the other end of the coaxial shunt is connected to the negative electrode of the programmable power supply. The oscilloscope is connected to the gate, the clamping circuit and the coaxial shunt. In the on-resistance measurement loop, the programmable power supply outputs a constant voltage. At the same time, a double pulse is applied to the gate of the measured power device through the pulse generator. After the oscilloscope captures the double pulse test waveform, it returns to the upper computer to analyze and obtain the on-resistance. After the measurement is completed, the device can be connected to the recovery loop or the stress loop. The recovery test loop is short-circuited, i.e. the three terminals are grounded. The second stress test loop is the same as the first stress test loop. The recovery test loop is similar to the first stress test loop. After the recovery time is consumed, it can still be switched to the first stress test loop to monitor the recovery process of the device. According to the upper computer program setting, the above steps are repeated until the program exit condition is met or manually exited. It can be understood that the repetition is not a simple mechanical repetition. This step allows flexible adjustment of the stress type, intensity and duration according to the specific needs of the experiment. According to the test purpose, the measurement parameter option can be changed, and the threshold voltage measurement loop or the on-resistance measurement loop can be selectively connected to realize the alternative measurement of the threshold voltage and the on-resistance.

[0095] The above dynamic stress evaluation and parameter detection method can realize real simulation of the dynamic gate stress suffered by the measured power device in actual working conditions, and accurately detect the electrical performance parameters of the measured power device under the real simulated gate stress applied to the measured power device, that is, by greatly reducing the stress interference in the measurement process and significantly shortening the measurement response time, the actual electrical performance parameters of the power device are detected, rather than only using the traditional gate stress test equipment to detect the actual electrical performance parameters of the power device by fixed gate stress. Therefore, the technical defect that the electrical performance parameters detected are not the actual electrical performance parameters of the power device due to the real-time change of the gate stress of the power device in actual working conditions, which causes the stress source given by the gate stress test equipment to be unable to simulate the dynamic gate stress suffered by the power device in actual working conditions, is overcome, and the detection accuracy of dynamic stress evaluation and parameter detection is improved.

[0096] It should be understood that, although each step in the flowchart involved in the above embodiments is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in the above embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be alternately executed with other steps or steps or stages in other steps.

[0097] Based on the same inventive concept, the embodiments of the present application also provide a dynamic stress evaluation and parameter detection system for implementing the above-mentioned dynamic stress evaluation and parameter detection method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more dynamic stress evaluation and parameter detection system embodiments provided below can refer to the limitations of the dynamic stress evaluation and parameter detection method in the above text, which will not be repeated here.

[0098] In one exemplary embodiment, as shown in Figure 4 A dynamic stress evaluation and parameter detection system is provided, which includes a host computer 401, a test circuit board 402, and a signal collector 403, wherein the test circuit board is disposed with a measured power device;

[0099] The host computer 401 is configured to send a test access instruction to the test circuit board when the gate stress applied to the power device under test is exhausted, and detect the electrical performance parameter of the power device under test based on the gate test signal transmitted by the signal collector.

[0100] The test circuit board 402 is configured to control the power device under test to be in a corresponding first stress test loop based on the test loop access instruction.

[0101] The signal collector 403 is configured to collect the gate test signal of the power device under test in the first stress test loop by the signal collector.

[0102] In one embodiment, the dynamic stress evaluation and parameter detection system includes a source table and a program-controlled power supply, the test circuit board includes a coaxial shunt and a clamping circuit, the gate test signal includes a first gate test voltage and a second gate test voltage, and the electrical performance parameter includes a threshold voltage and an on-resistance; the host computer 401 is further configured to:

[0103] Based on the voltage pulse signal transmitted by the program-controlled power supply to the power loop of the test circuit board, the first gate test voltage collected by the signal collector is received by the host computer, and the first gate test voltage is used as the trigger signal of the signal collector; after the signal collector is triggered by the first gate test voltage, the shunt current on the coaxial shunt and the clamping voltage on the clamping circuit are received; the on-resistance of the power device under test is detected according to the shunt current and the clamping voltage; based on the current pulse signal transmitted by the source table, the second gate test voltage collected by the signal collector is received by the host computer, and the threshold voltage of the power device under test is detected based on the second gate test voltage.

[0104] In one embodiment, the test circuit board includes a pulse generator and a gate drive; the dynamic stress evaluation and parameter detection system is further configured to:

[0105] Based on the signal adjustment instruction sent by the host computer, the initial pulse signal is adjusted by the pulse generator to obtain a target pulse control signal; based on the target pulse control signal, the gate stress is applied to the power device under test by the gate drive.

[0106] In one embodiment, the dynamic stress evaluation and parameter detection system is further configured to:

[0107] The amplitude of the initial pulse signal is adjusted to obtain the target pulse control signal; the frequency of the initial pulse signal is adjusted to obtain the target pulse control signal; and the duty cycle of the initial pulse signal is adjusted to obtain the target pulse control signal.

[0108] In one of the embodiments, the dynamic stress evaluation and parameter detection system is further configured to:

[0109] If the electrical performance parameter is between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test is not failed; and if the electrical performance parameter is not between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test is failed, wherein the first preset electrical performance parameter threshold is smaller than the second preset electrical performance parameter threshold.

[0110] In one of the embodiments, the test circuit board comprises a recovery test loop and a second stress test loop; and the dynamic stress evaluation and parameter detection system is further configured to:

[0111] After the electrical performance parameter of the power device under test is detected based on the gate test signal by the host computer, the method further comprises at least one of the following: performing recovery processing on the power device under test by connecting the power device under test to the recovery test loop; and detecting the electrical performance parameter of the power device under test by connecting the power device under test to the second stress test loop, wherein the gate stress of the first stress test loop and the second stress test loop is different.

[0112] Each of the modules in the dynamic stress evaluation and parameter detection system described above can be realized by software, hardware, and a combination thereof, in whole or in part. Each of the modules described above can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a memory in a computer device in software form, so as to be called and executed by a processor to perform the operations corresponding to each of the modules.

[0113] In one exemplary embodiment, a computer device is provided, which can be a terminal, and an internal structure diagram of the computer device can be as shown in Figure 5The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus. The communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to perform wired or wireless communication with external terminals. The wireless communication can be achieved through WIFI, mobile cellular network, NFC (Near Field Communication) or other technologies. The computer program is executed by the processor to implement a dynamic stress evaluation and parameter detection method. Those skilled in the art can understand that, Figure 5 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0114] In one embodiment, a computer device is also provided, including a memory and a processor. The memory stores a computer program. The processor executes the computer program to implement the steps in the above method embodiments.

[0115] In one embodiment, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the steps in the above method embodiments.

[0116] In one embodiment, a computer program product is provided, which includes a computer program. The computer program is executed by a processor to implement the steps in the above method embodiments.

[0117] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0118] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0119] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method of dynamic stress assessment and parameter detection, characterized in that, The application is applied to a dynamic stress evaluation and parameter detection system, the dynamic stress evaluation and parameter detection system comprises a host computer, a test circuit board and a signal collector, wherein the test circuit board is disposed with a power device to be tested; the method comprises: In the case that the stress application time corresponding to the gate stress applied to the power device to be tested is exhausted, the host computer sends a test loop access instruction to the test circuit board; The test circuit board controls the power device to be tested to be in a corresponding first stress test loop based on the test loop access instruction; The signal collector collects the gate test signal of the power device to be tested under the first stress test loop; The host computer detects the electrical performance parameters of the power device to be tested based on the gate test signal, wherein the dynamic stress evaluation and parameter detection system comprises a source table and a program-controlled power supply, the test circuit board comprises a coaxial shunt and a clamping circuit, the gate test signal comprises a first gate test voltage and a second gate test voltage, and the electrical performance parameters comprise a threshold voltage and an on-resistance; The host computer detects the electrical performance parameters of the power device to be tested based on the gate test signal, which comprises one of the following: Based on the voltage pulse signal sent by the program-controlled power supply to the power loop of the test circuit board, the host computer receives the first gate test voltage collected by the signal collector, and takes the first gate test voltage as the trigger signal of the signal collector, the signal collector is triggered by the first gate test voltage, and receives the shunt current on the coaxial shunt and the clamping voltage on the clamping circuit; according to the shunt current and the clamping voltage, the on-resistance of the power device to be tested is detected; Based on the current pulse signal sent by the source table, the host computer receives the second gate test voltage collected by the signal collector, and detects the threshold voltage of the power device to be tested based on the second gate test voltage.

2. The method of claim 1, wherein, The test circuit board comprises a pulse generator and a gate drive; Before the host computer sends a test loop access instruction to the test circuit board in the case that the stress application time corresponding to the gate stress applied to the power device to be tested is exhausted, the method further comprises: Based on the signal adjustment instruction sent by the host computer, the initial pulse signal is adjusted by the pulse generator to obtain a target pulse control signal; Based on the target pulse control signal, the gate drive applies a gate stress to the power device to be tested.

3. The method of claim 2, wherein, The initial pulse signal is adjusted to obtain a target pulse control signal, which at least comprises one of the following: The amplitude of the initial pulse signal is adjusted to obtain the target pulse control signal; The frequency of the initial pulse signal is adjusted to obtain the target pulse control signal; The duty cycle of the initial pulse signal is adjusted to obtain the target pulse control signal.

4. The method of claim 1, wherein, After the host computer detects the electrical performance parameters of the power device to be tested based on the gate test signal, the method further comprises: If the electrical performance parameter is between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the measured power device is not failed; If the electrical performance parameter is not between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the measured power device is failed, wherein the first preset electrical performance parameter threshold is smaller than the second preset electrical performance parameter threshold.

5. The method of claim 1, wherein, The test circuit board comprises a recovery test loop and a second stress test loop; After the upper computer detects the electrical performance parameter of the measured power device based on the gate test signal, the method further comprises one of the following: The measured power device is subjected to recovery processing by being connected to the recovery test loop; The electrical performance parameter of the measured power device is detected by being connected to the second stress test loop, wherein the gate stress of the first stress test loop and the second stress test loop is different.

6. A dynamic stress evaluation and parameter detection system, the system comprising a host computer, a test circuit board and a signal collector, wherein, The test circuit board is disposed with a measured power device; The upper computer is configured to send a test loop connection instruction to the test circuit board when the gate stress applied to the measured power device is exhausted, and detect the electrical performance parameter of the measured power device based on the gate test signal transmitted by the signal collector; The test circuit board is configured to control the measured power device to be in a corresponding first stress test loop based on the test loop connection instruction; The signal collector is configured to collect the gate test signal of the measured power device in the first stress test loop by the signal collector, wherein the dynamic stress evaluation and parameter detection system comprises a source table and a program-controlled power supply, the test circuit board comprises a coaxial shunt and a clamping circuit, the gate test signal comprises a first gate test voltage and a second gate test voltage, the electrical performance parameter comprises a threshold voltage and an on-resistance, and the upper computer is further configured to: Based on the voltage pulse signal transmitted by the program-controlled power supply to the power loop of the test circuit board, the first gate test voltage collected by the signal collector is received by the upper computer, and the first gate test voltage is used as a trigger signal of the signal collector, after the signal collector is triggered by the first gate test voltage, the shunt current on the coaxial shunt and the clamping voltage on the clamping circuit are received, the on-resistance of the measured power device is detected according to the shunt current and the clamping voltage, based on the current pulse signal transmitted by the source table, the second gate test voltage collected by the signal collector is received by the upper computer, and the threshold voltage of the measured power device is detected based on the second gate test voltage.

7. The system of claim 6, wherein, The test circuit board comprises a pulse generator and a gate drive; and the system is further configured to: Adjust the initial pulse signal through a pulse generator based on the signal adjustment instruction sent by the host computer to obtain a target pulse control signal; and apply gate stress to the power device under test through the gate drive based on the target pulse control signal. 8.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-7. The computer program, when executed by the processor, implements the steps of the method of any one of claims 1 to 5.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by the processor, implements the steps of the method of any one of claims 1 to 5.

10. A computer program product comprising a computer program, characterized in that, The computer program, when executed by the processor, implements the steps of the method of any one of claims 1 to 5. The computer program, when executed by the processor, implements the steps of the method of any one of claims 1 to 5.

Images