A reference source circuit

Abstract

An embodiment of the present application provides a reference source circuit, relating to the technical field of reference source circuits. The reference source circuit includes a bias circuit, a positive temperature coefficient voltage generating circuit, and a negative temperature coefficient voltage generating circuit. The bias circuit is used to provide bias current for the positive temperature coefficient voltage generating circuit and the negative temperature coefficient voltage generating circuit. The output end of the positive temperature coefficient voltage generating circuit is connected to the output end of the negative temperature coefficient voltage generating circuit, serving as the reference voltage output end of the reference source circuit. The temperature characteristics of the positive temperature coefficient voltage generating circuit and the negative temperature coefficient voltage generating circuit are opposite, and they have a mutually compensating effect, so that the final output voltage has no obvious temperature characteristics.

Description

Technical Field

[0001] The present application relates to the technical field of reference source circuits. Background Art

[0002] Currently, popular portable and wearable electronic products require low power consumption, making research in power management chips crucial. As a key module in ADC and power supply circuits, low-voltage, low-power analog circuits using standard CMOS processes are gaining increasing attention. Low-voltage analog circuits not only significantly reduce power consumption but also enhance circuit stability. In analog-to-digital conversion circuits, the reference source plays a crucial role, with its temperature coefficient determining the accuracy of the analog-to-digital converter.

[0003] How to design a reference voltage circuit with good temperature characteristics is the technical problem to be solved by this application. Summary of the Invention

[0004] The purpose of this application is to provide a reference voltage circuit to solve the technical problem of how to design a reference voltage circuit with good temperature characteristics.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions.

[0006] The present invention provides a reference source circuit, including a bias circuit, a positive temperature coefficient voltage generating circuit, and a negative temperature coefficient voltage generating circuit.

[0007] The bias circuit is used to provide bias current for the positive temperature coefficient voltage generating circuit and the negative temperature coefficient voltage generating circuit;

[0008] When the positive temperature coefficient voltage generating circuit works alone, the output voltage is positively correlated with the temperature;

[0009] The output voltage of the negative temperature coefficient voltage generating circuit is negatively correlated with the temperature when working alone;

[0010] The output end of the positive temperature coefficient voltage generating circuit and the output end of the negative temperature coefficient voltage generating circuit are connected to serve as the reference voltage output end of the reference source circuit.

[0011] Optionally, the positive temperature coefficient voltage generating circuit includes a first MOS tube, a first branch unit, a second branch unit and a voltage generating unit;

[0012] The gate terminal of the first MOS transistor is connected to the bias circuit, and the first MOS transistor generates a bias current according to the bias circuit;

[0013] The first branch unit and the second branch unit both include MOS tubes;

[0014] The bias current causes the MOS transistors in the first branch unit and the second branch unit to operate in a subthreshold region;

[0015] The gate-source voltage difference generated by the MOS tube in the first branch unit is a first voltage difference;

[0016] The gate-source voltage difference generated by the MOS transistor in the second branch unit is a second voltage difference; the second voltage difference is different from the first voltage difference;

[0017] The voltage generating unit generates a voltage according to a difference between the second voltage difference and the first voltage difference.

[0018] Optionally, the first branch unit includes n second MOS transistors connected in series; the second branch unit includes n third MOS transistors connected in series; n≥2;

[0019] The width-to-length ratio of the second MOS transistor is different from the width-to-length ratio of the third MOS transistor.

[0020] Optionally, the voltage generating unit includes a resistor, or the voltage generating unit includes a fourth MOS transistor and a bias unit;

[0021] The drain end of the fourth MOS transistor is connected to the first end of the second branch unit, the source end of the fourth MOS transistor is grounded, and the gate end of the fourth MOS transistor is connected to the bias unit;

[0022] The first end of the first branch unit is grounded, the second end of the first branch unit is connected to the second end of the second branch unit, and the current of the first MOS transistor flows into the second end of the first branch unit and the second end of the second branch unit.

[0023] Optionally, the bias unit includes a fifth MOS transistor and a sixth MOS transistor;

[0024] The source terminal of the fifth MOS transistor is connected to a voltage source, the gate terminal of the fifth MOS transistor is connected to the drain terminal of the fifth MOS transistor, the drain terminal of the fifth MOS transistor is connected to the drain terminal of the sixth MOS transistor, the drain terminal of the sixth MOS transistor is connected to the gate terminal of the sixth MOS transistor and the gate terminal of the fourth MOS transistor, and the source terminal of the sixth MOS transistor is grounded;

[0025] The gate terminal of the sixth MOS transistor provides a bias for the gate terminal of the fourth MOS transistor so that the fourth MOS transistor operates in a linear region or a deep linear region;

[0026] The drain end of the sixth MOS transistor serves as the output end of the positive temperature coefficient voltage generating circuit.

[0027] Optionally, the negative temperature coefficient voltage generating circuit includes a seventh MOS transistor and an eighth MOS transistor;

[0028] The gate terminal of the seventh MOS transistor is connected to the bias circuit, and the seventh MOS transistor generates a bias current according to the bias circuit;

[0029] The source end of the eighth MOS transistor is connected to the seventh MOS transistor, and the source end of the eighth MOS transistor is connected to the output end of the positive temperature coefficient voltage generating circuit, the gate end of the eighth MOS transistor is connected to the drain end of the eighth MOS transistor, and the drain end of the eighth MOS transistor is grounded.

[0030] Optionally, the reference source circuit further includes a startup circuit;

[0031] The control end of the startup circuit is connected to the reference voltage output end of the reference source circuit; the input end of the startup circuit is connected to the voltage source, and the output end of the startup circuit is connected to the bias circuit;

[0032] The startup circuit is used to start the bias circuit, and when the reference source circuit outputs normally, the startup circuit stops running.

[0033] Optionally, the bias circuit includes a gate voltage control circuit and a bias current generating circuit;

[0034] The startup circuit is used to inject current into the gate voltage control circuit during startup, so that the gate voltage control circuit operates in the subthreshold region;

[0035] The gate voltage control circuit is used to enable the bias current generating circuit to generate the bias current when operating in the subthreshold region.

[0036] Optionally, the bias circuit is a nA-level bias circuit;

[0037] The bias circuit includes M7 tube, M8 tube, M9 tube, M10 tube, M11 tube, M12 tube, M13 tube, M14 tube, M15 tube, M16 tube, M17 tube, M18 tube, M19 tube, M20 tube, M21 tube, M22 tube, M23 tube, M24 tube and M25 tube;

[0038] The M7 tube, the M10 tube, the M13 tube, the M14 tube, the M17 tube, the M19 tube, the M22 tube and the M23 tube are PMOS tubes;

[0039] The M8 tube, the M9 tube, the M11 tube, the M12 tube, the M15 tube, the M16 tube, the M20 tube, the M21 tube, the M24 tube and the M25 tube are NMOS tubes;

[0040] The source terminal of the M17 tube is connected to the voltage source VDD, the gate terminal is connected to the gate terminal and drain terminal of the M14 tube, and is connected to the voltage node VM of the startup circuit, and the drain terminal is connected to the drain terminal of the M18 tube;

[0041] The gate end of the M18 tube is connected to the gate end of the M22 tube, and the drain end is connected to the source end of the M19 tube;

[0042] The source terminal of the M22 tube is connected to the voltage source VDD, and the gate terminal is connected to the drain terminal and connected to the source terminal of the M23 tube;

[0043] The gate terminal of the M19 tube is connected to the gate terminal of the M23 tube, and the drain terminal is connected to the drain terminal and gate terminal of the M20 tube and serves as the VBIAS1 node;

[0044] The gate terminal of the M23 tube is connected to the drain terminal and is also connected to the drain terminal of the M24 tube;

[0045] The drain end of the M20 tube is connected to the gate end and connected to the gate end of the M24 tube, and the source end is connected to the M21 tube and serves as the VBIAS2 node;

[0046] The source end of the M24 tube is connected to the drain end of the M25 tube;

[0047] The gate terminal of the M21 tube is connected to the drain terminal, and the source terminal is grounded;

[0048] The gate terminal of the M25 tube is connected to the gate terminal and drain terminal of the M21 tube, and the source terminal is grounded;

[0049] The source terminal of the M7 tube is connected to the voltage source VDD, the gate terminal is connected to the drain terminal and is also connected to the drain terminal of the M8 tube and the gate terminal of the M10 tube;

[0050] The gate terminal of the M8 tube is connected to the VBIAS1 node, and the source terminal is connected to the drain terminal of the M9 tube;

[0051] The gate terminal of the M9 tube is connected to the VBIAS2 node, and the source terminal is grounded;

[0052] The source terminal of the M13 tube is connected to the voltage source VDD, the drain terminal is connected to the source terminal of the M10 tube and the source terminal of the M14 tube, and the gate terminal is connected to the drain terminal of the M22 tube, the gate terminal of the M22 tube, and the source terminal of the M23 tube;

[0053] The gate terminal of the M14 tube is connected to the drain terminal and is also connected to the drain terminal of the M15;

[0054] The gate end of the M11 tube is connected to the drain end and connected to the drain end of the M10 tube, and the source end is connected to the drain end of the M12 tube;

[0055] The gate terminal of the M12 tube is connected to the drain terminal and connected to the source terminal of the M11 tube, and the source terminal is grounded;

[0056] The gate end of the M15 tube is connected to the gate end and drain end of the M11 tube, and the source end is connected to the drain end of the M16 tube;

[0057] The gate end of the M16 tube is connected to the gate end and the drain end of the M12 tube, the drain end is connected to the source end of the M15 tube, and the source end is grounded.

[0058] Optionally, the startup circuit includes an M1 transistor, an M5 transistor, an M2 transistor, an M3 transistor, an M4 transistor, and an M6 transistor, wherein the M1 transistor and the M5 transistor are PMOS transistors, and the M2 transistor, the M3 transistor, the M4 transistor, and the M6 ​​transistor are NMOS transistors;

[0059] The M1 transistor and the M2 transistor form a first inverter, with a gate terminal connected to the reference voltage output terminal, a drain terminal connected to the gate terminal of the M3 transistor and the drain terminal of the M4 transistor and serving as the voltage node VM connected to the bias circuit; the M1 transistor source terminal is connected to the voltage source VDD, and the M2 transistor source terminal is grounded;

[0060] The source and drain ends of the M3 tube are connected to the ground to form a MOS capacitor;

[0061] The M5 transistor and the M6 ​​transistor form a second inverter, the gate terminal of which is connected to the voltage node VBIAS2 of the bias circuit, and the drain terminal of which is connected to the gate terminal of the M4 transistor; the source terminal of the M5 transistor is connected to the voltage source VDD, and the source terminal of the M6 ​​transistor is grounded.

[0062] Compared with the prior art, this application has the following beneficial effects:

[0063] In the reference source circuit provided in the embodiment of the present application, the temperature characteristics of the positive temperature coefficient voltage generating circuit and the negative temperature coefficient voltage generating circuit are opposite, and have a mutual compensation effect, so that the final output voltage has no obvious temperature characteristics, and the output voltage can be adjusted using a bias circuit to achieve the required voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 A schematic diagram of a reference source circuit provided in an embodiment of the present application;

[0066] Figure 2A schematic diagram of a positive temperature coefficient voltage generating circuit provided in an embodiment of the present application includes a first MOS transistor, a first branch unit, a second branch unit and a voltage generating unit;

[0067] Figure 3 A schematic diagram of a voltage generating unit including a resistor provided in an embodiment of the present application;

[0068] Figure 4 A schematic diagram of a voltage generating unit provided in an embodiment of the present application, including a fourth MOS transistor and a bias unit;

[0069] Figure 5 A schematic diagram of a bias unit provided in an embodiment of the present application including a fifth MOS transistor and a sixth MOS transistor;

[0070] Figure 6 A schematic diagram of a reference source circuit including a startup circuit and a nA-level bias circuit is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. The described embodiments are part of the embodiments of the present application, but not all of the embodiments. Generally, the components of the embodiments of the present application described in the drawings herein can be arranged and designed in various different configurations.

[0072] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is claimed, but rather merely represents selected embodiments of the present application. All other embodiments derived by persons of ordinary skill in the art based on the embodiments in this application without creative effort are intended to fall within the scope of protection of this application. The following embodiments and features therein may be combined with each other unless there is a conflict.

[0073] In the description of this application, it is necessary to explain:

[0074] Relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another entity or operation and do not necessarily require or imply any actual relationship or order between these entities or operations;

[0075] “Connection” should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0076] like Figure 1, the reference source circuit includes a bias circuit, a positive temperature coefficient voltage generating circuit and a negative temperature coefficient voltage generating circuit:

[0077] The bias circuit is used to provide bias current for the positive temperature coefficient voltage generating circuit and the negative temperature coefficient voltage generating circuit;

[0078] When the positive temperature coefficient voltage generating circuit works alone, the output voltage is positively correlated with the temperature;

[0079] The output voltage of the negative temperature coefficient voltage generating circuit is negatively correlated with the temperature when working alone;

[0080] The output end of the positive temperature coefficient voltage generating circuit and the output end of the negative temperature coefficient voltage generating circuit are connected to serve as the reference voltage output end of the reference source circuit.

[0081] Because the temperature characteristics of the positive temperature coefficient voltage generating circuit and the negative temperature coefficient voltage generating circuit are opposite, they produce a mutual compensation effect, so that the final output voltage has no obvious temperature characteristics. In addition, the output voltage can be adjusted by using a bias circuit to achieve the required voltage.

[0082] The traditional bandgap reference source is based on the V BE and ΔV BE The reference voltage is usually larger than the bandgap voltage, which makes it difficult to achieve low voltage and has gradually failed to meet the requirements. This reference source circuit can use the standard CMOS process to achieve low-voltage stable output.

[0083] like Figure 2 The positive temperature coefficient voltage generating circuit may include a first MOS transistor, a first branch unit, a second branch unit and a voltage generating unit. The first branch unit and the second branch unit both include MOS transistors.

[0084] The gate terminal of the first MOS transistor is connected to the bias circuit, and the first MOS transistor generates a bias current according to the bias circuit.

[0085] The bias current enables the MOS transistors in the first branch unit and the second branch unit to operate in the subthreshold region.

[0086] The voltage generated by the voltage generating unit is caused by the voltage difference between the first branch unit and the second branch unit: the gate-source voltage difference generated by the MOS transistor in the first branch unit is the first voltage difference; the gate-source voltage difference generated by the MOS transistor in the second branch unit is the second voltage difference; the second voltage difference is different from the first voltage difference; the difference between the second voltage difference and the first voltage difference causes the voltage generating unit to generate a voltage with a positive temperature coefficient, and then this positive temperature coefficient voltage is connected to the negative temperature coefficient voltage generating circuit.

[0087] The first branch unit includes n second MOS transistors connected in series, and the second branch unit includes n third MOS transistors connected in series, where n≥2. Therefore, the width-to-length ratio of the second MOS transistor is designed to be different from that of the third MOS transistor, so that the voltage generated by the voltage generating unit can be designed.

[0088] The first branch unit and the second branch unit can also be designed to have different numbers of MOS transistors connected in series. That is, designing the number of MOS transistors connected in series in the first branch unit and the second branch unit is also a way to design the voltage generated by the voltage generating unit.

[0089] like Figure 3 The voltage generating unit may include a resistor, and the voltage generated by the resistor is connected to the negative temperature coefficient voltage generating circuit.

[0090] Figure 3 An alternative to Figure 4 The voltage generating unit includes a fourth MOS transistor and a bias unit. The drain terminal of the fourth MOS transistor is connected to the first terminal of the second branch unit, the source terminal of the fourth MOS transistor is grounded, and the gate terminal of the fourth MOS transistor is connected to the bias unit. The first terminal of the first branch unit is grounded, the second terminal of the first branch unit is connected to the second terminal of the second branch unit, and the current of the first MOS transistor flows from the second terminal of the first branch unit and the second terminal of the second branch unit, while the current of the second branch unit flows through the fourth MOS transistor.

[0091] like Figure 5 The bias unit may include a fifth MOS transistor and a sixth MOS transistor. The source terminal of the fifth MOS transistor is connected to a voltage source, the gate terminal of the fifth MOS transistor is connected to the drain terminal of the fifth MOS transistor, the drain terminal of the fifth MOS transistor is connected to the drain terminal of the sixth MOS transistor, the drain terminal of the sixth MOS transistor is connected to the gate terminal of the sixth MOS transistor and the gate terminal of the fourth MOS transistor, and the source terminal of the sixth MOS transistor is grounded.

[0092] The gate terminal of the sixth MOS transistor provides a bias for the gate terminal of the fourth MOS transistor, causing the fourth MOS transistor to operate in a linear region or a deep linear region. The drain terminal of the fourth MOS transistor can serve as the output terminal of the positive temperature coefficient voltage generating circuit. The drain terminal of the sixth MOS transistor can also serve as the output terminal of the positive temperature coefficient voltage generating circuit. In this case, the output voltage of the positive temperature coefficient voltage generating circuit is adjusted by the width-to-length ratio of the sixth MOS transistor.

[0093] The voltage of the positive temperature coefficient voltage generating circuit is also affected by the bias circuit. The bias circuit can be designed as a nA-level bias circuit. The nA-level bias circuit provides a bias current within 1 μA, thereby obtaining a more precise and stable output voltage.

[0094] Figure 6 An implementation of a nA-level bias circuit is shown. Figure 6The reference source circuit in the embodiment may also include a startup circuit 1, a bias circuit 2, a positive temperature coefficient voltage generating circuit 3 and a negative temperature coefficient voltage generating circuit 4 connected in sequence. The nA level bias circuit may also be designed as Figure 6 Other designs except

[0095] like Figure 6 , the control end of the startup circuit is connected to the reference voltage output end of the reference source circuit, so the voltage of the control end of the startup circuit is the reference voltage V output by the reference source circuit REF ; The input of the startup circuit is connected to the voltage source V DD , the output end of the startup circuit is connected to the bias circuit.

[0096] The startup circuit is used to start the bias circuit, and when the reference source circuit outputs normally, the startup circuit stops running, thereby saving power consumption.

[0097] like Figure 6 , M1 and M2 form the first inverter, M5 and M6 form the second inverter, and the source and drain of M3 are connected to the ground to form a MOS capacitor. The principle is as follows:

[0098] In the initial state, the reference voltage V output by the reference source circuit REF In the low level state, the PMOS tube M1 is turned on, and the voltage source V DD Charge the MOS capacitor M3 to increase the voltage at node V M The voltage of the voltage node V M Inject current into the M17 tube in the bias circuit and make the MOS tube in the bias circuit work in the subthreshold region. At this moment, V BIAS2 The node is at high potential, and the M6 ​​tube is turned on to pull down the voltage so that the M4 tube does not work. When the bias current generating circuit is stably turned on, V BIAS2 The node is at a low potential, the M5 tube is turned on to pull up the node voltage, so that the M4 tube is turned on to pull down the drain voltage of the M4 tube, and the MOS capacitor M3 tube is discharged, V M The node stops injecting current into the bias circuit, completing startup and turning off the startup circuit.

[0099] In the bias circuit, M17 to M25 transistors form a gate voltage control circuit, M7 to M12 transistors form a bias current generating circuit, and the startup circuit injects current into the gate voltage control circuit at startup to make the gate voltage control circuit work in the subthreshold region; the gate voltage control circuit is used to generate a bias current through V BIAS1 and V BIAS2 The voltage at the node causes the bias current generating circuit to generate a bias current I BIAS .

[0100] The M13 transistor provides bias current for the M10 and M14 transistors, while the M8 and M9 transistors provide bias for the M7 transistor. The bias current can be adjusted by adjusting the area ratio of the M10 and M14 transistors. The bias current IBIAS generated by this bias circuit is:

[0101]

[0102] Where μ p is the hole mobility in the semiconductor, is the width-to-length ratio of the deep linear MOS tube M17, K is the Boltzmann constant, T is the absolute temperature, and q is the charge of the electron. In the subthreshold current expression, n is the subthreshold slope correction factor, n=(C OX +C D ) / C OX , C D K is the unit capacitance of the depletion region. In the submicron standard CMOS process, n ranges from 1 to 3, with a typical value of 1.5. M18 and K M22 The size ratio of the M18 tube and the M22 tube is set, that is, the size ratio of M18 and M22 is K M18 / K M22 .

[0103] M27 to M32 transistors are all in the subthreshold region. The leakage current formula in the subthreshold state is:

[0104]

[0105] Because V DS Much larger than V T ,so It can be approximately equal to 1.

[0106] Therefore, the leakage current formula of the MOS tube in the subthreshold state is:

[0107]

[0108] Therefore, the gate-source voltage formula of the subthreshold MOS tube can be obtained as follows:

[0109]

[0110] Where m is a process-related parameter, and its value is usually between 1 and 2. T is the thermovoltage, which is about 26mV at room temperature and is positively correlated with temperature.

[0111] The gate-source voltage of the branch formed by M27 to M29 is recorded as V GS1 The gate-source voltage of the branch formed by the M30 to M32 tubes is recorded as V GS2Calculate according to the above-mentioned gate-source voltage formula of subthreshold MOS tube:

[0112]

[0113] In the formula, α is the number of MOS transistor pairs stacked in the positive temperature coefficient voltage generation circuit. For example, in the figure, three pairs of MOS transistors are stacked, so the difference in α is 3. α can be adjusted by adjusting the number of stacked pairs. The cascaded connection of multiple NMOS transistors increases the amplitude of the positive temperature coefficient voltage generated by the positive temperature coefficient voltage generation circuit while reducing the impact of the drain effect on circuit performance.

[0114] V GS1 and V GS2 The difference is:

[0115]

[0116] V T Positively correlated with temperature, as the temperature increases, V T Increases, so the corresponding positive temperature coefficient voltage can be obtained by adjusting the value of α.

[0117] The implementation method of the positive temperature coefficient voltage generating circuit mentioned above and Figure 6 The illustrated embodiment has the following corresponding relationship: transistor M26 is the first MOS transistor, transistors M27 to M29 are the second MOS transistors, transistors M30 to M32 are the third MOS transistors, transistor M33 is the fourth MOS transistor, transistor M34 is the fifth MOS transistor, and transistor M35 is the sixth MOS transistor.

[0118] The M33 tube is a MOS tube working in the deep linear region. The drain-source current formula is:

[0119]

[0120] The M35 tube is a MOS tube operating in the saturation region, and its drain-source current formula is:

[0121]

[0122] Because the gate-source voltage of M33 and M35 tubes are equal, and the width-to-length ratio is equal, I M33 =βI M35 β is the value obtained when the gate-source voltage of the M33 tube and the M35 tube are equal and the width-to-length ratio is equal. β can be adjusted by adjusting the width-to-length ratio.

[0123] Therefore, the drain-source current of the M35 tube is:

[0124]

[0125] Since the drain-source voltage of the M33 tube is:

[0126]

[0127]

[0128] The M37 tube is a PMOS tube operating in the saturation region, and its current formula is:

[0129]

[0130] The gate-source voltage can be obtained as follows:

[0131]

[0132] V TH It is negatively correlated with temperature and decreases with increasing temperature.

[0133]

[0134] Therefore, by adjusting the values ​​of α, β and the width-to-length ratio of the M37 tube, a temperature-independent reference voltage source can be obtained with a wider temperature range and lower power consumption. At the same time, the full MOS structure used in this circuit can effectively reduce the layout area.

[0135] like Figure 6 , the negative temperature coefficient voltage generating circuit includes M36 tube and M37 tube;

[0136] The gate terminal of the M36 tube is connected to the bias circuit, and the M36 tube generates a bias current according to the bias circuit;

[0137] The source end of the M37 tube is connected to the drain end of the M36 tube, and the source end of the M37 tube is connected to the output end of the positive temperature coefficient voltage generating circuit. The gate end of the M37 tube is connected to the drain end of the M37 tube, and the drain end of the M37 tube is grounded.

[0138] V REF It is a temperature compensation voltage generated by combining the output of the positive temperature coefficient voltage generating circuit and the output of the negative temperature coefficient voltage generating circuit. Its formula is usually the weighted sum of the output of the positive temperature coefficient voltage generating circuit and the output of the negative temperature coefficient voltage generating circuit:

[0139] V REF =A×V PTAT +B×V CTAT

[0140] V PTAT Represents the output of the positive temperature coefficient voltage generating circuit when it works alone, V CTAT This represents the output of the negative temperature coefficient voltage generating circuit when it operates alone. A and B are constants.

[0141] It has been verified that the reference source circuit of the above structure can generate a reference voltage of 588.4~588.8mV within a power supply voltage of 1.2V and a temperature range of -55℃ to (+)150℃, realizing a low-voltage, low-power, wide-temperature-range reference source.

[0142] The above-described device and system embodiments are merely illustrative, and some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. Those skilled in the art may understand and implement the present invention without inventive effort.

[0143] The above are merely preferred embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A reference source circuit, characterized in that: Including bias circuit, positive temperature coefficient voltage generating circuit and negative temperature coefficient voltage generating circuit: The bias circuit is used to provide bias current for the positive temperature coefficient voltage generating circuit and the negative temperature coefficient voltage generating circuit; When the positive temperature coefficient voltage generating circuit works alone, the output voltage is positively correlated with the temperature; The output voltage of the negative temperature coefficient voltage generating circuit is negatively correlated with the temperature when working alone; The output end of the positive temperature coefficient voltage generating circuit and the output end of the negative temperature coefficient voltage generating circuit are connected to serve as the reference voltage output end of the reference source circuit; The bias circuit is a nA-level bias circuit; The bias circuit includes M7 tube, M8 tube, M9 tube, M10 tube, M11 tube, M12 tube, M13 tube, M14 tube, M15 tube, M16 tube, M17 tube, M18 tube, M19 tube, M20 tube, M21 tube, M22 tube, M23 tube, M24 tube and M25 tube; The M7 tube, the M10 tube, the M13 tube, the M14 tube, the M17 tube, the M19 tube, the M22 tube and the M23 tube are PMOS tubes; The M8 tube, the M9 tube, the M11 tube, the M12 tube, the M15 tube, the M16 tube, the M20 tube, the M21 tube, the M24 tube and the M25 tube are NMOS tubes; The source terminal of the M17 tube is connected to the voltage source, and the gate terminal is connected to the gate terminal and drain terminal of the M14 tube, and is connected to the voltage node V M The drain end is connected to the drain end of the M18 tube; The gate end of the M18 tube is connected to the gate end of the M22 tube, and the drain end is connected to the source end of the M19 tube; The source terminal of the M22 tube is connected to the voltage source, and the gate terminal is connected to the drain terminal and connected to the source terminal of the M23 tube; The gate end of the M19 tube is connected to the gate end of the M23 tube, and the drain end is connected to the drain end and gate end of the M20 tube and serves as V BIAS1 node; The gate terminal of the M23 tube is connected to the drain terminal and is also connected to the drain terminal of the M24 tube; The drain end of the M20 tube is connected to the gate end and connected to the gate end of the M24 tube, and the source end is connected to the gate end of the M21 tube and serves as V BIAS2 node; The source end of the M24 tube is connected to the drain end of the M25 tube; The gate terminal of the M21 tube is connected to the drain terminal, and the source terminal is grounded; The gate terminal of the M25 tube is connected to the gate terminal and drain terminal of the M21 tube, and the source terminal is grounded; The source terminal of the M7 tube is connected to a voltage source, the gate terminal is connected to the drain terminal, and is also connected to the drain terminal of the M8 tube and the gate terminal of the M10 tube; The M8 gate is connected to the V BIAS1 Node, the source end is connected to the drain end of the M9 tube; The M9 gate is connected to the V BIAS2 Node, source end is grounded; The source terminal of the M13 tube is connected to the voltage source, the drain terminal is connected to the source terminal of the M10 tube and the source terminal of the M14 tube, and the gate terminal is connected to the drain terminal of the M22 tube, the gate terminal of the M22 tube, and the source terminal of the M23 tube; The gate terminal of the M14 tube is connected to the drain terminal and is also connected to the drain terminal of the M15; The gate end of the M11 tube is connected to the drain end and connected to the drain end of the M10 tube, and the source end is connected to the drain end of the M12 tube; The gate terminal of the M12 tube is connected to the drain terminal and connected to the source terminal of the M11 tube, and the source terminal is grounded; The gate end of the M15 tube is connected to the gate end and drain end of the M11 tube, and the source end is connected to the drain end of the M16 tube; The gate end of the M16 tube is connected to the gate end and the drain end of the M12 tube, the drain end is connected to the source end of the M15 tube, and the source end is grounded.

2. The reference source circuit according to claim 1, wherein: The positive temperature coefficient voltage generating circuit includes a first MOS tube, a first branch unit, a second branch unit and a voltage generating unit; The gate terminal of the first MOS transistor is connected to the bias circuit, the source terminal of the first MOS transistor is connected to a voltage source, the drain terminal of the first MOS transistor is connected to the first branch unit and the second branch unit respectively, and the first MOS transistor generates a bias current according to the bias circuit; The first branch unit and the second branch unit both include MOS tubes; The bias current causes the MOS transistors in the first branch unit and the second branch unit to operate in a subthreshold region; The gate-source voltage difference generated by the MOS tube in the first branch unit is a first voltage difference; The gate-source voltage difference generated by the MOS transistor in the second branch unit is a second voltage difference; the second voltage difference is different from the first voltage difference; The voltage generating unit generates a voltage according to a difference between the second voltage difference and the first voltage difference.

3. The reference source circuit according to claim 2, wherein: The first branch unit includes n second MOS transistors connected in series; the second branch unit includes n third MOS transistors connected in series; n≥2; The width-to-length ratio of the second MOS transistor is different from the width-to-length ratio of the third MOS transistor.

4. The reference source circuit according to claim 2, wherein: The voltage generating unit includes a resistor, or the voltage generating unit includes a fourth MOS transistor and a bias unit; The drain end of the fourth MOS transistor is connected to the first end of the second branch unit, the source end of the fourth MOS transistor is grounded, and the gate end of the fourth MOS transistor is connected to the bias unit; The first end of the first branch unit is grounded, the second end of the first branch unit is connected to the second end of the second branch unit, and the current of the first MOS transistor flows into the second end of the first branch unit and the second end of the second branch unit.

5. The reference source circuit according to claim 4, wherein: The bias unit includes a fifth MOS transistor and a sixth MOS transistor; The source terminal of the fifth MOS transistor is connected to a voltage source, the gate terminal of the fifth MOS transistor is connected to the drain terminal of the fifth MOS transistor, the drain terminal of the fifth MOS transistor is connected to the drain terminal of the sixth MOS transistor, the drain terminal of the sixth MOS transistor is connected to the gate terminal of the sixth MOS transistor and the gate terminal of the fourth MOS transistor, and the source terminal of the sixth MOS transistor is grounded; The gate terminal of the sixth MOS transistor provides a bias for the gate terminal of the fourth MOS transistor so that the fourth MOS transistor operates in a linear region or a deep linear region; The drain end of the sixth MOS transistor serves as the output end of the positive temperature coefficient voltage generating circuit.

6. The reference source circuit according to claim 1, wherein: The negative temperature coefficient voltage generating circuit includes a seventh MOS transistor and an eighth MOS transistor; The gate terminal of the seventh MOS transistor is connected to the bias circuit, and the seventh MOS transistor generates a bias current according to the bias circuit; The source end of the eighth MOS transistor is connected to the seventh MOS transistor, and the source end of the eighth MOS transistor is connected to the output end of the positive temperature coefficient voltage generating circuit, the gate end of the eighth MOS transistor is connected to the drain end of the eighth MOS transistor, and the drain end of the eighth MOS transistor is grounded.

7. The reference source circuit according to claim 1, wherein: The reference source circuit also includes a startup circuit; The control end of the startup circuit is connected to the reference voltage output end of the reference source circuit; the input end of the startup circuit is connected to the voltage source, and the output end of the startup circuit is connected to the bias circuit; The startup circuit is used to start the bias circuit, and when the reference source circuit outputs normally, the startup circuit stops running.

8. The reference source circuit according to claim 7, wherein: The bias circuit includes a gate voltage control circuit and a bias current generating circuit; The startup circuit is used to inject current into the gate voltage control circuit during startup, so that the gate voltage control circuit operates in the subthreshold region; The gate voltage control circuit is used to enable the bias current generating circuit to generate the bias current when operating in the subthreshold region.

9. The reference source circuit according to claim 7, wherein: The startup circuit includes an M1 transistor, an M5 transistor, an M2 transistor, an M3 transistor, an M4 transistor, and an M6 transistor, wherein the M1 transistor and the M5 transistor are PMOS transistors, and the M2 transistor, the M3 transistor, the M4 transistor, and the M6 ​​transistor are NMOS transistors; The M1 transistor and the M2 transistor form a first inverter, the gate end is connected to the reference voltage output end, the drain end is connected to the gate end of the M3 transistor and the drain end of the M4 transistor and serves as the voltage node V connected to the bias circuit. M The M1 tube source terminal is connected to a voltage source, and the M2 tube source terminal is grounded; The source and drain ends of the M3 tube are connected to the ground to form a MOS capacitor; The M5 tube and the M6 ​​tube form a second inverter, and the gate terminal is connected to the V BIAS2 The node is connected, the drain end is connected to the gate end of the M4 tube; the source end of the M5 tube is connected to the voltage source, and the source end of the M6 ​​tube is grounded.

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